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ashikpoojari/Hardware-Security | RC5 CryptoCore/Rc5 Codes/rc5_pkg.vhd | 2 | 379 | Library IEEE;
Use IEEE.std_logic_1164.all;
Package rc5_pkg Is
--S Rom array
Type rom Is Array (0 to 25) of std_logic_vector (31 downto 0);
--L Rom array
Type L_rom Is Array (0 to 3) of std_logic_vector (31 downto 0);
--Type for RC5 State Machine
Type StateType IS
(
ST_idle,
ST_pre_round,
ST_round_op,
ST_ready
);
Signal state : StateType;
End rc5_pkg; | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_1_0/system_clock_splitter_1_0_stub.vhdl | 1 | 1382 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:06:44 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_1_0/system_clock_splitter_1_0_stub.vhdl
-- Design : system_clock_splitter_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_clock_splitter_1_0 is
Port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end system_clock_splitter_1_0;
architecture stub of system_clock_splitter_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_in,latch_edge,clk_out";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "clock_splitter,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_transform_0_1/ip/affine_block_ieee754_fp_multiplier_1_2/sim/affine_block_ieee754_fp_multiplier_1_2.vhd | 2 | 3266 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_multiplier:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_multiplier_1_2 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_multiplier_1_2;
ARCHITECTURE affine_block_ieee754_fp_multiplier_1_2_arch OF affine_block_ieee754_fp_multiplier_1_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_multiplier_1_2_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_multiplier IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_multiplier;
BEGIN
U0 : ieee754_fp_multiplier
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_multiplier_1_2_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd | 3 | 142619 | `protect begin_protected
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`protect end_protected
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 3 | 94635 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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6MKh1xrgtg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
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`protect end_protected
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_stub.vhdl | 1 | 5642 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:55:26 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_stub.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_processing_system7_0_0 is
Port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end system_processing_system7_0_0;
architecture stub of system_processing_system7_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_2/system_auto_us_2_stub.vhdl | 1 | 3720 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:17:20 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_2/system_auto_us_2_stub.vhdl
-- Design : system_auto_us_2
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_auto_us_2 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC
);
end system_auto_us_2;
architecture stub of system_auto_us_2 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_stub.vhdl | 1 | 5652 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:47:02 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_stub.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_processing_system7_0_0 is
Port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end system_processing_system7_0_0;
architecture stub of system_processing_system7_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_0/affine_block_ieee754_fp_multiplier_1_0_sim_netlist.vhdl | 1 | 200696 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_0/affine_block_ieee754_fp_multiplier_1_0_sim_netlist.vhdl
-- Design : affine_block_ieee754_fp_multiplier_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_multiplier_1_0_ieee754_fp_multiplier is
port (
z : out STD_LOGIC_VECTOR ( 7 downto 0 );
z_mantissa : out STD_LOGIC_VECTOR ( 22 downto 0 );
x : in STD_LOGIC_VECTOR ( 30 downto 0 );
y : in STD_LOGIC_VECTOR ( 30 downto 0 );
\y_11__s_port_\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of affine_block_ieee754_fp_multiplier_1_0_ieee754_fp_multiplier : entity is "ieee754_fp_multiplier";
end affine_block_ieee754_fp_multiplier_1_0_ieee754_fp_multiplier;
architecture STRUCTURE of affine_block_ieee754_fp_multiplier_1_0_ieee754_fp_multiplier is
signal L1 : STD_LOGIC;
signal \L1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \L1_carry__0_n_0\ : STD_LOGIC;
signal \L1_carry__0_n_1\ : STD_LOGIC;
signal \L1_carry__0_n_2\ : STD_LOGIC;
signal \L1_carry__0_n_3\ : STD_LOGIC;
signal \L1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \L1_carry__1_n_0\ : STD_LOGIC;
signal \L1_carry__1_n_1\ : STD_LOGIC;
signal \L1_carry__1_n_2\ : STD_LOGIC;
signal \L1_carry__1_n_3\ : STD_LOGIC;
signal \L1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__2_n_1\ : STD_LOGIC;
signal \L1_carry__2_n_2\ : STD_LOGIC;
signal \L1_carry__2_n_3\ : STD_LOGIC;
signal L1_carry_i_10_n_0 : STD_LOGIC;
signal L1_carry_i_11_n_0 : STD_LOGIC;
signal L1_carry_i_12_n_0 : STD_LOGIC;
signal L1_carry_i_13_n_0 : STD_LOGIC;
signal L1_carry_i_14_n_0 : STD_LOGIC;
signal L1_carry_i_15_n_0 : STD_LOGIC;
signal L1_carry_i_16_n_0 : STD_LOGIC;
signal L1_carry_i_17_n_0 : STD_LOGIC;
signal L1_carry_i_18_n_0 : STD_LOGIC;
signal L1_carry_i_19_n_0 : STD_LOGIC;
signal L1_carry_i_1_n_0 : STD_LOGIC;
signal L1_carry_i_20_n_0 : STD_LOGIC;
signal L1_carry_i_21_n_0 : STD_LOGIC;
signal L1_carry_i_22_n_0 : STD_LOGIC;
signal L1_carry_i_23_n_0 : STD_LOGIC;
signal L1_carry_i_24_n_0 : STD_LOGIC;
signal L1_carry_i_25_n_0 : STD_LOGIC;
signal L1_carry_i_26_n_0 : STD_LOGIC;
signal L1_carry_i_27_n_0 : STD_LOGIC;
signal L1_carry_i_28_n_0 : STD_LOGIC;
signal L1_carry_i_29_n_0 : STD_LOGIC;
signal L1_carry_i_2_n_0 : STD_LOGIC;
signal L1_carry_i_30_n_0 : STD_LOGIC;
signal L1_carry_i_31_n_0 : STD_LOGIC;
signal L1_carry_i_32_n_0 : STD_LOGIC;
signal L1_carry_i_33_n_0 : STD_LOGIC;
signal L1_carry_i_34_n_0 : STD_LOGIC;
signal L1_carry_i_35_n_0 : STD_LOGIC;
signal L1_carry_i_36_n_0 : STD_LOGIC;
signal L1_carry_i_37_n_0 : STD_LOGIC;
signal L1_carry_i_38_n_0 : STD_LOGIC;
signal L1_carry_i_39_n_0 : STD_LOGIC;
signal L1_carry_i_3_n_0 : STD_LOGIC;
signal L1_carry_i_40_n_0 : STD_LOGIC;
signal L1_carry_i_41_n_0 : STD_LOGIC;
signal L1_carry_i_42_n_0 : STD_LOGIC;
signal L1_carry_i_43_n_0 : STD_LOGIC;
signal L1_carry_i_44_n_0 : STD_LOGIC;
signal L1_carry_i_45_n_0 : STD_LOGIC;
signal L1_carry_i_46_n_0 : STD_LOGIC;
signal L1_carry_i_47_n_0 : STD_LOGIC;
signal L1_carry_i_48_n_0 : STD_LOGIC;
signal L1_carry_i_49_n_0 : STD_LOGIC;
signal L1_carry_i_4_n_0 : STD_LOGIC;
signal L1_carry_i_50_n_0 : STD_LOGIC;
signal L1_carry_i_51_n_0 : STD_LOGIC;
signal L1_carry_i_52_n_0 : STD_LOGIC;
signal L1_carry_i_53_n_0 : STD_LOGIC;
signal L1_carry_i_54_n_0 : STD_LOGIC;
signal L1_carry_i_5_n_0 : STD_LOGIC;
signal L1_carry_i_6_n_0 : STD_LOGIC;
signal L1_carry_i_7_n_0 : STD_LOGIC;
signal L1_carry_i_8_n_0 : STD_LOGIC;
signal L1_carry_i_9_n_0 : STD_LOGIC;
signal L1_carry_n_0 : STD_LOGIC;
signal L1_carry_n_1 : STD_LOGIC;
signal L1_carry_n_2 : STD_LOGIC;
signal L1_carry_n_3 : STD_LOGIC;
signal \_carry__0_i_1_n_0\ : STD_LOGIC;
signal \_carry__0_i_2_n_0\ : STD_LOGIC;
signal \_carry__0_i_3_n_0\ : STD_LOGIC;
signal \_carry__0_i_4_n_0\ : STD_LOGIC;
signal \_carry__0_n_0\ : STD_LOGIC;
signal \_carry__0_n_1\ : STD_LOGIC;
signal \_carry__0_n_2\ : STD_LOGIC;
signal \_carry__0_n_3\ : STD_LOGIC;
signal \_carry__0_n_4\ : STD_LOGIC;
signal \_carry__0_n_5\ : STD_LOGIC;
signal \_carry__0_n_6\ : STD_LOGIC;
signal \_carry__0_n_7\ : STD_LOGIC;
signal \_carry__1_i_1_n_0\ : STD_LOGIC;
signal \_carry__1_i_2_n_0\ : STD_LOGIC;
signal \_carry__1_i_3_n_0\ : STD_LOGIC;
signal \_carry__1_i_4_n_0\ : STD_LOGIC;
signal \_carry__1_n_0\ : STD_LOGIC;
signal \_carry__1_n_1\ : STD_LOGIC;
signal \_carry__1_n_2\ : STD_LOGIC;
signal \_carry__1_n_3\ : STD_LOGIC;
signal \_carry__1_n_4\ : STD_LOGIC;
signal \_carry__1_n_5\ : STD_LOGIC;
signal \_carry__1_n_6\ : STD_LOGIC;
signal \_carry__1_n_7\ : STD_LOGIC;
signal \_carry__2_i_1_n_0\ : STD_LOGIC;
signal \_carry__2_i_2_n_0\ : STD_LOGIC;
signal \_carry__2_i_3_n_0\ : STD_LOGIC;
signal \_carry__2_i_4_n_0\ : STD_LOGIC;
signal \_carry__2_n_0\ : STD_LOGIC;
signal \_carry__2_n_1\ : STD_LOGIC;
signal \_carry__2_n_2\ : STD_LOGIC;
signal \_carry__2_n_3\ : STD_LOGIC;
signal \_carry__2_n_4\ : STD_LOGIC;
signal \_carry__2_n_5\ : STD_LOGIC;
signal \_carry__2_n_6\ : STD_LOGIC;
signal \_carry__2_n_7\ : STD_LOGIC;
signal \_carry__3_i_1_n_0\ : STD_LOGIC;
signal \_carry__3_i_2_n_0\ : STD_LOGIC;
signal \_carry__3_i_3_n_0\ : STD_LOGIC;
signal \_carry__3_i_4_n_0\ : STD_LOGIC;
signal \_carry__3_n_0\ : STD_LOGIC;
signal \_carry__3_n_1\ : STD_LOGIC;
signal \_carry__3_n_2\ : STD_LOGIC;
signal \_carry__3_n_3\ : STD_LOGIC;
signal \_carry__3_n_4\ : STD_LOGIC;
signal \_carry__3_n_5\ : STD_LOGIC;
signal \_carry__3_n_6\ : STD_LOGIC;
signal \_carry__3_n_7\ : STD_LOGIC;
signal \_carry__4_i_1_n_0\ : STD_LOGIC;
signal \_carry__4_i_2_n_0\ : STD_LOGIC;
signal \_carry__4_i_3_n_0\ : STD_LOGIC;
signal \_carry__4_i_4_n_0\ : STD_LOGIC;
signal \_carry__4_n_0\ : STD_LOGIC;
signal \_carry__4_n_1\ : STD_LOGIC;
signal \_carry__4_n_2\ : STD_LOGIC;
signal \_carry__4_n_3\ : STD_LOGIC;
signal \_carry__4_n_4\ : STD_LOGIC;
signal \_carry__4_n_5\ : STD_LOGIC;
signal \_carry__4_n_6\ : STD_LOGIC;
signal \_carry__4_n_7\ : STD_LOGIC;
signal \_carry__5_i_1_n_0\ : STD_LOGIC;
signal \_carry__5_i_2_n_0\ : STD_LOGIC;
signal \_carry__5_i_3_n_0\ : STD_LOGIC;
signal \_carry__5_i_4_n_0\ : STD_LOGIC;
signal \_carry__5_n_0\ : STD_LOGIC;
signal \_carry__5_n_1\ : STD_LOGIC;
signal \_carry__5_n_2\ : STD_LOGIC;
signal \_carry__5_n_3\ : STD_LOGIC;
signal \_carry__5_n_4\ : STD_LOGIC;
signal \_carry__5_n_5\ : STD_LOGIC;
signal \_carry__5_n_6\ : STD_LOGIC;
signal \_carry__5_n_7\ : STD_LOGIC;
signal \_carry__6_i_1_n_0\ : STD_LOGIC;
signal \_carry__6_i_2_n_0\ : STD_LOGIC;
signal \_carry__6_n_3\ : STD_LOGIC;
signal \_carry__6_n_6\ : STD_LOGIC;
signal \_carry__6_n_7\ : STD_LOGIC;
signal \_carry_i_10_n_0\ : STD_LOGIC;
signal \_carry_i_11_n_0\ : STD_LOGIC;
signal \_carry_i_12_n_0\ : STD_LOGIC;
signal \_carry_i_13_n_0\ : STD_LOGIC;
signal \_carry_i_14_n_0\ : STD_LOGIC;
signal \_carry_i_15_n_0\ : STD_LOGIC;
signal \_carry_i_16_n_0\ : STD_LOGIC;
signal \_carry_i_17_n_0\ : STD_LOGIC;
signal \_carry_i_18_n_0\ : STD_LOGIC;
signal \_carry_i_19_n_0\ : STD_LOGIC;
signal \_carry_i_1_n_0\ : STD_LOGIC;
signal \_carry_i_20_n_0\ : STD_LOGIC;
signal \_carry_i_21_n_0\ : STD_LOGIC;
signal \_carry_i_22_n_0\ : STD_LOGIC;
signal \_carry_i_23_n_0\ : STD_LOGIC;
signal \_carry_i_24_n_0\ : STD_LOGIC;
signal \_carry_i_2_n_0\ : STD_LOGIC;
signal \_carry_i_3_n_0\ : STD_LOGIC;
signal \_carry_i_4_n_0\ : STD_LOGIC;
signal \_carry_i_6_n_0\ : STD_LOGIC;
signal \_carry_i_7_n_0\ : STD_LOGIC;
signal \_carry_i_8_n_0\ : STD_LOGIC;
signal \_carry_i_9_n_0\ : STD_LOGIC;
signal \_carry_n_0\ : STD_LOGIC;
signal \_carry_n_1\ : STD_LOGIC;
signal \_carry_n_2\ : STD_LOGIC;
signal \_carry_n_3\ : STD_LOGIC;
signal \_carry_n_4\ : STD_LOGIC;
signal \_carry_n_5\ : STD_LOGIC;
signal \_carry_n_6\ : STD_LOGIC;
signal \_carry_n_7\ : STD_LOGIC;
signal data0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal data1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \msb1__1\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal msb1_n_106 : STD_LOGIC;
signal msb1_n_107 : STD_LOGIC;
signal msb1_n_108 : STD_LOGIC;
signal msb1_n_109 : STD_LOGIC;
signal msb1_n_110 : STD_LOGIC;
signal msb1_n_111 : STD_LOGIC;
signal msb1_n_112 : STD_LOGIC;
signal msb1_n_113 : STD_LOGIC;
signal msb1_n_114 : STD_LOGIC;
signal msb1_n_115 : STD_LOGIC;
signal msb1_n_116 : STD_LOGIC;
signal msb1_n_117 : STD_LOGIC;
signal msb1_n_118 : STD_LOGIC;
signal msb1_n_119 : STD_LOGIC;
signal msb1_n_120 : STD_LOGIC;
signal msb1_n_121 : STD_LOGIC;
signal msb1_n_122 : STD_LOGIC;
signal msb1_n_123 : STD_LOGIC;
signal msb1_n_124 : STD_LOGIC;
signal msb1_n_125 : STD_LOGIC;
signal msb1_n_126 : STD_LOGIC;
signal msb1_n_127 : STD_LOGIC;
signal msb1_n_128 : STD_LOGIC;
signal msb1_n_129 : STD_LOGIC;
signal msb1_n_130 : STD_LOGIC;
signal msb1_n_131 : STD_LOGIC;
signal msb1_n_132 : STD_LOGIC;
signal msb1_n_133 : STD_LOGIC;
signal msb1_n_134 : STD_LOGIC;
signal msb1_n_135 : STD_LOGIC;
signal msb1_n_136 : STD_LOGIC;
signal msb1_n_137 : STD_LOGIC;
signal msb1_n_138 : STD_LOGIC;
signal msb1_n_139 : STD_LOGIC;
signal msb1_n_140 : STD_LOGIC;
signal msb1_n_141 : STD_LOGIC;
signal msb1_n_142 : STD_LOGIC;
signal msb1_n_143 : STD_LOGIC;
signal msb1_n_144 : STD_LOGIC;
signal msb1_n_145 : STD_LOGIC;
signal msb1_n_146 : STD_LOGIC;
signal msb1_n_147 : STD_LOGIC;
signal msb1_n_148 : STD_LOGIC;
signal msb1_n_149 : STD_LOGIC;
signal msb1_n_150 : STD_LOGIC;
signal msb1_n_151 : STD_LOGIC;
signal msb1_n_152 : STD_LOGIC;
signal msb1_n_153 : STD_LOGIC;
signal msb1_n_58 : STD_LOGIC;
signal msb1_n_59 : STD_LOGIC;
signal msb1_n_60 : STD_LOGIC;
signal msb1_n_61 : STD_LOGIC;
signal msb1_n_62 : STD_LOGIC;
signal msb1_n_63 : STD_LOGIC;
signal msb1_n_64 : STD_LOGIC;
signal msb1_n_65 : STD_LOGIC;
signal msb1_n_66 : STD_LOGIC;
signal msb1_n_67 : STD_LOGIC;
signal msb1_n_68 : STD_LOGIC;
signal msb1_n_69 : STD_LOGIC;
signal msb1_n_70 : STD_LOGIC;
signal msb1_n_71 : STD_LOGIC;
signal msb1_n_72 : STD_LOGIC;
signal msb1_n_73 : STD_LOGIC;
signal msb1_n_74 : STD_LOGIC;
signal msb1_n_75 : STD_LOGIC;
signal msb1_n_76 : STD_LOGIC;
signal msb1_n_77 : STD_LOGIC;
signal msb1_n_78 : STD_LOGIC;
signal msb1_n_79 : STD_LOGIC;
signal msb1_n_80 : STD_LOGIC;
signal msb1_n_81 : STD_LOGIC;
signal msb1_n_82 : STD_LOGIC;
signal msb1_n_83 : STD_LOGIC;
signal msb1_n_84 : STD_LOGIC;
signal msb1_n_85 : STD_LOGIC;
signal msb1_n_86 : STD_LOGIC;
signal msb1_n_87 : STD_LOGIC;
signal msb1_n_88 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal sel0 : STD_LOGIC_VECTOR ( 22 downto 0 );
signal \y_11__s_net_1\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[15]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[22]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[22]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[22]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_100_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_101_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_102_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_103_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_104_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_105_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_106_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_107_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_108_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_109_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_110_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_111_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_112_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_113_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_114_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_115_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_116_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_117_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_118_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_119_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_120_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_121_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_122_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_123_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_124_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_125_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_126_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_127_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_128_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_129_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_130_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_131_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_132_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_133_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_134_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_135_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_136_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_137_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_138_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_139_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_140_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_141_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_142_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_143_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_144_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_145_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_146_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_147_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_148_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_149_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_150_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_151_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_152_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_153_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_154_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_155_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_156_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_157_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_158_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_159_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_160_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_161_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_162_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_163_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_164_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_165_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_166_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_167_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_168_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_169_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_170_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_171_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_172_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_173_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_174_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_175_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_176_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_177_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_178_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_179_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_180_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_181_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_182_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_183_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_184_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_185_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_186_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_187_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_188_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_189_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_190_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_191_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_192_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_193_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_194_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_195_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_196_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_197_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_198_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_199_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_19_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_200_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_201_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_202_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_203_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_204_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_205_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_206_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_207_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_208_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_209_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_20_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_210_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_211_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_212_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_213_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_214_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_215_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_216_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_217_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_218_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_219_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_21_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_220_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_221_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_222_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_223_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_224_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_225_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_226_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_227_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_228_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_229_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_22_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_230_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_231_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_232_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_233_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_234_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_235_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_236_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_237_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_238_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_239_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_240_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_241_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_242_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_243_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_244_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_245_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_246_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_29_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_30_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_31_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_32_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_33_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_34_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_35_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_36_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_37_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_38_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_39_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_40_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_41_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_42_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_43_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_44_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_45_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_46_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_47_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_48_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_49_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_50_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_51_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_52_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_53_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_54_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_55_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_56_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_57_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_58_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_59_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_60_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_61_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_62_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_63_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_64_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_65_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_66_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_67_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_68_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_69_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_70_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_71_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_72_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_73_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_74_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_75_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_76_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_77_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_78_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_79_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_80_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_81_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_82_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_83_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_94_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_95_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_96_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_97_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_98_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_99_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_1\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_2\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_3\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_1_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_2_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_3_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_4_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_5_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_6_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_7_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_1\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_2\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_3\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_1\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_2\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_3\ : STD_LOGIC;
signal \z_exponent1_carry_i_1__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_1_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_2__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_2_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_3__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_3_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_4__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_4_n_0 : STD_LOGIC;
signal z_exponent1_carry_i_5_n_0 : STD_LOGIC;
signal z_exponent1_carry_n_0 : STD_LOGIC;
signal z_exponent1_carry_n_1 : STD_LOGIC;
signal z_exponent1_carry_n_2 : STD_LOGIC;
signal z_exponent1_carry_n_3 : STD_LOGIC;
signal NLW_L1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW__carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW__carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_msb1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_msb1_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_msb1_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_msb1__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_msb1__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_msb1__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_msb1__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 31 );
signal \NLW_msb1__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_z[22]_INST_0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_z[22]_INST_0_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_z_exponent0__0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_z_exponent1_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of L1_carry_i_18 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of L1_carry_i_19 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of L1_carry_i_22 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of L1_carry_i_23 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of L1_carry_i_27 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of L1_carry_i_30 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of L1_carry_i_31 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of L1_carry_i_33 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of L1_carry_i_34 : label is "soft_lutpair27";
attribute SOFT_HLUTNM of L1_carry_i_36 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of L1_carry_i_39 : label is "soft_lutpair29";
attribute SOFT_HLUTNM of L1_carry_i_46 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of L1_carry_i_47 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of L1_carry_i_49 : label is "soft_lutpair24";
attribute SOFT_HLUTNM of L1_carry_i_52 : label is "soft_lutpair29";
attribute SOFT_HLUTNM of L1_carry_i_53 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of L1_carry_i_54 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \_carry_i_11\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \_carry_i_18\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \_carry_i_19\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \_carry_i_20\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \_carry_i_22\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \_carry_i_24\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \_carry_i_6\ : label is "soft_lutpair27";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of msb1 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \msb1__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute SOFT_HLUTNM of \z[11]_INST_0_i_8\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \z[11]_INST_0_i_9\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \z[15]_INST_0_i_8\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_102\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_111\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_112\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_113\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_114\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_173\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_174\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_175\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_176\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_177\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_178\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_179\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_180\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_181\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_182\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_183\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_184\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_185\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_186\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_187\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_188\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_191\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_192\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_197\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_198\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_202\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_203\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_204\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_205\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_212\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_213\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_214\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_215\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_216\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_217\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_220\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_231\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_246\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_31\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_37\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_38\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_39\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_43\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_44\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_47\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_48\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_49\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_50\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_51\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_52\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_57\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_59\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_62\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_63\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_65\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_68\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_70\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_72\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_77\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_79\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_95\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_97\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \z[7]_INST_0_i_10\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \z[7]_INST_0_i_12\ : label is "soft_lutpair32";
attribute HLUTNM : string;
attribute HLUTNM of \z_exponent0__0_carry__0_i_2\ : label is "lutpair3";
attribute SOFT_HLUTNM of \z_exponent0__0_carry__0_i_8\ : label is "soft_lutpair2";
attribute HLUTNM of \z_exponent0__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \z_exponent0__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \z_exponent0__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \z_exponent0__0_carry_i_7\ : label is "lutpair0";
attribute HLUTNM of \z_exponent1_carry_i_1__0\ : label is "lutpair4";
attribute HLUTNM of \z_exponent1_carry_i_3__0\ : label is "lutpair2";
attribute HLUTNM of z_exponent1_carry_i_4 : label is "lutpair1";
attribute HLUTNM of \z_exponent1_carry_i_4__0\ : label is "lutpair3";
attribute HLUTNM of z_exponent1_carry_i_5 : label is "lutpair4";
begin
\y_11__s_net_1\ <= \y_11__s_port_\;
L1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => L1_carry_n_0,
CO(2) => L1_carry_n_1,
CO(1) => L1_carry_n_2,
CO(0) => L1_carry_n_3,
CYINIT => '1',
DI(3) => L1_carry_i_1_n_0,
DI(2) => L1_carry_i_2_n_0,
DI(1) => L1_carry_i_3_n_0,
DI(0) => L1_carry_i_4_n_0,
O(3 downto 0) => NLW_L1_carry_O_UNCONNECTED(3 downto 0),
S(3) => L1_carry_i_5_n_0,
S(2) => L1_carry_i_6_n_0,
S(1) => L1_carry_i_7_n_0,
S(0) => L1_carry_i_8_n_0
);
\L1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => L1_carry_n_0,
CO(3) => \L1_carry__0_n_0\,
CO(2) => \L1_carry__0_n_1\,
CO(1) => \L1_carry__0_n_2\,
CO(0) => \L1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \L1_carry__0_i_1_n_0\,
DI(2) => \L1_carry__0_i_2_n_0\,
DI(1) => \L1_carry__0_i_3_n_0\,
DI(0) => \L1_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_L1_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__0_i_5_n_0\,
S(2) => \L1_carry__0_i_6_n_0\,
S(1) => \L1_carry__0_i_7_n_0\,
S(0) => \L1_carry__0_i_8_n_0\
);
\L1_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_1_n_0\
);
\L1_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_2_n_0\
);
\L1_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_3_n_0\
);
\L1_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_4_n_0\
);
\L1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_5_n_0\
);
\L1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_6_n_0\
);
\L1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_7_n_0\
);
\L1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_8_n_0\
);
\L1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \L1_carry__0_n_0\,
CO(3) => \L1_carry__1_n_0\,
CO(2) => \L1_carry__1_n_1\,
CO(1) => \L1_carry__1_n_2\,
CO(0) => \L1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \L1_carry__1_i_1_n_0\,
DI(2) => \L1_carry__1_i_2_n_0\,
DI(1) => \L1_carry__1_i_3_n_0\,
DI(0) => \L1_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_L1_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__1_i_5_n_0\,
S(2) => \L1_carry__1_i_6_n_0\,
S(1) => \L1_carry__1_i_7_n_0\,
S(0) => \L1_carry__1_i_8_n_0\
);
\L1_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_1_n_0\
);
\L1_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_2_n_0\
);
\L1_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_3_n_0\
);
\L1_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_4_n_0\
);
\L1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_5_n_0\
);
\L1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_6_n_0\
);
\L1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_7_n_0\
);
\L1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_8_n_0\
);
\L1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \L1_carry__1_n_0\,
CO(3) => L1,
CO(2) => \L1_carry__2_n_1\,
CO(1) => \L1_carry__2_n_2\,
CO(0) => \L1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \L1_carry__2_i_1_n_0\,
DI(1) => \L1_carry__2_i_2_n_0\,
DI(0) => \L1_carry__2_i_3_n_0\,
O(3 downto 0) => \NLW_L1_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__2_i_4_n_0\,
S(2) => \L1_carry__2_i_5_n_0\,
S(1) => \L1_carry__2_i_6_n_0\,
S(0) => \L1_carry__2_i_7_n_0\
);
\L1_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_1_n_0\
);
\L1_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_2_n_0\
);
\L1_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_3_n_0\
);
\L1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_4_n_0\
);
\L1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_5_n_0\
);
\L1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_6_n_0\
);
\L1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_7_n_0\
);
L1_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_1_n_0
);
L1_carry_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"4555FFFF45554555"
)
port map (
I0 => L1_carry_i_24_n_0,
I1 => L1_carry_i_25_n_0,
I2 => L1_carry_i_26_n_0,
I3 => L1_carry_i_27_n_0,
I4 => L1_carry_i_28_n_0,
I5 => L1_carry_i_29_n_0,
O => L1_carry_i_10_n_0
);
L1_carry_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF7550000"
)
port map (
I0 => L1_carry_i_30_n_0,
I1 => L1_carry_i_31_n_0,
I2 => L1_carry_i_32_n_0,
I3 => L1_carry_i_33_n_0,
I4 => L1_carry_i_34_n_0,
I5 => L1_carry_i_35_n_0,
O => L1_carry_i_11_n_0
);
L1_carry_i_12: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_22_n_0,
I2 => L1_carry_i_19_n_0,
O => L1_carry_i_12_n_0
);
L1_carry_i_13: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(41),
I2 => \msb1__1\(43),
I3 => \msb1__1\(42),
I4 => L1_carry_i_34_n_0,
I5 => L1_carry_i_23_n_0,
O => L1_carry_i_13_n_0
);
L1_carry_i_14: unisim.vcomponents.LUT5
generic map(
INIT => X"A9AA5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
O => L1_carry_i_14_n_0
);
L1_carry_i_15: unisim.vcomponents.LUT6
generic map(
INIT => X"0200AAAAFDFF5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_15_n_0
);
L1_carry_i_16: unisim.vcomponents.LUT3
generic map(
INIT => X"65"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
O => L1_carry_i_16_n_0
);
L1_carry_i_17: unisim.vcomponents.LUT4
generic map(
INIT => X"10EF"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
O => L1_carry_i_17_n_0
);
L1_carry_i_18: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_34_n_0,
I1 => \msb1__1\(42),
I2 => \msb1__1\(43),
I3 => \msb1__1\(41),
I4 => \msb1__1\(40),
O => L1_carry_i_18_n_0
);
L1_carry_i_19: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_36_n_0,
I1 => \msb1__1\(26),
I2 => \msb1__1\(27),
I3 => \msb1__1\(25),
I4 => \msb1__1\(24),
O => L1_carry_i_19_n_0
);
L1_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => L1_carry_i_14_n_0,
I1 => L1_carry_i_15_n_0,
O => L1_carry_i_2_n_0
);
L1_carry_i_20: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(10),
I1 => \msb1__1\(11),
I2 => \msb1__1\(9),
I3 => \msb1__1\(8),
O => L1_carry_i_20_n_0
);
L1_carry_i_21: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(14),
I1 => \msb1__1\(15),
I2 => \msb1__1\(13),
I3 => \msb1__1\(12),
O => L1_carry_i_21_n_0
);
L1_carry_i_22: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_37_n_0,
I1 => \msb1__1\(16),
I2 => \msb1__1\(17),
I3 => \msb1__1\(19),
I4 => \msb1__1\(18),
O => L1_carry_i_22_n_0
);
L1_carry_i_23: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_33_n_0,
I1 => \msb1__1\(32),
I2 => \msb1__1\(33),
I3 => \msb1__1\(35),
I4 => \msb1__1\(34),
O => L1_carry_i_23_n_0
);
L1_carry_i_24: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000EFFFF"
)
port map (
I0 => \msb1__1\(39),
I1 => \msb1__1\(38),
I2 => \msb1__1\(41),
I3 => \msb1__1\(40),
I4 => L1_carry_i_29_n_0,
I5 => L1_carry_i_38_n_0,
O => L1_carry_i_24_n_0
);
L1_carry_i_25: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000F100"
)
port map (
I0 => L1_carry_i_39_n_0,
I1 => L1_carry_i_40_n_0,
I2 => L1_carry_i_41_n_0,
I3 => L1_carry_i_42_n_0,
I4 => \msb1__1\(35),
I5 => \msb1__1\(34),
O => L1_carry_i_25_n_0
);
L1_carry_i_26: unisim.vcomponents.LUT6
generic map(
INIT => X"1111110011111101"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(36),
I2 => \msb1__1\(33),
I3 => \msb1__1\(34),
I4 => \msb1__1\(35),
I5 => \msb1__1\(32),
O => L1_carry_i_26_n_0
);
L1_carry_i_27: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(41),
I1 => \msb1__1\(40),
O => L1_carry_i_27_n_0
);
L1_carry_i_28: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111011111111"
)
port map (
I0 => \msb1__1\(45),
I1 => \msb1__1\(44),
I2 => L1_carry_i_43_n_0,
I3 => L1_carry_i_44_n_0,
I4 => L1_carry_i_39_n_0,
I5 => L1_carry_i_45_n_0,
O => L1_carry_i_28_n_0
);
L1_carry_i_29: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(46),
I1 => \msb1__1\(47),
O => L1_carry_i_29_n_0
);
L1_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => L1_carry_i_16_n_0,
I1 => L1_carry_i_17_n_0,
O => L1_carry_i_3_n_0
);
L1_carry_i_30: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(41),
I2 => \msb1__1\(43),
I3 => \msb1__1\(42),
O => L1_carry_i_30_n_0
);
L1_carry_i_31: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(34),
I1 => \msb1__1\(35),
I2 => \msb1__1\(33),
I3 => \msb1__1\(32),
O => L1_carry_i_31_n_0
);
L1_carry_i_32: unisim.vcomponents.LUT6
generic map(
INIT => X"8A888A888A88AA88"
)
port map (
I0 => L1_carry_i_36_n_0,
I1 => L1_carry_i_46_n_0,
I2 => L1_carry_i_47_n_0,
I3 => L1_carry_i_37_n_0,
I4 => L1_carry_i_20_n_0,
I5 => L1_carry_i_21_n_0,
O => L1_carry_i_32_n_0
);
L1_carry_i_33: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(36),
I2 => \msb1__1\(38),
I3 => \msb1__1\(39),
O => L1_carry_i_33_n_0
);
L1_carry_i_34: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(47),
I1 => \msb1__1\(46),
I2 => \msb1__1\(45),
I3 => \msb1__1\(44),
O => L1_carry_i_34_n_0
);
L1_carry_i_35: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => L1_carry_i_48_n_0,
I1 => L1_carry_i_49_n_0,
I2 => L1_carry_i_34_n_0,
I3 => L1_carry_i_36_n_0,
I4 => L1_carry_i_21_n_0,
I5 => L1_carry_i_37_n_0,
O => L1_carry_i_35_n_0
);
L1_carry_i_36: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(28),
I1 => \msb1__1\(29),
I2 => \msb1__1\(30),
I3 => \msb1__1\(31),
O => L1_carry_i_36_n_0
);
L1_carry_i_37: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(23),
I1 => \msb1__1\(22),
I2 => \msb1__1\(20),
I3 => \msb1__1\(21),
O => L1_carry_i_37_n_0
);
L1_carry_i_38: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(42),
I1 => \msb1__1\(43),
O => L1_carry_i_38_n_0
);
L1_carry_i_39: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(23),
I1 => \msb1__1\(22),
I2 => \msb1__1\(18),
I3 => \msb1__1\(19),
O => L1_carry_i_39_n_0
);
L1_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"D"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => L1_carry_i_4_n_0
);
L1_carry_i_40: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFF2"
)
port map (
I0 => L1_carry_i_50_n_0,
I1 => L1_carry_i_51_n_0,
I2 => \msb1__1\(15),
I3 => \msb1__1\(14),
I4 => \msb1__1\(17),
I5 => \msb1__1\(16),
O => L1_carry_i_40_n_0
);
L1_carry_i_41: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFE0FF"
)
port map (
I0 => \msb1__1\(21),
I1 => \msb1__1\(20),
I2 => L1_carry_i_52_n_0,
I3 => L1_carry_i_53_n_0,
I4 => \msb1__1\(25),
I5 => \msb1__1\(24),
O => L1_carry_i_41_n_0
);
L1_carry_i_42: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111110001"
)
port map (
I0 => \msb1__1\(30),
I1 => \msb1__1\(31),
I2 => \msb1__1\(26),
I3 => \msb1__1\(27),
I4 => \msb1__1\(29),
I5 => \msb1__1\(28),
O => L1_carry_i_42_n_0
);
L1_carry_i_43: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \msb1__1\(2),
I1 => \msb1__1\(3),
I2 => \msb1__1\(26),
I3 => \msb1__1\(27),
I4 => L1_carry_i_54_n_0,
I5 => L1_carry_i_38_n_0,
O => L1_carry_i_43_n_0
);
L1_carry_i_44: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(10),
I3 => \msb1__1\(11),
O => L1_carry_i_44_n_0
);
L1_carry_i_45: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \msb1__1\(34),
I1 => \msb1__1\(35),
I2 => \msb1__1\(15),
I3 => \msb1__1\(14),
I4 => \msb1__1\(31),
I5 => \msb1__1\(30),
O => L1_carry_i_45_n_0
);
L1_carry_i_46: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(24),
I1 => \msb1__1\(25),
I2 => \msb1__1\(27),
I3 => \msb1__1\(26),
O => L1_carry_i_46_n_0
);
L1_carry_i_47: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(18),
I1 => \msb1__1\(19),
I2 => \msb1__1\(17),
I3 => \msb1__1\(16),
O => L1_carry_i_47_n_0
);
L1_carry_i_48: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(39),
I3 => \msb1__1\(38),
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => L1_carry_i_48_n_0
);
L1_carry_i_49: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(5),
I1 => \msb1__1\(4),
O => L1_carry_i_49_n_0
);
L1_carry_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_5_n_0
);
L1_carry_i_50: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF1"
)
port map (
I0 => \msb1__1\(4),
I1 => \msb1__1\(5),
I2 => \msb1__1\(11),
I3 => \msb1__1\(10),
I4 => \msb1__1\(6),
I5 => \msb1__1\(7),
O => L1_carry_i_50_n_0
);
L1_carry_i_51: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFFFE"
)
port map (
I0 => \msb1__1\(13),
I1 => \msb1__1\(12),
I2 => \msb1__1\(8),
I3 => \msb1__1\(9),
I4 => \msb1__1\(11),
I5 => \msb1__1\(10),
O => L1_carry_i_51_n_0
);
L1_carry_i_52: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(22),
I1 => \msb1__1\(23),
O => L1_carry_i_52_n_0
);
L1_carry_i_53: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(29),
I1 => \msb1__1\(28),
O => L1_carry_i_53_n_0
);
L1_carry_i_54: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(39),
I1 => \msb1__1\(38),
O => L1_carry_i_54_n_0
);
L1_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => L1_carry_i_15_n_0,
I1 => L1_carry_i_14_n_0,
O => L1_carry_i_6_n_0
);
L1_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => L1_carry_i_17_n_0,
I1 => L1_carry_i_16_n_0,
O => L1_carry_i_7_n_0
);
L1_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => L1_carry_i_8_n_0
);
L1_carry_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"00808888AAAAAAAA"
)
port map (
I0 => L1_carry_i_18_n_0,
I1 => L1_carry_i_19_n_0,
I2 => L1_carry_i_20_n_0,
I3 => L1_carry_i_21_n_0,
I4 => L1_carry_i_22_n_0,
I5 => L1_carry_i_23_n_0,
O => L1_carry_i_9_n_0
);
\_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \_carry_n_0\,
CO(2) => \_carry_n_1\,
CO(1) => \_carry_n_2\,
CO(0) => \_carry_n_3\,
CYINIT => \_carry_i_1_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \_carry_n_4\,
O(2) => \_carry_n_5\,
O(1) => \_carry_n_6\,
O(0) => \_carry_n_7\,
S(3) => \_carry_i_2_n_0\,
S(2) => \_carry_i_3_n_0\,
S(1) => \_carry_i_4_n_0\,
S(0) => p_0_in(1)
);
\_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \_carry_n_0\,
CO(3) => \_carry__0_n_0\,
CO(2) => \_carry__0_n_1\,
CO(1) => \_carry__0_n_2\,
CO(0) => \_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__0_n_4\,
O(2) => \_carry__0_n_5\,
O(1) => \_carry__0_n_6\,
O(0) => \_carry__0_n_7\,
S(3) => \_carry__0_i_1_n_0\,
S(2) => \_carry__0_i_2_n_0\,
S(1) => \_carry__0_i_3_n_0\,
S(0) => \_carry__0_i_4_n_0\
);
\_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_1_n_0\
);
\_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_2_n_0\
);
\_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_3_n_0\
);
\_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200AAAAFDFF5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_4_n_0\
);
\_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__0_n_0\,
CO(3) => \_carry__1_n_0\,
CO(2) => \_carry__1_n_1\,
CO(1) => \_carry__1_n_2\,
CO(0) => \_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__1_n_4\,
O(2) => \_carry__1_n_5\,
O(1) => \_carry__1_n_6\,
O(0) => \_carry__1_n_7\,
S(3) => \_carry__1_i_1_n_0\,
S(2) => \_carry__1_i_2_n_0\,
S(1) => \_carry__1_i_3_n_0\,
S(0) => \_carry__1_i_4_n_0\
);
\_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_1_n_0\
);
\_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_2_n_0\
);
\_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_3_n_0\
);
\_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_4_n_0\
);
\_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__1_n_0\,
CO(3) => \_carry__2_n_0\,
CO(2) => \_carry__2_n_1\,
CO(1) => \_carry__2_n_2\,
CO(0) => \_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__2_n_4\,
O(2) => \_carry__2_n_5\,
O(1) => \_carry__2_n_6\,
O(0) => \_carry__2_n_7\,
S(3) => \_carry__2_i_1_n_0\,
S(2) => \_carry__2_i_2_n_0\,
S(1) => \_carry__2_i_3_n_0\,
S(0) => \_carry__2_i_4_n_0\
);
\_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_1_n_0\
);
\_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_2_n_0\
);
\_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_3_n_0\
);
\_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_4_n_0\
);
\_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__2_n_0\,
CO(3) => \_carry__3_n_0\,
CO(2) => \_carry__3_n_1\,
CO(1) => \_carry__3_n_2\,
CO(0) => \_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__3_n_4\,
O(2) => \_carry__3_n_5\,
O(1) => \_carry__3_n_6\,
O(0) => \_carry__3_n_7\,
S(3) => \_carry__3_i_1_n_0\,
S(2) => \_carry__3_i_2_n_0\,
S(1) => \_carry__3_i_3_n_0\,
S(0) => \_carry__3_i_4_n_0\
);
\_carry__3_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_1_n_0\
);
\_carry__3_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_2_n_0\
);
\_carry__3_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_3_n_0\
);
\_carry__3_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_4_n_0\
);
\_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__3_n_0\,
CO(3) => \_carry__4_n_0\,
CO(2) => \_carry__4_n_1\,
CO(1) => \_carry__4_n_2\,
CO(0) => \_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__4_n_4\,
O(2) => \_carry__4_n_5\,
O(1) => \_carry__4_n_6\,
O(0) => \_carry__4_n_7\,
S(3) => \_carry__4_i_1_n_0\,
S(2) => \_carry__4_i_2_n_0\,
S(1) => \_carry__4_i_3_n_0\,
S(0) => \_carry__4_i_4_n_0\
);
\_carry__4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_1_n_0\
);
\_carry__4_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_2_n_0\
);
\_carry__4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_3_n_0\
);
\_carry__4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_4_n_0\
);
\_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__4_n_0\,
CO(3) => \_carry__5_n_0\,
CO(2) => \_carry__5_n_1\,
CO(1) => \_carry__5_n_2\,
CO(0) => \_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__5_n_4\,
O(2) => \_carry__5_n_5\,
O(1) => \_carry__5_n_6\,
O(0) => \_carry__5_n_7\,
S(3) => \_carry__5_i_1_n_0\,
S(2) => \_carry__5_i_2_n_0\,
S(1) => \_carry__5_i_3_n_0\,
S(0) => \_carry__5_i_4_n_0\
);
\_carry__5_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_1_n_0\
);
\_carry__5_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_2_n_0\
);
\_carry__5_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_3_n_0\
);
\_carry__5_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_4_n_0\
);
\_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__5_n_0\,
CO(3 downto 1) => \NLW__carry__6_CO_UNCONNECTED\(3 downto 1),
CO(0) => \_carry__6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW__carry__6_O_UNCONNECTED\(3 downto 2),
O(1) => \_carry__6_n_6\,
O(0) => \_carry__6_n_7\,
S(3 downto 2) => B"00",
S(1) => \_carry__6_i_1_n_0\,
S(0) => \_carry__6_i_2_n_0\
);
\_carry__6_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__6_i_1_n_0\
);
\_carry__6_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__6_i_2_n_0\
);
\_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBBABAA"
)
port map (
I0 => \msb1__1\(47),
I1 => \_carry_i_6_n_0\,
I2 => \_carry_i_7_n_0\,
I3 => \_carry_i_8_n_0\,
I4 => \_carry_i_9_n_0\,
O => \_carry_i_1_n_0\
);
\_carry_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => \_carry_i_10_n_0\
);
\_carry_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(42),
I1 => \msb1__1\(40),
O => \_carry_i_11_n_0\
);
\_carry_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(25),
I1 => \msb1__1\(24),
I2 => \msb1__1\(28),
I3 => \_carry_i_18_n_0\,
I4 => \msb1__1\(26),
I5 => \msb1__1\(27),
O => \_carry_i_12_n_0\
);
\_carry_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(15),
I1 => \msb1__1\(14),
I2 => \msb1__1\(18),
I3 => \_carry_i_19_n_0\,
I4 => \msb1__1\(16),
I5 => \msb1__1\(17),
O => \_carry_i_13_n_0\
);
\_carry_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EFEE"
)
port map (
I0 => \_carry_i_20_n_0\,
I1 => \msb1__1\(7),
I2 => \msb1__1\(6),
I3 => \msb1__1\(5),
I4 => \_carry_i_21_n_0\,
O => \_carry_i_14_n_0\
);
\_carry_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF00BA"
)
port map (
I0 => \msb1__1\(11),
I1 => \msb1__1\(10),
I2 => \msb1__1\(9),
I3 => \msb1__1\(12),
I4 => \_carry_i_22_n_0\,
I5 => \msb1__1\(13),
O => \_carry_i_15_n_0\
);
\_carry_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(20),
I1 => \msb1__1\(19),
I2 => \msb1__1\(23),
I3 => \_carry_i_23_n_0\,
I4 => \msb1__1\(21),
I5 => \msb1__1\(22),
O => \_carry_i_16_n_0\
);
\_carry_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(30),
I1 => \msb1__1\(29),
I2 => \msb1__1\(33),
I3 => \_carry_i_24_n_0\,
I4 => \msb1__1\(31),
I5 => \msb1__1\(32),
O => \_carry_i_17_n_0\
);
\_carry_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(32),
I1 => \msb1__1\(30),
O => \_carry_i_18_n_0\
);
\_carry_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(22),
I1 => \msb1__1\(20),
O => \_carry_i_19_n_0\
);
\_carry_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"555DAAA2"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
O => \_carry_i_2_n_0\
);
\_carry_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"5504"
)
port map (
I0 => \msb1__1\(4),
I1 => \msb1__1\(1),
I2 => \msb1__1\(2),
I3 => \msb1__1\(3),
O => \_carry_i_20_n_0\
);
\_carry_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF4"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(12),
I3 => \msb1__1\(10),
I4 => \msb1__1\(8),
O => \_carry_i_21_n_0\
);
\_carry_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(17),
I1 => \msb1__1\(15),
O => \_carry_i_22_n_0\
);
\_carry_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(27),
I1 => \msb1__1\(25),
O => \_carry_i_23_n_0\
);
\_carry_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(35),
O => \_carry_i_24_n_0\
);
\_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"10EF"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
O => \_carry_i_3_n_0\
);
\_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => L1_carry_i_16_n_0,
O => \_carry_i_4_n_0\
);
\_carry_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \_carry_i_10_n_0\,
O => p_0_in(1)
);
\_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \msb1__1\(46),
I1 => \msb1__1\(45),
I2 => \msb1__1\(44),
O => \_carry_i_6_n_0\
);
\_carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(35),
I1 => \msb1__1\(34),
I2 => \msb1__1\(38),
I3 => \_carry_i_11_n_0\,
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => \_carry_i_7_n_0\
);
\_carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55551110"
)
port map (
I0 => \_carry_i_12_n_0\,
I1 => \_carry_i_13_n_0\,
I2 => \_carry_i_14_n_0\,
I3 => \_carry_i_15_n_0\,
I4 => \_carry_i_16_n_0\,
I5 => \_carry_i_17_n_0\,
O => \_carry_i_8_n_0\
);
\_carry_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF00F4"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(39),
I2 => \msb1__1\(41),
I3 => \msb1__1\(42),
I4 => \msb1__1\(45),
I5 => \msb1__1\(43),
O => \_carry_i_9_n_0\
);
msb1: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 23) => B"0000001",
A(22 downto 0) => y(22 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_msb1_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => '0',
B(16 downto 0) => x(16 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_msb1_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_msb1_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_msb1_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_msb1_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_msb1_OVERFLOW_UNCONNECTED,
P(47) => msb1_n_58,
P(46) => msb1_n_59,
P(45) => msb1_n_60,
P(44) => msb1_n_61,
P(43) => msb1_n_62,
P(42) => msb1_n_63,
P(41) => msb1_n_64,
P(40) => msb1_n_65,
P(39) => msb1_n_66,
P(38) => msb1_n_67,
P(37) => msb1_n_68,
P(36) => msb1_n_69,
P(35) => msb1_n_70,
P(34) => msb1_n_71,
P(33) => msb1_n_72,
P(32) => msb1_n_73,
P(31) => msb1_n_74,
P(30) => msb1_n_75,
P(29) => msb1_n_76,
P(28) => msb1_n_77,
P(27) => msb1_n_78,
P(26) => msb1_n_79,
P(25) => msb1_n_80,
P(24) => msb1_n_81,
P(23) => msb1_n_82,
P(22) => msb1_n_83,
P(21) => msb1_n_84,
P(20) => msb1_n_85,
P(19) => msb1_n_86,
P(18) => msb1_n_87,
P(17) => msb1_n_88,
P(16 downto 0) => \msb1__1\(16 downto 0),
PATTERNBDETECT => NLW_msb1_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_msb1_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => msb1_n_106,
PCOUT(46) => msb1_n_107,
PCOUT(45) => msb1_n_108,
PCOUT(44) => msb1_n_109,
PCOUT(43) => msb1_n_110,
PCOUT(42) => msb1_n_111,
PCOUT(41) => msb1_n_112,
PCOUT(40) => msb1_n_113,
PCOUT(39) => msb1_n_114,
PCOUT(38) => msb1_n_115,
PCOUT(37) => msb1_n_116,
PCOUT(36) => msb1_n_117,
PCOUT(35) => msb1_n_118,
PCOUT(34) => msb1_n_119,
PCOUT(33) => msb1_n_120,
PCOUT(32) => msb1_n_121,
PCOUT(31) => msb1_n_122,
PCOUT(30) => msb1_n_123,
PCOUT(29) => msb1_n_124,
PCOUT(28) => msb1_n_125,
PCOUT(27) => msb1_n_126,
PCOUT(26) => msb1_n_127,
PCOUT(25) => msb1_n_128,
PCOUT(24) => msb1_n_129,
PCOUT(23) => msb1_n_130,
PCOUT(22) => msb1_n_131,
PCOUT(21) => msb1_n_132,
PCOUT(20) => msb1_n_133,
PCOUT(19) => msb1_n_134,
PCOUT(18) => msb1_n_135,
PCOUT(17) => msb1_n_136,
PCOUT(16) => msb1_n_137,
PCOUT(15) => msb1_n_138,
PCOUT(14) => msb1_n_139,
PCOUT(13) => msb1_n_140,
PCOUT(12) => msb1_n_141,
PCOUT(11) => msb1_n_142,
PCOUT(10) => msb1_n_143,
PCOUT(9) => msb1_n_144,
PCOUT(8) => msb1_n_145,
PCOUT(7) => msb1_n_146,
PCOUT(6) => msb1_n_147,
PCOUT(5) => msb1_n_148,
PCOUT(4) => msb1_n_149,
PCOUT(3) => msb1_n_150,
PCOUT(2) => msb1_n_151,
PCOUT(1) => msb1_n_152,
PCOUT(0) => msb1_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_msb1_UNDERFLOW_UNCONNECTED
);
\msb1__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 23) => B"0000001",
A(22 downto 0) => y(22 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_msb1__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 6) => B"000000000001",
B(5 downto 0) => x(22 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_msb1__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_msb1__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_msb1__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_msb1__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_msb1__0_OVERFLOW_UNCONNECTED\,
P(47 downto 31) => \NLW_msb1__0_P_UNCONNECTED\(47 downto 31),
P(30 downto 0) => \msb1__1\(47 downto 17),
PATTERNBDETECT => \NLW_msb1__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_msb1__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => msb1_n_106,
PCIN(46) => msb1_n_107,
PCIN(45) => msb1_n_108,
PCIN(44) => msb1_n_109,
PCIN(43) => msb1_n_110,
PCIN(42) => msb1_n_111,
PCIN(41) => msb1_n_112,
PCIN(40) => msb1_n_113,
PCIN(39) => msb1_n_114,
PCIN(38) => msb1_n_115,
PCIN(37) => msb1_n_116,
PCIN(36) => msb1_n_117,
PCIN(35) => msb1_n_118,
PCIN(34) => msb1_n_119,
PCIN(33) => msb1_n_120,
PCIN(32) => msb1_n_121,
PCIN(31) => msb1_n_122,
PCIN(30) => msb1_n_123,
PCIN(29) => msb1_n_124,
PCIN(28) => msb1_n_125,
PCIN(27) => msb1_n_126,
PCIN(26) => msb1_n_127,
PCIN(25) => msb1_n_128,
PCIN(24) => msb1_n_129,
PCIN(23) => msb1_n_130,
PCIN(22) => msb1_n_131,
PCIN(21) => msb1_n_132,
PCIN(20) => msb1_n_133,
PCIN(19) => msb1_n_134,
PCIN(18) => msb1_n_135,
PCIN(17) => msb1_n_136,
PCIN(16) => msb1_n_137,
PCIN(15) => msb1_n_138,
PCIN(14) => msb1_n_139,
PCIN(13) => msb1_n_140,
PCIN(12) => msb1_n_141,
PCIN(11) => msb1_n_142,
PCIN(10) => msb1_n_143,
PCIN(9) => msb1_n_144,
PCIN(8) => msb1_n_145,
PCIN(7) => msb1_n_146,
PCIN(6) => msb1_n_147,
PCIN(5) => msb1_n_148,
PCIN(4) => msb1_n_149,
PCIN(3) => msb1_n_150,
PCIN(2) => msb1_n_151,
PCIN(1) => msb1_n_152,
PCIN(0) => msb1_n_153,
PCOUT(47 downto 0) => \NLW_msb1__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_msb1__0_UNDERFLOW_UNCONNECTED\
);
\z[11]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[7]_INST_0_i_1_n_0\,
CO(3) => \z[11]_INST_0_i_1_n_0\,
CO(2) => \z[11]_INST_0_i_1_n_1\,
CO(1) => \z[11]_INST_0_i_1_n_2\,
CO(0) => \z[11]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(11 downto 8),
S(3) => sel0(11),
S(2) => \z[11]_INST_0_i_3_n_0\,
S(1 downto 0) => sel0(9 downto 8)
);
\z[11]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_11_n_0\,
O => sel0(11)
);
\z[11]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_50_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_47_n_0\,
I4 => \z[30]_INST_0_i_51_n_0\,
O => \z[11]_INST_0_i_3_n_0\
);
\z[11]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[11]_INST_0_i_6_n_0\,
O => sel0(9)
);
\z[11]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[11]_INST_0_i_7_n_0\,
O => sel0(8)
);
\z[11]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[11]_INST_0_i_8_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_50_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_52_n_0\,
O => \z[11]_INST_0_i_6_n_0\
);
\z[11]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[11]_INST_0_i_9_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[11]_INST_0_i_8_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_54_n_0\,
O => \z[11]_INST_0_i_7_n_0\
);
\z[11]_INST_0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_121_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_98_n_0\,
O => \z[11]_INST_0_i_8_n_0\
);
\z[11]_INST_0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_100_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_101_n_0\,
O => \z[11]_INST_0_i_9_n_0\
);
\z[15]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[11]_INST_0_i_1_n_0\,
CO(3) => \z[15]_INST_0_i_1_n_0\,
CO(2) => \z[15]_INST_0_i_1_n_1\,
CO(1) => \z[15]_INST_0_i_1_n_2\,
CO(0) => \z[15]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(15 downto 12),
S(3 downto 0) => sel0(15 downto 12)
);
\z[15]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_14_n_0\,
O => sel0(15)
);
\z[15]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_15_n_0\,
O => sel0(14)
);
\z[15]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[15]_INST_0_i_6_n_0\,
O => sel0(13)
);
\z[15]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[15]_INST_0_i_7_n_0\,
O => sel0(12)
);
\z[15]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[15]_INST_0_i_8_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_60_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_63_n_0\,
O => \z[15]_INST_0_i_6_n_0\
);
\z[15]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_48_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[15]_INST_0_i_8_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_65_n_0\,
O => \z[15]_INST_0_i_7_n_0\
);
\z[15]_INST_0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_142_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_120_n_0\,
O => \z[15]_INST_0_i_8_n_0\
);
\z[19]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[15]_INST_0_i_1_n_0\,
CO(3) => \z[19]_INST_0_i_1_n_0\,
CO(2) => \z[19]_INST_0_i_1_n_1\,
CO(1) => \z[19]_INST_0_i_1_n_2\,
CO(0) => \z[19]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(19 downto 16),
S(3 downto 0) => sel0(19 downto 16)
);
\z[19]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_17_n_0\,
O => sel0(19)
);
\z[19]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_18_n_0\,
O => sel0(18)
);
\z[19]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_19_n_0\,
O => sel0(17)
);
\z[19]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_20_n_0\,
O => sel0(16)
);
\z[22]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[19]_INST_0_i_1_n_0\,
CO(3 downto 2) => \NLW_z[22]_INST_0_i_1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \z[22]_INST_0_i_1_n_2\,
CO(0) => \z[22]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_z[22]_INST_0_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => z_mantissa(22 downto 20),
S(3) => '0',
S(2 downto 0) => sel0(22 downto 20)
);
\z[22]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F2F2FFF2"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_81_n_0\,
I2 => \z[30]_INST_0_i_76_n_0\,
I3 => L1,
I4 => \z[22]_INST_0_i_5_n_0\,
O => sel0(22)
);
\z[22]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_22_n_0\,
O => sel0(21)
);
\z[22]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F222F2FFFF22F2"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_82_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_67_n_0\,
I4 => L1,
I5 => \z[22]_INST_0_i_6_n_0\,
O => sel0(20)
);
\z[22]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_168_n_0\,
I1 => \z[30]_INST_0_i_154_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_159_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_158_n_0\,
O => \z[22]_INST_0_i_5_n_0\
);
\z[22]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_154_n_0\,
I1 => \z[30]_INST_0_i_155_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_158_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_152_n_0\,
O => \z[22]_INST_0_i_6_n_0\
);
\z[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(0),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(0),
I5 => \y_11__s_net_1\,
O => z(0)
);
\z[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(1),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(1),
I5 => \y_11__s_net_1\,
O => z(1)
);
\z[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(2),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(2),
I5 => \y_11__s_net_1\,
O => z(2)
);
\z[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(3),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(3),
I5 => \y_11__s_net_1\,
O => z(3)
);
\z[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(4),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(4),
I5 => \y_11__s_net_1\,
O => z(4)
);
\z[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(5),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(5),
I5 => \y_11__s_net_1\,
O => z(5)
);
\z[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(6),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(6),
I5 => \y_11__s_net_1\,
O => z(6)
);
\z[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(7),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(7),
I5 => \y_11__s_net_1\,
O => z(7)
);
\z[30]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFFFFFFFFFFF"
)
port map (
I0 => \z[30]_INST_0_i_5_n_0\,
I1 => \z[30]_INST_0_i_6_n_0\,
I2 => sel0(3),
I3 => sel0(0),
I4 => \z[30]_INST_0_i_9_n_0\,
I5 => sel0(2),
O => \z[30]_INST_0_i_1_n_0\
);
\z[30]_INST_0_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_44_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_37_n_0\,
I4 => \z[30]_INST_0_i_46_n_0\,
O => sel0(2)
);
\z[30]_INST_0_i_100\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_181_n_0\,
I1 => \z[30]_INST_0_i_182_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_183_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_184_n_0\,
O => \z[30]_INST_0_i_100_n_0\
);
\z[30]_INST_0_i_101\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_185_n_0\,
I1 => \z[30]_INST_0_i_186_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_187_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_188_n_0\,
O => \z[30]_INST_0_i_101_n_0\
);
\z[30]_INST_0_i_102\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_189_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_171_n_0\,
O => \z[30]_INST_0_i_102_n_0\
);
\z[30]_INST_0_i_103\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF4FFF7"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(3),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_103_n_0\
);
\z[30]_INST_0_i_104\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_183_n_0\,
I1 => \z[30]_INST_0_i_184_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_190_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_181_n_0\,
O => \z[30]_INST_0_i_104_n_0\
);
\z[30]_INST_0_i_105\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_187_n_0\,
I1 => \z[30]_INST_0_i_188_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_191_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_185_n_0\,
O => \z[30]_INST_0_i_105_n_0\
);
\z[30]_INST_0_i_106\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_175_n_0\,
I1 => \z[30]_INST_0_i_176_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_192_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_173_n_0\,
O => \z[30]_INST_0_i_106_n_0\
);
\z[30]_INST_0_i_107\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEAEFFFF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \_carry_n_4\,
I2 => L1,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(3),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_107_n_0\
);
\z[30]_INST_0_i_108\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_179_n_0\,
I1 => \z[30]_INST_0_i_180_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_193_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_177_n_0\,
O => \z[30]_INST_0_i_108_n_0\
);
\z[30]_INST_0_i_109\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF4F7FFFF"
)
port map (
I0 => \msb1__1\(0),
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \msb1__1\(2),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_109_n_0\
);
\z[30]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_47_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_48_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_49_n_0\,
O => \z[30]_INST_0_i_11_n_0\
);
\z[30]_INST_0_i_110\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_190_n_0\,
I1 => \z[30]_INST_0_i_181_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_195_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_183_n_0\,
O => \z[30]_INST_0_i_110_n_0\
);
\z[30]_INST_0_i_111\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_191_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_185_n_0\,
O => \z[30]_INST_0_i_111_n_0\
);
\z[30]_INST_0_i_112\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_196_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_187_n_0\,
O => \z[30]_INST_0_i_112_n_0\
);
\z[30]_INST_0_i_113\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_192_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_173_n_0\,
O => \z[30]_INST_0_i_113_n_0\
);
\z[30]_INST_0_i_114\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_197_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_175_n_0\,
O => \z[30]_INST_0_i_114_n_0\
);
\z[30]_INST_0_i_115\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FFF3FAAFFFFFFFF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_198_n_0\,
I3 => L1,
I4 => \_carry_n_4\,
I5 => \msb1__1\(0),
O => \z[30]_INST_0_i_115_n_0\
);
\z[30]_INST_0_i_116\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \z[30]_INST_0_i_199_n_0\,
I1 => \_carry__0_n_6\,
I2 => \_carry__5_n_6\,
I3 => \_carry__0_n_5\,
I4 => \z[30]_INST_0_i_200_n_0\,
I5 => \z[30]_INST_0_i_201_n_0\,
O => \z[30]_INST_0_i_116_n_0\
);
\z[30]_INST_0_i_117\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(1),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_117_n_0\
);
\z[30]_INST_0_i_118\: unisim.vcomponents.LUT5
generic map(
INIT => X"3C33AAAA"
)
port map (
I0 => \_carry_n_6\,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1,
O => \z[30]_INST_0_i_118_n_0\
);
\z[30]_INST_0_i_119\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEAEFFFF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \_carry_n_4\,
I2 => L1,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(1),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_119_n_0\
);
\z[30]_INST_0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_50_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_47_n_0\,
I4 => \z[30]_INST_0_i_51_n_0\,
O => sel0(10)
);
\z[30]_INST_0_i_120\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_176_n_0\,
I1 => \z[30]_INST_0_i_202_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_173_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_174_n_0\,
O => \z[30]_INST_0_i_120_n_0\
);
\z[30]_INST_0_i_121\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_180_n_0\,
I1 => \z[30]_INST_0_i_203_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_177_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_178_n_0\,
O => \z[30]_INST_0_i_121_n_0\
);
\z[30]_INST_0_i_122\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_184_n_0\,
I1 => \z[30]_INST_0_i_204_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_181_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_182_n_0\,
O => \z[30]_INST_0_i_122_n_0\
);
\z[30]_INST_0_i_123\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_188_n_0\,
I1 => \z[30]_INST_0_i_205_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_185_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_186_n_0\,
O => \z[30]_INST_0_i_123_n_0\
);
\z[30]_INST_0_i_124\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_206_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_207_n_0\,
I3 => \z[30]_INST_0_i_95_n_0\,
I4 => \z[30]_INST_0_i_208_n_0\,
O => \z[30]_INST_0_i_124_n_0\
);
\z[30]_INST_0_i_125\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_209_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_132_n_0\,
I3 => \z[30]_INST_0_i_95_n_0\,
I4 => \z[30]_INST_0_i_210_n_0\,
O => \z[30]_INST_0_i_125_n_0\
);
\z[30]_INST_0_i_126\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_96_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_206_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_207_n_0\,
O => \z[30]_INST_0_i_126_n_0\
);
\z[30]_INST_0_i_127\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_172_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_209_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_132_n_0\,
O => \z[30]_INST_0_i_127_n_0\
);
\z[30]_INST_0_i_128\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA03030AFA03F3F"
)
port map (
I0 => \z[30]_INST_0_i_211_n_0\,
I1 => \z[30]_INST_0_i_212_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_213_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_202_n_0\,
O => \z[30]_INST_0_i_128_n_0\
);
\z[30]_INST_0_i_129\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => \z[30]_INST_0_i_178_n_0\,
I1 => \z[30]_INST_0_i_214_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_180_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_203_n_0\,
O => \z[30]_INST_0_i_129_n_0\
);
\z[30]_INST_0_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_52_n_0\,
I1 => \z[30]_INST_0_i_53_n_0\,
I2 => \z[30]_INST_0_i_54_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_55_n_0\,
O => \z[30]_INST_0_i_13_n_0\
);
\z[30]_INST_0_i_130\: unisim.vcomponents.LUT6
generic map(
INIT => X"505FC0C0505FCFCF"
)
port map (
I0 => \z[30]_INST_0_i_182_n_0\,
I1 => \z[30]_INST_0_i_215_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_184_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_204_n_0\,
O => \z[30]_INST_0_i_130_n_0\
);
\z[30]_INST_0_i_131\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0AF3030A0AF3F3F"
)
port map (
I0 => \z[30]_INST_0_i_216_n_0\,
I1 => \z[30]_INST_0_i_217_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_188_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_205_n_0\,
O => \z[30]_INST_0_i_131_n_0\
);
\z[30]_INST_0_i_132\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(0),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(8),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_132_n_0\
);
\z[30]_INST_0_i_133\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF444F4FFF777F7"
)
port map (
I0 => \msb1__1\(4),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \_carry_n_4\,
I3 => L1,
I4 => L1_carry_i_14_n_0,
I5 => \msb1__1\(12),
O => \z[30]_INST_0_i_133_n_0\
);
\z[30]_INST_0_i_134\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(2),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(10),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_134_n_0\
);
\z[30]_INST_0_i_135\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(6),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(14),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_135_n_0\
);
\z[30]_INST_0_i_136\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_207_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_146_n_0\,
O => \z[30]_INST_0_i_136_n_0\
);
\z[30]_INST_0_i_137\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_218_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_148_n_0\,
O => \z[30]_INST_0_i_137_n_0\
);
\z[30]_INST_0_i_138\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(36),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(20),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_217_n_0\,
O => \z[30]_INST_0_i_138_n_0\
);
\z[30]_INST_0_i_139\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BB8888B8B88888"
)
port map (
I0 => \z[30]_INST_0_i_188_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(40),
I3 => L1_carry_i_14_n_0,
I4 => L1_carry_i_15_n_0,
I5 => \msb1__1\(24),
O => \z[30]_INST_0_i_139_n_0\
);
\z[30]_INST_0_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_56_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_58_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_59_n_0\,
O => \z[30]_INST_0_i_14_n_0\
);
\z[30]_INST_0_i_140\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(37),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(21),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_212_n_0\,
O => \z[30]_INST_0_i_140_n_0\
);
\z[30]_INST_0_i_141\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(33),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(17),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_202_n_0\,
O => \z[30]_INST_0_i_141_n_0\
);
\z[30]_INST_0_i_142\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_178_n_0\,
I1 => \z[30]_INST_0_i_214_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_180_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_203_n_0\,
O => \z[30]_INST_0_i_142_n_0\
);
\z[30]_INST_0_i_143\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_208_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_207_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_146_n_0\,
O => \z[30]_INST_0_i_143_n_0\
);
\z[30]_INST_0_i_144\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_210_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_132_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_133_n_0\,
O => \z[30]_INST_0_i_144_n_0\
);
\z[30]_INST_0_i_145\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_186_n_0\,
I1 => \z[30]_INST_0_i_217_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_188_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_205_n_0\,
O => \z[30]_INST_0_i_145_n_0\
);
\z[30]_INST_0_i_146\: unisim.vcomponents.LUT6
generic map(
INIT => X"4747FF47FFFFFF47"
)
port map (
I0 => \msb1__1\(5),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(13),
I3 => \_carry_n_4\,
I4 => L1,
I5 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_146_n_0\
);
\z[30]_INST_0_i_147\: unisim.vcomponents.LUT6
generic map(
INIT => X"77CF44CC77CF77CF"
)
port map (
I0 => \msb1__1\(9),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(1),
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \z[30]_INST_0_i_170_n_0\,
I5 => \msb1__1\(17),
O => \z[30]_INST_0_i_147_n_0\
);
\z[30]_INST_0_i_148\: unisim.vcomponents.LUT6
generic map(
INIT => X"7757555777F7FFF7"
)
port map (
I0 => \z[30]_INST_0_i_194_n_0\,
I1 => \msb1__1\(15),
I2 => \_carry_n_5\,
I3 => L1,
I4 => L1_carry_i_17_n_0,
I5 => \msb1__1\(7),
O => \z[30]_INST_0_i_148_n_0\
);
\z[30]_INST_0_i_149\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FFFF47474747"
)
port map (
I0 => \msb1__1\(19),
I1 => \z[30]_INST_0_i_194_n_0\,
I2 => \msb1__1\(3),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(11),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_149_n_0\
);
\z[30]_INST_0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_60_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_61_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_62_n_0\,
O => \z[30]_INST_0_i_15_n_0\
);
\z[30]_INST_0_i_150\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_133_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_166_n_0\,
O => \z[30]_INST_0_i_150_n_0\
);
\z[30]_INST_0_i_151\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5DD0511"
)
port map (
I0 => \z[30]_INST_0_i_163_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_151_n_0\
);
\z[30]_INST_0_i_152\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_219_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_211_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_212_n_0\,
O => \z[30]_INST_0_i_152_n_0\
);
\z[30]_INST_0_i_153\: unisim.vcomponents.LUT6
generic map(
INIT => X"505FC0C0505FCFCF"
)
port map (
I0 => \z[30]_INST_0_i_203_n_0\,
I1 => \z[30]_INST_0_i_220_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_178_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_214_n_0\,
O => \z[30]_INST_0_i_153_n_0\
);
\z[30]_INST_0_i_154\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \z[30]_INST_0_i_221_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_182_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_215_n_0\,
O => \z[30]_INST_0_i_154_n_0\
);
\z[30]_INST_0_i_155\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_222_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_216_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_217_n_0\,
O => \z[30]_INST_0_i_155_n_0\
);
\z[30]_INST_0_i_156\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_146_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_147_n_0\,
O => \z[30]_INST_0_i_156_n_0\
);
\z[30]_INST_0_i_157\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_134_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_157_n_0\
);
\z[30]_INST_0_i_158\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \z[30]_INST_0_i_223_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_203_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_220_n_0\,
O => \z[30]_INST_0_i_158_n_0\
);
\z[30]_INST_0_i_159\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_224_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_219_n_0\,
O => \z[30]_INST_0_i_159_n_0\
);
\z[30]_INST_0_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_63_n_0\,
I1 => \z[30]_INST_0_i_64_n_0\,
I2 => \z[30]_INST_0_i_65_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_66_n_0\,
O => \z[30]_INST_0_i_16_n_0\
);
\z[30]_INST_0_i_160\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_225_n_0\,
I1 => \z[30]_INST_0_i_222_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_221_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_226_n_0\,
O => \z[30]_INST_0_i_160_n_0\
);
\z[30]_INST_0_i_161\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_166_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_227_n_0\,
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \z[30]_INST_0_i_228_n_0\,
O => \z[30]_INST_0_i_161_n_0\
);
\z[30]_INST_0_i_162\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \msb1__1\(14),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(6),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(22),
O => \z[30]_INST_0_i_162_n_0\
);
\z[30]_INST_0_i_163\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \msb1__1\(10),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(2),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(18),
O => \z[30]_INST_0_i_163_n_0\
);
\z[30]_INST_0_i_164\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_223_n_0\,
I1 => \z[30]_INST_0_i_229_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_219_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_230_n_0\,
O => \z[30]_INST_0_i_164_n_0\
);
\z[30]_INST_0_i_165\: unisim.vcomponents.LUT5
generic map(
INIT => X"47CC47FF"
)
port map (
I0 => \msb1__1\(13),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(21),
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \msb1__1\(5),
O => \z[30]_INST_0_i_165_n_0\
);
\z[30]_INST_0_i_166\: unisim.vcomponents.LUT6
generic map(
INIT => X"4447CCCF4447FFFF"
)
port map (
I0 => \msb1__1\(8),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \z[30]_INST_0_i_170_n_0\,
I3 => \msb1__1\(16),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \msb1__1\(0),
O => \z[30]_INST_0_i_166_n_0\
);
\z[30]_INST_0_i_167\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BFB0B0B0BFBFBF"
)
port map (
I0 => \z[30]_INST_0_i_170_n_0\,
I1 => \msb1__1\(12),
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \msb1__1\(20),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \msb1__1\(4),
O => \z[30]_INST_0_i_167_n_0\
);
\z[30]_INST_0_i_168\: unisim.vcomponents.LUT6
generic map(
INIT => X"7477FFFF74770000"
)
port map (
I0 => \z[30]_INST_0_i_217_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => L1_carry_i_14_n_0,
I3 => \z[30]_INST_0_i_231_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_222_n_0\,
O => \z[30]_INST_0_i_168_n_0\
);
\z[30]_INST_0_i_169\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6FFFFAAA60000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1,
I5 => \_carry_n_5\,
O => \z[30]_INST_0_i_169_n_0\
);
\z[30]_INST_0_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_67_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_68_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_69_n_0\,
O => \z[30]_INST_0_i_17_n_0\
);
\z[30]_INST_0_i_170\: unisim.vcomponents.LUT6
generic map(
INIT => X"9A55FFFF9A550000"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z[30]_INST_0_i_232_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_170_n_0\
);
\z[30]_INST_0_i_171\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7FFF7FFF70FF7F"
)
port map (
I0 => \z[30]_INST_0_i_194_n_0\,
I1 => \msb1__1\(0),
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \msb1__1\(4),
I5 => \z[30]_INST_0_i_170_n_0\,
O => \z[30]_INST_0_i_171_n_0\
);
\z[30]_INST_0_i_172\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FFF7FF"
)
port map (
I0 => \msb1__1\(2),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \msb1__1\(6),
O => \z[30]_INST_0_i_172_n_0\
);
\z[30]_INST_0_i_173\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(29),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(13),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(45),
O => \z[30]_INST_0_i_173_n_0\
);
\z[30]_INST_0_i_174\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(37),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(21),
O => \z[30]_INST_0_i_174_n_0\
);
\z[30]_INST_0_i_175\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(25),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(9),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(41),
O => \z[30]_INST_0_i_175_n_0\
);
\z[30]_INST_0_i_176\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(33),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(17),
O => \z[30]_INST_0_i_176_n_0\
);
\z[30]_INST_0_i_177\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(27),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(11),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(43),
O => \z[30]_INST_0_i_177_n_0\
);
\z[30]_INST_0_i_178\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(19),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(35),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_178_n_0\
);
\z[30]_INST_0_i_179\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(23),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(7),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(39),
O => \z[30]_INST_0_i_179_n_0\
);
\z[30]_INST_0_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_68_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_70_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_71_n_0\,
O => \z[30]_INST_0_i_18_n_0\
);
\z[30]_INST_0_i_180\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACACF000"
)
port map (
I0 => \msb1__1\(15),
I1 => \msb1__1\(47),
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(31),
I4 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_180_n_0\
);
\z[30]_INST_0_i_181\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(30),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(14),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(46),
O => \z[30]_INST_0_i_181_n_0\
);
\z[30]_INST_0_i_182\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(38),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_182_n_0\
);
\z[30]_INST_0_i_183\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(26),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(10),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(42),
O => \z[30]_INST_0_i_183_n_0\
);
\z[30]_INST_0_i_184\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(18),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(34),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_184_n_0\
);
\z[30]_INST_0_i_185\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(28),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(12),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(44),
O => \z[30]_INST_0_i_185_n_0\
);
\z[30]_INST_0_i_186\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(36),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(20),
O => \z[30]_INST_0_i_186_n_0\
);
\z[30]_INST_0_i_187\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(24),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(8),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(40),
O => \z[30]_INST_0_i_187_n_0\
);
\z[30]_INST_0_i_188\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(16),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(32),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_188_n_0\
);
\z[30]_INST_0_i_189\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFFBFFFBFBF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \msb1__1\(2),
I2 => \z[30]_INST_0_i_194_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => L1,
I5 => \_carry_n_5\,
O => \z[30]_INST_0_i_189_n_0\
);
\z[30]_INST_0_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_72_n_0\,
I2 => \z[30]_INST_0_i_43_n_0\,
I3 => \z[30]_INST_0_i_70_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_73_n_0\,
O => \z[30]_INST_0_i_19_n_0\
);
\z[30]_INST_0_i_190\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(6),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(38),
O => \z[30]_INST_0_i_190_n_0\
);
\z[30]_INST_0_i_191\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(20),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(4),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(36),
O => \z[30]_INST_0_i_191_n_0\
);
\z[30]_INST_0_i_192\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(21),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(5),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(37),
O => \z[30]_INST_0_i_192_n_0\
);
\z[30]_INST_0_i_193\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(19),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(3),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(35),
O => \z[30]_INST_0_i_193_n_0\
);
\z[30]_INST_0_i_194\: unisim.vcomponents.LUT6
generic map(
INIT => X"5DA200005DA2FFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => L1_carry_i_12_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_194_n_0\
);
\z[30]_INST_0_i_195\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(18),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(2),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(34),
O => \z[30]_INST_0_i_195_n_0\
);
\z[30]_INST_0_i_196\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(16),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(0),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(32),
O => \z[30]_INST_0_i_196_n_0\
);
\z[30]_INST_0_i_197\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(17),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(1),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(33),
O => \z[30]_INST_0_i_197_n_0\
);
\z[30]_INST_0_i_198\: unisim.vcomponents.LUT5
generic map(
INIT => X"555DAAA2"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_198_n_0\
);
\z[30]_INST_0_i_199\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__2_n_4\,
I1 => \_carry__3_n_4\,
I2 => \_carry__4_n_4\,
I3 => \_carry__5_n_5\,
I4 => \z[30]_INST_0_i_233_n_0\,
O => \z[30]_INST_0_i_199_n_0\
);
\z[30]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \z[30]_INST_0_i_11_n_0\,
I1 => sel0(10),
I2 => \z[30]_INST_0_i_13_n_0\,
I3 => \z[30]_INST_0_i_14_n_0\,
I4 => \z[30]_INST_0_i_15_n_0\,
I5 => \z[30]_INST_0_i_16_n_0\,
O => \z[30]_INST_0_i_2_n_0\
);
\z[30]_INST_0_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_72_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_59_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_74_n_0\,
O => \z[30]_INST_0_i_20_n_0\
);
\z[30]_INST_0_i_200\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__1_n_4\,
I1 => \_carry__6_n_6\,
I2 => \_carry__0_n_7\,
I3 => \_carry__4_n_5\,
I4 => \z[30]_INST_0_i_234_n_0\,
O => \z[30]_INST_0_i_200_n_0\
);
\z[30]_INST_0_i_201\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__2_n_5\,
I1 => \_carry__6_n_7\,
I2 => \_carry__0_n_4\,
I3 => \_carry__5_n_7\,
I4 => \z[30]_INST_0_i_235_n_0\,
O => \z[30]_INST_0_i_201_n_0\
);
\z[30]_INST_0_i_202\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(41),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(25),
O => \z[30]_INST_0_i_202_n_0\
);
\z[30]_INST_0_i_203\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(39),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(23),
O => \z[30]_INST_0_i_203_n_0\
);
\z[30]_INST_0_i_204\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(42),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(26),
O => \z[30]_INST_0_i_204_n_0\
);
\z[30]_INST_0_i_205\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(40),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(24),
O => \z[30]_INST_0_i_205_n_0\
);
\z[30]_INST_0_i_206\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(5),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_206_n_0\
);
\z[30]_INST_0_i_207\: unisim.vcomponents.LUT6
generic map(
INIT => X"4747FF47FFFFFF47"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(9),
I3 => \_carry_n_4\,
I4 => L1,
I5 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_207_n_0\
);
\z[30]_INST_0_i_208\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFCF44FFFFCF77"
)
port map (
I0 => \msb1__1\(7),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \msb1__1\(3),
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \z[30]_INST_0_i_170_n_0\,
I5 => \msb1__1\(11),
O => \z[30]_INST_0_i_208_n_0\
);
\z[30]_INST_0_i_209\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(4),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_209_n_0\
);
\z[30]_INST_0_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"101010FF10101010"
)
port map (
I0 => \z[30]_INST_0_i_75_n_0\,
I1 => \z[30]_INST_0_i_76_n_0\,
I2 => \z[30]_INST_0_i_77_n_0\,
I3 => \z[30]_INST_0_i_78_n_0\,
I4 => \z[30]_INST_0_i_79_n_0\,
I5 => \z[30]_INST_0_i_80_n_0\,
O => \z[30]_INST_0_i_21_n_0\
);
\z[30]_INST_0_i_210\: unisim.vcomponents.LUT6
generic map(
INIT => X"CF44CF77FFFFFFFF"
)
port map (
I0 => \msb1__1\(6),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \msb1__1\(2),
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \msb1__1\(10),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_210_n_0\
);
\z[30]_INST_0_i_211\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(21),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(37),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_211_n_0\
);
\z[30]_INST_0_i_212\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(45),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(29),
O => \z[30]_INST_0_i_212_n_0\
);
\z[30]_INST_0_i_213\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(17),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(33),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_213_n_0\
);
\z[30]_INST_0_i_214\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(43),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(27),
O => \z[30]_INST_0_i_214_n_0\
);
\z[30]_INST_0_i_215\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F5F"
)
port map (
I0 => \msb1__1\(46),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(30),
O => \z[30]_INST_0_i_215_n_0\
);
\z[30]_INST_0_i_216\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(20),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(36),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_216_n_0\
);
\z[30]_INST_0_i_217\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(44),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(28),
O => \z[30]_INST_0_i_217_n_0\
);
\z[30]_INST_0_i_218\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF444F4FFF777F7"
)
port map (
I0 => \msb1__1\(3),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \_carry_n_4\,
I3 => L1,
I4 => L1_carry_i_14_n_0,
I5 => \msb1__1\(11),
O => \z[30]_INST_0_i_218_n_0\
);
\z[30]_INST_0_i_219\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(25),
I1 => \msb1__1\(41),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(33),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_219_n_0\
);
\z[30]_INST_0_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_81_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_82_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_83_n_0\,
O => \z[30]_INST_0_i_22_n_0\
);
\z[30]_INST_0_i_220\: unisim.vcomponents.LUT4
generic map(
INIT => X"3777"
)
port map (
I0 => \msb1__1\(47),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(31),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_220_n_0\
);
\z[30]_INST_0_i_221\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(26),
I1 => \msb1__1\(42),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(34),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_221_n_0\
);
\z[30]_INST_0_i_222\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(24),
I1 => \msb1__1\(40),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(32),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_222_n_0\
);
\z[30]_INST_0_i_223\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(27),
I1 => \msb1__1\(43),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(35),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_223_n_0\
);
\z[30]_INST_0_i_224\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(29),
I1 => \msb1__1\(45),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(37),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_224_n_0\
);
\z[30]_INST_0_i_225\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(28),
I1 => \msb1__1\(44),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(36),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_225_n_0\
);
\z[30]_INST_0_i_226\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0E0E0E0EFEFEF"
)
port map (
I0 => \z[30]_INST_0_i_236_n_0\,
I1 => \z[30]_INST_0_i_237_n_0\,
I2 => L1_carry_i_17_n_0,
I3 => \msb1__1\(46),
I4 => L1_carry_i_15_n_0,
I5 => \z[30]_INST_0_i_238_n_0\,
O => \z[30]_INST_0_i_226_n_0\
);
\z[30]_INST_0_i_227\: unisim.vcomponents.LUT4
generic map(
INIT => X"E2FF"
)
port map (
I0 => \_carry_n_4\,
I1 => L1,
I2 => L1_carry_i_14_n_0,
I3 => \msb1__1\(12),
O => \z[30]_INST_0_i_227_n_0\
);
\z[30]_INST_0_i_228\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFBA808A"
)
port map (
I0 => \msb1__1\(20),
I1 => \z[30]_INST_0_i_198_n_0\,
I2 => L1,
I3 => \_carry_n_4\,
I4 => \msb1__1\(4),
O => \z[30]_INST_0_i_228_n_0\
);
\z[30]_INST_0_i_229\: unisim.vcomponents.LUT6
generic map(
INIT => X"10105050101F5F5F"
)
port map (
I0 => \z[30]_INST_0_i_239_n_0\,
I1 => \msb1__1\(39),
I2 => L1_carry_i_17_n_0,
I3 => \msb1__1\(47),
I4 => L1_carry_i_15_n_0,
I5 => \z[30]_INST_0_i_240_n_0\,
O => \z[30]_INST_0_i_229_n_0\
);
\z[30]_INST_0_i_230\: unisim.vcomponents.LUT6
generic map(
INIT => X"50503030505F3F3F"
)
port map (
I0 => \z[30]_INST_0_i_241_n_0\,
I1 => \z[30]_INST_0_i_242_n_0\,
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_243_n_0\,
I4 => \z[30]_INST_0_i_198_n_0\,
I5 => \z[30]_INST_0_i_244_n_0\,
O => \z[30]_INST_0_i_230_n_0\
);
\z[30]_INST_0_i_231\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => L1_carry_i_15_n_0,
I1 => \msb1__1\(36),
O => \z[30]_INST_0_i_231_n_0\
);
\z[30]_INST_0_i_232\: unisim.vcomponents.LUT6
generic map(
INIT => X"AEAEAEAEFFFFFFAE"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_29_n_0,
I2 => L1_carry_i_28_n_0,
I3 => \z[30]_INST_0_i_245_n_0\,
I4 => L1_carry_i_25_n_0,
I5 => L1_carry_i_24_n_0,
O => \z[30]_INST_0_i_232_n_0\
);
\z[30]_INST_0_i_233\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__2_n_6\,
I1 => \_carry__1_n_6\,
I2 => \_carry__3_n_6\,
I3 => \_carry__1_n_7\,
O => \z[30]_INST_0_i_233_n_0\
);
\z[30]_INST_0_i_234\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__2_n_7\,
I1 => L1,
I2 => \_carry__3_n_5\,
I3 => \_carry__1_n_5\,
O => \z[30]_INST_0_i_234_n_0\
);
\z[30]_INST_0_i_235\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__5_n_4\,
I1 => \_carry__3_n_7\,
I2 => \_carry__4_n_6\,
I3 => \_carry__4_n_7\,
O => \z[30]_INST_0_i_235_n_0\
);
\z[30]_INST_0_i_236\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3CC333341441111"
)
port map (
I0 => \msb1__1\(38),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_236_n_0\
);
\z[30]_INST_0_i_237\: unisim.vcomponents.LUT6
generic map(
INIT => X"343344441C11CCCC"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_237_n_0\
);
\z[30]_INST_0_i_238\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808880820200020"
)
port map (
I0 => \msb1__1\(30),
I1 => L1_carry_i_13_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \_carry_i_1_n_0\,
I4 => \z[30]_INST_0_i_232_n_0\,
I5 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_238_n_0\
);
\z[30]_INST_0_i_239\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808880820200020"
)
port map (
I0 => \msb1__1\(23),
I1 => L1_carry_i_13_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \_carry_i_1_n_0\,
I4 => \z[30]_INST_0_i_232_n_0\,
I5 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_239_n_0\
);
\z[30]_INST_0_i_240\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800888820220000"
)
port map (
I0 => \msb1__1\(31),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_240_n_0\
);
\z[30]_INST_0_i_241\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(21),
O => \z[30]_INST_0_i_241_n_0\
);
\z[30]_INST_0_i_242\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(37),
O => \z[30]_INST_0_i_242_n_0\
);
\z[30]_INST_0_i_243\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(29),
O => \z[30]_INST_0_i_243_n_0\
);
\z[30]_INST_0_i_244\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(45),
O => \z[30]_INST_0_i_244_n_0\
);
\z[30]_INST_0_i_245\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF5D5"
)
port map (
I0 => L1_carry_i_27_n_0,
I1 => \msb1__1\(32),
I2 => \z[30]_INST_0_i_246_n_0\,
I3 => \msb1__1\(33),
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => \z[30]_INST_0_i_245_n_0\
);
\z[30]_INST_0_i_246\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(35),
I1 => \msb1__1\(34),
O => \z[30]_INST_0_i_246_n_0\
);
\z[30]_INST_0_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"4700FFFF47004700"
)
port map (
I0 => \z[30]_INST_0_i_94_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_96_n_0\,
I3 => \z[30]_INST_0_i_43_n_0\,
I4 => \z[30]_INST_0_i_97_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_29_n_0\
);
\z[30]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \z[30]_INST_0_i_17_n_0\,
I1 => \z[30]_INST_0_i_18_n_0\,
I2 => \z[30]_INST_0_i_19_n_0\,
I3 => \z[30]_INST_0_i_20_n_0\,
I4 => \z[30]_INST_0_i_21_n_0\,
I5 => \z[30]_INST_0_i_22_n_0\,
O => \z[30]_INST_0_i_3_n_0\
);
\z[30]_INST_0_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_98_n_0\,
I1 => \z[30]_INST_0_i_99_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_100_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_101_n_0\,
O => \z[30]_INST_0_i_30_n_0\
);
\z[30]_INST_0_i_31\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_102_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_103_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_31_n_0\
);
\z[30]_INST_0_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_104_n_0\,
I1 => \z[30]_INST_0_i_105_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_99_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_106_n_0\,
O => \z[30]_INST_0_i_32_n_0\
);
\z[30]_INST_0_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"47FF474700FF0000"
)
port map (
I0 => \z[30]_INST_0_i_107_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_94_n_0\,
I3 => \z[30]_INST_0_i_97_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_33_n_0\
);
\z[30]_INST_0_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_101_n_0\,
I1 => \z[30]_INST_0_i_104_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_98_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_99_n_0\,
O => \z[30]_INST_0_i_34_n_0\
);
\z[30]_INST_0_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"4700FFFF47004700"
)
port map (
I0 => \z[30]_INST_0_i_107_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_94_n_0\,
I3 => \z[30]_INST_0_i_43_n_0\,
I4 => \z[30]_INST_0_i_102_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_35_n_0\
);
\z[30]_INST_0_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_99_n_0\,
I1 => \z[30]_INST_0_i_106_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_101_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_104_n_0\,
O => \z[30]_INST_0_i_36_n_0\
);
\z[30]_INST_0_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_106_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_108_n_0\,
O => \z[30]_INST_0_i_37_n_0\
);
\z[30]_INST_0_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_104_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_105_n_0\,
O => \z[30]_INST_0_i_38_n_0\
);
\z[30]_INST_0_i_39\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_103_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_109_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_39_n_0\
);
\z[30]_INST_0_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_110_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_111_n_0\,
I3 => L1_carry_i_16_n_0,
I4 => \z[30]_INST_0_i_112_n_0\,
O => \z[30]_INST_0_i_40_n_0\
);
\z[30]_INST_0_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_108_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_113_n_0\,
I3 => L1_carry_i_16_n_0,
I4 => \z[30]_INST_0_i_114_n_0\,
O => \z[30]_INST_0_i_41_n_0\
);
\z[30]_INST_0_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFD8"
)
port map (
I0 => L1,
I1 => L1_carry_i_16_n_0,
I2 => \_carry_n_6\,
I3 => \z[30]_INST_0_i_115_n_0\,
I4 => \z[30]_INST_0_i_95_n_0\,
O => \z[30]_INST_0_i_42_n_0\
);
\z[30]_INST_0_i_43\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => \z[30]_INST_0_i_116_n_0\,
O => \z[30]_INST_0_i_43_n_0\
);
\z[30]_INST_0_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_105_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_110_n_0\,
O => \z[30]_INST_0_i_44_n_0\
);
\z[30]_INST_0_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040F00000404"
)
port map (
I0 => \z[30]_INST_0_i_117_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_115_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_45_n_0\
);
\z[30]_INST_0_i_46\: unisim.vcomponents.LUT5
generic map(
INIT => X"10FF1010"
)
port map (
I0 => \z[30]_INST_0_i_95_n_0\,
I1 => \z[30]_INST_0_i_119_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_109_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
O => \z[30]_INST_0_i_46_n_0\
);
\z[30]_INST_0_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_120_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_121_n_0\,
O => \z[30]_INST_0_i_47_n_0\
);
\z[30]_INST_0_i_48\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_122_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_123_n_0\,
O => \z[30]_INST_0_i_48_n_0\
);
\z[30]_INST_0_i_49\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_124_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_125_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_49_n_0\
);
\z[30]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_29_n_0\,
I1 => \z[30]_INST_0_i_30_n_0\,
I2 => \z[30]_INST_0_i_31_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_32_n_0\,
O => \z[30]_INST_0_i_5_n_0\
);
\z[30]_INST_0_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_123_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_100_n_0\,
O => \z[30]_INST_0_i_50_n_0\
);
\z[30]_INST_0_i_51\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_125_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_126_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_51_n_0\
);
\z[30]_INST_0_i_52\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_126_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_127_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_52_n_0\
);
\z[30]_INST_0_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_121_n_0\,
I1 => \z[30]_INST_0_i_98_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_123_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_100_n_0\,
O => \z[30]_INST_0_i_53_n_0\
);
\z[30]_INST_0_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"47FF474700FF0000"
)
port map (
I0 => \z[30]_INST_0_i_94_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_96_n_0\,
I3 => \z[30]_INST_0_i_127_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_54_n_0\
);
\z[30]_INST_0_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_100_n_0\,
I1 => \z[30]_INST_0_i_101_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_121_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_98_n_0\,
O => \z[30]_INST_0_i_55_n_0\
);
\z[30]_INST_0_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_128_n_0\,
I1 => \z[30]_INST_0_i_129_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_130_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_131_n_0\,
O => \z[30]_INST_0_i_56_n_0\
);
\z[30]_INST_0_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => \z[30]_INST_0_i_116_n_0\,
O => \z[30]_INST_0_i_57_n_0\
);
\z[30]_INST_0_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_132_n_0\,
I1 => \z[30]_INST_0_i_133_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_134_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_58_n_0\
);
\z[30]_INST_0_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_136_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_137_n_0\,
O => \z[30]_INST_0_i_59_n_0\
);
\z[30]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_33_n_0\,
I1 => \z[30]_INST_0_i_34_n_0\,
I2 => \z[30]_INST_0_i_35_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_36_n_0\,
O => \z[30]_INST_0_i_6_n_0\
);
\z[30]_INST_0_i_60\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_138_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_139_n_0\,
I3 => \_carry_i_10_n_0\,
I4 => \z[30]_INST_0_i_122_n_0\,
O => \z[30]_INST_0_i_60_n_0\
);
\z[30]_INST_0_i_61\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_140_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_141_n_0\,
I3 => \_carry_i_10_n_0\,
I4 => \z[30]_INST_0_i_142_n_0\,
O => \z[30]_INST_0_i_61_n_0\
);
\z[30]_INST_0_i_62\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_58_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_143_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_62_n_0\
);
\z[30]_INST_0_i_63\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_143_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_144_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_63_n_0\
);
\z[30]_INST_0_i_64\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_142_n_0\,
I1 => \z[30]_INST_0_i_120_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_145_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_122_n_0\,
O => \z[30]_INST_0_i_64_n_0\
);
\z[30]_INST_0_i_65\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_144_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_124_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_65_n_0\
);
\z[30]_INST_0_i_66\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_122_n_0\,
I1 => \z[30]_INST_0_i_123_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_142_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_120_n_0\,
O => \z[30]_INST_0_i_66_n_0\
);
\z[30]_INST_0_i_67\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_146_n_0\,
I1 => \z[30]_INST_0_i_147_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_148_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_149_n_0\,
O => \z[30]_INST_0_i_67_n_0\
);
\z[30]_INST_0_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_150_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_151_n_0\,
O => \z[30]_INST_0_i_68_n_0\
);
\z[30]_INST_0_i_69\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_152_n_0\,
I1 => \z[30]_INST_0_i_153_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_154_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_155_n_0\,
O => \z[30]_INST_0_i_69_n_0\
);
\z[30]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_37_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_38_n_0\,
I4 => \z[30]_INST_0_i_39_n_0\,
O => sel0(3)
);
\z[30]_INST_0_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_137_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_156_n_0\,
O => \z[30]_INST_0_i_70_n_0\
);
\z[30]_INST_0_i_71\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_155_n_0\,
I1 => \z[30]_INST_0_i_130_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_152_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_153_n_0\,
O => \z[30]_INST_0_i_71_n_0\
);
\z[30]_INST_0_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_157_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_150_n_0\,
O => \z[30]_INST_0_i_72_n_0\
);
\z[30]_INST_0_i_73\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_153_n_0\,
I1 => \z[30]_INST_0_i_128_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_155_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_130_n_0\,
O => \z[30]_INST_0_i_73_n_0\
);
\z[30]_INST_0_i_74\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_130_n_0\,
I1 => \z[30]_INST_0_i_131_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_153_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_128_n_0\,
O => \z[30]_INST_0_i_74_n_0\
);
\z[30]_INST_0_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A2AAAA02A2"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_158_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_159_n_0\,
I4 => \_carry_i_1_n_0\,
I5 => \z[30]_INST_0_i_160_n_0\,
O => \z[30]_INST_0_i_75_n_0\
);
\z[30]_INST_0_i_76\: unisim.vcomponents.LUT6
generic map(
INIT => X"4C4C4C4040404C40"
)
port map (
I0 => \z[30]_INST_0_i_161_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_162_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_163_n_0\,
O => \z[30]_INST_0_i_76_n_0\
);
\z[30]_INST_0_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \z[30]_INST_0_i_81_n_0\,
I1 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_77_n_0\
);
\z[30]_INST_0_i_78\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_164_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_155_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_154_n_0\,
O => \z[30]_INST_0_i_78_n_0\
);
\z[30]_INST_0_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_67_n_0\,
O => \z[30]_INST_0_i_79_n_0\
);
\z[30]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A80FFFF8A808A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_40_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_41_n_0\,
I4 => \z[30]_INST_0_i_42_n_0\,
I5 => \z[30]_INST_0_i_43_n_0\,
O => sel0(0)
);
\z[30]_INST_0_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \z[30]_INST_0_i_82_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
O => \z[30]_INST_0_i_80_n_0\
);
\z[30]_INST_0_i_81\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_148_n_0\,
I1 => \z[30]_INST_0_i_149_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_147_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_165_n_0\,
O => \z[30]_INST_0_i_81_n_0\
);
\z[30]_INST_0_i_82\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC05F5FCFC05050"
)
port map (
I0 => \z[30]_INST_0_i_163_n_0\,
I1 => \z[30]_INST_0_i_135_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_166_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_167_n_0\,
O => \z[30]_INST_0_i_82_n_0\
);
\z[30]_INST_0_i_83\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_158_n_0\,
I1 => \z[30]_INST_0_i_152_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_168_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_154_n_0\,
O => \z[30]_INST_0_i_83_n_0\
);
\z[30]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_41_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_44_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_45_n_0\,
O => \z[30]_INST_0_i_9_n_0\
);
\z[30]_INST_0_i_94\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF4F7"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \msb1__1\(5),
I4 => \z[30]_INST_0_i_170_n_0\,
O => \z[30]_INST_0_i_94_n_0\
);
\z[30]_INST_0_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => \_carry_n_7\,
I1 => \_carry_i_10_n_0\,
I2 => L1,
O => \z[30]_INST_0_i_95_n_0\
);
\z[30]_INST_0_i_96\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF4F7"
)
port map (
I0 => \msb1__1\(3),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_170_n_0\,
I3 => \msb1__1\(7),
I4 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_96_n_0\
);
\z[30]_INST_0_i_97\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_171_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_172_n_0\,
O => \z[30]_INST_0_i_97_n_0\
);
\z[30]_INST_0_i_98\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_173_n_0\,
I1 => \z[30]_INST_0_i_174_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_175_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_176_n_0\,
O => \z[30]_INST_0_i_98_n_0\
);
\z[30]_INST_0_i_99\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_177_n_0\,
I1 => \z[30]_INST_0_i_178_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_179_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_180_n_0\,
O => \z[30]_INST_0_i_99_n_0\
);
\z[3]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \z[3]_INST_0_i_1_n_0\,
CO(2) => \z[3]_INST_0_i_1_n_1\,
CO(1) => \z[3]_INST_0_i_1_n_2\,
CO(0) => \z[3]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => sel0(0),
O(3 downto 0) => z_mantissa(3 downto 0),
S(3) => \z[3]_INST_0_i_2_n_0\,
S(2) => \z[3]_INST_0_i_3_n_0\,
S(1) => sel0(1),
S(0) => \z[3]_INST_0_i_5_n_0\
);
\z[3]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_37_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_38_n_0\,
I4 => \z[30]_INST_0_i_39_n_0\,
O => \z[3]_INST_0_i_2_n_0\
);
\z[3]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_44_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_37_n_0\,
I4 => \z[30]_INST_0_i_46_n_0\,
O => \z[3]_INST_0_i_3_n_0\
);
\z[3]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_9_n_0\,
O => sel0(1)
);
\z[3]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAA9AA"
)
port map (
I0 => sel0(0),
I1 => \z[30]_INST_0_i_3_n_0\,
I2 => \z[3]_INST_0_i_6_n_0\,
I3 => \z[3]_INST_0_i_7_n_0\,
I4 => \z[3]_INST_0_i_8_n_0\,
I5 => \z[3]_INST_0_i_9_n_0\,
O => \z[3]_INST_0_i_5_n_0\
);
\z[3]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => sel0(0),
I1 => sel0(2),
I2 => \z[7]_INST_0_i_8_n_0\,
I3 => \z[7]_INST_0_i_6_n_0\,
O => \z[3]_INST_0_i_6_n_0\
);
\z[3]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \z[7]_INST_0_i_9_n_0\,
I1 => sel0(10),
I2 => \z[30]_INST_0_i_11_n_0\,
I3 => \z[30]_INST_0_i_15_n_0\,
O => \z[3]_INST_0_i_7_n_0\
);
\z[3]_INST_0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \z[15]_INST_0_i_7_n_0\,
I1 => \z[15]_INST_0_i_6_n_0\,
I2 => sel0(3),
I3 => \z[7]_INST_0_i_7_n_0\,
O => \z[3]_INST_0_i_8_n_0\
);
\z[3]_INST_0_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \z[30]_INST_0_i_9_n_0\,
I1 => \z[11]_INST_0_i_6_n_0\,
I2 => \z[11]_INST_0_i_7_n_0\,
I3 => \z[30]_INST_0_i_14_n_0\,
O => \z[3]_INST_0_i_9_n_0\
);
\z[7]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[3]_INST_0_i_1_n_0\,
CO(3) => \z[7]_INST_0_i_1_n_0\,
CO(2) => \z[7]_INST_0_i_1_n_1\,
CO(1) => \z[7]_INST_0_i_1_n_2\,
CO(0) => \z[7]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(7 downto 4),
S(3 downto 0) => sel0(7 downto 4)
);
\z[7]_INST_0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_98_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_99_n_0\,
O => \z[7]_INST_0_i_10_n_0\
);
\z[7]_INST_0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_101_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_104_n_0\,
O => \z[7]_INST_0_i_11_n_0\
);
\z[7]_INST_0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_99_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_106_n_0\,
O => \z[7]_INST_0_i_12_n_0\
);
\z[7]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_6_n_0\,
O => sel0(7)
);
\z[7]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_7_n_0\,
O => sel0(6)
);
\z[7]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_8_n_0\,
O => sel0(5)
);
\z[7]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_9_n_0\,
O => sel0(4)
);
\z[7]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_10_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[11]_INST_0_i_9_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_29_n_0\,
O => \z[7]_INST_0_i_6_n_0\
);
\z[7]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_11_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_10_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_33_n_0\,
O => \z[7]_INST_0_i_7_n_0\
);
\z[7]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_12_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_11_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_35_n_0\,
O => \z[7]_INST_0_i_8_n_0\
);
\z[7]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_38_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_12_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_31_n_0\,
O => \z[7]_INST_0_i_9_n_0\
);
\z_exponent0__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \z_exponent0__0_carry_n_0\,
CO(2) => \z_exponent0__0_carry_n_1\,
CO(1) => \z_exponent0__0_carry_n_2\,
CO(0) => \z_exponent0__0_carry_n_3\,
CYINIT => '1',
DI(3) => \z_exponent0__0_carry_i_1_n_0\,
DI(2) => \z_exponent0__0_carry_i_2_n_0\,
DI(1) => \z_exponent0__0_carry_i_3_n_0\,
DI(0) => '1',
O(3 downto 0) => data0(3 downto 0),
S(3) => \z_exponent0__0_carry_i_4_n_0\,
S(2) => \z_exponent0__0_carry_i_5_n_0\,
S(1) => \z_exponent0__0_carry_i_6_n_0\,
S(0) => \z_exponent0__0_carry_i_7_n_0\
);
\z_exponent0__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \z_exponent0__0_carry_n_0\,
CO(3) => \NLW_z_exponent0__0_carry__0_CO_UNCONNECTED\(3),
CO(2) => \z_exponent0__0_carry__0_n_1\,
CO(1) => \z_exponent0__0_carry__0_n_2\,
CO(0) => \z_exponent0__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \z_exponent0__0_carry__0_i_1_n_0\,
DI(1) => \z_exponent0__0_carry__0_i_2_n_0\,
DI(0) => \z_exponent0__0_carry__0_i_3_n_0\,
O(3 downto 0) => data0(7 downto 4),
S(3) => \z_exponent0__0_carry__0_i_4_n_0\,
S(2) => \z_exponent0__0_carry__0_i_5_n_0\,
S(1) => \z_exponent0__0_carry__0_i_6_n_0\,
S(0) => \z_exponent0__0_carry__0_i_7_n_0\
);
\z_exponent0__0_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFA9A900"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => y(28),
I4 => x(28),
O => \z_exponent0__0_carry__0_i_1_n_0\
);
\z_exponent0__0_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => y(27),
I3 => x(27),
O => \z_exponent0__0_carry__0_i_2_n_0\
);
\z_exponent0__0_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF1E1E00"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => y(26),
I4 => x(26),
O => \z_exponent0__0_carry__0_i_3_n_0\
);
\z_exponent0__0_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999699969999996"
)
port map (
I0 => x(30),
I1 => y(30),
I2 => x(29),
I3 => y(29),
I4 => \msb1__1\(47),
I5 => \msb1__1\(46),
O => \z_exponent0__0_carry__0_i_4_n_0\
);
\z_exponent0__0_carry__0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96969669"
)
port map (
I0 => \z_exponent0__0_carry__0_i_1_n_0\,
I1 => y(29),
I2 => x(29),
I3 => \msb1__1\(46),
I4 => \msb1__1\(47),
O => \z_exponent0__0_carry__0_i_5_n_0\
);
\z_exponent0__0_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"56A9A956A95656A9"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => \z_exponent0__0_carry__0_i_2_n_0\,
I4 => y(28),
I5 => x(28),
O => \z_exponent0__0_carry__0_i_6_n_0\
);
\z_exponent0__0_carry__0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => \z_exponent0__0_carry__0_i_3_n_0\,
I3 => x(27),
I4 => y(27),
O => \z_exponent0__0_carry__0_i_7_n_0\
);
\z_exponent0__0_carry__0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => L1_carry_i_10_n_0,
I2 => L1_carry_i_11_n_0,
O => \z_exponent0__0_carry__0_i_8_n_0\
);
\z_exponent0__0_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F660"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => y(25),
I3 => x(25),
O => \z_exponent0__0_carry_i_1_n_0\
);
\z_exponent0__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => L1_carry_i_10_n_0,
O => \z_exponent0__0_carry_i_2_n_0\
);
\z_exponent0__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => \_carry_i_1_n_0\,
O => \z_exponent0__0_carry_i_3_n_0\
);
\z_exponent0__0_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E11E1EE11EE1E11E"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \z_exponent0__0_carry_i_1_n_0\,
I4 => y(26),
I5 => x(26),
O => \z_exponent0__0_carry_i_4_n_0\
);
\z_exponent0__0_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \z_exponent0__0_carry_i_2_n_0\,
I3 => y(25),
I4 => x(25),
O => \z_exponent0__0_carry_i_5_n_0\
);
\z_exponent0__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y(24),
I1 => L1_carry_i_10_n_0,
I2 => x(24),
I3 => \z_exponent0__0_carry_i_3_n_0\,
O => \z_exponent0__0_carry_i_6_n_0\
);
\z_exponent0__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => \_carry_i_1_n_0\,
O => \z_exponent0__0_carry_i_7_n_0\
);
z_exponent1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => z_exponent1_carry_n_0,
CO(2) => z_exponent1_carry_n_1,
CO(1) => z_exponent1_carry_n_2,
CO(0) => z_exponent1_carry_n_3,
CYINIT => '0',
DI(3) => \z_exponent0__0_carry_i_1_n_0\,
DI(2) => \z_exponent0__0_carry_i_2_n_0\,
DI(1) => \z_exponent1_carry_i_1__0_n_0\,
DI(0) => x(23),
O(3 downto 0) => data1(3 downto 0),
S(3) => \z_exponent1_carry_i_2__0_n_0\,
S(2) => \z_exponent1_carry_i_3__0_n_0\,
S(1) => z_exponent1_carry_i_4_n_0,
S(0) => z_exponent1_carry_i_5_n_0
);
\z_exponent1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => z_exponent1_carry_n_0,
CO(3) => \NLW_z_exponent1_carry__0_CO_UNCONNECTED\(3),
CO(2) => \z_exponent1_carry__0_n_1\,
CO(1) => \z_exponent1_carry__0_n_2\,
CO(0) => \z_exponent1_carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \z_exponent0__0_carry__0_i_1_n_0\,
DI(1) => \z_exponent0__0_carry__0_i_2_n_0\,
DI(0) => \z_exponent0__0_carry__0_i_3_n_0\,
O(3 downto 0) => data1(7 downto 4),
S(3) => z_exponent1_carry_i_1_n_0,
S(2) => z_exponent1_carry_i_2_n_0,
S(1) => z_exponent1_carry_i_3_n_0,
S(0) => \z_exponent1_carry_i_4__0_n_0\
);
z_exponent1_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"6999699969999996"
)
port map (
I0 => x(30),
I1 => y(30),
I2 => x(29),
I3 => y(29),
I4 => \msb1__1\(47),
I5 => \msb1__1\(46),
O => z_exponent1_carry_i_1_n_0
);
\z_exponent1_carry_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => y(23),
I1 => \_carry_i_1_n_0\,
O => \z_exponent1_carry_i_1__0_n_0\
);
z_exponent1_carry_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"96969669"
)
port map (
I0 => \z_exponent0__0_carry__0_i_1_n_0\,
I1 => y(29),
I2 => x(29),
I3 => \msb1__1\(46),
I4 => \msb1__1\(47),
O => z_exponent1_carry_i_2_n_0
);
\z_exponent1_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"E11E1EE11EE1E11E"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \z_exponent0__0_carry_i_1_n_0\,
I4 => y(26),
I5 => x(26),
O => \z_exponent1_carry_i_2__0_n_0\
);
z_exponent1_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"56A9A956A95656A9"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => \z_exponent0__0_carry__0_i_2_n_0\,
I4 => y(28),
I5 => x(28),
O => z_exponent1_carry_i_3_n_0
);
\z_exponent1_carry_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => y(25),
I3 => x(25),
I4 => \z_exponent0__0_carry_i_2_n_0\,
O => \z_exponent1_carry_i_3__0_n_0\
);
z_exponent1_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => L1_carry_i_10_n_0,
I3 => \z_exponent1_carry_i_1__0_n_0\,
O => z_exponent1_carry_i_4_n_0
);
\z_exponent1_carry_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => y(27),
I3 => x(27),
I4 => \z_exponent0__0_carry__0_i_3_n_0\,
O => \z_exponent1_carry_i_4__0_n_0\
);
z_exponent1_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => y(23),
I1 => \_carry_i_1_n_0\,
I2 => x(23),
O => z_exponent1_carry_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_multiplier_1_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_ieee754_fp_multiplier_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_ieee754_fp_multiplier_1_0 : entity is "affine_block_ieee754_fp_multiplier_1_0,ieee754_fp_multiplier,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_ieee754_fp_multiplier_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_ieee754_fp_multiplier_1_0 : entity is "ieee754_fp_multiplier,Vivado 2016.4";
end affine_block_ieee754_fp_multiplier_1_0;
architecture STRUCTURE of affine_block_ieee754_fp_multiplier_1_0 is
signal \z[30]_INST_0_i_23_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_24_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_25_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_26_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_27_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_28_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_84_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_85_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_86_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_87_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_88_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_89_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_90_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_91_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_92_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_93_n_0\ : STD_LOGIC;
signal z_mantissa : STD_LOGIC_VECTOR ( 22 downto 0 );
begin
U0: entity work.affine_block_ieee754_fp_multiplier_1_0_ieee754_fp_multiplier
port map (
x(30 downto 0) => x(30 downto 0),
y(30 downto 0) => y(30 downto 0),
\y_11__s_port_\ => \z[30]_INST_0_i_4_n_0\,
z(7 downto 0) => z(30 downto 23),
z_mantissa(22 downto 0) => z_mantissa(22 downto 0)
);
\z[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(0),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(0)
);
\z[10]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(10),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(10)
);
\z[11]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(11),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(11)
);
\z[12]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(12),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(12)
);
\z[13]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(13),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(13)
);
\z[14]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(14),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(14)
);
\z[15]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(15),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(15)
);
\z[16]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(16),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(16)
);
\z[17]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(17),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(17)
);
\z[18]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(18),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(18)
);
\z[19]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(19),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(19)
);
\z[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(1),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(1)
);
\z[20]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(20),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(20)
);
\z[21]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(21),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(21)
);
\z[22]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(22),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(22)
);
\z[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(2),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(2)
);
\z[30]_INST_0_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => x(29),
I1 => x(4),
I2 => x(11),
I3 => x(13),
I4 => \z[30]_INST_0_i_84_n_0\,
O => \z[30]_INST_0_i_23_n_0\
);
\z[30]_INST_0_i_24\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => x(25),
I1 => x(20),
I2 => x(15),
I3 => x(22),
I4 => \z[30]_INST_0_i_85_n_0\,
O => \z[30]_INST_0_i_24_n_0\
);
\z[30]_INST_0_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \z[30]_INST_0_i_86_n_0\,
I1 => \z[30]_INST_0_i_87_n_0\,
I2 => \z[30]_INST_0_i_88_n_0\,
I3 => x(24),
I4 => x(10),
I5 => x(2),
O => \z[30]_INST_0_i_25_n_0\
);
\z[30]_INST_0_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y(30),
I1 => y(5),
I2 => y(0),
I3 => y(1),
I4 => \z[30]_INST_0_i_89_n_0\,
O => \z[30]_INST_0_i_26_n_0\
);
\z[30]_INST_0_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y(29),
I1 => y(18),
I2 => y(2),
I3 => y(10),
I4 => \z[30]_INST_0_i_90_n_0\,
O => \z[30]_INST_0_i_27_n_0\
);
\z[30]_INST_0_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \z[30]_INST_0_i_91_n_0\,
I1 => \z[30]_INST_0_i_92_n_0\,
I2 => \z[30]_INST_0_i_93_n_0\,
I3 => y(12),
I4 => y(20),
I5 => y(4),
O => \z[30]_INST_0_i_28_n_0\
);
\z[30]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"101010FF10101010"
)
port map (
I0 => \z[30]_INST_0_i_23_n_0\,
I1 => \z[30]_INST_0_i_24_n_0\,
I2 => \z[30]_INST_0_i_25_n_0\,
I3 => \z[30]_INST_0_i_26_n_0\,
I4 => \z[30]_INST_0_i_27_n_0\,
I5 => \z[30]_INST_0_i_28_n_0\,
O => \z[30]_INST_0_i_4_n_0\
);
\z[30]_INST_0_i_84\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(9),
I1 => x(3),
I2 => x(17),
I3 => x(7),
O => \z[30]_INST_0_i_84_n_0\
);
\z[30]_INST_0_i_85\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(18),
I1 => x(30),
I2 => x(21),
I3 => x(6),
O => \z[30]_INST_0_i_85_n_0\
);
\z[30]_INST_0_i_86\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(14),
I1 => x(12),
I2 => x(8),
I3 => x(27),
O => \z[30]_INST_0_i_86_n_0\
);
\z[30]_INST_0_i_87\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => x(28),
I1 => x(23),
I2 => x(19),
I3 => x(1),
O => \z[30]_INST_0_i_87_n_0\
);
\z[30]_INST_0_i_88\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(0),
I1 => x(26),
I2 => x(16),
I3 => x(5),
O => \z[30]_INST_0_i_88_n_0\
);
\z[30]_INST_0_i_89\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(14),
I1 => y(8),
I2 => y(24),
I3 => y(27),
O => \z[30]_INST_0_i_89_n_0\
);
\z[30]_INST_0_i_90\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(7),
I1 => y(26),
I2 => y(17),
I3 => y(6),
O => \z[30]_INST_0_i_90_n_0\
);
\z[30]_INST_0_i_91\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(21),
I1 => y(15),
I2 => y(22),
I3 => y(23),
O => \z[30]_INST_0_i_91_n_0\
);
\z[30]_INST_0_i_92\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => y(19),
I1 => y(28),
I2 => y(9),
I3 => y(3),
O => \z[30]_INST_0_i_92_n_0\
);
\z[30]_INST_0_i_93\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(16),
I1 => y(25),
I2 => y(13),
I3 => y(11),
O => \z[30]_INST_0_i_93_n_0\
);
\z[31]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y(31),
I1 => x(31),
O => z(31)
);
\z[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(3),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(3)
);
\z[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(4),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(4)
);
\z[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(5),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(5)
);
\z[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(6),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(6)
);
\z[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(7),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(7)
);
\z[8]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(8),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(8)
);
\z[9]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(9),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(9)
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd | 4 | 15236 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_" &
"loaded,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C" &
"_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=" &
"0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=7,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 22.1485 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "7",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 22.1485 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_hessian/vga_hessian.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd | 4 | 15236 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_" &
"loaded,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C" &
"_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=" &
"0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=7,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 22.1485 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "7",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 22.1485 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_0_0/sim/system_rgb888_to_g8_0_0.vhd | 4 | 3255 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_g8:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_g8_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
g8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END system_rgb888_to_g8_0_0;
ARCHITECTURE system_rgb888_to_g8_0_0_arch OF system_rgb888_to_g8_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_g8_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_g8 IS
PORT (
clk : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
g8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT rgb888_to_g8;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb888_to_g8
PORT MAP (
clk => clk,
rgb888 => rgb888,
g8 => g8
);
END system_rgb888_to_g8_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_util_vector_logic_0_0/system_util_vector_logic_0_0_sim_netlist.vhdl | 1 | 2056 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:27:54 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_util_vector_logic_0_0/system_util_vector_logic_0_0_sim_netlist.vhdl
-- Design : system_util_vector_logic_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_util_vector_logic_0_0 is
port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_util_vector_logic_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_util_vector_logic_0_0 : entity is "system_util_vector_logic_0_0,util_vector_logic,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_util_vector_logic_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_util_vector_logic_0_0 : entity is "util_vector_logic,Vivado 2016.4";
end system_util_vector_logic_0_0;
architecture STRUCTURE of system_util_vector_logic_0_0 is
begin
\Res[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Op1(0),
I1 => Op2(0),
O => Res(0)
);
end STRUCTURE;
| mit |
Digilent/vivado-library | ip/Zmods/ZmodDigitizerController/tb/tb_TestAD96xx_92xxSPI_Model_all.vhd | 2 | 5777 |
-------------------------------------------------------------------------------
--
-- File: tb_TestAD96xx_92xxSPI_Model_all.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 May 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Test bench used to instantiate the tb_TestAD96xx_92xxSPI_Model as multiple
-- entities so that all supported errors are inserted in the SPI transactions
-- initiated. This test bench is used to test if the tb_TestAD96xx_92xxSPI_Model
-- correctly reports the deliberately inserted errors.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_TestAD96xx_92xxSPI_Model_all is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 0
);
end tb_TestAD96xx_92xxSPI_Model_all;
architecture Behavioral of tb_TestAD96xx_92xxSPI_Model_all is
begin
-- Test the ADI_2WireSPI_Model for a write operation and no
-- error inserted.
InstWrNoErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 0,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a read operation and no
-- error inserted.
InstRdNoErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 0,
kCmdRdWr => '1',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- sSDIO to sSPI_Clk Setup Time error inserted for the SPI transaction.
InstWrData2ClkSetupErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 1,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- CS to sSPI_Clk and a data to sSPI_Clk setup time error inserted
-- for the SPI transaction.
InstWrCs2ClkSetupErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 2,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- sSDIO to sSPI_Clk hold time error inserted for the SPI transaction.
InstWrData2ClkHoldErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 3,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- sCS to sSPI_Clk hold time error inserted for the SPI transaction.
InstWrCs2ClkHoldErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 4,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- pulse width errors and a SPI clock period error inserted
-- for the SPI transaction.
InstSclkPulsePeriodErr : entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 5,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with an
-- extra address bit error inserted for the SPI transaction.
InstNoBitErr : entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 6,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
end Behavioral;
| mit |
Digilent/vivado-library | ip/MIPI_CSI_2_RX/hdl/CRC16_behavioral.vhd | 1 | 3954 | -------------------------------------------------------------------------------
--
-- File: CRC16_behavioral.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
-- Additional Comments: Sub-optimal implementation of CRC-16, with untested
-- bByteIgnore.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CRC16 is
Generic (
kLaneCount : natural range 1 to 4 := 2
);
Port (
ByteClk : in STD_LOGIC;
bData : in STD_LOGIC_VECTOR (kLaneCount*8-1 downto 0);
bDataEnable : in std_logic;
bKeep : in STD_LOGIC_VECTOR (kLaneCount-1 downto 0);
bCRC : out STD_LOGIC_VECTOR (15 downto 0);
bRst : in STD_LOGIC);
end CRC16;
architecture Behavioral of CRC16 is
function crc16_serial ( crc : std_logic_vector;
data_in : std_logic) return std_logic_vector is
variable crc_new : std_logic_vector(15 downto 0);
begin
if ((crc(0) xor data_in) = '1') then
crc_new := ('0' & crc(15 downto 1)) xor x"8408";
else
crc_new := '0' & crc(15 downto 1);
end if;
return crc_new;
end crc16_serial;
signal crc : std_logic_vector(15 downto 0);
begin
process(ByteClk)
variable crc_temp : std_logic_vector(15 downto 0);
begin
if Rising_Edge(ByteClk) then
if (bRst = '1') then
crc <= x"FFFF";
elsif (bDataEnable = '1') then
crc_temp := crc;
if std_match(bKeep, "1111") then
for i in 0 to 32-0*8-1 loop
crc_temp := crc16_serial(crc_temp, bData(i));
end loop;
elsif std_match(bKeep, "0111") then
for i in 0 to 32-1*8-1 loop
crc_temp := crc16_serial(crc_temp, bData(i));
end loop;
elsif std_match(bKeep, "-011") then
for i in 0 to 32-2*8-1 loop
crc_temp := crc16_serial(crc_temp, bData(i));
end loop;
elsif std_match(bKeep, "--01") then
for i in 0 to 32-3*8-1 loop
crc_temp := crc16_serial(crc_temp, bData(i));
end loop;
end if;
crc <= crc_temp;
end if;
end if;
end process;
bCRC <= crc;
end Behavioral;
| mit |
Digilent/vivado-library | ip/video_scaler/hdl/vhdl/start_for_Mat2AXImb6.vhd | 1 | 4650 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Mat2AXImb6_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Mat2AXImb6_shiftReg;
architecture rtl of start_for_Mat2AXImb6_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity start_for_Mat2AXImb6 is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Mat2AXImb6 is
component start_for_Mat2AXImb6_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
if (mOutPtr = conv_std_logic_vector(0, 3)) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
internal_empty_n <= '1';
if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Mat2AXImb6_shiftReg : start_for_Mat2AXImb6_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| mit |
Digilent/vivado-library | ip/video_scaler/hdl/vhdl/fifo_w32_d3_A.vhd | 1 | 4597 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w32_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w32_d3_A_shiftReg;
architecture rtl of fifo_w32_d3_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fifo_w32_d3_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w32_d3_A is
component fifo_w32_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
if (mOutPtr = conv_std_logic_vector(0, 3)) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
internal_empty_n <= '1';
if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w32_d3_A_shiftReg : fifo_w32_d3_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| mit |
Digilent/vivado-library | ip/Zmods/ZmodScopeController/tb/tb_TestConfigADC.vhd | 1 | 7773 |
-------------------------------------------------------------------------------
--
-- File: tb_TestConfigADC.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench is used to illustrate the ConfigADC module behavior.
-- It does not represent an extensive test of the module. The external
-- indirect access SPI interface is not used. The AD96xx_92xxSPI_Model is however
-- requested to deliberately insert an error on the InsertError port to test
-- the response of the configuration state machine error reporting circuitry.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodADC.all;
entity tb_TestConfigADC is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 1;
kADC_ClkDiv : integer range 1 to 8 := 4
);
end tb_TestConfigADC;
architecture Behavioral of tb_TestConfigADC is
signal SysClk100 : std_logic := '1';
signal asRst_n : std_logic := '0';
signal sSPI_Clk, sSDIO : std_logic := 'X';
signal sCS : std_logic := '1';
signal InsertError : std_logic;
signal sCmdTxAxisTvalid : std_logic;
signal sCmdTxAxisTready : std_logic;
signal sCmdTxAxisTdata : std_logic_vector(31 downto 0);
signal sCmdRxAxisTvalid : STD_LOGIC;
signal sCmdRxAxisTready : std_logic;
signal sCmdRxAxisTdata : std_logic_vector (31 downto 0);
signal sInitDoneADC : std_logic;
signal sConfigError : std_logic;
constant kSysClkPeriod : time := 10ns; -- System Clock Period
begin
ConfigADC_inst: entity work.ConfigADC
Generic Map(
kZmodID => kZmodID,
kADC_ClkDiv => kADC_ClkDiv,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth,
kSimulation => true
)
Port Map(
--
SysClk100 => SysClk100,
asRst_n => asRst_n,
sInitDoneADC => sInitDoneADC,
sConfigError => sConfigError,
--AD9648 SPI interface signals
sADC_Sclk => sSPI_Clk,
sADC_SDIO => sSDIO,
sADC_CS => sCS,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata
);
TestCmdFIFO: entity work.SPI_IAP_TestModule
Generic Map(
kZmodID => kZmodID
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
sInitDoneADC => sInitDoneADC,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata
);
AD96xx_92xx_inst: entity work.AD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
InsertError => InsertError,
sSPI_Clk => sSPI_Clk,
sSDIO => sSDIO,
sCS => sCS
);
Clock: process
begin
for i in 0 to (kCount5ms*3) loop
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
end loop;
wait;
end process;
Main: process
begin
-- Hold the reset condition for 10 clock cycles
-- (one clock cycle is sufficient, however 10 clock cycles makes
-- it easier to visualize the reset condition in simulation).
asRst_n <= '0';
InsertError <= '0';
wait for 10 * kSysClkPeriod;
-- Signals are assigned at test bench level on the falling edge of SysClk100.
wait until falling_edge(SysClk100);
-- Release reset and perform the ADC initialization with no error inserted.
asRst_n <= '1';
-- Check if the sInitDoneADC signal is asserted and sConfigError is de-asserted
-- after the configuration timeout period (determined empirically)
wait for kCount5ms * kSysClkPeriod;
assert (sInitDoneADC = '1')
report "sInitDoneADC signal not asserted when expected" & LF & HT & HT
severity ERROR;
assert (sConfigError = '0')
report "sConfigError signal not de-asserted when expected" & LF & HT & HT
severity ERROR;
-- Hold the reset condition for 10 clock cycles
-- (one clock cycle is sufficient, however 10 clock cycles makes
-- it easier to visualize the reset condition in simulation).
asRst_n <= '0';
wait for 10*kSysClkPeriod;
wait until falling_edge(SysClk100);
-- Request the ADI_2WireSPI_Model to deliberately insert a register read error.
InsertError <= '1';
asRst_n <= '1';
-- Check if the sInitDoneADC signal is de-asserted and sConfigError is asserted
-- after the configuration timeout period (determined empirically) in the case
-- of an erroneous response of the ADC
wait for kCount5ms * kSysClkPeriod;
assert (sInitDoneADC = '0')
report "sInitDoneADC signal is erroneously asserted" & LF & HT & HT
severity ERROR;
assert (sConfigError = '1')
report "sConfigError signal not asserted when expected" & LF & HT & HT
severity ERROR;
wait;
end process;
end Behavioral;
| mit |
Digilent/vivado-library | ip/Zmods/ZmodScopeController/src/ADI_SPI.vhd | 1 | 15875 |
-------------------------------------------------------------------------------
--
-- File: ADI_SPI.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module manages the SPI communication with the Analog Devices 3 wire SPI
-- configuration interface
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.math_real.all;
use work.PkgZmodADC.all;
entity ADI_SPI is
Generic
(
-- The sSPI_Clk signal is obtained by dividing SysClk100 to 2^kSysClkDiv.
kSysClkDiv : integer range 2 to 63 := 4;
-- The number of data bits for the data phase of the transaction:
-- only 8 data bits currently supported.
kDataWidth : integer range 8 to 8 := 8;
-- The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 8 to 16 := 16
);
Port (
-- input clock (100MHZ).
SysClk100 : in STD_LOGIC;
-- active low synchronous reset signal.
asRst_n : in STD_LOGIC;
--AD92xx/AD96xx SPI interface signals.
sSPI_Clk : out STD_LOGIC;
sSDIO : inout STD_LOGIC;
sCS : out STD_LOGIC := '1';
--Upper layer Interface signals
--a pulse on this input initiates the transfers, also used to register upper layer interface inputs.
sApStart : in STD_LOGIC;
--SPI read data output.
sRdData : out std_logic_vector(kDataWidth - 1 downto 0);
--SPI command data.
sWrData : in std_logic_vector(kDataWidth - 1 downto 0);
--SPI command register address.
sAddr : in std_logic_vector(kCommandWidth - 4 downto 0);
--Number of data bytes + 1; not currently used (for future development).
sWidth : in std_logic_vector(1 downto 0);
--Select between Read/Write operations.
sRdWr : in STD_LOGIC;
--A pulse is generated on this output once the SPI transfer is successfully completed.
sDone : out STD_LOGIC;
--Busy flag; sApStart ignored while this signal is asserted .
sBusy : out STD_LOGIC);
end ADI_SPI;
architecture Behavioral of ADI_SPI is
function MAX(In1 : integer; In2 : integer)
return integer is
begin
if (In1 > In2) then
return In1;
else
return In2;
end if;
end function;
constant kZeros : unsigned (kSysClkDiv - 1 downto 0) := (others => '0');
constant kOnes : unsigned (kSysClkDiv - 1 downto 0) := (others => '1');
signal sClkCounter : unsigned(kSysClkDiv - 1 downto 0) := (others => '0');
signal sSPI_ClkRst: std_logic;
signal sRdDataR : std_logic_vector(kDataWidth - 1 downto 0);
signal sTxVector : std_logic_vector (kDataWidth + kCommandWidth - 1 downto 0);
signal sRxData : std_logic;
signal sTxData : std_logic := '0';
signal sTxShift, sRxShift : std_logic;
signal sLdTx : std_logic;
signal sApStartR, sApStartPulse : std_logic;
constant kCounterMax : integer := MAX((kDataWidth + kCommandWidth + 1), kCS_PulseWidthHigh);
constant kCounterNumBits : integer := integer(ceil(log2(real(kCounterMax))));
signal sCounter : unsigned (kCounterNumBits-1 downto 0);
signal sCounterInt : integer range 0 to (2**kCounterNumBits-1);
signal sCntRst_n, sTxCntEn, sRxCntEn, sDoneCntEn : std_logic := '0';
signal sBitCount : integer range 0 to kDataWidth; --Maximum 4 byte transfers for Analog Devices 2 Wire SPI
signal sDir : std_logic := '0';
signal sDirFsm : std_logic;
signal sCS_Fsm : std_logic;
signal sDoneFsm : std_logic;
signal sBusyFsm : std_logic;
signal sCurrentState : FsmStatesSPI_t := StIdle;
signal sNextState : FsmStatesSPI_t;
-- signals used for debug purposes
-- signal fsm_state, fsm_state_r : std_logic_vector(3 downto 0);
signal kHalfScale : unsigned (kSysClkDiv - 1 downto 0);
begin
kHalfScale <= '1' & kZeros(kSysClkDiv - 2 downto 0);
------------------------------------------------------------------------------------------
-- SPI interface signal assignment
------------------------------------------------------------------------------------------
InstIOBUF : IOBUF -- instantiate SDIO three state output buffer.
generic map (
DRIVE => 12,
IOSTANDARD => "LVCMOS18",
SLEW => "SLOW")
port map (
O => sRxData, -- Buffer output
IO => sSDIO, -- Buffer inout port (connect directly to top-level port)
I => sTxData, -- Buffer input
T => sDir -- 3-state enable input, high=input, low=output
);
-- Three state buffer direction control register.
ProcDir: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sDir <= '0';
elsif (rising_edge(SysClk100)) then
if (sLdTx = '1') then
sDir <= sDirFsm;
else
if ((sClkCounter = kOnes) or (sCS_Fsm = '1')) then
sDir <= sDirFsm;
end if;
end if;
end if;
end process;
ProcRegCS: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCS <= '1';
--fsm_state_r <= (others => '0');
elsif (rising_edge (SysClk100)) then
sCS <= sCS_Fsm;
--fsm_state_r <= fsm_state;
end if;
end process;
sSPI_Clk <= sClkCounter(kSysClkDiv - 1 );
------------------------------------------------------------------------------------------
-- Input clock frequency divider
------------------------------------------------------------------------------------------
ProcClkCounter: process (SysClk100, asRst_n) --clock frequency divider
begin
if (asRst_n = '0') then
sClkCounter <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sSPI_ClkRst = '1') then
sClkCounter <= (others => '0');
else
sClkCounter <= sClkCounter + 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Transmit logic
------------------------------------------------------------------------------------------
sBitCount <= kDataWidth;
ProcApStartReg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sApStartR <= '0';
elsif (rising_edge(SysClk100)) then
sApStartR <= sApStart;
end if;
end process;
sApStartPulse <= sApStart and (not sApStartR);
ProcShiftTx: process (SysClk100, asRst_n) --Transmit shift register
begin
if (asRst_n = '0') then
sTxVector <= (others => '0');--sRdWr & "00" & sAddr & sWrData;
sTxData <= '0';
elsif (rising_edge(SysClk100)) then
if (sApStartPulse = '1') then
--sTxVector <= sRdWr & sWidth & sAddr & sWrData;
sTxVector <= sRdWr & "00" & sAddr & sWrData;
sTxData <= '0';
else
if(sTxShift = '1') then
--data is placed on the falling edge (sClkCounter = kZeros) of sSPI_Clk for the transmit phase.
if ((sClkCounter = kZeros) and (sCounterInt <= kDataWidth+kCommandWidth)) then
sTxVector(kDataWidth + kCommandWidth - 1 downto 0) <= sTxVector(kDataWidth + kCommandWidth - 2 downto 0) & '0';
sTxData <= sTxVector(kDataWidth + kCommandWidth - 1);
elsif (sCounterInt > kDataWidth+kCommandWidth) then
sTxData <= '0';
end if;
else
sTxData <= '0';
end if;
end if;
end if;
end process;
ProcTxCount: process (asRst_n, sTxShift, sLdTx, sClkCounter) --Transmit bit count
begin
if ((asRst_n = '0') or (sLdTx = '1')) then
sTxCntEn <= '0';
else
if(sTxShift = '1') then
--The TX bit count incremented on the falling edge of the sSPI_Clk (sClkCounter = kZeros).
if (sClkCounter = kZeros) then
sTxCntEn <= '1';
else
sTxCntEn <= '0';
end if;
else
sTxCntEn <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Receive logic
------------------------------------------------------------------------------------------
-- Receive deserializer.
ProcShiftRx: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRdDataR <= (others =>'0');
elsif (rising_edge(SysClk100)) then
if (sRxShift = '0') then
sRdDataR <= (others =>'0');
else
if ((sRxShift = '1') and (sClkCounter = kHalfScale)) then
--The read data is sampled on the rising edge of the sSPI_Clk (sClkCounter = kHalfScale).
sRdDataR(kDataWidth - 1 downto 0) <= sRdDataR(kDataWidth - 2 downto 0) & sRxData;
end if;
end if;
end if;
end process;
ProcRxCount: process (asRst_n, sRxShift, sClkCounter, kHalfScale) --Receive bit count
begin
if ((asRst_n = '0') or (sRxShift = '0')) then
sRxCntEn <= '0';
else
if (sRxShift = '1') then
--The RX bit count is incremented on the rising edge of the sSPI_Clk (sClkCounter = kHalfScale).
if (sClkCounter = kHalfScale) then
sRxCntEn <= '1';
else
sRxCntEn <= '0';
end if;
else
sRxCntEn <= '0';
end if;
end if;
end process;
-- Register SPI read data once read instruction is completed.
ProcRdData: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRdData <= (others => '0');
sDone <= '0';
elsif (rising_edge (SysClk100)) then
sDone <= sDoneFsm;
if (sDoneFsm = '1') then
sRdData <= sRdDataR;
end if;
end if;
end process;
ProcBusy: process (SysClk100, asRst_n) --register sBusyFsm output
begin
if (asRst_n = '0') then
sBusy <= '1';
elsif (rising_edge (SysClk100)) then
sBusy <= sBusyFsm;
end if;
end process;
--Counter used by both transmit and receive logic; sCS minimum pulse width high is also timed by this counter.
ProcCounter: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCounter <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sCntRst_n = '0') then
sCounter <= (others => '0');
else
if ((sTxCntEn = '1') or (sRxCntEn = '1') or (sDoneCntEn = '1')) then
sCounter <= sCounter + 1;
end if;
end if;
end if;
end process;
sCounterInt <= to_integer (sCounter);
------------------------------------------------------------------------------------------
-- SPI State Machine
------------------------------------------------------------------------------------------
ProcFsmSync: process (SysClk100, asRst_n) --State machine synchronous process
begin
if (asRst_n = '0') then
sCurrentState <= StIdle;
elsif (rising_edge (SysClk100)) then
sCurrentState <= sNextState;
end if;
end process;
--Next State decode logic
ProcNextStateAndOutputDecode: process (sCurrentState, sApStart, sRdWr, sCounterInt, sClkCounter, sBitCount)
begin
sNextState <= sCurrentState;
sDirFsm <= '0';
sCS_Fsm <= '1';
sDoneFsm <= '0';
sRxShift <= '0';
sTxShift <= '0';
--fsm_state <= (others => '0');
sLdTx <= '0';
sSPI_ClkRst <= '1';
sCntRst_n <= '0';
sDoneCntEn <= '0';
sBusyFsm <= '1';
case (sCurrentState) is
when StIdle =>
--fsm_state <= "0000";
sBusyFsm <= '0';
sLdTx <= '1';
if (sApStart = '1') then
if (sRdWr = '1') then
sNextState <= StRead1;
else
sNextState <= StWrite;
end if;
end if;
when StRead1 => --send command bytes
--fsm_state <= "0001";
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = kCommandWidth) then
sDirFsm <= '1';
sNextState <= StRead2;
end if;
when StRead2 => --send last command bit; change three state buffer direction
--fsm_state <= "0010";
sDirFsm <= '1';
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = kCommandWidth + 1) then
sNextState <= StRead3;
sCntRst_n <= '0';
end if;
when StRead3 => --receive register read data
--fsm_state <= "0011";
sDirFsm <= '1';
sCS_Fsm <= '0';
sRxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if ((sCounterInt = sBitCount) and (sClkCounter = kOnes + 1)) then
--this condition assures a sSPI_Clk pulse width low of 2 SysClk100 cycles for last data bit
sCntRst_n <= '0';
sDirFsm <= '0';
sNextState <= StDone;
end if;
when StWrite => --send SPI command and register data
--fsm_state <= "0100";
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = (sBitCount + kCommandWidth + 1)) then
sSPI_ClkRst <= '1';
sNextState <= StDone;
end if;
when StDone => --signal SPI instruction complete
--fsm_state <= "0101";
sDoneFsm <= '1';
sNextState <= StAssertCS;
when StAssertCS => --hold CS high for at least kCS_PulseWidthHigh SysClk100 cycles
--fsm_state <= "0111";
sCntRst_n <= '1';
sDoneCntEn <= '1';
if (sCounterInt = kCS_PulseWidthHigh) then
sNextState <= StIdle;
end if;
when others =>
--fsm_state <= (others => '1');
sNextState <= StIdle;
end case;
end process;
end Behavioral; | mit |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/vhdl/Loop_loop_height_fYi.vhd | 1 | 13862 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_fYi_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_fYi_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 => "00000000", 1 => "00000101", 2 => "00001000", 3 => "00001011",
4 => "00001101", 5 => "00001111", 6 => "00010010", 7 => "00010100",
8 => "00010110", 9 => "00010111", 10 => "00011001", 11 => "00011011",
12 => "00011101", 13 => "00011110", 14 => "00100000", 15 => "00100010",
16 => "00100011", 17 => "00100101", 18 => "00100110", 19 => "00101000",
20 => "00101001", 21 => "00101011", 22 => "00101100", 23 => "00101110",
24 => "00101111", 25 => "00110001", 26 => "00110010", 27 => "00110011",
28 => "00110101", 29 => "00110110", 30 => "00110111", 31 => "00111001",
32 => "00111010", 33 => "00111011", 34 => "00111100", 35 => "00111110",
36 => "00111111", 37 => "01000000", 38 => "01000001", 39 => "01000011",
40 => "01000100", 41 => "01000101", 42 => "01000110", 43 => "01001000",
44 => "01001001", 45 => "01001010", 46 => "01001011", 47 => "01001100",
48 => "01001101", 49 => "01001110", 50 => "01010000", 51 => "01010001",
52 => "01010010", 53 => "01010011", 54 => "01010100", 55 => "01010101",
56 => "01010110", 57 => "01010111", 58 => "01011001", 59 => "01011010",
60 => "01011011", 61 => "01011100", 62 => "01011101", 63 => "01011110",
64 => "01011111", 65 => "01100000", 66 => "01100001", 67 => "01100010",
68 => "01100011", 69 => "01100100", 70 => "01100101", 71 => "01100110",
72 => "01100111", 73 => "01101000", 74 => "01101001", 75 => "01101010",
76 => "01101011", 77 => "01101100", 78 => "01101101", 79 => "01101110",
80 => "01101111", 81 => "01110000", 82 => "01110001", 83 => "01110010",
84 => "01110011", 85 => "01110100", 86 => "01110101", 87 => "01110110",
88 => "01110111", 89 => "01111000", 90 => "01111001", 91 => "01111010",
92 => "01111011", 93 => "01111100", 94 => "01111101", 95 => "01111110",
96 => "01111111", 97 => "10000000", 98 => "10000001", 99 => "10000010",
100 => "10000011", 101 => "10000100", 102 to 103=> "10000101", 104 => "10000110",
105 => "10000111", 106 => "10001000", 107 => "10001001", 108 => "10001010",
109 => "10001011", 110 => "10001100", 111 => "10001101", 112 => "10001110",
113 to 114=> "10001111", 115 => "10010000", 116 => "10010001", 117 => "10010010",
118 => "10010011", 119 => "10010100", 120 => "10010101", 121 => "10010110",
122 to 123=> "10010111", 124 => "10011000", 125 => "10011001", 126 => "10011010",
127 => "10011011", 128 => "10011100", 129 => "10011101", 130 to 131=> "10011110",
132 => "10011111", 133 => "10100000", 134 => "10100001", 135 => "10100010",
136 => "10100011", 137 to 138=> "10100100", 139 => "10100101", 140 => "10100110",
141 => "10100111", 142 => "10101000", 143 => "10101001", 144 to 145=> "10101010",
146 => "10101011", 147 => "10101100", 148 => "10101101", 149 => "10101110",
150 to 151=> "10101111", 152 => "10110000", 153 => "10110001", 154 => "10110010",
155 => "10110011", 156 to 157=> "10110100", 158 => "10110101", 159 => "10110110",
160 => "10110111", 161 to 162=> "10111000", 163 => "10111001", 164 => "10111010",
165 => "10111011", 166 to 167=> "10111100", 168 => "10111101", 169 => "10111110",
170 => "10111111", 171 to 172=> "11000000", 173 => "11000001", 174 => "11000010",
175 => "11000011", 176 to 177=> "11000100", 178 => "11000101", 179 => "11000110",
180 => "11000111", 181 to 182=> "11001000", 183 => "11001001", 184 => "11001010",
185 => "11001011", 186 to 187=> "11001100", 188 => "11001101", 189 => "11001110",
190 to 191=> "11001111", 192 => "11010000", 193 => "11010001", 194 => "11010010",
195 to 196=> "11010011", 197 => "11010100", 198 => "11010101", 199 to 200=> "11010110",
201 => "11010111", 202 => "11011000", 203 to 204=> "11011001", 205 => "11011010",
206 => "11011011", 207 to 208=> "11011100", 209 => "11011101", 210 => "11011110",
211 to 212=> "11011111", 213 => "11100000", 214 => "11100001", 215 to 216=> "11100010",
217 => "11100011", 218 => "11100100", 219 to 220=> "11100101", 221 => "11100110",
222 => "11100111", 223 to 224=> "11101000", 225 => "11101001", 226 => "11101010",
227 to 228=> "11101011", 229 => "11101100", 230 => "11101101", 231 to 232=> "11101110",
233 => "11101111", 234 => "11110000", 235 to 236=> "11110001", 237 => "11110010",
238 to 239=> "11110011", 240 => "11110100", 241 => "11110101", 242 to 243=> "11110110",
244 => "11110111", 245 => "11111000", 246 to 247=> "11111001", 248 => "11111010",
249 to 250=> "11111011", 251 => "11111100", 252 => "11111101", 253 to 254=> "11111110",
255 => "11111111" );
signal mem1 : mem_array := (
0 => "00000000", 1 => "00000101", 2 => "00001000", 3 => "00001011",
4 => "00001101", 5 => "00001111", 6 => "00010010", 7 => "00010100",
8 => "00010110", 9 => "00010111", 10 => "00011001", 11 => "00011011",
12 => "00011101", 13 => "00011110", 14 => "00100000", 15 => "00100010",
16 => "00100011", 17 => "00100101", 18 => "00100110", 19 => "00101000",
20 => "00101001", 21 => "00101011", 22 => "00101100", 23 => "00101110",
24 => "00101111", 25 => "00110001", 26 => "00110010", 27 => "00110011",
28 => "00110101", 29 => "00110110", 30 => "00110111", 31 => "00111001",
32 => "00111010", 33 => "00111011", 34 => "00111100", 35 => "00111110",
36 => "00111111", 37 => "01000000", 38 => "01000001", 39 => "01000011",
40 => "01000100", 41 => "01000101", 42 => "01000110", 43 => "01001000",
44 => "01001001", 45 => "01001010", 46 => "01001011", 47 => "01001100",
48 => "01001101", 49 => "01001110", 50 => "01010000", 51 => "01010001",
52 => "01010010", 53 => "01010011", 54 => "01010100", 55 => "01010101",
56 => "01010110", 57 => "01010111", 58 => "01011001", 59 => "01011010",
60 => "01011011", 61 => "01011100", 62 => "01011101", 63 => "01011110",
64 => "01011111", 65 => "01100000", 66 => "01100001", 67 => "01100010",
68 => "01100011", 69 => "01100100", 70 => "01100101", 71 => "01100110",
72 => "01100111", 73 => "01101000", 74 => "01101001", 75 => "01101010",
76 => "01101011", 77 => "01101100", 78 => "01101101", 79 => "01101110",
80 => "01101111", 81 => "01110000", 82 => "01110001", 83 => "01110010",
84 => "01110011", 85 => "01110100", 86 => "01110101", 87 => "01110110",
88 => "01110111", 89 => "01111000", 90 => "01111001", 91 => "01111010",
92 => "01111011", 93 => "01111100", 94 => "01111101", 95 => "01111110",
96 => "01111111", 97 => "10000000", 98 => "10000001", 99 => "10000010",
100 => "10000011", 101 => "10000100", 102 to 103=> "10000101", 104 => "10000110",
105 => "10000111", 106 => "10001000", 107 => "10001001", 108 => "10001010",
109 => "10001011", 110 => "10001100", 111 => "10001101", 112 => "10001110",
113 to 114=> "10001111", 115 => "10010000", 116 => "10010001", 117 => "10010010",
118 => "10010011", 119 => "10010100", 120 => "10010101", 121 => "10010110",
122 to 123=> "10010111", 124 => "10011000", 125 => "10011001", 126 => "10011010",
127 => "10011011", 128 => "10011100", 129 => "10011101", 130 to 131=> "10011110",
132 => "10011111", 133 => "10100000", 134 => "10100001", 135 => "10100010",
136 => "10100011", 137 to 138=> "10100100", 139 => "10100101", 140 => "10100110",
141 => "10100111", 142 => "10101000", 143 => "10101001", 144 to 145=> "10101010",
146 => "10101011", 147 => "10101100", 148 => "10101101", 149 => "10101110",
150 to 151=> "10101111", 152 => "10110000", 153 => "10110001", 154 => "10110010",
155 => "10110011", 156 to 157=> "10110100", 158 => "10110101", 159 => "10110110",
160 => "10110111", 161 to 162=> "10111000", 163 => "10111001", 164 => "10111010",
165 => "10111011", 166 to 167=> "10111100", 168 => "10111101", 169 => "10111110",
170 => "10111111", 171 to 172=> "11000000", 173 => "11000001", 174 => "11000010",
175 => "11000011", 176 to 177=> "11000100", 178 => "11000101", 179 => "11000110",
180 => "11000111", 181 to 182=> "11001000", 183 => "11001001", 184 => "11001010",
185 => "11001011", 186 to 187=> "11001100", 188 => "11001101", 189 => "11001110",
190 to 191=> "11001111", 192 => "11010000", 193 => "11010001", 194 => "11010010",
195 to 196=> "11010011", 197 => "11010100", 198 => "11010101", 199 to 200=> "11010110",
201 => "11010111", 202 => "11011000", 203 to 204=> "11011001", 205 => "11011010",
206 => "11011011", 207 to 208=> "11011100", 209 => "11011101", 210 => "11011110",
211 to 212=> "11011111", 213 => "11100000", 214 => "11100001", 215 to 216=> "11100010",
217 => "11100011", 218 => "11100100", 219 to 220=> "11100101", 221 => "11100110",
222 => "11100111", 223 to 224=> "11101000", 225 => "11101001", 226 => "11101010",
227 to 228=> "11101011", 229 => "11101100", 230 => "11101101", 231 to 232=> "11101110",
233 => "11101111", 234 => "11110000", 235 to 236=> "11110001", 237 => "11110010",
238 to 239=> "11110011", 240 => "11110100", 241 => "11110101", 242 to 243=> "11110110",
244 => "11110111", 245 => "11111000", 246 to 247=> "11111001", 248 => "11111010",
249 to 250=> "11111011", 251 => "11111100", 252 => "11111101", 253 to 254=> "11111110",
255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_fYi is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_fYi is
component Loop_loop_height_fYi_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_fYi_rom_U : component Loop_loop_height_fYi_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
| mit |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign | Interpolation_not_complete/prj_sub.vhd | 1 | 1081 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:56:19 07/08/05
-- Design Name:
-- Module Name: prj_sub - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity prj_sub is
Port ( Pixel_in1 : in std_logic_vector(8 downto 0);
Pixel_in2 : in std_logic_vector(8 downto 0);
sub_out : out std_logic_vector(8 downto 0));
end prj_sub;
architecture Behavioral of prj_sub is
begin
sub_out <= Pixel_in1 + ((not Pixel_in2) + '1' );
end Behavioral;
| mit |
Digilent/vivado-library | ip/Zmods/ZmodAWGController/tb/AD9717_RegisterDecode.vhd | 1 | 18623 |
-------------------------------------------------------------------------------
--
-- File: AD9717_RegisterDecode.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodAWG1411_Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module implements the register set for the AD9717 simulation model
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.PkgZmodDAC.all;
entity AD9717_RegisterDecode is
Generic (
-- Parameter identifying the Zmod:
-- 7 -> Zmod AWG 1411 - (AD9717)
kZmodID : integer range 7 to 7 := 7;
-- Register address width
kAddrWidth : integer range 0 to 32 := 5;
-- Register data width: only 8 data bits currently supported
kRegDataWidth : integer range 0 to 32 := 8
);
Port (
-- 100MHZ clock input
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain)
asRst_n : in STD_LOGIC;
-- When InsertError is asserted the model produces an erroneous reading for register address x01
InsertError : in STD_LOGIC;
-- Signal indicating that the data phase of he register write SPI transaction is completed and aDataDecode is valid
sDataWriteDecodeReady : in STD_LOGIC;
-- Signal indicating that the address phase of the SPI transaction is completed and aAddrDecode is valid
sAddrDecodeReady : in STD_LOGIC;
-- Input register data used to update internal egister values for write register operations
sDataDecode : in STD_LOGIC_VECTOR (kRegDataWidth-1 downto 0);
-- Register address input
sAddrDecode : in STD_LOGIC_VECTOR (kAddrWidth-1 downto 0);
-- Output register data produced by this module upon address decode for register read operations
sRegDataOut : out STD_LOGIC_VECTOR (kRegDataWidth-1 downto 0)
);
end AD9717_RegisterDecode;
architecture Behavioral of AD9717_RegisterDecode is
signal sAddrDecodeReadyPulse, sAddrDecodeReadyDly : std_logic := '0';
signal sDataWriteDecodeReadyPulse, sDataWriteDecodeReadyDly : std_logic := '0';
signal sReg00 : std_logic_vector(7 downto 0) := x"00";
signal sReg01 : std_logic_vector(7 downto 0) := x"40";
signal sReg02 : std_logic_vector(7 downto 0) := x"34";
signal sReg03 : std_logic_vector(7 downto 0) := x"00";
signal sReg04 : std_logic_vector(7 downto 0) := x"00";
signal sReg05 : std_logic_vector(7 downto 0) := x"00";
signal sReg06 : std_logic_vector(7 downto 0) := x"00";
signal sReg07 : std_logic_vector(7 downto 0) := x"00";
signal sReg08 : std_logic_vector(7 downto 0) := x"00";
signal sReg09 : std_logic_vector(7 downto 0) := x"00";
signal sReg0A : std_logic_vector(7 downto 0) := x"00";
signal sReg0B : std_logic_vector(7 downto 0) := x"00";
signal sReg0C : std_logic_vector(7 downto 0) := x"00";
signal sReg0D : std_logic_vector(7 downto 0) := x"00";
signal sReg0E : std_logic_vector(7 downto 0) := x"00";
signal sReg0F : std_logic_vector(7 downto 0) := x"00";
signal sReg10 : std_logic_vector(7 downto 0) := x"00";
signal sReg11 : std_logic_vector(7 downto 0) := x"34";
signal sReg12 : std_logic_vector(7 downto 0) := x"00";
signal sReg14 : std_logic_vector(7 downto 0) := x"00";
signal sReg1F : std_logic_vector(7 downto 0) := x"04";
signal sCalstatQ_TimerRst_n, sCalstatI_TimerRst_n : std_logic;
signal sCalstatQ_Timer, sCalstatI_Timer : unsigned (23 downto 0);
signal sSetCalstatQ, sSetCalstatI : std_logic;
signal sAddrAux : integer range 0 to 511;
begin
sAddrAux <= to_integer (unsigned (std_logic_vector'((sAddrDecode))));
-- The following section generates a pulse when sAddrDecodeReady is asserted.
-- This pulse indicates that the command phase of the SPI read transaction is
-- completed and that sAddrDecode contains valid data.
ProcAddrDecodeDly: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sAddrDecodeReadyDly <= '0';
elsif (rising_edge(SysClk100)) then
sAddrDecodeReadyDly <= sAddrDecodeReady;
end if;
end process;
sAddrDecodeReadyPulse <= sAddrDecodeReady and (not sAddrDecodeReadyDly);
-- Process managing register read operations
ReadRegister: process(SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRegDataOut <= (others => '0');
elsif (rising_edge (SysClk100)) then
if (sAddrDecodeReadyPulse = '1') then
case (sAddrDecode) is
when "00000" =>
sRegDataOut <= sReg00;
when "00001" =>
if (InsertError = '0') then
sRegDataOut <= sReg01;
else
sRegDataOut <= x"00";
end if;
when "00010" =>
sRegDataOut <= sReg02;
when "00011" =>
sRegDataOut <= sReg03;
when "00100" =>
sRegDataOut <= sReg04;
when "00101" =>
sRegDataOut <= sReg05;
when "00110" =>
sRegDataOut <= sReg06;
when "00111" =>
sRegDataOut <= sReg07;
when "01000" =>
sRegDataOut <= sReg08;
when "01001" =>
sRegDataOut <= sReg09;
when "01010" =>
sRegDataOut <= sReg0A;
when "01011" =>
sRegDataOut <= sReg0B;
when "01100" =>
sRegDataOut <= sReg0C;
when "01101" =>
sRegDataOut <= sReg0D;
when "01110" =>
sRegDataOut <= sReg0E;
when "01111" =>
sRegDataOut <= sReg0F;
when "10000" =>
sRegDataOut <= sReg10;
when "10001" =>
sRegDataOut <= sReg11;
when "10010" =>
sRegDataOut <= sReg12;
when "10100" =>
sRegDataOut <= sReg14;
when "11111" =>
sRegDataOut <= sReg1F;
when others =>
sRegDataOut <= x"00";
report "Invalid Read Address." & LF & HT & HT
severity ERROR;
end case;
end if;
end if;
end process ReadRegister;
-- The following section generates a pulse when sDataWriteDecodeReady is asserted.
-- This pulse indicates that the command phase of the SPI write transaction is
-- completed and that sAddrDecode contains valid data.
ProcDataDecodeDly: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sDataWriteDecodeReadyDly <= '0';
elsif (rising_edge(SysClk100)) then
sDataWriteDecodeReadyDly <= sDataWriteDecodeReady;
end if;
end process;
sDataWriteDecodeReadyPulse <= sDataWriteDecodeReady and (not sDataWriteDecodeReadyDly);
-- Process managing register write operations (Reg0F is treated separately).
WriteRegister: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg00 <= x"00";
sReg01 <= x"40";
sReg02 <= x"34";
sReg03 <= x"00";
sReg04 <= x"00";
sReg05 <= x"00";
sReg06 <= x"00";
sReg07 <= x"00";
sReg08 <= x"00";
sReg09 <= x"00";
sReg0A <= x"00";
sReg0B <= x"00";
sReg0C <= x"00";
sReg0D <= x"00";
sReg0E(7 downto 6) <= "00";
sReg0E(3 downto 0) <= x"0";
sReg10 <= x"00";
sReg11 <= x"34";
sReg12 <= x"00";
sReg14 <= x"00";
sReg1F <= x"04";
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
case (sAddrDecode) is
when "00000" =>
sReg00(7 downto 4) <= sDataDecode(7 downto 4);
when "00001" =>
sReg01 <= sDataDecode;
when "00010" =>
sReg02 <= sDataDecode;
when "00011" =>
sReg03(5 downto 0) <= sDataDecode(5 downto 0);
when "00100" =>
sReg04(7) <= sDataDecode(7);
sReg04(5 downto 0) <= sDataDecode(5 downto 0);
when "00101" =>
sReg05(7) <= sDataDecode(7);
sReg05(5 downto 0) <= sDataDecode(5 downto 0);
when "00110" =>
sReg06(5 downto 0) <= sDataDecode(5 downto 0);
when "00111" =>
sReg07(7) <= sDataDecode(7);
sReg07(5 downto 0) <= sDataDecode(5 downto 0);
when "01000" =>
sReg08(7) <= sDataDecode(7);
sReg08(5 downto 0) <= sDataDecode(5 downto 0);
when "01001" =>
sReg09 <= sDataDecode;
when "01010" =>
sReg0A <= sDataDecode;
when "01011" =>
sReg0B <= sDataDecode;
when "01100" =>
sReg0C <= sDataDecode;
when "01101" =>
sReg0D(5 downto 0) <= sDataDecode(5 downto 0);
when "01110" =>
sReg0E(7 downto 6) <= sDataDecode(7 downto 6);
sReg0E(3 downto 0) <= sDataDecode(3 downto 0);
when "01111" =>
-- sReg0F(7 downto 6) <= sDataDecode(7 downto 6);
-- sReg0F(3 downto 0) <= sDataDecode(3 downto 0);
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
when "10000" =>
sReg10(5 downto 0) <= sDataDecode(5 downto 0);
when "10001" =>
sReg11(5 downto 0) <= sDataDecode(5 downto 0);
when "10010" =>
sReg12(7 downto 6) <= sDataDecode(7 downto 6);
sReg12(4 downto 0) <= sDataDecode(4 downto 0);
when "10100" =>
sReg14(7 downto 6) <= sDataDecode(7 downto 6);
sReg14(4 downto 0) <= sDataDecode(4 downto 0);
when "11111" =>
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
when others =>
report "Invalid Write Address." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
end case;
-- Soft Reset
elsif (sReg00(5) = '1') then
sReg01 <= x"40";
sReg02 <= x"34";
sReg03 <= x"00";
sReg04 <= x"00";
sReg05 <= x"00";
sReg06 <= x"00";
sReg07 <= x"00";
sReg08 <= x"00";
sReg09 <= x"00";
sReg0A <= x"00";
sReg0B <= x"00";
sReg0C <= x"00";
sReg0D <= x"00";
sReg0E(7 downto 6) <= "00";
sReg0E(3 downto 0) <= x"0";
sReg10 <= x"00";
sReg11 <= x"34";
sReg12 <= x"00";
sReg14 <= x"00";
sReg1F <= x"04";
end if;
end if;
end process WriteRegister;
-- Counter used to implement the CALSTATQ bit behavior
ProcCalstatQ_Tmr: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCalstatQ_Timer <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sCalstatQ_TimerRst_n = '0') then
sCalstatQ_Timer <= (others => '0');
else
sCalstatQ_Timer <= sCalstatQ_Timer + 1;
end if;
end if;
end process;
-- Counter used to implement the CALSTATI bit behavior
ProcCalstatI_Tmr: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCalstatI_Timer <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sCalstatI_TimerRst_n = '0') then
sCalstatI_Timer <= (others => '0');
else
sCalstatI_Timer <= sCalstatI_Timer + 1;
end if;
end if;
end process;
ProcEnCalstatQ_TmrRst: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCalstatQ_TimerRst_n <= '0';
elsif (rising_edge(SysClk100)) then
if (sReg0E(5) = '1') then
sCalstatQ_TimerRst_n <= '1';
else
sCalstatQ_TimerRst_n <= '0';
end if;
end if;
end process;
ProcEnCalstatI_TmrRst: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCalstatI_TimerRst_n <= '0';
elsif (rising_edge(SysClk100)) then
if (sReg0E(4) = '1') then
sCalstatI_TimerRst_n <= '1';
else
sCalstatI_TimerRst_n <= '0';
end if;
end if;
end process;
-- Configure the CALSELQ bit in the Cal Control register (0x0E)
-- for register write operations.
-- Clear CALSELQ when the Q DAC self-calibration is complete.
WriteReg0E_CALSELQ: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg0E(5) <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
if (sAddrDecode = "01110") then
sReg0E(5) <= sDataDecode(5);
end if;
elsif (sSetCalstatQ = '1') then
sReg0E(5) <= '0';
end if;
end if;
end process;
-- Configure the CALSELI bit in the Cal Control register (0x0E)
-- for register write operations.
-- Clear CALSELQ when the I DAC self-calibration is complete.
WriteReg0E_CALSELI: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg0E(4) <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
if (sAddrDecode = "01110") then
sReg0E(4) <= sDataDecode(5);
end if;
elsif (sSetCalstatI = '1') then
sReg0E(4) <= '0';
end if;
end if;
end process;
-- Manage the CALSTATQ bit in the Cal Memory register (0x0F).
-- Write operations at this address have no effect (except
-- reporting an error).
-- CALSTATQ is set at a predefined interval after the CALSETQ
-- bit in the Cal Control register is set.
-- CALSTATQ is cleared when he CALRSTQ bit in the Memory R/W
-- register (0x12) is set.
WriteReg0F_CALSTATQ: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg0F(7) <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
if (sAddrDecode = "01111") then
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
end if;
elsif (sReg12(7) = '1') then
sReg0F(7) <= '0';
elsif (sSetCalstatQ = '1') then
sReg0F(7) <= '1';
end if;
end if;
end process;
-- Manage the CALSTATI bit in the Cal Memory register (0x0F).
-- Write operations at this address have no effect (except
-- reporting an error).
-- CALSTATI is set at a predefined interval after the CALSETI
-- bit in the Cal Control register is set.
-- CALSTATI is cleared when he CALRSTI bit in the Memory R/W
-- register (0x12) is set.
WriteReg0F_CALSTATI: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg0F(6) <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
if (sAddrDecode = "01111") then
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
end if;
elsif (sReg12(6) = '1') then
sReg0F(6) <= '0';
elsif (sSetCalstatI = '1') then
sReg0F(6) <= '1';
end if;
end if;
end process;
-- Process used to set CALSTATQ in 300 calibration clock cycles (kCalTimeout) after
-- the self calibration process has been enabled
ProcStCalstatQ: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sSetCalstatQ <= '0';
elsif (rising_edge(SysClk100)) then
if (sCalstatQ_Timer = kCalTimeout) then
sSetCalstatQ <= '1';
else
sSetCalstatQ <= '0';
end if;
end if;
end process;
-- Process used to set CALSTATI in 300 calibration clock cycles (kCalTimeout) after
-- the self calibration process has been enabled
ProcStCalstatI: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sSetCalstatI <= '0';
elsif (rising_edge(SysClk100)) then
if (sCalstatI_Timer = kCalTimeout) then
sSetCalstatI <= '1';
else
sSetCalstatI <= '0';
end if;
end if;
end process;
end Behavioral;
| mit |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign | Interpolation_not_complete/Gout.vhd | 1 | 4517 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:59:03 07/14/05
-- Design Name:
-- Module Name: Gout - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Gout is
generic
(
width : integer := 8
);
Port
(
-- Dhor42
g1 : in std_logic_vector( width downto 0 ); -- G41
g2 : in std_logic_vector( width downto 0 ); -- G43
b1 : in std_logic_vector( width downto 0 ); -- R40
b2 : in std_logic_vector( width downto 0 ); -- R42
b3 : in std_logic_vector( width downto 0 ); -- R44
b4 : in std_logic_vector( width downto 0 ); -- R42
-- Dver42
g1_2 : in std_logic_vector( width downto 0 ); -- G32
g2_2 : in std_logic_vector( width downto 0 ); -- G52
b1_2 : in std_logic_vector( width downto 0 ); -- R22
b2_2 : in std_logic_vector( width downto 0 ); -- R42
b3_2 : in std_logic_vector( width downto 0 ); -- R62
b4_2 : in std_logic_vector( width downto 0 ); -- R42
-- Dhor44
g3 : in std_logic_vector( width downto 0 ); -- G43
g4 : in std_logic_vector( width downto 0 ); -- G45
b5 : in std_logic_vector( width downto 0 ); -- R42
b6 : in std_logic_vector( width downto 0 ); -- R44
b7 : in std_logic_vector( width downto 0 ); -- R46
b8 : in std_logic_vector( width downto 0 ); -- R44
-- Dver44
g3_2 : in std_logic_vector( width downto 0 ); -- G34
g4_2 : in std_logic_vector( width downto 0 ); -- G54
b5_2 : in std_logic_vector( width downto 0 ); -- R24
b6_2 : in std_logic_vector( width downto 0 ); -- R44
b7_2 : in std_logic_vector( width downto 0 ); -- R64
b8_2 : in std_logic_vector( width downto 0 ); -- R44
G_bar1 : out std_logic_vector( width downto 0 );
G_bar2 : out std_logic_vector( width downto 0 )
-- E_in1 : in std_logic_vector( width downto 0 ); -- G22
-- E_in2 : in std_logic_vector( width downto 0 ); -- G23
-- E_in3 : in std_logic_vector( width downto 0 ); -- G43
-- E_in4 : in std_logic_vector( width downto 0 ); -- G24
-- E : out std_logic_vector( 18 downto 0 )
);
end Gout;
architecture Behavioral of Gout is
component combine_g_bar
Port ( g1 : in std_logic_vector(8 downto 0);
g2 : in std_logic_vector(8 downto 0);
b1 : in std_logic_vector(8 downto 0);
b2 : in std_logic_vector(8 downto 0);
b3 : in std_logic_vector(8 downto 0);
b4 : in std_logic_vector(8 downto 0);
g1_2 : in std_logic_vector(8 downto 0);
g2_2 : in std_logic_vector(8 downto 0);
b1_2 : in std_logic_vector(8 downto 0);
b2_2 : in std_logic_vector(8 downto 0);
b3_2 : in std_logic_vector(8 downto 0);
b4_2 : in std_logic_vector(8 downto 0);
g_bar : out std_logic_vector(8 downto 0));
end component;
--component combine_E_out_G_in
-- Port ( G1 : in std_logic_vector(8 downto 0);
-- G_bar1 : in std_logic_vector(8 downto 0);
-- G2 : in std_logic_vector(8 downto 0);
-- G3 : in std_logic_vector(8 downto 0);
-- G4 : in std_logic_vector(8 downto 0);
-- G_bar2 : in std_logic_vector(8 downto 0);
-- E : out std_logic_vector(18 downto 0));
--end component;
--signal G_bar1:std_logic_vector(8 downto 0);
--signal G_bar2:std_logic_vector(8 downto 0);
--signal E_OUT:std_logic_vector(18 downto 0);
begin
element1: combine_g_bar port map(g1 , g2 , b1 , b2 , b3 , b4 ,g1_2 , g2_2 , b1_2 , b2_2 , b3_2 , b4_2 , G_bar1); -- ~G42
element2: combine_g_bar port map(g3 , g4 , b5 , b6 , b7 , b8 ,g3_2 , g4_2 , b5_2 , b6_2 , b7_2 , b8_2 , G_bar2); -- ~G44
--G_bar1 <= G_bar1;
--G_bar2 <= G_bar2;
-- Ehor = ( | G22 - ~G42 | + 2 * | G23 - G43 | + | G24 - ~G44 | * 256 / ( G23 + G43 )
--element3: combine_E_out_G_in port map(E_in1 , G_bar1 , E_in2 , E_in3 , E_in4 , G_bar2 ,E_OUT);
--E <= E_OUT;
end Behavioral;
| mit |
Digilent/vivado-library | ip/video_scaler/hdl/vhdl/video_scaler.vhd | 1 | 46074 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity video_scaler is
generic (
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER := 32 );
port (
s_axi_ctrl_AWVALID : IN STD_LOGIC;
s_axi_ctrl_AWREADY : OUT STD_LOGIC;
s_axi_ctrl_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
s_axi_ctrl_WVALID : IN STD_LOGIC;
s_axi_ctrl_WREADY : OUT STD_LOGIC;
s_axi_ctrl_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_ctrl_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0);
s_axi_ctrl_ARVALID : IN STD_LOGIC;
s_axi_ctrl_ARREADY : OUT STD_LOGIC;
s_axi_ctrl_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
s_axi_ctrl_RVALID : OUT STD_LOGIC;
s_axi_ctrl_RREADY : IN STD_LOGIC;
s_axi_ctrl_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_ctrl_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_ctrl_BVALID : OUT STD_LOGIC;
s_axi_ctrl_BREADY : IN STD_LOGIC;
s_axi_ctrl_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
stream_out_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_out_TVALID : OUT STD_LOGIC;
stream_out_TREADY : IN STD_LOGIC );
end;
architecture behav of video_scaler is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"video_scaler,hls_ip_2018_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=6.670000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=6.380000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=24,HLS_SYN_DSP=68,HLS_SYN_FF=14153,HLS_SYN_LUT=10721,HLS_VERSION=2018_2}";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant C_S_AXI_WSTRB_WIDTH : INTEGER range 63 downto 0 := 4;
constant C_S_AXI_ADDR_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_lv24_0 : STD_LOGIC_VECTOR (23 downto 0) := "000000000000000000000000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_ready : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal in_width : STD_LOGIC_VECTOR (31 downto 0);
signal in_height : STD_LOGIC_VECTOR (31 downto 0);
signal out_width : STD_LOGIC_VECTOR (31 downto 0);
signal out_height : STD_LOGIC_VECTOR (31 downto 0);
signal Block_Mat_exit45_pro_U0_ap_start : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_ap_done : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_ap_continue : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_ap_idle : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_ap_ready : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_start_out : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_start_write : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_img_in_rows_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal Block_Mat_exit45_pro_U0_img_in_rows_V_out_write : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_img_in_cols_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal Block_Mat_exit45_pro_U0_img_in_cols_V_out_write : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_img_out_rows_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal Block_Mat_exit45_pro_U0_img_out_rows_V_out_write : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_img_out_cols_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal Block_Mat_exit45_pro_U0_img_out_cols_V_out_write : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_start : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_done : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_continue : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_idle : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_ready : STD_LOGIC;
signal AXIvideo2Mat_U0_stream_in_TREADY : STD_LOGIC;
signal AXIvideo2Mat_U0_img_rows_V_read : STD_LOGIC;
signal AXIvideo2Mat_U0_img_cols_V_read : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_0_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_1_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_2_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_rows_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal AXIvideo2Mat_U0_img_rows_V_out_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_cols_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal AXIvideo2Mat_U0_img_cols_V_out_write : STD_LOGIC;
signal Resize_U0_ap_start : STD_LOGIC;
signal Resize_U0_ap_done : STD_LOGIC;
signal Resize_U0_ap_continue : STD_LOGIC;
signal Resize_U0_ap_idle : STD_LOGIC;
signal Resize_U0_ap_ready : STD_LOGIC;
signal Resize_U0_start_out : STD_LOGIC;
signal Resize_U0_start_write : STD_LOGIC;
signal Resize_U0_p_src_rows_V_read : STD_LOGIC;
signal Resize_U0_p_src_cols_V_read : STD_LOGIC;
signal Resize_U0_p_src_data_stream_0_V_read : STD_LOGIC;
signal Resize_U0_p_src_data_stream_1_V_read : STD_LOGIC;
signal Resize_U0_p_src_data_stream_2_V_read : STD_LOGIC;
signal Resize_U0_p_dst_rows_V_read : STD_LOGIC;
signal Resize_U0_p_dst_cols_V_read : STD_LOGIC;
signal Resize_U0_p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Resize_U0_p_dst_data_stream_0_V_write : STD_LOGIC;
signal Resize_U0_p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Resize_U0_p_dst_data_stream_1_V_write : STD_LOGIC;
signal Resize_U0_p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Resize_U0_p_dst_data_stream_2_V_write : STD_LOGIC;
signal Resize_U0_p_dst_rows_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal Resize_U0_p_dst_rows_V_out_write : STD_LOGIC;
signal Resize_U0_p_dst_cols_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal Resize_U0_p_dst_cols_V_out_write : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_start : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_done : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_continue : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_idle : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_ready : STD_LOGIC;
signal Mat2AXIvideo_U0_img_rows_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_cols_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_0_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_1_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_2_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_stream_out_TDATA : STD_LOGIC_VECTOR (23 downto 0);
signal Mat2AXIvideo_U0_stream_out_TVALID : STD_LOGIC;
signal Mat2AXIvideo_U0_stream_out_TKEEP : STD_LOGIC_VECTOR (2 downto 0);
signal Mat2AXIvideo_U0_stream_out_TSTRB : STD_LOGIC_VECTOR (2 downto 0);
signal Mat2AXIvideo_U0_stream_out_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TID : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sync_continue : STD_LOGIC;
signal img_in_rows_V_c_full_n : STD_LOGIC;
signal img_in_rows_V_c_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_in_rows_V_c_empty_n : STD_LOGIC;
signal img_in_cols_V_c_full_n : STD_LOGIC;
signal img_in_cols_V_c_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_in_cols_V_c_empty_n : STD_LOGIC;
signal img_out_rows_V_c_full_n : STD_LOGIC;
signal img_out_rows_V_c_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_out_rows_V_c_empty_n : STD_LOGIC;
signal img_out_cols_V_c_full_n : STD_LOGIC;
signal img_out_cols_V_c_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_out_cols_V_c_empty_n : STD_LOGIC;
signal img_in_data_stream_0_full_n : STD_LOGIC;
signal img_in_data_stream_0_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_in_data_stream_0_empty_n : STD_LOGIC;
signal img_in_data_stream_1_full_n : STD_LOGIC;
signal img_in_data_stream_1_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_in_data_stream_1_empty_n : STD_LOGIC;
signal img_in_data_stream_2_full_n : STD_LOGIC;
signal img_in_data_stream_2_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_in_data_stream_2_empty_n : STD_LOGIC;
signal img_in_rows_V_c13_full_n : STD_LOGIC;
signal img_in_rows_V_c13_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_in_rows_V_c13_empty_n : STD_LOGIC;
signal img_in_cols_V_c14_full_n : STD_LOGIC;
signal img_in_cols_V_c14_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_in_cols_V_c14_empty_n : STD_LOGIC;
signal img_out_data_stream_s_full_n : STD_LOGIC;
signal img_out_data_stream_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_out_data_stream_s_empty_n : STD_LOGIC;
signal img_out_data_stream_1_full_n : STD_LOGIC;
signal img_out_data_stream_1_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_out_data_stream_1_empty_n : STD_LOGIC;
signal img_out_data_stream_2_full_n : STD_LOGIC;
signal img_out_data_stream_2_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_out_data_stream_2_empty_n : STD_LOGIC;
signal img_out_rows_V_c15_full_n : STD_LOGIC;
signal img_out_rows_V_c15_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_out_rows_V_c15_empty_n : STD_LOGIC;
signal img_out_cols_V_c16_full_n : STD_LOGIC;
signal img_out_cols_V_c16_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_out_cols_V_c16_empty_n : STD_LOGIC;
signal ap_sync_done : STD_LOGIC;
signal ap_sync_ready : STD_LOGIC;
signal ap_sync_reg_AXIvideo2Mat_U0_ap_ready : STD_LOGIC := '0';
signal ap_sync_AXIvideo2Mat_U0_ap_ready : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_ready_count : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready : STD_LOGIC := '0';
signal ap_sync_Block_Mat_exit45_pro_U0_ap_ready : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_ap_ready_count : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal start_for_Resize_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Resize_U0_full_n : STD_LOGIC;
signal start_for_Resize_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Resize_U0_empty_n : STD_LOGIC;
signal AXIvideo2Mat_U0_start_full_n : STD_LOGIC;
signal AXIvideo2Mat_U0_start_write : STD_LOGIC;
signal start_for_Mat2AXIvideo_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Mat2AXIvideo_U0_full_n : STD_LOGIC;
signal start_for_Mat2AXIvideo_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Mat2AXIvideo_U0_empty_n : STD_LOGIC;
signal Mat2AXIvideo_U0_start_full_n : STD_LOGIC;
signal Mat2AXIvideo_U0_start_write : STD_LOGIC;
component Block_Mat_exit45_pro IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
in_width : IN STD_LOGIC_VECTOR (31 downto 0);
in_height : IN STD_LOGIC_VECTOR (31 downto 0);
out_width : IN STD_LOGIC_VECTOR (31 downto 0);
out_height : IN STD_LOGIC_VECTOR (31 downto 0);
img_in_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_in_rows_V_out_full_n : IN STD_LOGIC;
img_in_rows_V_out_write : OUT STD_LOGIC;
img_in_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_in_cols_V_out_full_n : IN STD_LOGIC;
img_in_cols_V_out_write : OUT STD_LOGIC;
img_out_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_out_rows_V_out_full_n : IN STD_LOGIC;
img_out_rows_V_out_write : OUT STD_LOGIC;
img_out_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_out_cols_V_out_full_n : IN STD_LOGIC;
img_out_cols_V_out_write : OUT STD_LOGIC );
end component;
component AXIvideo2Mat IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC;
img_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_rows_V_out_full_n : IN STD_LOGIC;
img_rows_V_out_write : OUT STD_LOGIC;
img_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_cols_V_out_full_n : IN STD_LOGIC;
img_cols_V_out_write : OUT STD_LOGIC );
end component;
component Resize IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
p_src_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
p_src_rows_V_empty_n : IN STD_LOGIC;
p_src_rows_V_read : OUT STD_LOGIC;
p_src_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
p_src_cols_V_empty_n : IN STD_LOGIC;
p_src_cols_V_read : OUT STD_LOGIC;
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
p_dst_rows_V_empty_n : IN STD_LOGIC;
p_dst_rows_V_read : OUT STD_LOGIC;
p_dst_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
p_dst_cols_V_empty_n : IN STD_LOGIC;
p_dst_cols_V_read : OUT STD_LOGIC;
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC;
p_dst_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
p_dst_rows_V_out_full_n : IN STD_LOGIC;
p_dst_rows_V_out_write : OUT STD_LOGIC;
p_dst_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
p_dst_cols_V_out_full_n : IN STD_LOGIC;
p_dst_cols_V_out_write : OUT STD_LOGIC );
end component;
component Mat2AXIvideo IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
stream_out_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
stream_out_TVALID : OUT STD_LOGIC;
stream_out_TREADY : IN STD_LOGIC;
stream_out_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component fifo_w32_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (31 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (31 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w32_d3_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (31 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (31 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w8_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_Resize_U0 IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_Mat2AXImb6 IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component video_scaler_ctrl_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
in_width : OUT STD_LOGIC_VECTOR (31 downto 0);
in_height : OUT STD_LOGIC_VECTOR (31 downto 0);
out_width : OUT STD_LOGIC_VECTOR (31 downto 0);
out_height : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
video_scaler_ctrl_s_axi_U : component video_scaler_ctrl_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH)
port map (
AWVALID => s_axi_ctrl_AWVALID,
AWREADY => s_axi_ctrl_AWREADY,
AWADDR => s_axi_ctrl_AWADDR,
WVALID => s_axi_ctrl_WVALID,
WREADY => s_axi_ctrl_WREADY,
WDATA => s_axi_ctrl_WDATA,
WSTRB => s_axi_ctrl_WSTRB,
ARVALID => s_axi_ctrl_ARVALID,
ARREADY => s_axi_ctrl_ARREADY,
ARADDR => s_axi_ctrl_ARADDR,
RVALID => s_axi_ctrl_RVALID,
RREADY => s_axi_ctrl_RREADY,
RDATA => s_axi_ctrl_RDATA,
RRESP => s_axi_ctrl_RRESP,
BVALID => s_axi_ctrl_BVALID,
BREADY => s_axi_ctrl_BREADY,
BRESP => s_axi_ctrl_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
in_width => in_width,
in_height => in_height,
out_width => out_width,
out_height => out_height);
Block_Mat_exit45_pro_U0 : component Block_Mat_exit45_pro
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Block_Mat_exit45_pro_U0_ap_start,
start_full_n => start_for_Resize_U0_full_n,
ap_done => Block_Mat_exit45_pro_U0_ap_done,
ap_continue => Block_Mat_exit45_pro_U0_ap_continue,
ap_idle => Block_Mat_exit45_pro_U0_ap_idle,
ap_ready => Block_Mat_exit45_pro_U0_ap_ready,
start_out => Block_Mat_exit45_pro_U0_start_out,
start_write => Block_Mat_exit45_pro_U0_start_write,
in_width => in_width,
in_height => in_height,
out_width => out_width,
out_height => out_height,
img_in_rows_V_out_din => Block_Mat_exit45_pro_U0_img_in_rows_V_out_din,
img_in_rows_V_out_full_n => img_in_rows_V_c_full_n,
img_in_rows_V_out_write => Block_Mat_exit45_pro_U0_img_in_rows_V_out_write,
img_in_cols_V_out_din => Block_Mat_exit45_pro_U0_img_in_cols_V_out_din,
img_in_cols_V_out_full_n => img_in_cols_V_c_full_n,
img_in_cols_V_out_write => Block_Mat_exit45_pro_U0_img_in_cols_V_out_write,
img_out_rows_V_out_din => Block_Mat_exit45_pro_U0_img_out_rows_V_out_din,
img_out_rows_V_out_full_n => img_out_rows_V_c_full_n,
img_out_rows_V_out_write => Block_Mat_exit45_pro_U0_img_out_rows_V_out_write,
img_out_cols_V_out_din => Block_Mat_exit45_pro_U0_img_out_cols_V_out_din,
img_out_cols_V_out_full_n => img_out_cols_V_c_full_n,
img_out_cols_V_out_write => Block_Mat_exit45_pro_U0_img_out_cols_V_out_write);
AXIvideo2Mat_U0 : component AXIvideo2Mat
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => AXIvideo2Mat_U0_ap_start,
ap_done => AXIvideo2Mat_U0_ap_done,
ap_continue => AXIvideo2Mat_U0_ap_continue,
ap_idle => AXIvideo2Mat_U0_ap_idle,
ap_ready => AXIvideo2Mat_U0_ap_ready,
stream_in_TDATA => stream_in_TDATA,
stream_in_TVALID => stream_in_TVALID,
stream_in_TREADY => AXIvideo2Mat_U0_stream_in_TREADY,
stream_in_TKEEP => stream_in_TKEEP,
stream_in_TSTRB => stream_in_TSTRB,
stream_in_TUSER => stream_in_TUSER,
stream_in_TLAST => stream_in_TLAST,
stream_in_TID => stream_in_TID,
stream_in_TDEST => stream_in_TDEST,
img_rows_V_dout => img_in_rows_V_c_dout,
img_rows_V_empty_n => img_in_rows_V_c_empty_n,
img_rows_V_read => AXIvideo2Mat_U0_img_rows_V_read,
img_cols_V_dout => img_in_cols_V_c_dout,
img_cols_V_empty_n => img_in_cols_V_c_empty_n,
img_cols_V_read => AXIvideo2Mat_U0_img_cols_V_read,
img_data_stream_0_V_din => AXIvideo2Mat_U0_img_data_stream_0_V_din,
img_data_stream_0_V_full_n => img_in_data_stream_0_full_n,
img_data_stream_0_V_write => AXIvideo2Mat_U0_img_data_stream_0_V_write,
img_data_stream_1_V_din => AXIvideo2Mat_U0_img_data_stream_1_V_din,
img_data_stream_1_V_full_n => img_in_data_stream_1_full_n,
img_data_stream_1_V_write => AXIvideo2Mat_U0_img_data_stream_1_V_write,
img_data_stream_2_V_din => AXIvideo2Mat_U0_img_data_stream_2_V_din,
img_data_stream_2_V_full_n => img_in_data_stream_2_full_n,
img_data_stream_2_V_write => AXIvideo2Mat_U0_img_data_stream_2_V_write,
img_rows_V_out_din => AXIvideo2Mat_U0_img_rows_V_out_din,
img_rows_V_out_full_n => img_in_rows_V_c13_full_n,
img_rows_V_out_write => AXIvideo2Mat_U0_img_rows_V_out_write,
img_cols_V_out_din => AXIvideo2Mat_U0_img_cols_V_out_din,
img_cols_V_out_full_n => img_in_cols_V_c14_full_n,
img_cols_V_out_write => AXIvideo2Mat_U0_img_cols_V_out_write);
Resize_U0 : component Resize
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Resize_U0_ap_start,
start_full_n => start_for_Mat2AXIvideo_U0_full_n,
ap_done => Resize_U0_ap_done,
ap_continue => Resize_U0_ap_continue,
ap_idle => Resize_U0_ap_idle,
ap_ready => Resize_U0_ap_ready,
start_out => Resize_U0_start_out,
start_write => Resize_U0_start_write,
p_src_rows_V_dout => img_in_rows_V_c13_dout,
p_src_rows_V_empty_n => img_in_rows_V_c13_empty_n,
p_src_rows_V_read => Resize_U0_p_src_rows_V_read,
p_src_cols_V_dout => img_in_cols_V_c14_dout,
p_src_cols_V_empty_n => img_in_cols_V_c14_empty_n,
p_src_cols_V_read => Resize_U0_p_src_cols_V_read,
p_src_data_stream_0_V_dout => img_in_data_stream_0_dout,
p_src_data_stream_0_V_empty_n => img_in_data_stream_0_empty_n,
p_src_data_stream_0_V_read => Resize_U0_p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout => img_in_data_stream_1_dout,
p_src_data_stream_1_V_empty_n => img_in_data_stream_1_empty_n,
p_src_data_stream_1_V_read => Resize_U0_p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout => img_in_data_stream_2_dout,
p_src_data_stream_2_V_empty_n => img_in_data_stream_2_empty_n,
p_src_data_stream_2_V_read => Resize_U0_p_src_data_stream_2_V_read,
p_dst_rows_V_dout => img_out_rows_V_c_dout,
p_dst_rows_V_empty_n => img_out_rows_V_c_empty_n,
p_dst_rows_V_read => Resize_U0_p_dst_rows_V_read,
p_dst_cols_V_dout => img_out_cols_V_c_dout,
p_dst_cols_V_empty_n => img_out_cols_V_c_empty_n,
p_dst_cols_V_read => Resize_U0_p_dst_cols_V_read,
p_dst_data_stream_0_V_din => Resize_U0_p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n => img_out_data_stream_s_full_n,
p_dst_data_stream_0_V_write => Resize_U0_p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din => Resize_U0_p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n => img_out_data_stream_1_full_n,
p_dst_data_stream_1_V_write => Resize_U0_p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din => Resize_U0_p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n => img_out_data_stream_2_full_n,
p_dst_data_stream_2_V_write => Resize_U0_p_dst_data_stream_2_V_write,
p_dst_rows_V_out_din => Resize_U0_p_dst_rows_V_out_din,
p_dst_rows_V_out_full_n => img_out_rows_V_c15_full_n,
p_dst_rows_V_out_write => Resize_U0_p_dst_rows_V_out_write,
p_dst_cols_V_out_din => Resize_U0_p_dst_cols_V_out_din,
p_dst_cols_V_out_full_n => img_out_cols_V_c16_full_n,
p_dst_cols_V_out_write => Resize_U0_p_dst_cols_V_out_write);
Mat2AXIvideo_U0 : component Mat2AXIvideo
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Mat2AXIvideo_U0_ap_start,
ap_done => Mat2AXIvideo_U0_ap_done,
ap_continue => Mat2AXIvideo_U0_ap_continue,
ap_idle => Mat2AXIvideo_U0_ap_idle,
ap_ready => Mat2AXIvideo_U0_ap_ready,
img_rows_V_dout => img_out_rows_V_c15_dout,
img_rows_V_empty_n => img_out_rows_V_c15_empty_n,
img_rows_V_read => Mat2AXIvideo_U0_img_rows_V_read,
img_cols_V_dout => img_out_cols_V_c16_dout,
img_cols_V_empty_n => img_out_cols_V_c16_empty_n,
img_cols_V_read => Mat2AXIvideo_U0_img_cols_V_read,
img_data_stream_0_V_dout => img_out_data_stream_s_dout,
img_data_stream_0_V_empty_n => img_out_data_stream_s_empty_n,
img_data_stream_0_V_read => Mat2AXIvideo_U0_img_data_stream_0_V_read,
img_data_stream_1_V_dout => img_out_data_stream_1_dout,
img_data_stream_1_V_empty_n => img_out_data_stream_1_empty_n,
img_data_stream_1_V_read => Mat2AXIvideo_U0_img_data_stream_1_V_read,
img_data_stream_2_V_dout => img_out_data_stream_2_dout,
img_data_stream_2_V_empty_n => img_out_data_stream_2_empty_n,
img_data_stream_2_V_read => Mat2AXIvideo_U0_img_data_stream_2_V_read,
stream_out_TDATA => Mat2AXIvideo_U0_stream_out_TDATA,
stream_out_TVALID => Mat2AXIvideo_U0_stream_out_TVALID,
stream_out_TREADY => stream_out_TREADY,
stream_out_TKEEP => Mat2AXIvideo_U0_stream_out_TKEEP,
stream_out_TSTRB => Mat2AXIvideo_U0_stream_out_TSTRB,
stream_out_TUSER => Mat2AXIvideo_U0_stream_out_TUSER,
stream_out_TLAST => Mat2AXIvideo_U0_stream_out_TLAST,
stream_out_TID => Mat2AXIvideo_U0_stream_out_TID,
stream_out_TDEST => Mat2AXIvideo_U0_stream_out_TDEST);
img_in_rows_V_c_U : component fifo_w32_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit45_pro_U0_img_in_rows_V_out_din,
if_full_n => img_in_rows_V_c_full_n,
if_write => Block_Mat_exit45_pro_U0_img_in_rows_V_out_write,
if_dout => img_in_rows_V_c_dout,
if_empty_n => img_in_rows_V_c_empty_n,
if_read => AXIvideo2Mat_U0_img_rows_V_read);
img_in_cols_V_c_U : component fifo_w32_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit45_pro_U0_img_in_cols_V_out_din,
if_full_n => img_in_cols_V_c_full_n,
if_write => Block_Mat_exit45_pro_U0_img_in_cols_V_out_write,
if_dout => img_in_cols_V_c_dout,
if_empty_n => img_in_cols_V_c_empty_n,
if_read => AXIvideo2Mat_U0_img_cols_V_read);
img_out_rows_V_c_U : component fifo_w32_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit45_pro_U0_img_out_rows_V_out_din,
if_full_n => img_out_rows_V_c_full_n,
if_write => Block_Mat_exit45_pro_U0_img_out_rows_V_out_write,
if_dout => img_out_rows_V_c_dout,
if_empty_n => img_out_rows_V_c_empty_n,
if_read => Resize_U0_p_dst_rows_V_read);
img_out_cols_V_c_U : component fifo_w32_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit45_pro_U0_img_out_cols_V_out_din,
if_full_n => img_out_cols_V_c_full_n,
if_write => Block_Mat_exit45_pro_U0_img_out_cols_V_out_write,
if_dout => img_out_cols_V_c_dout,
if_empty_n => img_out_cols_V_c_empty_n,
if_read => Resize_U0_p_dst_cols_V_read);
img_in_data_stream_0_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_0_V_din,
if_full_n => img_in_data_stream_0_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_0_V_write,
if_dout => img_in_data_stream_0_dout,
if_empty_n => img_in_data_stream_0_empty_n,
if_read => Resize_U0_p_src_data_stream_0_V_read);
img_in_data_stream_1_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_1_V_din,
if_full_n => img_in_data_stream_1_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_1_V_write,
if_dout => img_in_data_stream_1_dout,
if_empty_n => img_in_data_stream_1_empty_n,
if_read => Resize_U0_p_src_data_stream_1_V_read);
img_in_data_stream_2_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_2_V_din,
if_full_n => img_in_data_stream_2_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_2_V_write,
if_dout => img_in_data_stream_2_dout,
if_empty_n => img_in_data_stream_2_empty_n,
if_read => Resize_U0_p_src_data_stream_2_V_read);
img_in_rows_V_c13_U : component fifo_w32_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_rows_V_out_din,
if_full_n => img_in_rows_V_c13_full_n,
if_write => AXIvideo2Mat_U0_img_rows_V_out_write,
if_dout => img_in_rows_V_c13_dout,
if_empty_n => img_in_rows_V_c13_empty_n,
if_read => Resize_U0_p_src_rows_V_read);
img_in_cols_V_c14_U : component fifo_w32_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_cols_V_out_din,
if_full_n => img_in_cols_V_c14_full_n,
if_write => AXIvideo2Mat_U0_img_cols_V_out_write,
if_dout => img_in_cols_V_c14_dout,
if_empty_n => img_in_cols_V_c14_empty_n,
if_read => Resize_U0_p_src_cols_V_read);
img_out_data_stream_s_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Resize_U0_p_dst_data_stream_0_V_din,
if_full_n => img_out_data_stream_s_full_n,
if_write => Resize_U0_p_dst_data_stream_0_V_write,
if_dout => img_out_data_stream_s_dout,
if_empty_n => img_out_data_stream_s_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_0_V_read);
img_out_data_stream_1_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Resize_U0_p_dst_data_stream_1_V_din,
if_full_n => img_out_data_stream_1_full_n,
if_write => Resize_U0_p_dst_data_stream_1_V_write,
if_dout => img_out_data_stream_1_dout,
if_empty_n => img_out_data_stream_1_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_1_V_read);
img_out_data_stream_2_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Resize_U0_p_dst_data_stream_2_V_din,
if_full_n => img_out_data_stream_2_full_n,
if_write => Resize_U0_p_dst_data_stream_2_V_write,
if_dout => img_out_data_stream_2_dout,
if_empty_n => img_out_data_stream_2_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_2_V_read);
img_out_rows_V_c15_U : component fifo_w32_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Resize_U0_p_dst_rows_V_out_din,
if_full_n => img_out_rows_V_c15_full_n,
if_write => Resize_U0_p_dst_rows_V_out_write,
if_dout => img_out_rows_V_c15_dout,
if_empty_n => img_out_rows_V_c15_empty_n,
if_read => Mat2AXIvideo_U0_img_rows_V_read);
img_out_cols_V_c16_U : component fifo_w32_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Resize_U0_p_dst_cols_V_out_din,
if_full_n => img_out_cols_V_c16_full_n,
if_write => Resize_U0_p_dst_cols_V_out_write,
if_dout => img_out_cols_V_c16_dout,
if_empty_n => img_out_cols_V_c16_empty_n,
if_read => Mat2AXIvideo_U0_img_cols_V_read);
start_for_Resize_U0_U : component start_for_Resize_U0
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_Resize_U0_din,
if_full_n => start_for_Resize_U0_full_n,
if_write => Block_Mat_exit45_pro_U0_start_write,
if_dout => start_for_Resize_U0_dout,
if_empty_n => start_for_Resize_U0_empty_n,
if_read => Resize_U0_ap_ready);
start_for_Mat2AXImb6_U : component start_for_Mat2AXImb6
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_Mat2AXIvideo_U0_din,
if_full_n => start_for_Mat2AXIvideo_U0_full_n,
if_write => Resize_U0_start_write,
if_dout => start_for_Mat2AXIvideo_U0_dout,
if_empty_n => start_for_Mat2AXIvideo_U0_empty_n,
if_read => Mat2AXIvideo_U0_ap_ready);
ap_sync_reg_AXIvideo2Mat_U0_ap_ready_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_sync_reg_AXIvideo2Mat_U0_ap_ready <= ap_const_logic_0;
else
if (((ap_sync_ready and ap_start) = ap_const_logic_1)) then
ap_sync_reg_AXIvideo2Mat_U0_ap_ready <= ap_const_logic_0;
else
ap_sync_reg_AXIvideo2Mat_U0_ap_ready <= ap_sync_AXIvideo2Mat_U0_ap_ready;
end if;
end if;
end if;
end process;
ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready <= ap_const_logic_0;
else
if (((ap_sync_ready and ap_start) = ap_const_logic_1)) then
ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready <= ap_const_logic_0;
else
ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready <= ap_sync_Block_Mat_exit45_pro_U0_ap_ready;
end if;
end if;
end if;
end process;
AXIvideo2Mat_U0_ap_ready_count_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_0 = AXIvideo2Mat_U0_ap_ready) and (ap_sync_ready = ap_const_logic_1))) then
AXIvideo2Mat_U0_ap_ready_count <= std_logic_vector(unsigned(AXIvideo2Mat_U0_ap_ready_count) - unsigned(ap_const_lv2_1));
elsif (((ap_const_logic_1 = AXIvideo2Mat_U0_ap_ready) and (ap_sync_ready = ap_const_logic_0))) then
AXIvideo2Mat_U0_ap_ready_count <= std_logic_vector(unsigned(AXIvideo2Mat_U0_ap_ready_count) + unsigned(ap_const_lv2_1));
end if;
end if;
end process;
Block_Mat_exit45_pro_U0_ap_ready_count_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_0 = Block_Mat_exit45_pro_U0_ap_ready) and (ap_sync_ready = ap_const_logic_1))) then
Block_Mat_exit45_pro_U0_ap_ready_count <= std_logic_vector(unsigned(Block_Mat_exit45_pro_U0_ap_ready_count) - unsigned(ap_const_lv2_1));
elsif (((ap_const_logic_1 = Block_Mat_exit45_pro_U0_ap_ready) and (ap_sync_ready = ap_const_logic_0))) then
Block_Mat_exit45_pro_U0_ap_ready_count <= std_logic_vector(unsigned(Block_Mat_exit45_pro_U0_ap_ready_count) + unsigned(ap_const_lv2_1));
end if;
end if;
end process;
AXIvideo2Mat_U0_ap_continue <= ap_const_logic_1;
AXIvideo2Mat_U0_ap_start <= ((ap_sync_reg_AXIvideo2Mat_U0_ap_ready xor ap_const_logic_1) and ap_start);
AXIvideo2Mat_U0_start_full_n <= ap_const_logic_1;
AXIvideo2Mat_U0_start_write <= ap_const_logic_0;
Block_Mat_exit45_pro_U0_ap_continue <= ap_const_logic_1;
Block_Mat_exit45_pro_U0_ap_start <= ((ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready xor ap_const_logic_1) and ap_start);
Mat2AXIvideo_U0_ap_continue <= ap_const_logic_1;
Mat2AXIvideo_U0_ap_start <= start_for_Mat2AXIvideo_U0_empty_n;
Mat2AXIvideo_U0_start_full_n <= ap_const_logic_1;
Mat2AXIvideo_U0_start_write <= ap_const_logic_0;
Resize_U0_ap_continue <= ap_const_logic_1;
Resize_U0_ap_start <= start_for_Resize_U0_empty_n;
ap_done <= Mat2AXIvideo_U0_ap_done;
ap_idle <= (Resize_U0_ap_idle and Mat2AXIvideo_U0_ap_idle and Block_Mat_exit45_pro_U0_ap_idle and AXIvideo2Mat_U0_ap_idle);
ap_ready <= ap_sync_ready;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sync_AXIvideo2Mat_U0_ap_ready <= (ap_sync_reg_AXIvideo2Mat_U0_ap_ready or AXIvideo2Mat_U0_ap_ready);
ap_sync_Block_Mat_exit45_pro_U0_ap_ready <= (ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready or Block_Mat_exit45_pro_U0_ap_ready);
ap_sync_continue <= ap_const_logic_1;
ap_sync_done <= Mat2AXIvideo_U0_ap_done;
ap_sync_ready <= (ap_sync_Block_Mat_exit45_pro_U0_ap_ready and ap_sync_AXIvideo2Mat_U0_ap_ready);
start_for_Mat2AXIvideo_U0_din <= (0=>ap_const_logic_1, others=>'-');
start_for_Resize_U0_din <= (0=>ap_const_logic_1, others=>'-');
stream_in_TREADY <= AXIvideo2Mat_U0_stream_in_TREADY;
stream_out_TDATA <= Mat2AXIvideo_U0_stream_out_TDATA;
stream_out_TDEST <= Mat2AXIvideo_U0_stream_out_TDEST;
stream_out_TID <= Mat2AXIvideo_U0_stream_out_TID;
stream_out_TKEEP <= Mat2AXIvideo_U0_stream_out_TKEEP;
stream_out_TLAST <= Mat2AXIvideo_U0_stream_out_TLAST;
stream_out_TSTRB <= Mat2AXIvideo_U0_stream_out_TSTRB;
stream_out_TUSER <= Mat2AXIvideo_U0_stream_out_TUSER;
stream_out_TVALID <= Mat2AXIvideo_U0_stream_out_TVALID;
end behav;
| mit |
Digilent/vivado-library | ip/dvi2rgb/src/ResyncToBUFG.vhd | 14 | 3719 | -------------------------------------------------------------------------------
--
-- File: ResyncToBUFG.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 7 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module inserts a BUFG on the PixelClk path so that the pixel bus can be
-- routed globally on the device. It also synchronizes data to the new BUFG
-- clock.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ResyncToBUFG is
Port (
-- Video in
piData : in std_logic_vector(23 downto 0);
piVDE : in std_logic;
piHSync : in std_logic;
piVSync : in std_logic;
PixelClkIn : in std_logic;
-- Video out
poData : out std_logic_vector(23 downto 0);
poVDE : out std_logic;
poHSync : out std_logic;
poVSync : out std_logic;
PixelClkOut : out std_logic
);
end ResyncToBUFG;
architecture Behavioral of ResyncToBUFG is
signal PixelClkInt : std_logic;
begin
-- Insert BUFG on clock path
InstBUFG: BUFG
port map (
O => PixelClkInt, -- 1-bit output: Clock output
I => PixelClkIn -- 1-bit input: Clock input
);
PixelClkOut <= PixelClkInt;
-- Try simple registering
RegisterData: process(PixelClkInt)
begin
if Rising_Edge(PixelClkInt) then
poData <= piData;
poVDE <= piVDE;
poHSync <= piHSync;
poVSync <= piVSync;
end if;
end process RegisterData;
end Behavioral;
| mit |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_stretch_AXILiteS_s_axi.vhd | 1 | 10199 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity hls_contrast_stretch_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
-- user signals
height :out STD_LOGIC_VECTOR(15 downto 0);
width :out STD_LOGIC_VECTOR(15 downto 0);
min :out STD_LOGIC_VECTOR(7 downto 0);
max :out STD_LOGIC_VECTOR(7 downto 0)
);
end entity hls_contrast_stretch_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : reserved
-- 0x04 : reserved
-- 0x08 : reserved
-- 0x0c : reserved
-- 0x10 : Data signal of height
-- bit 15~0 - height[15:0] (Read/Write)
-- others - reserved
-- 0x14 : reserved
-- 0x18 : Data signal of width
-- bit 15~0 - width[15:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- 0x20 : Data signal of min
-- bit 7~0 - min[7:0] (Read/Write)
-- others - reserved
-- 0x24 : reserved
-- 0x28 : Data signal of max
-- bit 7~0 - max[7:0] (Read/Write)
-- others - reserved
-- 0x2c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of hls_contrast_stretch_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_HEIGHT_DATA_0 : INTEGER := 16#10#;
constant ADDR_HEIGHT_CTRL : INTEGER := 16#14#;
constant ADDR_WIDTH_DATA_0 : INTEGER := 16#18#;
constant ADDR_WIDTH_CTRL : INTEGER := 16#1c#;
constant ADDR_MIN_DATA_0 : INTEGER := 16#20#;
constant ADDR_MIN_CTRL : INTEGER := 16#24#;
constant ADDR_MAX_DATA_0 : INTEGER := 16#28#;
constant ADDR_MAX_CTRL : INTEGER := 16#2c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_height : UNSIGNED(15 downto 0) := (others => '0');
signal int_width : UNSIGNED(15 downto 0) := (others => '0');
signal int_min : UNSIGNED(7 downto 0) := (others => '0');
signal int_max : UNSIGNED(7 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_HEIGHT_DATA_0 =>
rdata_data <= RESIZE(int_height(15 downto 0), 32);
when ADDR_WIDTH_DATA_0 =>
rdata_data <= RESIZE(int_width(15 downto 0), 32);
when ADDR_MIN_DATA_0 =>
rdata_data <= RESIZE(int_min(7 downto 0), 32);
when ADDR_MAX_DATA_0 =>
rdata_data <= RESIZE(int_max(7 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
height <= STD_LOGIC_VECTOR(int_height);
width <= STD_LOGIC_VECTOR(int_width);
min <= STD_LOGIC_VECTOR(int_min);
max <= STD_LOGIC_VECTOR(int_max);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_HEIGHT_DATA_0) then
int_height(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_height(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_WIDTH_DATA_0) then
int_width(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_width(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_MIN_DATA_0) then
int_min(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_min(7 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_MAX_DATA_0) then
int_max(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_max(7 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| mit |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/vhdl/Loop_loop_height_fYi.vhd | 1 | 6097 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_fYi_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_fYi_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "00000000", 1 => "00000010", 2 => "00000100", 3 => "00000111",
4 => "00001001", 5 => "00001011", 6 => "00001101", 7 => "00001111",
8 => "00010001", 9 => "00010011", 10 => "00010110", 11 => "00011000",
12 => "00011010", 13 => "00011100", 14 => "00011110", 15 => "00100000",
16 => "00100010", 17 => "00100100", 18 => "00100110", 19 => "00101000",
20 => "00101010", 21 => "00101100", 22 => "00101110", 23 => "00110000",
24 => "00110010", 25 => "00110100", 26 => "00110110", 27 => "00111000",
28 => "00111010", 29 => "00111100", 30 => "00111110", 31 => "01000000",
32 => "01000010", 33 => "01000011", 34 => "01000101", 35 => "01000111",
36 => "01001001", 37 => "01001011", 38 => "01001101", 39 => "01001111",
40 => "01010000", 41 => "01010010", 42 => "01010100", 43 => "01010110",
44 => "01011000", 45 => "01011001", 46 => "01011011", 47 => "01011101",
48 => "01011111", 49 => "01100001", 50 => "01100010", 51 => "01100100",
52 => "01100110", 53 => "01100111", 54 => "01101001", 55 => "01101011",
56 => "01101100", 57 => "01101110", 58 => "01110000", 59 => "01110001",
60 => "01110011", 61 => "01110101", 62 => "01110110", 63 => "01111000",
64 => "01111010", 65 => "01111011", 66 => "01111101", 67 => "01111110",
68 => "10000000", 69 => "10000001", 70 => "10000011", 71 => "10000100",
72 => "10000110", 73 => "10001000", 74 => "10001001", 75 => "10001011",
76 => "10001100", 77 => "10001101", 78 => "10001111", 79 => "10010000",
80 => "10010010", 81 => "10010011", 82 => "10010101", 83 => "10010110",
84 => "10011000", 85 => "10011001", 86 => "10011010", 87 => "10011100",
88 => "10011101", 89 => "10011111", 90 => "10100000", 91 => "10100001",
92 => "10100011", 93 => "10100100", 94 => "10100101", 95 => "10100111",
96 => "10101000", 97 => "10101001", 98 => "10101010", 99 => "10101100",
100 => "10101101", 101 => "10101110", 102 => "10101111", 103 => "10110001",
104 => "10110010", 105 => "10110011", 106 => "10110100", 107 => "10110110",
108 => "10110111", 109 => "10111000", 110 => "10111001", 111 => "10111010",
112 => "10111011", 113 => "10111101", 114 => "10111110", 115 => "10111111",
116 => "11000000", 117 => "11000001", 118 => "11000010", 119 => "11000011",
120 => "11000100", 121 => "11000101", 122 => "11000110", 123 => "11000111",
124 => "11001000", 125 => "11001001", 126 => "11001010", 127 => "11001011",
128 => "11001100", 129 => "11001101", 130 => "11001110", 131 => "11001111",
132 => "11010000", 133 => "11010001", 134 => "11010010", 135 => "11010011",
136 => "11010100", 137 => "11010101", 138 => "11010110", 139 => "11010111",
140 => "11011000", 141 => "11011001", 142 to 143=> "11011010", 144 => "11011011",
145 => "11011100", 146 => "11011101", 147 => "11011110", 148 to 149=> "11011111",
150 => "11100000", 151 => "11100001", 152 to 153=> "11100010", 154 => "11100011",
155 => "11100100", 156 to 157=> "11100101", 158 => "11100110", 159 => "11100111",
160 to 161=> "11101000", 162 => "11101001", 163 to 164=> "11101010", 165 => "11101011",
166 to 167=> "11101100", 168 to 169=> "11101101", 170 => "11101110", 171 to 172=> "11101111",
173 to 174=> "11110000", 175 to 176=> "11110001", 177 to 178=> "11110010", 179 => "11110011",
180 to 181=> "11110100", 182 to 184=> "11110101", 185 to 186=> "11110110", 187 to 188=> "11110111",
189 to 190=> "11111000", 191 to 193=> "11111001", 194 to 196=> "11111010", 197 to 199=> "11111011",
200 to 202=> "11111100", 203 to 205=> "11111101", 206 to 210=> "11111110", 211 to 255=> "11111111" );
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_fYi is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_fYi is
component Loop_loop_height_fYi_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_fYi_rom_U : component Loop_loop_height_fYi_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
| mit |
Digilent/vivado-library | ip/Zmods/ZmodDigitizerController/tb/tb_TestAD96xx_92xxSPI_Model.vhd | 1 | 17874 |
-------------------------------------------------------------------------------
--
-- File: tb_TestAD96xx_92xxSPI_Model.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Test bench used to validate the AD96xx_92xxSPI_Model simulation model.
-- Errors encoded by the kErrorType generic are deliberately inserted in subsequent
-- SPI transactions.
-- This test bench will be instantiated as multiple entities in the
-- tb_TestAD96xx_92xxSPI_Model_all to cover all supported error types.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodDigitizer.all;
entity tb_TestAD96xx_92xxSPI_Model is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 0;
-- kErrorType encodes the error introduced by the test bench:
-- 0-No error.
-- 1-Insert sSDIO to sSPI_Clk Setup Time error for Cmd[2] and Data[2] bits of kSclkHigh.
-- 2-Insert CS to sSPI_Clk and data to sSPI_Clk (on Cmd[15]) setup time error of 1ns.
-- 3-Insert sSDIO to sSPI_Clk hold time error of 1ns for command bit 2.
-- 4-Insert sCS to sSPI_Clk hold time error of 1ns; sSPI_Clk pulse width errors
-- and hold time error also inserted on Data[0].
-- 5-Insert pulse width errors (0.5ns) and TestSPI_Clk period errors Cmd[2] and Data[2].
-- 6-Send extra address bit (25 bit transfer).
kErrorType : integer := 1;
--kCmdRdWr selects between read and write operations: '1' -> read; '0' -> write.
kCmdRdWr : std_logic := '0';
-- Command address; Error reporting depends on the kCmdAddr's value!
-- Transition on the error affected bits is necessary!
kCmdAddr : std_logic_vector (12 downto 0) := "0000000000101";
-- Command address; Error reporting depends on the kCmdAddr's value!
kCmdData : std_logic_vector (7 downto 0) := x"AA";
-- The number of data bits for the data phase of the transaction:
-- only 8 data bits currently supported.
kNoDataBits : integer := 8;
-- The number of bits of the command phase of the SPI transaction.
kNoCommandBits : integer := 16
);
end tb_TestAD96xx_92xxSPI_Model;
architecture Behavioral of tb_TestAD96xx_92xxSPI_Model is
signal asRst_n : std_logic := '0';
signal TestSPI_Clk, tSDIO : std_logic := 'X';
signal tCS : std_logic := '1';
signal tCommand : std_logic_vector(15 downto 0);
signal tData : std_logic_vector(7 downto 0);
signal SysClk100 : std_logic := '1';
begin
Clock: process
begin
for i in 0 to 1000 loop
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
end loop;
wait;
end process;
AD96xx_AD92xx_inst: entity work.AD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
InsertError => '0',
sSPI_Clk => TestSPI_Clk,
sSDIO => tSDIO,
sCS => tCS
);
Main: process
begin
-- Assert the reset signal
asRst_n <= '0';
-- Hold the reset condition for 10 clock cycles
-- (one clock cycle is sufficient, however 10 clock cycles makes
-- it easier to visualize the reset condition in simulation).
wait for kSysClkPeriod*10;
asRst_n <= '1';
if (kErrorType = 0) then
if (kCmdRdWr = '1') then
-- Read operation: SPI read register correct sequence.
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for ktS;
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end loop;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= 'Z';
wait for kSclkLow*3;
end loop;
wait for ktH;
tSDIO <= '0';
tCS <= '1';
else
-- Write operation: SPI read register correct sequence.
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for ktS;
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end loop;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i > 0) then
tSDIO <= tData(i-1);
else
tSDIO <= 'Z';
end if;
wait for kSclkLow*3;
end loop;
wait for ktH;
tSDIO <= '0';
tCS <= '1';
end if;
elsif (kErrorType = 1) then
if (kCmdRdWr = '1') then
-- Read operation not currently supported for this error type.
TestSPI_Clk <= '0';
tCS <= '1';
tSDIO <= '0';
else
-- Write operation: Insert tSDIO to TestSPI_Clk Setup Time error for Cmd[2]
-- and Data[2] bits of kSclkHigh.
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for ktS;
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
if (i = 1) then
report "Insert sSDIO to sSPI_Clk setup time error on Cmd[2]" & LF & HT & HT;
tSDIO <= tCommand(i+1);
end if;
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i /= 2) then
tSDIO <= tCommand(i);
end if;
wait for kSclkLow*3;
end loop;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
if (i = 2) then
report "Insert sSDIO to sSPI_Clk setup time error on Data[2]" & LF & HT & HT;
tSDIO <= tData(i);
end if;
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i > 0) then
if (i /= 3) then
tSDIO <= tData(i-1);
end if;
else
tSDIO <= 'Z';
end if;
wait for kSclkLow*3;
end loop;
wait for ktH;
tSDIO <= '0';
tCS <= '1';
end if;
elsif (kErrorType = 2) then
if (kCmdRdWr = '1') then
-- Read operation not currently supported for this error type.
TestSPI_Clk <= '0';
tCS <= '1';
tSDIO <= '0';
else
-- Write operation: Insert tCS to TestSPI_Clk and tSDIO to TestSPI_Clk
-- (on Cmd[15]) setup time error of 1ns.
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for (ktS - 1 ns);
report "Insert sCS and sSDIO (Cmd[15]) to sSPI_Clk setup time error" & LF & HT & HT;
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end loop;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i > 0) then
tSDIO <= tData(i-1);
else
tSDIO <= 'Z';
end if;
wait for kSclkLow*3;
end loop;
wait for ktH;
tSDIO <= '0';
tCS <= '1';
end if;
elsif (kErrorType = 3) then
if (kCmdRdWr = '1') then
-- Read operation not currently supported for this error type.
TestSPI_Clk <= '0';
tCS <= '1';
tSDIO <= '0';
else
-- Write operation: Insert sSDIO to TestSPI_Clk hold time error of 1ns
-- for command bit 2.
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for (ktS);
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
wait for (ktDH - 1 ns);
if (i = 1) then
report "Insert sSDIO (Cmd[2]) to sSPI_Clk hold time error" & LF & HT & HT;
tSDIO <= tCommand(i);
end if;
wait for (kSclkHigh*3 - ktDH + 1ns);
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end loop;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i > 0) then
tSDIO <= tData(i-1);
else
tSDIO <= 'Z';
end if;
wait for kSclkLow*3;
end loop;
wait for ktH;
tSDIO <= '0';
tCS <= '1';
end if;
elsif (kErrorType = 4) then
if (kCmdRdWr = '1') then
-- Read operation not currently supported for this error type.
TestSPI_Clk <= '0';
tCS <= '1';
tSDIO <= '0';
else
-- Write operation: Insert tCS to TestSPI_Clk hold time error of 1ns;
-- TestSPI_Clk pulse width errors and hold time error also inserted on Data[0].
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for (ktS);
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
wait for (kSclkHigh*3);
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end loop;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
if (i = 0) then
wait for ((ktH - 1ns)/2);
report "insert sSPI_Clk pulse width error and sSDIO (Data[0]) to sSPI_Clk hold time error" & LF & HT & HT;
else
wait for kSclkHigh*3;
end if;
TestSPI_Clk <= '0';
if (i > 0) then
tSDIO <= tData(i-1);
else
tSDIO <= 'Z';
end if;
if (i = 0) then
wait for ((ktH - 1ns)/2);
report "insert sCS to sSPI_Clk hold and sSPI_CLK pulse width errors" & LF & HT & HT;
tCS <= '1';
else
wait for kSclkLow*3;
end if;
end loop;
tSDIO <= '0';
tCS <= '1';
end if;
elsif (kErrorType = 5) then
if (kCmdRdWr = '1') then
-- Read operation not currently supported for this error type.
TestSPI_Clk <= '0';
tCS <= '1';
tSDIO <= '0';
else
-- Write operation: insert pulse width errors (0.5ns) and TestSPI_Clk
-- period errors on Cmd[2] and Data[2].
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for ktS;
for i in (kNoCommandBits - 2) downto 0 loop
if (i=1) then
-- Rising edge of address bit 2.
TestSPI_Clk <= '1';
wait for (kSclkHigh - 0.5ns);
report "Insert sSPI_Clk pulse width high error on Cmd[2]" & LF & HT & HT;
TestSPI_Clk <= '0';
-- Place address bit 1 on SDIO.
tSDIO <= tCommand(i);
wait for (kSclkLow - 0.5ns);
report "Insert sSPI_Clk pulse width low and period error on Cmd[2]" & LF & HT & HT;
else
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end if;
end loop;
for i in (kNoDataBits) downto 0 loop
if (i = 2) then
TestSPI_Clk <= '1';
wait for (kSclkHigh - 0.5ns);
report "Insert sSPI_Clk pulse width high error on Data[2]" & LF & HT & HT;
TestSPI_Clk <= '0';
tSDIO <= tData(i-1);
wait for (kSclkLow - 0.5ns);
report "Insert sSPI_Clk pulse width low and period error on Data[2]" & LF & HT & HT;
else
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i > 0) then
tSDIO <= tData(i-1);
else
tSDIO <= 'Z';
end if;
wait for kSclkLow*3;
end if;
end loop;
wait for ktH;
tSDIO <= '0';
tCS <= '1';
end if;
elsif (kErrorType = 6) then
if (kCmdRdWr = '1') then
-- Read operation not currently supported for this error type.
TestSPI_Clk <= '0';
tCS <= '1';
tSDIO <= '0';
else
-- Write operation: send extra command bit (25 bit transfer).
tCommand <= kCmdRdWr & "00" & kCmdAddr;
tData <= kCmdData;
TestSPI_Clk <= '0';
tSDIO <= '0';
tCS <= '1';
wait for kSysClkPeriod;
tCS <= '0';
tSDIO <= tCommand(15);
wait for ktS;
for i in (kNoCommandBits - 2) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= tCommand(i);
wait for kSclkLow*3;
end loop;
-- Add extra command bit.
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
tSDIO <= tCommand(0);
wait for kSclkLow*3;
for i in (kNoDataBits) downto 0 loop
TestSPI_Clk <= '1';
wait for kSclkHigh*3;
TestSPI_Clk <= '0';
if (i > 0) then
tSDIO <= tData(i-1);
else
tSDIO <= 'Z';
end if;
wait for kSclkLow*3;
end loop;
wait for ktH;
report "Insert Extra bit in transaction" & LF & HT & HT;
tSDIO <= '0';
tCS <= '1';
wait for 100 ns;
end if;
end if;
wait;
end process;
end Behavioral;
| mit |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign | Interpolation_not_complete/CPA.vhd | 1 | 1114 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:31:31 07/06/05
-- Design Name:
-- Module Name: CPA - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPA is
port( A , B : in std_logic_vector(7 downto 0);
-- C0 : in std_logic;
S : out std_logic_vector(7 downto 0);
C8 : out std_logic );
end CPA;
architecture Behavioral of CPA is
signal sum : std_logic_vector( 8 downto 0);
begin
sum <= ('0'& A) + ('0' & B) ;
C8 <= sum(8);
S <= sum(7 downto 0);
end Behavioral;
| mit |
Digilent/vivado-library | ip/MIPI_CSI_2_RX/hdl/DebugLib.vhd | 1 | 7790 | -------------------------------------------------------------------------------
--
-- File: DebugLib.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DebugLib is
COMPONENT ila_rxclk
PORT (
clk : IN STD_LOGIC;
trig_out : OUT STD_LOGIC;
trig_out_ack : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_vidclk
PORT (
clk : IN STD_LOGIC;
trig_in : IN STD_LOGIC;
trig_in_ack : OUT STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe20 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe21 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe30 : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
probe31 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe32 : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
probe33 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe34 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe35 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_rxclk_lane
PORT (
clk : IN STD_LOGIC;
trig_out : OUT STD_LOGIC;
trig_out_ack : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT ;
type DebugLMLane_t is record
rbSkwRdEn : std_logic;
rbSkwWrEn : std_logic;
rbSkwFull : std_logic;
rbActiveHS : std_logic;
rbSyncHS : std_logic;
rbValidHS : std_logic;
rbDataHS : std_logic_vector(7 downto 0);
end record;
constant C_M_AXIS_TDATA_WIDTH : natural := 40;
constant kMaxLaneCount : natural := 4;
type DebugLMLanes_t is array(0 to kMaxLaneCount - 1) of DebugLMLane_t;
type DebugLM_t is record
state : std_logic_vector(2 downto 0);
rbByteCnt : std_logic_vector(1 downto 0);
end record;
type DebugLLP_t is record
-- LLP CDC FIFO signals, RxByteClkHS domain
rbRst : std_logic;
rbOvf : std_logic;
rbFIFO_Rstn : std_logic;
-- LLP CDC FIFO signals, video_clk domain
mRst : std_logic;
mFIFO_Tvalid : std_logic;
mFIFO_Tready : std_logic;
mFIFO_Tlast : std_logic;
mFIFO_Tdata : std_logic_vector(kMaxLaneCount*8-1 downto 0);
mFIFO_Tkeep : std_logic_vector(kMaxLaneCount-1 downto 0);
mIsHeader : std_logic; -- '1' for CSI-2 header
mECC_En : std_logic; -- Enable signal for ECC processing
mECC_Ready : std_logic; -- ECC block ready to accept new data
mECC_Valid : std_logic; -- ECC processing done, output valid
mECC_Error : std_logic; -- ECC processing done, input had errors
mWC : std_logic_vector(15 downto 0); --Word Count from header
mDT : std_logic_vector(5 downto 0); --Data Type from header
mFlush : std_logic; -- flushes packet from CDC FIFO
mKeep : std_logic; -- passes flushed packet through
mWordCount : std_logic_vector(15 downto 0);
-- Counted, CRC- and header-stripped packet
mReg_Tvalid : std_logic;
mReg_Tready : std_logic;
mReg_Tlast : std_logic;
mReg_Tuser : std_logic;
mReg_Tdata : std_logic_vector(kMaxLaneCount*8-1 downto 0);
mReg_Tkeep : std_logic_vector(kMaxLaneCount-1 downto 0);
mCRC_Sent : std_logic_vector(15 downto 0); -- Transmitted packet CRC
mCRC_En : std_logic; -- Enable signal for CRC processing
mCRC_Rst : std_logic; -- Reset signal for CRC processing
mCRC_Out : std_logic_vector(15 downto 0); -- Receiver packet CRC
-- Video-formatted packet written to Line Buffer
mFmt_Tvalid : std_logic;
mFmt_Tready : std_logic;
mFmt_Tlast : std_logic;
mFmt_Tuser : std_logic;
mFmt_Tdata : std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
mFmt_cnt : std_logic_vector(2 downto 0);
mBufDataCnt : std_logic_vector(10 downto 0);
end record;
end package;
| mit |
Digilent/vivado-library | ip/dvi2rgb/src/TMDS_Clocking.vhd | 1 | 12258 | -------------------------------------------------------------------------------
--
-- File: TMDS_Clocking.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 10 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates all the necessary primitives to obtain a fast
-- serial clock from the TMDS Clock pins to be used for deserializing the TMDS
-- Data channels. Connect this module directly to the top-level TMDS Clock pins
-- and a 200/300 MHz reference clock.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity TMDS_Clocking is
Generic (
kClkRange : natural := 1); -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
Port (
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
RefClk : in std_logic; -- 200MHz reference clock for IDELAY primitives; independent of DVI_Clk!
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
SerialClk : out std_logic;
PixelClk : out std_logic;
aLocked : out std_logic;
dbg_rDlyRst : out std_logic;
dbg_rRdyRst : out std_logic;
dbg_rMMCM_Reset : out std_logic;
dbg_rBUFR_Rst : out std_logic;
dbg_rMMCM_Locked : out std_logic
);
end TMDS_Clocking;
architecture Behavioral of TMDS_Clocking is
constant kDlyRstDelay : natural := 32;
signal aDlyLckd, rDlyRst, rBUFR_Rst, rLockLostRst : std_logic;
signal rDlyRstCnt : natural range 0 to kDlyRstDelay - 1 := kDlyRstDelay - 1;
signal clkfbout_hdmi_clk, CLK_IN_hdmi_clk, CLK_OUT_1x_hdmi_clk, CLK_OUT_5x_hdmi_clk : std_logic;
signal clkout1b_unused, clkout2_unused, clkout2b_unused, clkout3_unused, clkout3b_unused, clkout4_unused, clkout5_unused, clkout6_unused,
drdy_unused, psdone_unused, clkfbstopped_unused, clkinstopped_unused, clkfboutb_unused, clkout0b_unused, clkout1_unused : std_logic;
signal do_unused : std_logic_vector(15 downto 0);
signal LOCKED_int, rRdyRst : std_logic;
signal aMMCM_Locked, rMMCM_Locked_ms, rMMCM_Locked, rMMCM_LckdFallingFlag, rMMCM_LckdRisingFlag : std_logic;
signal rMMCM_Reset_q : std_logic_vector(1 downto 0);
signal rMMCM_Locked_q : std_logic_vector(1 downto 0);
begin
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal rLockLostRst can be used as
-- asynchronous reset for any flip-flop in the RefClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => RefClk,
oRst => rLockLostRst);
--IDELAYCTRL must be reset after configuration or refclk lost for 52ns(K7), 72ns(A7) at least
ResetIDELAYCTRL: process(rLockLostRst, RefClk)
begin
if Rising_Edge(RefClk) then
if (rLockLostRst = '1') then
rDlyRstCnt <= kDlyRstDelay - 1;
rDlyRst <= '1';
elsif (rDlyRstCnt /= 0) then
rDlyRstCnt <= rDlyRstCnt - 1;
else
rDlyRst <= '0';
end if;
end if;
end process;
IDelayCtrlX: IDELAYCTRL
port map (
RDY => aDlyLckd,
REFCLK => RefClk,
RST => rDlyRst);
RdyLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aDlyLckd,
OutClk => RefClk,
oRst => rRdyRst);
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "TMDS_33")
port map
(
O => CLK_IN_hdmi_clk,
I => TMDS_Clk_p,
IB => TMDS_Clk_n);
-- The TMDS Clk channel carries a character-rate frequency reference
-- In a single Clk period a whole character (10 bits) is transmitted
-- on each data channel. For deserialization of data channel a faster,
-- serial clock needs to be generated. In 7-series architecture an
-- ISERDESE2 primitive doing a 10:1 deserialization in DDR mode needs
-- a fast 5x clock and a slow 1x clock. These two clocks are generated
-- below with an MMCME2_ADV and BUFR primitive.
-- Caveats:
-- 1. The primitive uses a multiply-by-5 and divide-by-1 to generate
-- a 5x fast clock.
-- While changes in the frequency of the TMDS Clk are tracked by the
-- MMCM, for some TMDS Clk frequencies the datasheet specs for the VCO
-- frequency limits are not met. In other words, there is no single
-- set of MMCM multiply and divide values that can work for the whole
-- range of resolutions and pixel clock frequencies.
-- For example: MMCM_FVCOMIN = 600 MHz
-- MMCM_FVCOMAX = 1200 MHz for Artix-7 -1 speed grade
-- while FVCO = FIN * MULT_F
-- The TMDS Clk for 720p resolution in 74.25 MHz
-- FVCO = 74.25 * 10 = 742.5 MHz, which is between FVCOMIN and FVCOMAX
-- However, the TMDS Clk for 1080p resolution in 148.5 MHz
-- FVCO = 148.5 * 10 = 1480 MHZ, which is above FVCOMAX
-- In the latter case, MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result
-- in a correct VCO frequency, while still generating 5x and 1x clocks
-- 2. The MMCM+BUFIO+BUFR combination results in the highest possible
-- frequencies. PLLE2_ADV could work only with BUFGs, which limits
-- the maximum achievable frequency. The reason is that only the MMCM
-- has dedicated route to BUFIO.
-- If a PLLE2_ADV with BUFGs are used a second CLKOUTx can be used to
-- generate the 1x clock.
DVI_ClkGenerator: MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => real(kClkRange) * 5.0,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(kClkRange) * 1.0,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => real(kClkRange) * 6.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_hdmi_clk,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => CLK_OUT_5x_hdmi_clk,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_hdmi_clk,
CLKIN1 => CLK_IN_hdmi_clk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => aMMCM_Locked,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => rMMCM_Reset_q(0));
-- 5x fast serial clock
SerialClkBuffer: BUFIO
port map (
O => SerialClk, -- 1-bit output: Clock output (connect to I/O clock loads).
I => CLK_OUT_5x_hdmi_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
-- 1x slow parallel clock
PixelClkBuffer: BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => PixelClk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => rBUFR_Rst, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => CLK_OUT_5x_hdmi_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
rBUFR_Rst <= rMMCM_LckdRisingFlag; --pulse CLR on BUFR once the clock returns
MMCM_Reset: process(rLockLostRst, RefClk)
begin
if (rLockLostRst = '1') then
rMMCM_Reset_q <= (others => '1'); -- MMCM_RSTMINPULSE Minimum Reset Pulse Width 5.00ns = two RefClk periods min
elsif Rising_Edge(RefClk) then
if (rMMCM_LckdFallingFlag = '1') then
rMMCM_Reset_q <= (others => '1');
else
rMMCM_Reset_q <= '0' & rMMCM_Reset_q(rMMCM_Reset_q'high downto 1);
end if;
end if;
end process MMCM_Reset;
MMCM_LockSync: entity work.SyncAsync
port map (
aReset => '0',
aIn => aMMCM_Locked,
OutClk => RefClk,
oOut => rMMCM_Locked);
MMCM_LockedDetect: process(RefClk)
begin
if Rising_Edge(RefClk) then
rMMCM_Locked_q <= rMMCM_Locked & rMMCM_Locked_q(1);
rMMCM_LckdFallingFlag <= rMMCM_Locked_q(1) and not rMMCM_Locked;
rMMCM_LckdRisingFlag <= not rMMCM_Locked_q(1) and rMMCM_Locked;
end if;
end process MMCM_LockedDetect;
GlitchFreeLocked: process(rRdyRst, RefClk)
begin
if (rRdyRst = '1') then
aLocked <= '0';
elsif Rising_Edge(RefClk) then
aLocked <= rMMCM_Locked_q(0);
end if;
end process GlitchFreeLocked;
dbg_rDlyRst <= rDlyRst;
dbg_rRdyRst <= rRdyRst;
dbg_rMMCM_Reset <= rMMCM_Reset_q(0);
dbg_rBUFR_Rst <= rBUFR_Rst;
dbg_rMMCM_Locked <= rMMCM_Locked;
end Behavioral;
| mit |
Digilent/vivado-library | ip/Zmods/ZmodScopeController/tb/tb_TestConfigRelay.vhd | 1 | 18284 |
-------------------------------------------------------------------------------
--
-- File: tb_TestConfigRelay.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench is used to test the ConfigRelay module.
-- The HFD4_5L_LatchingRelay module tests if the relay configuration input
-- (sChxCouplingConfig, sChxGainConfig) of the ConfigRelay module triggers
-- the correct relay drive signals sequence and timing. In addition, this
-- test bench tests the ConfigRelay module's relay state outputs
-- (sChxCouplingState, sChxGainState) against the expected values.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodADC.all;
entity tb_TestConfigRelay is
Generic (
-- Relay dynamic/static configuration
kExtRelayConfigEn : boolean := true;
--External configuration ports initial value/static configuration option
kCh1CouplingConfigInit : std_logic := '0';
kCh2CouplingConfigInit : std_logic := '0';
kCh1GainConfigInit : std_logic := '0';
kCh2GainConfigInit : std_logic := '0'
);
end tb_TestConfigRelay;
architecture Behavioral of tb_TestConfigRelay is
signal SysClk100 : std_logic := '0';
signal ADC_SamplingClk : std_logic := '0';
signal asRst_n, acRst, asRst : std_logic;
signal sCh1CouplingConfig : std_logic;
signal sCh2CouplingConfig : std_logic;
signal sCh1GainConfig : std_logic;
signal sCh2GainConfig : std_logic;
--Relay drive signals
signal sCh1CouplingH : std_logic;
signal sCh1CouplingL : std_logic;
signal sCh2CouplingH : std_logic;
signal sCh2CouplingL : std_logic;
signal sCh1GainH : std_logic;
signal sCh1GainL : std_logic;
signal sCh2GainH : std_logic;
signal sCh2GainL : std_logic;
signal sRelayComH : std_logic;
signal sRelayComL : std_logic;
signal sInitDoneRelay : std_logic;
signal sCh1CouplingState : std_logic;
signal sCh2CouplingState : std_logic;
signal sCh1GainState : std_logic;
signal sCh2GainState : std_logic;
signal sInitDoneRelayPush : std_logic;
signal sInitDoneRelayRdy : std_logic;
signal sInitDoneRelayIdata, cInitDoneRelayOdata : std_logic_vector (0 downto 0);
signal cInitDoneRelayOvld : std_logic;
begin
sInitDoneRelayIdata(0) <= sInitDoneRelay;
ConfigRelay_inst: entity work.ConfigRelays
Generic Map(
kExtRelayConfigEn => kExtRelayConfigEn,
kCh1CouplingStatic => kCh1CouplingConfigInit,
kCh2CouplingStatic => kCh2CouplingConfigInit,
kCh1GainStatic => kCh1GainConfigInit,
kCh2GainStatic => kCh2GainConfigInit,
kSimulation => true
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
sCh1CouplingConfig => sCh1CouplingConfig,
sCh2CouplingConfig => sCh2CouplingConfig,
sCh1GainConfig => sCh1GainConfig,
sCh2GainConfig => sCh2GainConfig,
--Relay state
sCh1CouplingState => sCh1CouplingState,
sCh2CouplingState => sCh2CouplingState,
sCh1GainState => sCh1GainState,
sCh2GainState => sCh2GainState,
--Relay drive signals
sCh1CouplingH => sCh1CouplingH,
sCh1CouplingL => sCh1CouplingL,
sCh2CouplingH => sCh2CouplingH,
sCh2CouplingL => sCh2CouplingL,
sCh1GainH => sCh1GainH,
sCh1GainL => sCh1GainL,
sCh2GainH => sCh2GainH,
sCh2GainL => sCh2GainL,
sRelayComH => sRelayComH,
sRelayComL => sRelayComL,
sInitDoneRelay => sInitDoneRelay,
sInitDoneRelayPush => sInitDoneRelayPush,
sInitDoneRelayRdy => sInitDoneRelayRdy
);
InstCouplingSelectRelayCh1: entity work.HFD4_5L_LatchingRelay
Generic Map(
kExtRelayConfigEn => kExtRelayConfigEn,
kRelayConfigStatic => kCh1CouplingConfigInit
)
Port Map(
sRelayConfig => sCh1CouplingConfig,
--Relay drive signals
sRelayDriverH => sCh1CouplingH,
sRelayDriverL => sCh1CouplingL,
sRelayComH => sRelayComH,
sRelayComL => sRelayComL
);
InstCouplingSelectRelayCh2: entity work.HFD4_5L_LatchingRelay
Generic Map(
kExtRelayConfigEn => kExtRelayConfigEn,
kRelayConfigStatic => kCh2CouplingConfigInit
)
Port Map(
sRelayConfig => sCh2CouplingConfig,
--Relay drive signals
sRelayDriverH => sCh2CouplingH,
sRelayDriverL => sCh2CouplingL,
sRelayComH => sRelayComH,
sRelayComL => sRelayComL
);
InstGainSelectRelayCh1: entity work.HFD4_5L_LatchingRelay
Generic Map(
kExtRelayConfigEn => kExtRelayConfigEn,
kRelayConfigStatic => kCh1GainConfigInit
)
Port Map(
sRelayConfig => sCh1GainConfig,
--Relay drive signals
sRelayDriverH => sCh1GainH,
sRelayDriverL => sCh1GainL,
sRelayComH => sRelayComH,
sRelayComL => sRelayComL
);
InstGainSelectRelayCh2: entity work.HFD4_5L_LatchingRelay
Generic Map(
kExtRelayConfigEn => kExtRelayConfigEn,
kRelayConfigStatic => kCh2GainConfigInit
)
Port Map(
sRelayConfig => sCh2GainConfig,
--Relay drive signals
sRelayDriverH => sCh2GainH,
sRelayDriverL => sCh2GainL,
sRelayComH => sRelayComH,
sRelayComL => sRelayComL
);
InstInitDoneRelaySync: entity work.HandshakeData
generic map (
kDataWidth => 1
)
port map (
InClk => SysClk100,
OutClk => ADC_SamplingClk,
iData => sInitDoneRelayIdata,
oData => cInitDoneRelayOdata,
iPush => sInitDoneRelayPush,
iRdy => sInitDoneRelayRdy,
oAck => '1',
oValid => cInitDoneRelayOvld,
aiReset => asRst,
aoReset => acRst);
ProcSystmClock: process
begin
for i in 0 to 5000000 loop
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
end loop;
wait;
end process;
ProcSamplingClock: process
begin
for i in 0 to 5000000 loop
wait for kSysClkPeriod/2;
ADC_SamplingClk <= not ADC_SamplingClk;
wait for kSysClkPeriod/2;
ADC_SamplingClk <= not ADC_SamplingClk;
end loop;
wait;
end process;
-- Process generating the input stimuli for the ConfigRelay module;
-- The relay state outputs are not checked at all time against the
-- expected values, but instead at critical moments.
-- The relay state is first verified after initialization. Afterwards,
-- each relay is set and reset. After each operation, the relay
-- state outputs are tested.
ProcMain: process
begin
-- Hold the reset condition for 10 clock cycles
-- (one clock cycle is sufficient, however 10 clock cycles makes
-- it easier to visualize the reset condition in simulation).
asRst_n <= '0';
acRst <= '1';
asRst <= '1';
sCh1CouplingConfig <= '0';
sCh2CouplingConfig <= '0';
sCh1GainConfig <= '0';
sCh2GainConfig <= '0';
wait for 10 * kSysClkPeriod;
wait until falling_edge(ADC_SamplingClk);
--initialize relays
asRst_n <= '1';
acRst <= '0';
asRst <= '0';
sCh1CouplingConfig <= kCh1CouplingConfigInit;
sCh2CouplingConfig <= kCh2CouplingConfigInit;
sCh1GainConfig <= kCh1GainConfigInit;
sCh2GainConfig <= kCh2GainConfigInit;
-- Test relay state after initialization.
wait until sInitDoneRelay = '1';
assert (sCh1CouplingState = kCh1CouplingConfigInit)
report "Ch1 coupling select relay initialization state error" & LF & HT & HT
severity ERROR;
assert (sCh2CouplingState = kCh2CouplingConfigInit)
report "Ch2 coupling select relay initialization state error" & LF & HT & HT
severity ERROR;
assert (sCh1GainState = kCh1GainConfigInit)
report "Ch1 gain select relay initialization state error" & LF & HT & HT
severity ERROR;
assert (sCh2GainState = kCh2GainConfigInit)
report "Ch2 gain select relay initialization state error" & LF & HT & HT
severity ERROR;
wait until falling_edge(SysClk100);
if (kExtRelayConfigEn = true) then
-- If static relay configuration is used no further relay state
-- modifications are possible.
-- For dynamic control, the first test performed is the
-- reset of Ch1 coupling select relay.
sCh1CouplingConfig <= '1';
sCh2CouplingConfig <= kCh2CouplingConfigInit;
sCh1GainConfig <= kCh1GainConfigInit;
sCh2GainConfig <= kCh2GainConfigInit;
-- Check if the above command produced a change in the relay state.
if (kCh1CouplingConfigInit /= '1') then
wait until sInitDoneRelay = '1';
end if;
assert (sCh1CouplingState = '1')
report "Ch1 coupling select relay state error after Ch1 coupling select relay reset" & LF & HT & HT
severity ERROR;
assert (sCh2CouplingState = kCh2CouplingConfigInit)
report "Ch2 coupling select relay state error after Ch1 coupling select relay reset" & LF & HT & HT
severity ERROR;
assert (sCh1GainState = kCh1GainConfigInit)
report "Ch1 gain select relay state error after Ch1 coupling select relay reset" & LF & HT & HT
severity ERROR;
assert (sCh2GainState = kCh2GainConfigInit)
report "Ch2 gain select relay state error after Ch1 coupling select relay reset" & LF & HT & HT
severity ERROR;
wait until falling_edge(SysClk100);
-- Set Ch1 coupling select relay.
sCh1CouplingConfig <= '0';
sCh2CouplingConfig <= kCh2CouplingConfigInit;
sCh1GainConfig <= kCh1GainConfigInit;
sCh2GainConfig <= kCh2GainConfigInit;
wait until sInitDoneRelay = '1';
assert (sCh1CouplingState = '0')
report "Ch1 coupling select relay state error after Ch1 coupling select relay set" & LF & HT & HT
severity ERROR;
assert (sCh2CouplingState = kCh2CouplingConfigInit)
report "Ch2 coupling select relay state error after Ch1 coupling select relay set" & LF & HT & HT
severity ERROR;
assert (sCh1GainState = kCh1GainConfigInit)
report "Ch1 gain select relay state error after Ch1 coupling seect relay set" & LF & HT & HT
severity ERROR;
assert (sCh2GainState = kCh2GainConfigInit)
report "Ch2 gain select relay state error after Ch1 coupling select relay set" & LF & HT & HT
severity ERROR;
wait until falling_edge(SysClk100);
-- Reset Ch2 coupling select relay.
sCh1CouplingConfig <= '0';
sCh2CouplingConfig <= '1';
sCh1GainConfig <= kCh1GainConfigInit;
sCh2GainConfig <= kCh2GainConfigInit;
-- Check if the above command produced a change in the relay state.
if (kCh2CouplingConfigInit /= '1') then
wait until sInitDoneRelay = '1';
end if;
assert (sCh1CouplingState = '0')
report "Ch1 coupling select relay state error after Ch2 coupling select relay reset" & LF & HT & HT
severity ERROR;
assert (sCh2CouplingState = '1')
report "Ch2 coupling select relay state error after Ch2 coupling select relay reset" & LF & HT & HT
severity ERROR;
assert (sCh1GainState = kCh1GainConfigInit)
report "Ch1 gain select relay state error after Ch2 coupling select relay reset" & LF & HT & HT
severity ERROR;
assert (sCh2GainState = kCh2GainConfigInit)
report "Ch2 gain select relay state error after Ch2 coupling select relay reset" & LF & HT & HT
severity ERROR;
wait until falling_edge(SysClk100);
-- Set Ch2 coupling select relay.
sCh1CouplingConfig <= '0';
sCh2CouplingConfig <= '0';
sCh1GainConfig <= kCh1GainConfigInit;
sCh2GainConfig <= kCh2GainConfigInit;
wait until sInitDoneRelay = '1';
assert (sCh1CouplingState = '0')
report "Ch1 coupling select relay state error after Ch2 coupling select relay set" & LF & HT & HT
severity ERROR;
assert (sCh2CouplingState = '0')
report "Ch2 coupling select relay state error after Ch2 coupling select relay set" & LF & HT & HT
severity ERROR;
assert (sCh1GainState = kCh1GainConfigInit)
report "Ch1 gain select relay state error after Ch2 coupling select relay set" & LF & HT & HT
severity ERROR;
assert (sCh2GainState = kCh2GainConfigInit)
report "Ch2 gain select relay state error after Ch2 coupling select relay set" & LF & HT & HT
severity ERROR;
wait until falling_edge(SysClk100);
-- Reset Ch1 gain select relay.
sCh1CouplingConfig <= '0';
sCh2CouplingConfig <= '0';
sCh1GainConfig <= '1';
sCh2GainConfig <= kCh2GainConfigInit;
-- Check if the above command produced a change in the relay state.
if (sCh1GainConfig /= '1') then
wait until sInitDoneRelay = '1';
end if;
assert (sCh1CouplingState = '0')
report "Ch1 coupling select relay state error after Ch1 gain select relay reset" & LF & HT & HT
severity ERROR;
assert (sCh2CouplingState = '0')
report "Ch2 coupling select relay state error after Ch1 gain select relay reset" & LF & HT & HT
severity ERROR;
assert (sCh1GainState = '1')
report "Ch1 gain select relay state error after Ch1 gain select relay reset" & LF & HT & HT
severity ERROR;
assert (sCh2GainState = kCh2GainConfigInit)
report "Ch2 gain select relay state error after Ch1 gain select relay reset" & LF & HT & HT
severity ERROR;
wait until falling_edge(SysClk100);
-- Set Ch1 gain select relay.
sCh1CouplingConfig <= '0';
sCh2CouplingConfig <= '0';
sCh1GainConfig <= '0';
sCh2GainConfig <= kCh2GainConfigInit;
wait until sInitDoneRelay = '1';
assert (sCh1CouplingState = '0')
report "Ch1 coupling select relay state error after Ch1 gain select relay set" & LF & HT & HT
severity ERROR;
assert (sCh2CouplingState = '0')
report "Ch2 coupling select relay state error after Ch1 gain select relay set" & LF & HT & HT
severity ERROR;
assert (sCh1GainState = '0')
report "Ch1 gain select relay state error after Ch1 gain select relay set" & LF & HT & HT
severity ERROR;
assert (sCh2GainState = kCh2GainConfigInit)
report "Ch2 gain select relay state error after Ch1 gain select relay set" & LF & HT & HT
severity ERROR;
wait until falling_edge(SysClk100);
-- Reset Ch2 gain select relay.
sCh1CouplingConfig <= '0';
sCh2CouplingConfig <= '0';
sCh1GainConfig <= '0';
sCh2GainConfig <= '1';
-- Check if the above command produced a change in the relay state.
if (sCh2GainConfig /= '1') then
wait until sInitDoneRelay = '1';
end if;
assert (sCh1CouplingState = '0')
report "Ch1 coupling select relay state error after Ch2 gain select relay reset" & LF & HT & HT
severity ERROR;
assert (sCh2CouplingState = '0')
report "Ch2 coupling select relay state error after Ch2 gain select relay reset" & LF & HT & HT
severity ERROR;
assert (sCh1GainState = '0')
report "Ch1 gain select relay state error after Ch2 gain select relay reset" & LF & HT & HT
severity ERROR;
assert (sCh2GainState = '1')
report "Ch2 gain select relay state error after Ch2 gain select relay reset" & LF & HT & HT
severity ERROR;
wait until falling_edge(SysClk100);
-- Set Ch2 gain select relay.
sCh1CouplingConfig <= '0';
sCh2CouplingConfig <= '0';
sCh1GainConfig <= '0';
sCh2GainConfig <= '0';
wait until sInitDoneRelay = '1';
assert (sCh1CouplingState = '0')
report "Ch1 coupling select relay state error after Ch2 gain select relay set" & LF & HT & HT
severity ERROR;
assert (sCh2CouplingState = '0')
report "Ch2 coupling select relay state error after Ch2 gain select relay set" & LF & HT & HT
severity ERROR;
assert (sCh1GainState = '0')
report "Ch1 gain select relay state error after Ch2 gain select relay set" & LF & HT & HT
severity ERROR;
assert (sCh2GainState = '0')
report "Ch2 gain select relay state error after Ch2 gain select relay set" & LF & HT & HT
severity ERROR;
wait until falling_edge(SysClk100);
end if;
wait;
end process;
end Behavioral;
| mit |
Digilent/vivado-library | ip/dvi2rgb/src/SyncBase.vhd | 15 | 3854 | -------------------------------------------------------------------------------
--
-- File: SyncBase.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes a signal (iIn) in one clock domain (InClk) with
-- another clock domain (OutClk) and provides it on oOut.
-- The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncBase is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
InClk : in std_logic;
iIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncBase;
architecture Behavioral of SyncBase is
signal iIn_q : std_logic;
begin
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aReset, InClk)
begin
if (aReset = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aReset => aReset,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral;
| mit |
Digilent/vivado-library | ip/Zmods/ZmodDigitizerController/tb/tb_TestDataPathCalib.vhd | 1 | 20449 |
-------------------------------------------------------------------------------
--
-- File: tb_TestDataPathCalib.vhd
-- Author: Tudor Gherman, Robert Bocos
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench instantiates the DataPath and ADC_Calibration modules of the
-- ZmodScopeController. A ramp signal is used to simulate the ADC data
-- and a data checker compares the output of the DataPath module against the
-- expected data (generated by CalibDataReference) and generates an error
-- message if a mismatch occurs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.PkgZmodDigitizer.all;
entity tb_TestDataPathCalib is
Generic (
-- ADC number of bits
kADC_Width : integer range 10 to 16 := 14;
-- Sampling Clock Period in ns;
kSamplingPeriod : real range 2.5 to 100.0:= 8.138;
-- kSimTestMode generic allows the test bench to instantiate the
-- ADC_Calibration modules to be instantiated either in test mode
-- or in normal operation.
kSimTestMode : std_logic := '0';
-- ADC dynamic/static calibration
kExtCalibEn : boolean := false;
-- Channel1 low gain multiplicative (gain) compensation coefficient parameter
kCh1LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010110010";
-- Channel1 low gain additive (offset) compensation coefficient parameter
kCh1LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101";
-- Channel1 high gain multiplicative (gain) compensation coefficient parameter
kCh1HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010110010";
-- Channel1 high gain additive (offset) compensation coefficient parameter
kCh1HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101";
-- Channel2 low gain multiplicative (gain) compensation coefficient parameter
kCh2LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010110010";
-- Channel2 low gain additive (offset) compensation coefficient parameter
kCh2LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101";
-- Channel2 high gain multiplicative (gain) compensation coefficient parameter
kCh2HgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel2 high gain additive (offset) compensation coefficient parameter
kCh2HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101"
);
end tb_TestDataPathCalib;
architecture Behavioral of tb_TestDataPathCalib is
constant kNumClockCycles : integer := 3*(2**14);
signal SysClk100 : std_logic := '0';
signal rZmodDcoPLL_Lock : std_logic;
signal asRst_n : std_logic := '0';
signal asRst : std_logic := '1';
signal ZmodDcoClk, ZmodDcoClkDly : std_logic := '0';
signal DcoClkOut : std_logic := '0';
signal adoRst_n : std_logic := '0';
signal adoRst : std_logic := '1';
signal diZmodADC_Data, diZmodADC_DataDly : std_logic_vector(kADC_Width-1 downto 0) := (others => '0');
signal ZmodDataSel : std_logic_vector (2 downto 0);
signal diZmodADC_DataCnt : unsigned (kADC_Width-1 downto 0);
signal doDataValid, doDataCalibValid : std_logic;
signal doChannelA, doChannelB : std_logic_vector(kADC_Width-1 downto 0);
signal doChannel1_Test, doChannel2_Test : std_logic_vector(kADC_Width-1 downto 0);
signal doChA_TestDly, doChB_TestDly : std_logic_vector(kADC_Width-1 downto 0);
signal doTestMode : std_logic;
signal doCh1Calib, doCh2Calib : std_logic_vector(15 downto 0);
signal doCh1OutInt, doCh2OutInt : integer;
signal doCh1TestInt, doCh2TestInt : integer;
signal doCh1Diff, doCh2Diff : integer;
signal doExtCh1LgMultCoef : std_logic_vector(17 downto 0);
signal doExtCh1LgAddCoef : std_logic_vector(17 downto 0);
signal doExtCh1HgMultCoef : std_logic_vector(17 downto 0);
signal doExtCh1HgAddCoef : std_logic_vector(17 downto 0);
signal doExtCh2LgMultCoef : std_logic_vector(17 downto 0);
signal doExtCh2LgAddCoef : std_logic_vector(17 downto 0);
signal doExtCh2HgMultCoef : std_logic_vector(17 downto 0);
signal doExtCh2HgAddCoef : std_logic_vector(17 downto 0);
signal diDataGenCntEn, diDataGenRst_n : std_logic;
signal doEnableAcquisition : std_logic;
signal doDataAcceptanceReady : std_logic;--This signal would be equivalent to a doDataAxisTready given by an AXI Stream Slave
constant kADC_SamplingClkPeriod : time := 8.138ns;
constant RefClkPeriod : time := 10ns;
constant kVal1 : std_logic_vector (15 downto 0) := x"AAAA";
constant kVal2 : std_logic_vector (15 downto 0) := x"5555";
constant kValMin : std_logic_vector (15 downto 0) := x"8000";
constant kValMax : std_logic_vector (15 downto 0) := x"7FFF";
-- Calibration constants used to test the dynamic calibration behavior
constant kCh1LgMultCoefDynamic : std_logic_vector (17 downto 0) := "010000110101100101";
constant kCh1LgAddCoefDynamic : std_logic_vector (17 downto 0) := "111111101111011011";
constant kCh1HgMultCoefDynamic : std_logic_vector (17 downto 0) := "010001101000010001";
constant kCh1HgAddCoefDynamic : std_logic_vector (17 downto 0) := "111111101110111000";
constant kCh2LgMultCoefDynamic : std_logic_vector (17 downto 0) := "010000101001111010";
constant kCh2LgAddCoefDynamic : std_logic_vector (17 downto 0) := "000000000000010000";
constant kCh2HgMultCoefDynamic : std_logic_vector (17 downto 0) := "010001011010101111";
constant kCh2HgAddCoefDynamic : std_logic_vector (17 downto 0) := "000000001000000111";
begin
InstDataPath : entity work.DataPath
Generic Map(
kSamplingPeriod => kSamplingPeriod,
kADC_Width => kADC_Width
)
Port Map(
RefClk => SysClk100,
arRst => asRst,
adoRst => adoRst,
DcoClkIn => ZmodDcoClk,
DcoClkOut => DcoClkOut,
rDcoMMCM_LockState => rZmodDcoPLL_Lock,
doEnableAcquisition => doEnableAcquisition,
diADC_Data => diZmodADC_DataDly,
doChannelA => doChannelA,
doChannelB => doChannelB,
doDataOutValid => doDataValid
);
InstDataPathDlyCh1 : entity work.DataPathLatency
Generic Map (
kNumFIFO_Stages => 0,
kDataWidth => kADC_Width
)
Port Map(
ZmodDcoClk => DcoClkOut,
ZmodDcoClkDly => ZmodDcoClkDly,
doDataIn => diZmodADC_DataDly,
doChA_DataOut => doChA_TestDly,
doChB_DataOut => doChB_TestDly);
InstCalibDataRefCh1 : entity work.CalibDataReference
Generic Map (
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kLgMultCoefStatic => kCh1LgMultCoefStatic,
kLgAddCoefStatic => kCh1LgAddCoefStatic,
kHgMultCoefStatic => kCh1HgMultCoefStatic,
kHgAddCoefStatic => kCh1HgAddCoefStatic,
kInvert => true,
kLatency => 2,
kTestLatency => 1
)
Port Map(
SamplingClk => DcoClkOut,
cTestMode => doTestMode,
cChIn => doChA_TestDly,
cChOut => doChannel1_Test,
cExtLgMultCoef => doExtCh1LgMultCoef,
cExtLgAddCoef => doExtCh1LgAddCoef,
cExtHgMultCoef => doExtCh1HgMultCoef,
cExtHgAddCoef => doExtCh1HgAddCoef,
cGainState => '1' --Force High Gain
);
InstCalibDataRefCh2 : entity work.CalibDataReference
Generic Map (
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kLgMultCoefStatic => kCh2LgMultCoefStatic,
kLgAddCoefStatic => kCh2LgAddCoefStatic,
kHgMultCoefStatic => kCh2HgMultCoefStatic,
kHgAddCoefStatic => kCh2HgAddCoefStatic,
kInvert => false,
kLatency => 2,
kTestLatency => 1
)
Port Map(
SamplingClk => DcoClkOut,
cTestMode => doTestMode,
cChIn => doChB_TestDly,
cChOut => doChannel2_Test,
cExtLgMultCoef => doExtCh2LgMultCoef,
cExtLgAddCoef => doExtCh2LgAddCoef,
cExtHgMultCoef => doExtCh2HgMultCoef,
cExtHgAddCoef => doExtCh2HgAddCoef,
cGainState => '1' --Force High Gain
);
InstCh1ADC_Calibration : entity work.GainOffsetCalib
Generic Map(
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kInvert => true,
kLgMultCoefStatic => kCh1LgMultCoefStatic,
kLgAddCoefStatic => kCh1LgAddCoefStatic,
kHgMultCoefStatic => kCh1HgMultCoefStatic,
kHgAddCoefStatic => kCh1HgAddCoefStatic
)
Port Map
(
SamplingClk => DcoClkOut,
acRst_n => adoRst_n,
cTestMode => doTestMode,
cDataAcceptanceReady => doDataAcceptanceReady,
cExtLgMultCoef => doExtCh1LgMultCoef,
cExtLgAddCoef => doExtCh1LgAddCoef,
cExtHgMultCoef => doExtCh1HgMultCoef,
cExtHgAddCoef => doExtCh1HgAddCoef,
cGainState => '1', --Force High Gain
cDataRaw => doChannelA,
cDataInValid => doDataValid,
cCalibDataOut => doCh1Calib,
cDataCalibValid => doDataCalibValid
);
InstCh2ADC_Calibration : entity work.GainOffsetCalib
Generic Map(
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kInvert => false,
kLgMultCoefStatic => kCh2LgMultCoefStatic,
kLgAddCoefStatic => kCh2LgAddCoefStatic,
kHgMultCoefStatic => kCh2HgMultCoefStatic,
kHgAddCoefStatic => kCh2HgAddCoefStatic
)
Port Map
(
SamplingClk => DcoClkOut,
acRst_n => adoRst_n,
cTestMode => doTestMode,
cDataAcceptanceReady => doDataAcceptanceReady,
cExtLgMultCoef => doExtCh2LgMultCoef,
cExtLgAddCoef => doExtCh2LgAddCoef,
cExtHgMultCoef => doExtCh2HgMultCoef,
cExtHgAddCoef => doExtCh2HgAddCoef,
cGainState => '1', --Force High Gain
cDataRaw => doChannelB,
cDataInValid => '0',
cCalibDataOut => doCh2Calib,
cDataCalibValid => open --both channels share the same valid signal
);
doCh1OutInt <= to_integer(signed(doCh1Calib(15 downto 16-kADC_Width)));
doCh2OutInt <= to_integer(signed(doCh2Calib(15 downto 16-kADC_Width)));
doCh1TestInt <= to_integer(signed(doChannel1_Test));
doCh2TestInt <= to_integer(signed(doChannel2_Test));
doCh1Diff <= doCh1OutInt - doCh1TestInt;
doCh2Diff <= doCh2OutInt - doCh2TestInt;
-- Generate Reference Clock
RefClock: process
begin
for i in 0 to kNumClockCycles loop
wait for RefClkPeriod/2;
SysClk100 <= not SysClk100;
wait for RefClkPeriod/2;
SysClk100 <= not SysClk100;
end loop;
wait;
end process;
-- Generate ZmodDcoClk.
ZmodDcoClkProc: process
begin
wait for kTdcoMax;
for i in 0 to kNumClockCycles/2 loop
wait for kADC_SamplingClkPeriod/2;
ZmodDcoClk <= not ZmodDcoClk;
wait for kADC_SamplingClkPeriod/2;
ZmodDcoClk <= not ZmodDcoClk;
end loop;
-- Simulate DcoClk loss for 100 samples.
-- 100 is a random choice, it has no particular meaning.
wait for kADC_SamplingClkPeriod * 100;
for i in 0 to (kNumClockCycles/2 - 100) loop
wait for kADC_SamplingClkPeriod/2;
ZmodDcoClk <= not ZmodDcoClk;
wait for kADC_SamplingClkPeriod/2;
ZmodDcoClk <= not ZmodDcoClk;
end loop;
wait;
end process;
ZmodDcoClkDly <= ZmodDcoClk after
(IDDR_ClockPhase(kSamplingPeriod)/360.0)*kADC_SamplingClkPeriod;
-- Ramp signal generator
ProcDataGen: process (ZmodDcoClk)
begin
if ((adoRst_n = '0') or (diDataGenRst_n = '0')) then
diZmodADC_DataCnt <= (others => '0');
elsif (falling_edge(ZmodDcoClk) or rising_edge(ZmodDcoClk)) then
if (diDataGenCntEn = '1') then
diZmodADC_DataCnt <= diZmodADC_DataCnt + 1;
end if;
end if;
end process;
-- Mux that allows selecting (simulating) different patterns
-- on the ADC data interface.
ProcZmodDataMux: process (diZmodADC_DataCnt, ZmodDataSel)
begin
case (ZmodDataSel) is
when ("000") =>
diZmodADC_Data <= kVal1(kADC_Width-1 downto 0);
when ("001") =>
diZmodADC_Data <= kVal2(kADC_Width-1 downto 0);
when ("010") =>
diZmodADC_Data <= std_logic_vector(diZmodADC_DataCnt);
when ("011") =>
diZmodADC_Data <= kValMin(15 downto 16-kADC_Width);
when ("100") =>
diZmodADC_Data <= kValMax(15 downto 16-kADC_Width);
when others =>
diZmodADC_Data <= std_logic_vector(diZmodADC_DataCnt);
end case;
end process;
diZmodADC_DataDly <= diZmodADC_Data after (kADC_SamplingClkPeriod/4);
ProcRefClkDomainStimuli: process
begin
asRst <= '0';
wait;
end process;
adoRst <= not adoRst_n;
ProcDcoClkOutDomainStimuli: process
begin
adoRst_n <= '0';
doTestMode <= kSimTestMode;
doExtCh1LgMultCoef <= kCh1LgMultCoefDynamic;
doExtCh1LgAddCoef <= kCh1LgAddCoefDynamic;
doExtCh1HgMultCoef <= kCh1HgMultCoefDynamic;
doExtCh1HgAddCoef <= kCh1HgAddCoefDynamic;
doExtCh2LgMultCoef <= kCh2LgMultCoefDynamic;
doExtCh2LgAddCoef <= kCh2LgAddCoefDynamic;
doExtCh2HgMultCoef <= kCh2HgMultCoefDynamic;
doExtCh2HgAddCoef <= kCh2HgAddCoefDynamic;
doEnableAcquisition <= '0';
doDataAcceptanceReady <= '0';
-- Keep the adoRst_n reset asserted for 10 clock cycles.
wait for 10 * kADC_SamplingClkPeriod;
-- Modify signals on the falling edge of DcoClkOut.
wait until falling_edge(DcoClkOut);
adoRst_n <= '1';
doEnableAcquisition <= '1';
doDataAcceptanceReady <= '1';
-- Optionally the cInitDone signal can be disabled to observe the system behavior.
-- No sort of automatic testing is carried out for this optional test.
-- The effect of ADC or relay initialization on the valid signal is tested
-- at the top level test bench (tb_TestTop) level.
wait until falling_edge(DcoClkOut);
-- Keep dInitDone low for 500 clock cycles (this number has no specific relevance).
wait for (500) * kADC_SamplingClkPeriod;
wait;
end process;
ProcDcoDomainStimuli: process
begin
diDataGenRst_n <= '0';
diDataGenCntEn <= '0';
ZmodDataSel <= "000";
-- Keep the acRst_n reset asserted for 10 clock cycles.
wait for 10 * kADC_SamplingClkPeriod;
-- Modify signals on the falling edge of ZmodDcoClk.
wait until falling_edge(ZmodDcoClk);
diDataGenRst_n <= '1';
diDataGenCntEn <= '1';
ZmodDataSel <= "000";
-- A counter will be used to generate the input test data for the DataPath module.
-- However, since a 1LSB error is tolerated so that the CalibDataReference can work
-- with real (floating point) values, synchronization problems may not be detected.
-- For this reason, at the beginning of the test 2 values that differ by more than
-- 1 LSB will be generated. By this means, the test assures that the DataPath and
-- ADC_Calibration outputs are correctly synchronized with CalibDataReference.
-- To make sure that the synchronization FIFO comes out of reset when the various
-- patterns are applied to the input, the process will wait for the data valid
-- signal to be asserted.
wait until doDataValid = '1';
wait until rising_edge(ZmodDcoClk);
ZmodDataSel <= "000";
wait until rising_edge(ZmodDcoClk);
ZmodDataSel <= "001";
wait until rising_edge(ZmodDcoClk);
-- Test IP response for minimum negative and maximum positive input
-- The value will be hold for 100 clock cycles (no specific relevance
-- for the time this value is held constant).
ZmodDataSel <= "011";
wait for kADC_SamplingClkPeriod*100;
wait until rising_edge(ZmodDcoClk);
ZmodDataSel <= "100";
wait for kADC_SamplingClkPeriod*100;
wait until rising_edge(ZmodDcoClk);
ZmodDataSel <= "010";
-- Optionally the dInitDone signal can be disabled to observe the system behavior.
-- No sort of automatic testing is carried out for this optional test.
-- The effect of ADC or relay initialization on the valid signal is tested
-- at the top level test bench (tb_TestTop) level.
-- Modify signals on the falling edge of ZmodDcoClk.
wait until falling_edge(ZmodDcoClk);
-- Keep dInitDone low for 500 clock cycles (this number has no specific relevance).
wait for (500) * kADC_SamplingClkPeriod;
wait;
end process;
-- Check the calibration module (ADC_Calbration) outputs against the expected values.
ProcCh1CheckCalibData: process
begin
wait until rZmodDcoPLL_Lock = '1';
wait until doCh1TestInt'event or doCh1OutInt'event;
-- doCh1Diff is generated on the rising edge of DcoClkOut
-- and checked on the negative edge of DcoClkOut.
wait until falling_edge(DcoClkOut);
if (doDataCalibValid = '1') then
assert (abs(doCh1Diff) < 2)
report "Calibration error: mismatch between expected data and actual data" & LF & HT & HT &
"Expected: " & integer'image(to_integer(signed(doChannel1_Test))) & LF & HT & HT &
"Actual: " & integer'image(doCh1OutInt) & LF & HT & HT &
"Difference: " & integer'image(doCh1Diff)
severity ERROR;
end if;
end process;
ProcCh2CheckCalibData: process
begin
wait until rZmodDcoPLL_Lock = '1';
wait until doCh2TestInt'event or doCh2OutInt'event;
-- doCh2Diff is generated on the rising edge of DcoClkOut
-- and checked on the negative edge of DcoClkOut.
wait until falling_edge(DcoClkOut);
if (doDataCalibValid = '1') then
assert (abs(doCh2Diff) < 2)
report "Calibration error: mismatch between expected data and actual data" & LF & HT & HT &
"Expected: " & integer'image(to_integer(signed(doChannel2_Test))) & LF & HT & HT &
"Actual: " & integer'image(doCh2OutInt) & LF & HT & HT &
"Difference: " & integer'image(doCh2Diff)
severity ERROR;
end if;
end process;
-- Test DataPathLatency module. The data generated by the DataPath module
-- is expected to be identical to the data generated by the DataPathLatency
-- module. This test is used to validate the DataPathLatency used in the top
-- level test bench.
ProcDataPathDlyTest: process
begin
wait until rZmodDcoPLL_Lock = '1';
wait until doChannelA'event or doChannelB'event or doChB_TestDly'event or doChA_TestDly'event;
if (doDataValid = '1') then
wait until falling_edge(DcoClkOut);
assert ((doChannelA = doChA_TestDly) and (doChannelB = doChB_TestDly))
report "DataPathLatency synchronization error" & LF & HT & HT
severity ERROR;
end if;
end process;
end Behavioral;
| mit |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/vhdl/start_for_Loop_lojbC.vhd | 1 | 4490 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Loop_lojbC_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Loop_lojbC_shiftReg;
architecture rtl of start_for_Loop_lojbC_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_Loop_lojbC is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Loop_lojbC is
component start_for_Loop_lojbC_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Loop_lojbC_shiftReg : start_for_Loop_lojbC_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| mit |
Digilent/vivado-library | ip/axi_i2s_adi_1.2/hdl/i2s_controller.vhd | 7 | 8371 | -- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.fifo_synchronizer;
use axi_i2s_adi_v1_00_a.i2s_clkgen;
use axi_i2s_adi_v1_00_a.i2s_tx;
use axi_i2s_adi_v1_00_a.i2s_rx;
entity i2s_controller is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_NUM_CH : integer := 1;
C_HAS_TX : integer := 1;
C_HAS_RX : integer := 1
);
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
data_clk : in std_logic; -- Data clock should be less than clk / 4
BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Bit Clock
LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Frame Clock
SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Output
SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Input
tx_enable : in Boolean; -- Enable TX
tx_ack : out std_logic; -- Request new Slot Data
tx_stb : in std_logic; -- Request new Slot Data
tx_data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in
rx_enable : in Boolean; -- Enable RX
rx_ack : in std_logic;
rx_stb : out std_logic; -- Valid Slot Data
rx_data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out
-- Runtime parameter
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255
);
end i2s_controller;
architecture Behavioral of i2s_controller is
constant NUM_TX : integer := C_HAS_TX * C_NUM_CH;
constant NUM_RX : integer := C_HAS_RX * C_NUM_CH;
signal enable : Boolean;
signal tick : std_logic;
signal tick_d1 : std_logic;
signal tick_d2 : std_logic;
signal BCLK_O_int : std_logic;
signal LRCLK_O_int : std_logic;
signal tx_bclk : std_logic;
signal tx_lrclk : std_logic;
signal tx_sdata : std_logic_vector(C_NUM_CH - 1 downto 0);
signal tx_tick : std_logic;
signal tx_channel_sync : std_logic;
signal tx_frame_sync : std_logic;
signal bclk_tick : std_logic;
signal rx_bclk : std_logic;
signal rx_lrclk : std_logic;
signal rx_sdata : std_logic_vector(NUM_RX - 1 downto 0);
signal rx_channel_sync : std_logic;
signal rx_frame_sync : std_logic;
signal tx_sync_fifo_out : std_logic_vector(3 + NUM_TX downto 0);
signal tx_sync_fifo_in : std_logic_vector(3 + NUM_TX downto 0);
signal rx_sync_fifo_out : std_logic_vector(3 + NUM_RX downto 0);
signal rx_sync_fifo_in : std_logic_vector(3 + NUM_RX downto 0);
begin
enable <= rx_enable or tx_enable;
-- Generate tick signal in the DATA_CLK_I domain
process (data_clk)
begin
if rising_edge(data_clk) then
if resetn = '0' then
tick <= '0';
else
tick <= not tick;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if resetn = '0' then
tick_d1 <= '0';
tick_d2 <= '0';
else
tick_d1 <= tick;
tick_d2 <= tick_d1;
end if;
end if;
end process;
tx_tick <= tick_d2 xor tick_d1;
tx_sync_fifo_in(0) <= tx_channel_sync;
tx_sync_fifo_in(1) <= tx_frame_sync;
tx_sync_fifo_in(2) <= tx_bclk;
tx_sync_fifo_in(3) <= tx_lrclk;
tx_sync_fifo_in(3 + NUM_TX downto 4) <= tx_sdata;
process (data_clk)
begin
if rising_edge(data_clk) then
if resetn = '0' then
BCLK_O <= (others => '1');
LRCLK_O <= (others => '1');
SDATA_O <= (others => '0');
else
if C_BCLK_POL = 0 then
BCLK_O <= (others => tx_sync_fifo_out(2));
else
BCLK_O <= (others => not tx_sync_fifo_out(2));
end if;
if C_LRCLK_POL = 0 then
LRCLK_O <= (others => tx_sync_fifo_out(3));
else
LRCLK_O <= (others => not tx_sync_fifo_out(3));
end if;
if C_HAS_TX = 1 then
SDATA_O <= tx_sync_fifo_out(3 + NUM_TX downto 4);
end if;
if C_HAS_RX = 1 then
rx_sync_fifo_in(3 downto 0) <= tx_sync_fifo_out(3 downto 0);
rx_sync_fifo_in(3 + NUM_RX downto 4) <= SDATA_I;
end if;
end if;
end if;
end process;
tx_sync: entity fifo_synchronizer
generic map (
DEPTH => 4,
WIDTH => NUM_TX + 4
)
port map (
resetn => resetn,
in_clk => clk,
in_data => tx_sync_fifo_in,
in_tick => tx_tick,
out_clk => data_clk,
out_data => tx_sync_fifo_out
);
clkgen: entity i2s_clkgen
port map(
clk => clk,
resetn => resetn,
enable => enable,
tick => tx_tick,
bclk_div_rate => bclk_div_rate,
lrclk_div_rate => lrclk_div_rate,
channel_sync => tx_channel_sync,
frame_sync => tx_frame_sync,
bclk => tx_bclk,
lrclk => tx_lrclk
);
tx_gen: if C_HAS_TX = 1 generate
tx: entity i2s_tx
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_NUM => NUM_TX
)
port map (
clk => clk,
resetn => resetn,
enable => tx_enable,
channel_sync => tx_channel_sync,
frame_sync => tx_frame_sync,
bclk => tx_bclk,
sdata => tx_sdata,
ack => tx_ack,
stb => tx_stb,
data => tx_data
);
end generate;
rx_gen: if C_HAS_RX = 1 generate
rx: entity i2s_rx
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_NUM => NUM_RX
)
port map (
clk => clk,
resetn => resetn,
enable => rx_enable,
channel_sync => rx_channel_sync,
frame_sync => rx_frame_sync,
bclk => rx_bclk,
sdata => rx_sdata,
ack => rx_ack,
stb => rx_stb,
data => rx_data
);
rx_channel_sync <= rx_sync_fifo_out(0);
rx_frame_sync <= rx_sync_fifo_out(1);
rx_bclk <= rx_sync_fifo_out(2);
rx_lrclk <= rx_sync_fifo_out(3);
rx_sdata <= rx_sync_fifo_out(3 + NUM_RX downto 4);
rx_sync: entity fifo_synchronizer
generic map (
DEPTH => 4,
WIDTH => NUM_RX + 4
)
port map (
resetn => resetn,
in_clk => data_clk,
in_data => rx_sync_fifo_in,
in_tick => '1',
out_clk => clk,
out_data => rx_sync_fifo_out
);
end generate;
end Behavioral;
| mit |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign | comparator/com_dataflow_1/com_dataflow_1.vhd | 1 | 641 | entity COM is
--generic (D:time);
port (N1, N0, M1, M0: in bit;
GE, LE, E, G, L: out bit);
end COM;
--
-- Optimum two-level product of sums data flow model.
--
architecture POSDF of COM is
signal Z1,Z0: bit;
begin
Z1 <= (not N0 or M1 or M0) and (not N1 or M1) and
(not N1 or not N0 or M0);
Z0 <= (N1 or N0 or not M0) and (N1 or not M1) and
(N0 or not M1 or not M0);
LE <= Z1; --after D;
GE <= Z0; --after D;
E <= Z1 and Z0; --after D;
G <= Z0 and not Z1; --after D;
L <= Z1 and not Z0; --after D;
end POSDF;
--Figure 8.12 VHDL description of data flow model for device COM. | mit |
Digilent/vivado-library | ip/Zmods/ZmodScopeController/tb/CalibDataReference.vhd | 2 | 9370 |
-------------------------------------------------------------------------------
--
-- File: CalibDataReference.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module generates the reference output data for the GainOffsetCaib module.
-- It is supposed to run in parallel with the GainOffsetCaib module as part of
-- the test bench and share the same inputs. Malfunctions of the GainOffsetCaib
-- can be detected by comparing its output with the output of this module.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.numeric_std.all;
entity CalibDataReference is
Generic (
-- ADC/DAC number of bits
kWidth : integer range 10 to 16 := 14;
-- ADC/DAC dynamic/static calibration
kExtCalibEn : boolean := true;
-- Channel1 low gain multiplicative (gain) compensation coefficient parameter
kLgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel1 low gain additive (offset) compensation coefficient parameter
kLgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- Channel1 high gain multiplicative (gain) compensation coefficient parameter
kHgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel1 high gain additive (offset) compensation coefficient parameter
kHgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- Invert input data sign
kInvert : boolean := false;
-- Calibration stage latency
kLatency : integer := 2;
-- Calibration stage latency in test mode; Must be > 1 and < kLatency
-- The GainOffsetCaib module has different latencies in test mode
-- and in normal operation.
kTestLatency : integer := 1
);
Port (
-- Sampling clock
SamplingClk : in STD_LOGIC;
-- cTestMode is used to bypass the calibration block. When this signal
-- is asserted, raw samples are provided on the output data port.
cTestMode : in STD_LOGIC;
-- Data input port
cChIn : in STD_LOGIC_VECTOR (kWidth-1 downto 0);
-- Data output port
cChOut : out STD_LOGIC_VECTOR (kWidth-1 downto 0);
--Channel1 low gain gain compensation coefficient external port
cExtLgMultCoef : in std_logic_vector (17 downto 0);
--Channel1 low gain offset compensation coefficient external port
cExtLgAddCoef : in std_logic_vector (17 downto 0);
--Channel1 high gain gain compensation coefficient external port
cExtHgMultCoef : in std_logic_vector (17 downto 0);
--Channel1 high gain offset compensation coefficient external port;
cExtHgAddCoef : in std_logic_vector (17 downto 0);
-- Gain Relay State (1 -> High Gain; 0 -> Low Gain)
cGainState : in std_logic
);
end CalibDataReference;
architecture Behavioral of CalibDataReference is
signal cLgCoefAdd, cHgCoefAdd, cLgCoefMult, cHgCoefMult : signed (17 downto 0);
signal cLgMult, cHgMult : signed (35 downto 0) := (others => '0');
signal cChOutAux : std_logic_vector (kWidth-1 downto 0);
type ADC_ChArray_t is array (kLatency-1 downto 0) of std_logic_vector(kWidth-1 downto 0);
signal cChInDelayed : ADC_ChArray_t := (others => (others => '0'));
signal cLgCoefAddReal : real;
signal cHgCoefAddReal : real;
signal cLgCoefMultReal : real;
signal cHgCoefMultReal : real;
signal cChOutReal : real;
signal cChInReal : real;
signal cChInSigned : signed (kWidth-1 downto 0);
signal sChOutSigned : signed (kWidth-1 downto 0);
constant kTwoPow17 : real := 2.0**17.0;
constant kTwoPow16 : real := 2.0**16.0;
constant kTwoPowNadc : real := 2.0**real((kWidth-1));
-- Constants representing the minimum (negative) value and the maximum
-- (positive) value that cChIn can take. If inversion is requested by
-- setting kInvert to "true", in case cChIn = kValMin, the inversion
-- can't be performed directly on kWidth. The output of the inversion
-- needs to be forced to kValMax.
constant kValMin : std_logic_vector (15 downto 0) := x"8000";
constant kValMax : std_logic_vector (15 downto 0) := x"7FFF";
begin
-- Determine the value of the gain and offset calibration coefficients
-- based on the static/dynamic configuration option (kExtCalibEn).
cLgCoefAdd <= signed(kLgAddCoefStatic) when kExtCalibEn = false
else signed(cExtLgAddCoef);
cHgCoefAdd <= signed(kHgAddCoefStatic) when kExtCalibEn = false
else signed(cExtHgAddCoef);
cLgCoefMult <= signed(kLgMultCoefStatic) when kExtCalibEn = false
else signed(cExtLgMultCoef);
cHgCoefMult <= signed(kHgMultCoefStatic) when kExtCalibEn = false
else signed(cExtHgMultCoef);
-- The necessity of these operations is explained in the IP's
-- documentation.
cLgCoefAddReal <= Real(to_integer(cLgCoefAdd))/kTwoPow17;
cHgCoefAddReal <= Real(to_integer(cHgCoefAdd))/kTwoPow17;
cLgCoefMultReal <= Real(to_integer(cLgCoefMult))/kTwoPow16;
cHgCoefMultReal <= Real(to_integer(cHgCoefMult))/kTwoPow16;
-- Invert raw data input if the analog channel is inverted at the
-- ADC/DAC input. Inversion of the minimum negative value (-2^kWidth)
-- needs to be done explicitly.
ProcInvert : process (cChIn)
begin
if (kInvert = false) then
-- For the inverted channel, because the inversion is done at the FPGA
-- level, the minimum negative value is -2^kWidth+1. For symmetry
-- reasons the non inverted channel also limits the minimum negative value
-- at -2^kWidth+1.
if (cChIn = kValMin(15 downto 16-kWidth)) then
cChInSigned <= signed(kValMax(15 downto 16-kWidth))+1;
else
cChInSigned <= signed(cChIn);
end if;
else
if (cChIn = kValMin(15 downto 16-kWidth)) then
cChInSigned <= signed(kValMax(15 downto 16-kWidth));
else
cChInSigned <= - signed (cChIn);
end if;
end if;
end process;
cChInReal <= Real(to_integer(cChInSigned));
-- Apply the offset and gain coefficients to the input samples.
cChOutReal <= (cChInReal*cLgCoefMultReal+cLgCoefAddReal*kTwoPowNadc) when (cGainState = '0')
else (cChInReal*cHgCoefMultReal+cHgCoefAddReal*kTwoPowNadc);
-- Saturate output.
ProcCalib : process (cChOutReal)
begin
if (cChOutReal > (kTwoPowNadc-1.0)) then
sChOutSigned <= to_signed(integer(kTwoPowNadc-1.0),kWidth);
elsif (cChOutReal < (-kTwoPowNadc)) then
sChOutSigned <= to_signed(integer(-kTwoPowNadc),kWidth);
else
sChOutSigned <= to_signed(integer(cChOutReal),kWidth);
end if;
end process;
-- Bypass the calibration process if the cTestMode signal is asserted.
cChOutAux <= std_logic_vector (sChOutSigned) when (cTestMode = '0') else cChIn;
-- Simulate the GainOffsetCaib module latency.
ProcDelay : process (SamplingClk)
begin
if (rising_edge(SamplingClk)) then
cChInDelayed(0) <= cChOutAux;
for Index in 1 to (kLatency-1) loop
cChInDelayed (Index) <= cChInDelayed (Index - 1);
end loop;
end if;
end process;
ProcOutput : process (cChInDelayed)
begin
if (cTestMode = '0') then
cChOut <= cChInDelayed(kLatency-1);
else
cChOut <= cChInDelayed(kTestLatency-1);
end if;
end process;
end Behavioral;
| mit |
Digilent/vivado-library | ip/clock_forwarder/hdl/clock_forwarder.vhd | 1 | 1829 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity clock_forwarder is
generic (
kArch : string := "artix7"
);
port (
aRst : in std_logic;
InClk : in std_logic;
iCE : in std_logic;
OutClk : out std_logic
);
end clock_forwarder;
architecture arch_imp of clock_forwarder is
begin
zynquplus: if kArch = "zynquplus" or kArch = "kintexuplus" or kArch = "virtexuplus" generate
begin
ODDRE1_inst : ODDRE1
generic map (
IS_C_INVERTED => '0', -- Optional inversion for C
IS_D1_INVERTED => '0', -- Unsupported, do not use
IS_D2_INVERTED => '0', -- Unsupported, do not use
SRVAL => '0' -- Initializes the ODDRE1 Flip-Flops to the specified value ('0', '1')
)
port map (
Q => OutClk, -- 1-bit output: Data output to IOB
C => InClk, -- 1-bit input: High-speed clock input
D1 => '1', -- 1-bit input: Parallel data input 1
D2 => '0', -- 1-bit input: Parallel data input 2
SR => aRst -- 1-bit input: Active High Async Reset
);
end generate zynquplus;
nonzynquplus: if not (kArch = "zynquplus" or kArch = "kintexuplus" or kArch = "virtexuplus") generate
begin
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => OutClk, -- 1-bit DDR output
C => InClk, -- 1-bit clock input
CE => iCE, -- 1-bit clock enable input
D1 => '1', -- 1-bit data input (positive edge)
D2 => '0', -- 1-bit data input (negative edge)
R => aRst, -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate nonzynquplus;
end arch_imp;
| mit |
Digilent/vivado-library | ip/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_rx_fifo.vhd | 7 | 1726 | library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
period_len : in integer range 0 to 65535;
-- Read port
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_rx_fifo is
signal out_stb : std_logic;
signal period_count : integer range 0 to 65535;
signal last : std_logic;
begin
M_AXIS_TVALID <= out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => in_ack,
in_data => in_data,
out_stb => out_stb,
out_ack => M_AXIS_TREADY,
out_data => M_AXIS_TDATA
);
M_AXIS_TKEEP <= "1111";
M_AXIS_TLAST <= '1' when period_count = 0 else '0';
period_counter: process(M_AXIS_ACLK) is
begin
if resetn = '0' then
period_count <= period_len;
else
if out_stb = '1' and M_AXIS_TREADY = '1' then
if period_count = 0 then
period_count <= period_len;
else
period_count <= period_count - 1;
end if;
end if;
end if;
end process;
end; | mit |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/vhdl/Loop_loop_height_jbC.vhd | 1 | 6941 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_jbC_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_jbC_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "00000000", 1 => "00000010", 2 => "00000011", 3 => "00000101",
4 => "00000110", 5 => "00001000", 6 => "00001010", 7 => "00001011",
8 => "00001101", 9 => "00001110", 10 => "00010000", 11 => "00010001",
12 => "00010011", 13 => "00010100", 14 => "00010110", 15 => "00010111",
16 => "00011001", 17 => "00011011", 18 => "00011100", 19 => "00011110",
20 => "00011111", 21 => "00100001", 22 => "00100010", 23 => "00100100",
24 => "00100101", 25 => "00100111", 26 => "00101000", 27 => "00101001",
28 => "00101011", 29 => "00101100", 30 => "00101110", 31 => "00101111",
32 => "00110001", 33 => "00110010", 34 => "00110100", 35 => "00110101",
36 => "00110111", 37 => "00111000", 38 => "00111001", 39 => "00111011",
40 => "00111100", 41 => "00111110", 42 => "00111111", 43 => "01000000",
44 => "01000010", 45 => "01000011", 46 => "01000101", 47 => "01000110",
48 => "01000111", 49 => "01001001", 50 => "01001010", 51 => "01001011",
52 => "01001101", 53 => "01001110", 54 => "01010000", 55 => "01010001",
56 => "01010010", 57 => "01010100", 58 => "01010101", 59 => "01010110",
60 => "01011000", 61 => "01011001", 62 => "01011010", 63 => "01011011",
64 => "01011101", 65 => "01011110", 66 => "01011111", 67 => "01100001",
68 => "01100010", 69 => "01100011", 70 => "01100100", 71 => "01100110",
72 => "01100111", 73 => "01101000", 74 => "01101010", 75 => "01101011",
76 => "01101100", 77 => "01101101", 78 => "01101110", 79 => "01110000",
80 => "01110001", 81 => "01110010", 82 => "01110011", 83 => "01110101",
84 => "01110110", 85 => "01110111", 86 => "01111000", 87 => "01111001",
88 => "01111011", 89 => "01111100", 90 => "01111101", 91 => "01111110",
92 => "01111111", 93 => "10000000", 94 => "10000010", 95 => "10000011",
96 => "10000100", 97 => "10000101", 98 => "10000110", 99 => "10000111",
100 => "10001000", 101 => "10001010", 102 => "10001011", 103 => "10001100",
104 => "10001101", 105 => "10001110", 106 => "10001111", 107 => "10010000",
108 => "10010001", 109 => "10010010", 110 => "10010100", 111 => "10010101",
112 => "10010110", 113 => "10010111", 114 => "10011000", 115 => "10011001",
116 => "10011010", 117 => "10011011", 118 => "10011100", 119 => "10011101",
120 => "10011110", 121 => "10011111", 122 => "10100000", 123 => "10100001",
124 => "10100010", 125 => "10100011", 126 => "10100100", 127 => "10100101",
128 => "10100110", 129 => "10100111", 130 => "10101000", 131 => "10101001",
132 => "10101010", 133 => "10101011", 134 => "10101100", 135 => "10101101",
136 => "10101110", 137 => "10101111", 138 => "10110000", 139 => "10110001",
140 => "10110010", 141 => "10110011", 142 => "10110100", 143 => "10110101",
144 => "10110110", 145 to 146=> "10110111", 147 => "10111000", 148 => "10111001",
149 => "10111010", 150 => "10111011", 151 => "10111100", 152 => "10111101",
153 => "10111110", 154 to 155=> "10111111", 156 => "11000000", 157 => "11000001",
158 => "11000010", 159 => "11000011", 160 => "11000100", 161 to 162=> "11000101",
163 => "11000110", 164 => "11000111", 165 => "11001000", 166 => "11001001",
167 to 168=> "11001010", 169 => "11001011", 170 => "11001100", 171 => "11001101",
172 to 173=> "11001110", 174 => "11001111", 175 => "11010000", 176 to 177=> "11010001",
178 => "11010010", 179 => "11010011", 180 => "11010100", 181 to 182=> "11010101",
183 => "11010110", 184 to 185=> "11010111", 186 => "11011000", 187 => "11011001",
188 to 189=> "11011010", 190 => "11011011", 191 to 192=> "11011100", 193 => "11011101",
194 => "11011110", 195 to 196=> "11011111", 197 => "11100000", 198 to 199=> "11100001",
200 => "11100010", 201 to 202=> "11100011", 203 to 204=> "11100100", 205 => "11100101",
206 to 207=> "11100110", 208 => "11100111", 209 to 210=> "11101000", 211 to 212=> "11101001",
213 => "11101010", 214 to 215=> "11101011", 216 to 217=> "11101100", 218 => "11101101",
219 to 220=> "11101110", 221 to 222=> "11101111", 223 to 224=> "11110000", 225 to 226=> "11110001",
227 to 228=> "11110010", 229 => "11110011", 230 to 231=> "11110100", 232 to 233=> "11110101",
234 to 235=> "11110110", 236 to 237=> "11110111", 238 to 240=> "11111000", 241 to 242=> "11111001",
243 to 244=> "11111010", 245 to 246=> "11111011", 247 to 248=> "11111100", 249 to 251=> "11111101",
252 to 253=> "11111110", 254 to 255=> "11111111" );
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_jbC is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_jbC is
component Loop_loop_height_jbC_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_jbC_rom_U : component Loop_loop_height_jbC_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
| mit |
Digilent/vivado-library | ip/Zmods/ZmodAWGController/src/GainOffsetCalib.vhd | 2 | 10718 |
-------------------------------------------------------------------------------
--
-- File: GainOffsetCalib.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module applies the gain and offset calibration to the raw data samples
-- received from the DataPath module.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity GainOffsetCalib is
Generic (
-- ADC/DAC number of bits
kWidth : integer range 10 to 16 := 14;
-- ADC/DAC dynamic/static calibration
kExtCalibEn : boolean := true;
-- When asserted, kInvert determines the sign inversion of the data samples
-- received. Used to compensate the physical inversion of some of the
-- channels on the PCB at the ADC/DAC input/output on the Zmod.
kInvert : boolean := false;
-- Low gain multiplicative (gain) compensation coefficient parameter
kLgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Low gain additive (offset) compensation coefficient parameter
kLgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- High gain multiplicative (gain) compensation coefficient parameter
kHgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- High gain additive (offset) compensation coefficient parameter
kHgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000"
);
Port (
-- Sampling clock
SamplingClk : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in the SamplingClk domain)
acRst_n : in STD_LOGIC;
-- cTestMode is used to bypass the calibration block. When this signal
-- is asserted, raw samples are provided on the data interface
cTestMode : in STD_LOGIC;
-- Low gain gain compensation coefficient external port
cExtLgMultCoef : in std_logic_vector (17 downto 0);
-- Low gain offset compensation coefficient external port
cExtLgAddCoef : in std_logic_vector (17 downto 0);
-- High gain gain compensation coefficient external port
cExtHgMultCoef : in std_logic_vector (17 downto 0);
-- High gain offset compensation coefficient external port
cExtHgAddCoef : in std_logic_vector (17 downto 0);
-- Gain Relay State (1 -> High Gain; 0 -> Low Gain)
cGainState : in std_logic;
-- Raw data input
cDataRaw : in STD_LOGIC_VECTOR (kWidth-1 downto 0);
-- Raw data valid signal
cDataInValid : in STD_LOGIC;
-- Calibrated output data
cCalibDataOut : out STD_LOGIC_VECTOR (15 downto 0);
-- Output data valid signal
cDataCalibValid : out STD_LOGIC
);
end GainOffsetCalib;
architecture Behavioral of GainOffsetCalib is
signal cDataRaw18bSigned : signed(17 downto 0);
signal cDataRaw18b : std_logic_vector(17 downto 0);
signal cCalibMult : signed(35 downto 0);
signal cCalibAdd : signed(35 downto 0);
signal cCoefAdd : std_logic_vector(35 downto 0);
signal cCoefAddSigned : signed(35 downto 0);
signal cCoefMult : std_logic_vector(17 downto 0);
signal cCoefMultSigned : signed(17 downto 0);
signal cCoefMultLg, cCoefMultHg : std_logic_vector (17 downto 0);
signal cCoefAddLg, cCoefAddHg : std_logic_vector (17 downto 0);
signal cDataInValidR : STD_LOGIC;
constant kDummy : std_logic_vector (17-kWidth downto 0) := (others => '0');
begin
--Channel1 low gain gain compensation coefficient (output port or IP parameter).
cCoefMultLg <= cExtLgMultCoef when kExtCalibEn = true else kLgMultCoefStatic;
--Channel1 high gain gain compensation coefficient (output port or IP parameter).
cCoefMultHg <= cExtHgMultCoef when kExtCalibEn = true else kHgMultCoefStatic;
--Channel1 low gain offset compensation coefficient (output port or IP parameter).
cCoefAddLg <= cExtLgAddCoef when kExtCalibEn = true else kLgAddCoefStatic;
--Channel1 high gain offset compensation coefficient (output port or IP parameter).
cCoefAddHg <= cExtHgAddCoef when kExtCalibEn = true else kHgAddCoefStatic;
-- Numerical representation of the calibration module's signals:
-- The first operation of the calibration block is represented by the multiplication
-- of the raw data input by the multiplicative coefficient. The multiplier's
-- operands are represented as follows:
-- 1. The input raw data is considered to be a fractional number < 1, consisting
-- of a sign bit and 17 fractional bits.
-- 2. The multiplicative coefficient, which can be slightly higher or slightly
-- lower than 1, is also represented on 18 bits, i.e. 1 sign bit, 1 integer bit,
-- and 16 fractional bis.
-- The result of the multiplication is a 36 bit number, consisting of a sign bit,
-- 2 integer bits and 33 fractional bits. Thus, to apply the additive coefficient,
-- (which is interpreted by the module as a 18 bit fractional number - 1 sign bit
-- + 17 fractional bits)the additive coefficient is also converted to this format
-- (sign extended by 2 bits and padded with 16 fractional bits).
-- Determine the additive coefficient based on the channel's gain relay state
-- and convert it to a 36 bit representation (as explained above).
ProcAddCoef : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCoefAdd <= (others => '0');
elsif (rising_edge(SamplingClk)) then
if (cGainState = '0') then --Low Gain
cCoefAdd <= cCoefAddLg(17) & cCoefAddLg(17) & cCoefAddLg & x"0000";
else --High Gain
cCoefAdd <= cCoefAddHg(17) & cCoefAddHg(17) & cCoefAddHg & x"0000";
end if;
end if;
end process;
-- Determine the multiplicative coefficient based on the channel's gain relay state.
ProcMultCoef : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCoefMult <= "010000000000000000";
elsif (rising_edge(SamplingClk)) then
if (cGainState = '0') then
cCoefMult <= cCoefMultLg;
else
cCoefMult <= cCoefMultHg;
end if;
end if;
end process;
cDataRaw18b <= cDataRaw & kDummy;
-- Invert raw data input if the analog channel is inverted at the
-- ADC/DAC input/output. Inversion of the minimum negative value (-2^kWidth)
-- needs to be done explicitly.
ProcInvert : process (cDataRaw18b)
begin
if (kInvert = false) then
if (cDataRaw18b = "100000000000000000") then
-- For the inverted channel, because the inversion is done at the FPGA
-- level, the minimum negative value is -2^kWidth+1. For symmetry
-- reasons the non inverted channel also limits the minimum negative value
-- at -2^kWidth+1.
cDataRaw18bSigned <= "100000000000000001";
else
cDataRaw18bSigned <= signed(cDataRaw18b);
end if;
else
if (cDataRaw18b = "100000000000000000") then
cDataRaw18bSigned <= "011111111111111111";
else
cDataRaw18bSigned <= - signed (cDataRaw18b);
end if;
end if;
end process;
cCoefMultSigned <= signed (cCoefMult);
cCoefAddSigned <= signed (cCoefAdd);
-- Apply the multiplicative coefficient. Register multiplication result.
ProcRegMultResult : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCalibMult <= (others => '0');
cDataInValidR <= '0';
elsif (rising_edge(SamplingClk)) then
cCalibMult <= cDataRaw18bSigned * cCoefMultSigned;
--Data out valid flag must be synchronized with its corresponding sample.
cDataInValidR <= cDataInValid;
end if;
end process;
-- Apply additive coefficient.
cCalibAdd <= cCalibMult + cCoefAddSigned;
-- Register calibration result; the calibration output is saturated at
-- 2^kWidth - 1 for positive values or -2^kWidth for negative values;
-- the calibration process is bypassed if cTestMode = '1'.
ProcCalib : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCalibDataOut <= (others => '0');
cDataCalibValid <= '0';
elsif (rising_edge(SamplingClk)) then
if (cTestMode = '0') then
if ((cCalibAdd(35) = '1') and (cCalibAdd(34 downto 33) /= "11")) then
cCalibDataOut <= x"8000";
elsif ((cCalibAdd(35) = '0') and (cCalibAdd(34 downto 33) /= "00")) then
cCalibDataOut <= x"7FFF";
else
cCalibDataOut <= std_logic_vector (cCalibAdd(33 downto 18));
end if;
--Data out valid flag must be synchronized with its corresponding sample.
cDataCalibValid <= cDataInValidR;
else
cCalibDataOut <= cDataRaw18b(17 downto 2);
cDataCalibValid <= cDataInValid;
end if;
end if;
end process;
end Behavioral;
| mit |
Digilent/vivado-library | ip/Zmods/ZmodDigitizerController/tb/ClockGen_I2C_DataCheck.vhd | 1 | 8724 | -------------------------------------------------------------------------------
--
-- File: ClockGen_I2C_DataCheck.vhd
-- Author: Elod Gyorgy, Robert Bocos
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This modules checks the data sent over I2C by the ConfigClockGen module
-- and compares it with the actual configuration data. Sends out an ERROR
-- when there is a mismatch.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
use work.PkgZmodDigitizer.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ClockGen_I2C_DataCheck is
Generic (
kSampleClkFreqInMHz : natural := 100;
kSlaveAddress : std_logic_vector(7 downto 1) := "1101000";
kFreqSel : integer range 0 to 7 := 0
);
Port (
SampleClk : in STD_LOGIC; --at least fSCL*10
sRst : in std_logic;
sI2C_DataOut : out std_logic_vector(7 downto 0);
-- two-wire interface
aSDA_I : in STD_LOGIC;
aSDA_O : out STD_LOGIC;
aSDA_T : out STD_LOGIC;
aSCL_I : in STD_LOGIC;
aSCL_O : out STD_LOGIC;
aSCL_T : out STD_LOGIC);
end ClockGen_I2C_DataCheck;
architecture Behavioral of ClockGen_I2C_DataCheck is
signal sState, sNstate : FsmStatesI2C_t := stIdle;
signal sI2C_DataIn : std_logic_vector(7 downto 0);
signal sI2C_Stb, sI2C_Done, sI2C_End, sI2C_RdWrn : std_logic;
signal sCmdCnt : unsigned(6 downto 0) := (others => '0');
signal sIncCmdCnt : std_logic := '0';
signal sRstCmdCnt : std_logic := '0';
begin
-- Instantiate the I2C Slave Receiver
I2C_SlaveController: entity work.TWI_SlaveCtl
generic map (
SLAVE_ADDRESS => kSlaveAddress & '0',
kSampleClkFreqInMHz => kSampleClkFreqInMHz)
port map (
D_I => (others => '0'),
D_O => sI2C_DataIn,
RD_WRN_O => sI2C_RdWrn,
END_O => sI2C_End,
DONE_O => sI2C_Done,
STB_I => sI2C_Stb,
SampleClk => SampleClk,
SRST => sRst,
--two-wire interface
SDA_I => aSDA_I,
SDA_O => aSDA_O,
SDA_T => aSDA_T,
SCL_I => aSCL_I,
SCL_O => aSCL_O,
SCL_T => aSCL_T);
RegisteredOutputs: process (SampleClk)
begin
if (sRst = '1') then
sRstCmdCnt <= '0';
elsif Rising_Edge(SampleClk) then
if (sI2C_Done = '1') then
if (sState = stRegAddress_H or sState = stRegAddress_L or sState = stRegData_H or sState = stRegData_L) then
sI2C_DataOut <= sI2C_DataIn;
sRstCmdCnt <= '1';
elsif (sState = stCheckCmdCnt) then
sRstCmdCnt <= '1';
end if;
elsif (sI2C_End = '1') then
sRstCmdCnt <= '0';
end if;
end if;
end process RegisteredOutputs;
ProcCmdCheck: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sI2C_Done = '1') then
if (sState = stRegAddress_H) then
assert sI2C_DataIn = CDCE_I2C_Cmds(kFreqSel)(to_integer(sCmdCnt))(31 downto 24)
report "Mismatch between sent CDCE I2C commands and received CDCE I2C commands" & LF & HT & HT
severity ERROR;
elsif (sState = stRegAddress_L) then
assert sI2C_DataIn = CDCE_I2C_Cmds(kFreqSel)(to_integer(sCmdCnt))(23 downto 16)
report "Mismatch between sent CDCE I2C commands and received CDCE I2C commands" & LF & HT & HT
severity ERROR;
elsif (sState = stRegData_H) then
assert sI2C_DataIn = CDCE_I2C_Cmds(kFreqSel)(to_integer(sCmdCnt))(15 downto 8)
report "Mismatch between sent CDCE I2C commands and received CDCE I2C commands" & LF & HT & HT
severity ERROR;
elsif (sState = stRegData_L) then
assert sI2C_DataIn = CDCE_I2C_Cmds(kFreqSel)(to_integer(sCmdCnt))(7 downto 0)
report "Mismatch between sent CDCE I2C commands and received CDCE I2C commands" & LF & HT & HT
severity ERROR;
end if;
end if;
end if;
end process ProcCmdCheck;
-- Counter used to track the number of successfully received commands.
ProcCmdCounter: process (SampleClk, sRst)
begin
if (sRst = '1') then
sCmdCnt <= (others => '0');
elsif (rising_edge(SampleClk)) then
if (sRstCmdCnt = '0') then
sCmdCnt <= (others => '0');
elsif (sIncCmdCnt = '1') then
sCmdCnt <= sCmdCnt + 1;
end if;
end if;
end process;
-- State machine synchronous process.
SyncProc: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sRst = '1') then
sState <= stIdle;
else
sState <= sNstate;
end if;
end if;
end process SyncProc;
--MOORE State-Machine - Outputs based on state only
sI2C_Stb <= '1' when (sState = stRegAddress_H or sState = stRegAddress_L or sState = stRegData_H or sState = stRegData_L) else '0';
sIncCmdCnt <= '1' when (sState = StCheckCmdCnt) else '0';
NextStateDecode: process (sState, sI2C_Done, sI2C_End, sI2C_RdWrn)
begin
--declare default state for next_state to avoid latches
sNstate <= sState;
case (sState) is
when stIdle =>
if (sI2C_Done = '1') then
if (sI2C_RdWrn = '1') then
sNstate <= stIdle;
else
sNstate <= stRegAddress_H;
end if;
end if;
when stRegAddress_H =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= stRegAddress_L;
end if;
when stRegAddress_L =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= stRegData_H;
end if;
when stRegData_H =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= stRegData_L;
end if;
when stRegData_L =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= StCheckCmdCnt;
end if;
when StCheckCmdCnt =>
if (sI2C_End = '1') then
sNstate <= stIdle;
else
sNstate <= stRegAddress_H;
end if;
when others =>
sNstate <= stIdle;
end case;
end process NextStateDecode;
end Behavioral; | mit |
chriz2600/DreamcastHDMI | Core/source/adv7513/i2c_master.vhd | 1 | 14369 | --------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/01/2012 Scott Larson
-- Initial Public Release
-- Version 2.0 06/20/2014 Scott Larson
-- Added ability to interface with different slaves in the same transaction
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
-- Corrected timing of when ack_error signal clears
-- Version 2.1 10/21/2014 Scott Larson
-- Replaced gated clock with clock enable
-- Adjusted timing of SCL during start and stop conditions
-- Version 2.2 02/05/2015 Scott Larson
-- Corrected small SDA glitch introduced in version 2.1
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC; --serial clock output of i2c bus
divider : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --data clock for sda
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
BEGIN
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO 255; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
data_clk_prev <= data_clk; --store previous value of data clock
IF(count = divider(31 downto 24)-1) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
IF(count < divider(7 downto 0)) THEN
scl_clk <= '0';
data_clk <= '0';
ELSIF(count < divider(15 downto 8)) THEN
scl_clk <= '0';
data_clk <= '1';
ELSIF(count < divider(23 downto 16)) THEN
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
ELSE
scl_clk <= '1';
data_clk <= '0';
END IF;
-- IF(count < div1) THEN
-- scl_clk <= '0';
-- data_clk <= '0';
-- ELSIF(count < div2) THEN
-- scl_clk <= '0';
-- data_clk <= '1';
-- ELSIF(count < div3) THEN
-- scl_clk <= '1'; --release scl
-- IF(scl = '0') THEN --detect if slave is stretching clock
-- stretch <= '1';
-- ELSE
-- stretch <= '0';
-- END IF;
-- data_clk <= '1';
-- ELSE
-- scl_clk <= '1';
-- data_clk <= '0';
-- END IF;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
ELSIF(clk'EVENT AND clk = '1') THEN
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
CASE state IS
WHEN ready => --idle state
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack2; --go to slave acknowledge (write)
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another write
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
busy <= '0'; --unflag busy
state <= ready; --go to idle state
END CASE;
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
scl_ena <= '1'; --enable scl output
ack_error <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN stop =>
scl_ena <= '0'; --disable scl
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS;
--set sda output
WITH state SELECT
sda_ena_n <= data_clk_prev WHEN start, --generate start condition
NOT data_clk_prev WHEN stop, --generate stop condition
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
END logic;
| mit |
chrismasters/fpga-space-invaders | project/ipcore_dir/ram/simulation/random.vhd | 101 | 4108 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| mit |
chrismasters/fpga-space-invaders | project/ipcore_dir/testmem/simulation/bmg_tb_pkg.vhd | 101 | 6006 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
| mit |
chrismasters/fpga-space-invaders | project/doublebyteregister.vhd | 1 | 790 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DoubleByteRegister is
Port (
clk : in STD_LOGIC;
load : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (15 downto 0);
dataOut : out STD_LOGIC_VECTOR (15 downto 0)
);
end DoubleByteRegister;
architecture Behavioral of DoubleByteRegister is
begin
loadproc:
process (clk)
begin
-- if (rising_edge(clk)) then
if (falling_edge(clk)) then
if (load = '1') then
dataOut <= dataIn;
end if;
end if;
end process loadproc;
end Behavioral;
| mit |
chrismasters/fpga-space-invaders | project/ipcore_dir/ram/simulation/ram_tb.vhd | 1 | 4292 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ram_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ram_tb IS
END ENTITY;
ARCHITECTURE ram_tb_ARCH OF ram_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ram_synth_inst:ENTITY work.ram_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/SinDPStratixVf400_safe_path.vhd | 10 | 427 | -- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END SinDPStratixVf400_safe_path;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/dp_lnclzpipe.vhd | 10 | 7272 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNCLZPIPE.VHD ***
--*** ***
--*** Function: Double Precision CLZ pipelined ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnclzpipe IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END dp_lnclzpipe;
ARCHITECTURE rtl of dp_lnclzpipe IS
type positiontype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionff, positionmux : positiontype;
signal zerogroup, zerogroupff, firstzero : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lastman : STD_LOGIC_VECTOR (6 DOWNTO 1);
component dp_pos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(64) OR mantissa(63) OR mantissa(62) OR mantissa(61) OR mantissa(60) OR mantissa(59);
zerogroup(2) <= mantissa(58) OR mantissa(57) OR mantissa(56) OR mantissa(55) OR mantissa(54) OR mantissa(53);
zerogroup(3) <= mantissa(52) OR mantissa(51) OR mantissa(50) OR mantissa(49) OR mantissa(48) OR mantissa(47);
zerogroup(4) <= mantissa(46) OR mantissa(45) OR mantissa(44) OR mantissa(43) OR mantissa(42) OR mantissa(41);
zerogroup(5) <= mantissa(40) OR mantissa(39) OR mantissa(38) OR mantissa(37) OR mantissa(36) OR mantissa(35);
zerogroup(6) <= mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31) OR mantissa(30) OR mantissa(29);
zerogroup(7) <= mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25) OR mantissa(24) OR mantissa(23);
zerogroup(8) <= mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19) OR mantissa(18) OR mantissa(17);
zerogroup(9) <= mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13) OR mantissa(12) OR mantissa(11);
zerogroup(10) <= mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7) OR mantissa(6) OR mantissa(5);
zerogroup(11) <= mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
pa: dp_pos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(64 DOWNTO 59),position=>position(1)(6 DOWNTO 1));
pb: dp_pos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(58 DOWNTO 53),position=>position(2)(6 DOWNTO 1));
pc: dp_pos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(52 DOWNTO 47),position=>position(3)(6 DOWNTO 1));
pd: dp_pos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(46 DOWNTO 41),position=>position(4)(6 DOWNTO 1));
pe: dp_pos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(40 DOWNTO 35),position=>position(5)(6 DOWNTO 1));
pf: dp_pos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(34 DOWNTO 29),position=>position(6)(6 DOWNTO 1));
pg: dp_pos
GENERIC MAP (start=>36)
PORT MAP (ingroup=>mantissa(28 DOWNTO 23),position=>position(7)(6 DOWNTO 1));
ph: dp_pos
GENERIC MAP (start=>42)
PORT MAP (ingroup=>mantissa(22 DOWNTO 17),position=>position(8)(6 DOWNTO 1));
pi: dp_pos
GENERIC MAP (start=>48)
PORT MAP (ingroup=>mantissa(16 DOWNTO 11),position=>position(9)(6 DOWNTO 1));
pj: dp_pos
GENERIC MAP (start=>54)
PORT MAP (ingroup=>mantissa(10 DOWNTO 5),position=>position(10)(6 DOWNTO 1));
pk: dp_pos
GENERIC MAP (start=>60)
PORT MAP (ingroup=>lastman,position=>position(11)(6 DOWNTO 1));
lastman <= mantissa(4 DOWNTO 1) & "00";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 11 LOOP
zerogroupff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
FOR j IN 1 TO 6 LOOP
positionff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
zerogroupff <= zerogroup;
FOR k IN 1 TO 11 LOOP
positionff(k)(6 DOWNTO 1) <= position(k)(6 DOWNTO 1);
END LOOP;
END IF;
END PROCESS;
firstzero(1) <= zerogroupff(1);
firstzero(2) <= NOT(zerogroupff(1)) AND zerogroupff(2);
firstzero(3) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND zerogroupff(3);
firstzero(4) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND zerogroupff(4);
firstzero(5) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND zerogroupff(5);
firstzero(6) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND NOT(zerogroupff(5)) AND zerogroupff(6);
firstzero(7) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND zerogroupff(7);
firstzero(8) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND
NOT(zerogroupff(7)) AND zerogroupff(8);
firstzero(9) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND
NOT(zerogroupff(7)) AND NOT(zerogroupff(8)) AND zerogroupff(9);
firstzero(10) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND
NOT(zerogroupff(7)) AND NOT(zerogroupff(8)) AND NOT(zerogroupff(9)) AND zerogroupff(10);
firstzero(11) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND
NOT(zerogroupff(7)) AND NOT(zerogroupff(8)) AND NOT(zerogroupff(9)) AND
NOT(zerogroupff(10)) AND zerogroupff(11);
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= positionff(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 11 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (positionff(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(11)(6 DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fp_tanlut1.vhd | 10 | 94202 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_TANLUT1.VHD ***
--*** ***
--*** Function: Tangent Look Up Table ***
--*** (Generated by MATLAB Utility) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_tanlut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_tanlut1;
ARCHITECTURE rtl OF fp_tanlut1 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5);
WHEN "000000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131072,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174764,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5);
WHEN "000000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131074,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174780,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(1,5);
WHEN "000000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196617,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(130,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(1,5);
WHEN "000000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131082,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175036,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5);
WHEN "000000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163860,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219287,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5);
WHEN "000000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196644,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(2074,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5);
WHEN "000000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229433,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48174,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5);
WHEN "000001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131114,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(179133,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147516,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(204485,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163923,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(100723,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180334,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(261788,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196752,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33207,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213175,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71403,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229604,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(246559,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246041,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166927,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131242,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(244778,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139469,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(18368,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147699,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126224,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155934,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110829,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164174,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39099,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172418,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(240249,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180668,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(257224,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188924,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(157429,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197186,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(8449,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205453,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140199,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213727,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96362,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222007,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(207256,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230295,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16983,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(238589,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118443,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246891,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(56191,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255200,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161457,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131758,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(251787,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135921,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182851,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140088,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(170994,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144259,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(251287,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148435,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196795,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152616,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(42877,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156801,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(87190,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160991,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(103258,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165186,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126910,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169386,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194144,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173592,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78984,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(177803,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79918,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182019,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(233473,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186242,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52073,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190470,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96910,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194704,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142940,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198944,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(227466,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(203191,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125851,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207444,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(137961,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211704,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39590,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215970,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(131044,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220243,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(188568,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224523,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(250786,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(228811,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94417,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233106,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(20713,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69033,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(241718,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16848,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246035,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166180,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250361,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32888,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(254694,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(181681,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259036,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(128971,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131693,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(88946,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133872,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184862,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136056,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110880,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138244,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(150087,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140437,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61438,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142634,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(128336,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144836,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110058,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147043,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(28193,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149254,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166641,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(151471,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(23046,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153692,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(143802,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155919,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(26909,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158150,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219127,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160387,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218828,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162630,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48862,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164877,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(256563,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167131,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78745,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169390,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63145,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171654,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(233418,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173925,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89145,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176201,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(178694,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178484,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(2082,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180772,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108121,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(183066,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(259423,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(185367,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218831,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187675,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(11570,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189988,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(187394,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192308,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(247729,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194635,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218538,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196969,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126042,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(199309,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(258866,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(201657,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(119470,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204011,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(259160,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(206373,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180942,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208742,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174537,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211119,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5664,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213502,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(226767,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215894,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79866,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218293,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118006,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220700,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108111,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223115,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79560,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(225538,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62056,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(227969,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85630,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180644,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(232856,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(115658,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(235312,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(183865,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237777,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(154523,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240251,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(59395,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(242733,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(192751,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(245225,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62806,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(247725,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(226729,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250235,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(193502,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(252754,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(258933,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255283,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194946,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(257822,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36018,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(260370,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79189,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131464,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48818,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132748,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63557,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134037,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(101912,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135331,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182207,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136631,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(60853,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137936,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(18783,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139246,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(75024,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140561,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248849,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141883,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(35488,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143209,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241146,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144542,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(99421,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145880,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(154894,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147224,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(165983,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148574,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153522,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149930,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(138624,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(151292,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142687,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152660,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(187397,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154035,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32592,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155415,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(224845,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156803,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(313,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158196,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(168333,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159596,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(227841,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(161003,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202385,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162417,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(115847,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163837,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(254593,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165265,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118901,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166699,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(257978,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168141,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(172818,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169590,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(151210,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171046,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219176,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172510,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140977,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173981,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(205552,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175460,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(177949,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176947,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85768,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178441,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219166,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179944,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(82294,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(181454,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(228309,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182973,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(162236,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(184500,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175979,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186036,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37616,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187580,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39982,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189132,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214250,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190694,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(67791,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192264,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(157055,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(193843,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(252568,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(195432,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125382,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197030,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71365,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198637,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(124791,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(200254,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(58341,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(201880,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169556,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(203516,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(232268,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205163,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(20904,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(206819,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96928,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208485,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(235993,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(210162,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214385,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211850,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71183,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213548,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108271,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215257,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(103923,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216977,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(99249,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218708,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(136066,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220450,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(256917,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222204,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(242940,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223970,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(138174,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(225747,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249580,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(227537,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(98477,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229338,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(255571,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231152,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(243824,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(232979,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111333,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(234818,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169210,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(236670,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(205169,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(238536,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(7833,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240414,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153192,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(242306,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169612,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244212,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110728,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246132,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31174,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248065,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248754,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250014,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33745,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251976,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230368,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(253954,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111078,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255946,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(260182,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(257954,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214570,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259978,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36603,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(262017,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52004,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132036,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31728,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133071,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(199603,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134115,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(170119,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135167,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(239798,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136228,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(181565,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137298,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31195,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138376,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(87334,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139463,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125082,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140559,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182447,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141665,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36078,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142779,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249858,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143904,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(77779,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145038,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85397,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(146182,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52708,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147336,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(22748,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148500,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39467,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149674,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(147762,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(150859,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(131351,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152055,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37096,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153261,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175023,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154479,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69779,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155708,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33524,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156948,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(117385,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158200,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111488,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159464,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69279,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160740,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45413,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162028,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(95789,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163329,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(15442,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164642,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125012,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165968,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(222206,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167308,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(106129,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168661,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(101608,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(170028,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(10664,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161129,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172803,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(95974,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(174212,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(146219,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175636,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(120264,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(177075,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(90370,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178529,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(130571,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179999,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(54581,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(181484,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202287,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182986,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(129087,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(184504,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(178815,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186039,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173083,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187591,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(197786,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189161,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78873,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190748,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(168858,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192354,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36174,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(193978,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(38109,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(195621,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(10173,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197283,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52606,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198965,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(6187,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(200666,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(238745,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202389,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(72398,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204132,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142943,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205897,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(40664,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207683,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(145442,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(209492,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(54008,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211323,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(152917,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213178,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45809,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215056,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126393,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216959,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5720,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218886,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85177,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220838,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(245917,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222817,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111146,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224822,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94854,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(226854,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(91265,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(228913,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(261427,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231001,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(246970,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233118,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218857,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(235265,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(91152,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237442,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45510,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(239650,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(7099,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(241889,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169116,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244161,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(206583,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246467,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63025,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248806,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(212871,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251181,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(88861,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(253591,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(179473,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(256038,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194218,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(258523,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(112522,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(261046,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184058,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131804,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202396,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133106,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(127604,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134429,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5700,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135772,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241668,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137138,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196914,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138527,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(24498,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139938,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(145076,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141373,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(198575,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142833,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(93021,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144318,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(4818,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145828,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(116886,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147365,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94683,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148929,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(135102,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(150521,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180373,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152142,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180573,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153793,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94005,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155474,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(149742,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(157187,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61623,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158932,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(77284,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160710,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(192200,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162523,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(150199,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164371,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230433,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166256,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(199372,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168179,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(97853,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(170140,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241724,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172142,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173961,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(174185,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(238269,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176272,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(6999,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178402,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(116996,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180578,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173338,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182802,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61011,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(185074,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(208074,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187398,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(13879,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189773,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(209544,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192203,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(237754,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194690,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89118,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197235,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(41457,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(199840,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(137068,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202508,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184378,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205242,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(21881,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208043,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(44347,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(210914,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(156319,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213859,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36498,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216879,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(188732,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(219979,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(109619,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223161,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126346,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(226429,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89021,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229786,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(160435,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233237,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33224,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(236784,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(244509,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240434,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(83006,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244189,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(215105,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248056,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(68494,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(252038,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196984,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(256142,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(189406,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(260373,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249093,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132369,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(76283,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134621,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153043,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136947,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(90777,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139350,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(80594,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141834,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118724,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144404,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(12410,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147063,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(172855,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149818,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(49588,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152672,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(235640,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155633,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(117182,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158705,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(242792,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(161896,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(237423,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165213,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125600,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168663,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(83253,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172254,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191313,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175996,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191297,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179899,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(29637,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(183972,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142533,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188228,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(171026,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192680,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(38953,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197340,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248662,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202226,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(84469,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207353,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16170,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(212739,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(177173,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218406,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161382,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224376,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140334,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230674,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(156722,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237328,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218000,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244370,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(144312,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251834,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(222783,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259761,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(51093,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134097,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16112,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138592,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(11144,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143394,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(60483,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148536,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(104003,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154056,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37731,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159996,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218457,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191255,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173350,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(113148,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180890,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(176944,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189110,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(163200,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198106,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(211327,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207994,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(247747,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218914,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(252397,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "110000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231037,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174172,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "110000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244573,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(197553,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "110000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259786,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(53842,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "110000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138503,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202780,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148332,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62994,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159656,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230897,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172847,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(240508,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(183509,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207041,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(119228,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229756,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71260,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(258060,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153597,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147154,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32322,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5);
WHEN "110001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171195,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78299,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5);
WHEN "110001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204618,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(105365,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5);
WHEN "110001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(254248,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(141622,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5);
WHEN "110001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167825,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(19278,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(14,5);
WHEN "110010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246850,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(149873,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(14,5);
WHEN "110010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233251,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(216105,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(15,5);
WHEN "110010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132278,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191927,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(19,5);
WHEN others =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_hypot_s5.vhd | 10 | 263346 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_hypot_s5
-- VHDL created on Tue Mar 12 11:24:00 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_hypot_s5 is
port (
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_hypot_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid10_fpHypotTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid11_fpHypotTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpHypotTest_q : std_logic_vector (7 downto 0);
signal oFracXSqr_uid45_fpHypotTest_a : std_logic_vector (23 downto 0);
signal oFracXSqr_uid45_fpHypotTest_b : std_logic_vector (23 downto 0);
signal oFracXSqr_uid45_fpHypotTest_s1 : std_logic_vector (47 downto 0);
signal oFracXSqr_uid45_fpHypotTest_pr : UNSIGNED (47 downto 0);
signal oFracXSqr_uid45_fpHypotTest_q : std_logic_vector (47 downto 0);
signal oFracYSqr_uid46_fpHypotTest_a : std_logic_vector (23 downto 0);
signal oFracYSqr_uid46_fpHypotTest_b : std_logic_vector (23 downto 0);
signal oFracYSqr_uid46_fpHypotTest_s1 : std_logic_vector (47 downto 0);
signal oFracYSqr_uid46_fpHypotTest_pr : UNSIGNED (47 downto 0);
signal oFracYSqr_uid46_fpHypotTest_q : std_logic_vector (47 downto 0);
signal bias_uid47_fpHypotTest_q : std_logic_vector (6 downto 0);
signal cWFP2_uid66_fpHypotTest_q : std_logic_vector (4 downto 0);
signal oFracA_uid68_fpHypotTest_s : std_logic_vector (0 downto 0);
signal oFracA_uid68_fpHypotTest_q : std_logic_vector (23 downto 0);
signal z_uid71_fpHypotTest_q : std_logic_vector (4 downto 0);
signal excAZero_uid74_fpHypotTest_s : std_logic_vector (0 downto 0);
signal excAZero_uid74_fpHypotTest_q : std_logic_vector (0 downto 0);
signal excBZero_uid75_fpHypotTest_s : std_logic_vector (0 downto 0);
signal excBZero_uid75_fpHypotTest_q : std_logic_vector (0 downto 0);
signal zerosWFp1_uid77_fpHypotTest_q : std_logic_vector (23 downto 0);
signal oFracAPostExc_uid79_fpHypotTest_s : std_logic_vector (0 downto 0);
signal oFracAPostExc_uid79_fpHypotTest_q : std_logic_vector (23 downto 0);
signal biasP1Signal_uid99_fpHypotTest_q : std_logic_vector (6 downto 0);
signal expRMux_uid104_fpHypotTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid104_fpHypotTest_q : std_logic_vector (9 downto 0);
signal xRegOrZero_uid121_fpHypotTest_a : std_logic_vector(0 downto 0);
signal xRegOrZero_uid121_fpHypotTest_b : std_logic_vector(0 downto 0);
signal xRegOrZero_uid121_fpHypotTest_q : std_logic_vector(0 downto 0);
signal yRegOrZero_uid123_fpHypotTest_a : std_logic_vector(0 downto 0);
signal yRegOrZero_uid123_fpHypotTest_b : std_logic_vector(0 downto 0);
signal yRegOrZero_uid123_fpHypotTest_q : std_logic_vector(0 downto 0);
signal NaNFracRPostExc_uid133_fpHypotTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx2Pad16_uid149_alignShift_uid81_fpHypotTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx1Pad2_uid157_alignShift_uid81_fpHypotTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage1Idx2Pad4_uid160_alignShift_uid81_fpHypotTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad6_uid163_alignShift_uid81_fpHypotTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid173_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid173_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid173_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid173_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid173_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid173_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid174_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid174_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid174_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid174_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid174_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid174_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid175_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid175_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid175_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid175_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid175_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid175_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0_q : std_logic_vector (23 downto 0);
signal reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0_q : std_logic_vector (23 downto 0);
signal reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q : std_logic_vector (9 downto 0);
signal reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0_q : std_logic_vector (9 downto 0);
signal reg_expDiff_uid65_fpHypotTest_0_to_shiftedOut_uid67_fpHypotTest_0_q : std_logic_vector (9 downto 0);
signal reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2_q : std_logic_vector (4 downto 0);
signal reg_rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_q : std_logic_vector (0 downto 0);
signal reg_highBBits_uid83_fpHypotTest_0_to_sumAHighB_uid84_fpHypotTest_1_q : std_logic_vector (23 downto 0);
signal reg_lowRangeB_uid82_fpHypotTest_0_to_soSPreNorm_uid82_uid85_fpHypotTest_0_q : std_logic_vector (0 downto 0);
signal reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0_q : std_logic_vector (33 downto 0);
signal reg_normCatFracSoS_uid93_uid93_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_1_q : std_logic_vector (24 downto 0);
signal reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q : std_logic_vector (9 downto 0);
signal reg_addrTable_uid107_fpHypotTest_0_to_memoryC2_uid175_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid176_sqrtPolynomialEvaluator_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid175_sqrtTableGenerator_lutmem_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0_q : std_logic_vector (20 downto 0);
signal reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid178_uid181_sqrtPolynomialEvaluator_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0_q : std_logic_vector (28 downto 0);
signal reg_fracRPreInc_uid110_fpHypotTest_0_to_fracRPostInc_uid111_fpHypotTest_0_q : std_logic_vector (24 downto 0);
signal reg_fracRPostIncMSBU_uid113_fpHypotTest_0_to_expRPostInc_uid114_fpHypotTest_1_q : std_logic_vector (0 downto 0);
signal reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q : std_logic_vector (10 downto 0);
signal reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_q : std_logic_vector (7 downto 0);
signal ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_q : std_logic_vector (7 downto 0);
signal ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q : std_logic_vector (9 downto 0);
signal ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b_q : std_logic_vector (0 downto 0);
signal ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b_q : std_logic_vector (9 downto 0);
signal ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c_q : std_logic_vector (23 downto 0);
signal ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d_q : std_logic_vector (23 downto 0);
signal ld_expXIsZero_uid14_fpHypotTest_q_to_excAZero_uid74_fpHypotTest_d_q : std_logic_vector (0 downto 0);
signal ld_oFracB_uid69_fpHypotTest_q_to_oFracBPostExc_uid78_fpHypotTest_c_q : std_logic_vector (23 downto 0);
signal ld_oFracAPostExc_uid79_fpHypotTest_q_to_sumAHighB_uid84_fpHypotTest_a_q : std_logic_vector (23 downto 0);
signal ld_expOddSelect_uid103_fpHypotTest_q_to_expRMux_uid104_fpHypotTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid139_fpHypotTest_b_to_expRPostExc_uid141_fpHypotTest_d_q : std_logic_vector (7 downto 0);
signal ld_RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_b_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b_to_reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_inputreg_q : std_logic_vector (9 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_reset0 : std_logic;
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_ia : std_logic_vector (9 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_iq : std_logic_vector (9 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_q : std_logic_vector (9 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena_q : signal is true;
signal ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_inputreg_q : std_logic_vector (9 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_reset0 : std_logic;
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_ia : std_logic_vector (9 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_iq : std_logic_vector (9 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_q : std_logic_vector (9 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_eq : std_logic;
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena_q : signal is true;
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_eq : std_logic;
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena_q : signal is true;
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena_q : signal is true;
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_reset0 : std_logic;
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena_q : signal is true;
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_reset0 : std_logic;
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_eq : std_logic;
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena_q : signal is true;
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_reset0 : std_logic;
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena_q : signal is true;
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena_q : signal is true;
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena_q : signal is true;
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena_q : signal is true;
signal ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal pGTEq_uid60_fpHypotTest_a : std_logic_vector(12 downto 0);
signal pGTEq_uid60_fpHypotTest_b : std_logic_vector(12 downto 0);
signal pGTEq_uid60_fpHypotTest_o : std_logic_vector (12 downto 0);
signal pGTEq_uid60_fpHypotTest_cin : std_logic_vector (0 downto 0);
signal pGTEq_uid60_fpHypotTest_n : std_logic_vector (0 downto 0);
signal shiftedOut_uid67_fpHypotTest_a : std_logic_vector(12 downto 0);
signal shiftedOut_uid67_fpHypotTest_b : std_logic_vector(12 downto 0);
signal shiftedOut_uid67_fpHypotTest_o : std_logic_vector (12 downto 0);
signal shiftedOut_uid67_fpHypotTest_cin : std_logic_vector (0 downto 0);
signal shiftedOut_uid67_fpHypotTest_n : std_logic_vector (0 downto 0);
signal sqrtUnderflow_uid115_fpHypotTest_a : std_logic_vector(13 downto 0);
signal sqrtUnderflow_uid115_fpHypotTest_b : std_logic_vector(13 downto 0);
signal sqrtUnderflow_uid115_fpHypotTest_o : std_logic_vector (13 downto 0);
signal sqrtUnderflow_uid115_fpHypotTest_cin : std_logic_vector (0 downto 0);
signal sqrtUnderflow_uid115_fpHypotTest_n : std_logic_vector (0 downto 0);
signal sqrtOverflow_uid117_fpHypotTest_a : std_logic_vector(13 downto 0);
signal sqrtOverflow_uid117_fpHypotTest_b : std_logic_vector(13 downto 0);
signal sqrtOverflow_uid117_fpHypotTest_o : std_logic_vector (13 downto 0);
signal sqrtOverflow_uid117_fpHypotTest_cin : std_logic_vector (0 downto 0);
signal sqrtOverflow_uid117_fpHypotTest_n : std_logic_vector (0 downto 0);
signal fracRPostInc_uid111_fpHypotTest_a : std_logic_vector(25 downto 0);
signal fracRPostInc_uid111_fpHypotTest_b : std_logic_vector(25 downto 0);
signal fracRPostInc_uid111_fpHypotTest_o : std_logic_vector (25 downto 0);
signal fracRPostInc_uid111_fpHypotTest_q : std_logic_vector (25 downto 0);
signal expCatRndBit_uid91_uid92_fpHypotTest_q : std_logic_vector (33 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpHypotTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpHypotTest_b : std_logic_vector (7 downto 0);
signal fracX_uid8_fpHypotTest_in : std_logic_vector (22 downto 0);
signal fracX_uid8_fpHypotTest_b : std_logic_vector (22 downto 0);
signal expY_uid7_fpHypotTest_in : std_logic_vector (30 downto 0);
signal expY_uid7_fpHypotTest_b : std_logic_vector (7 downto 0);
signal fracY_uid9_fpHypotTest_in : std_logic_vector (22 downto 0);
signal fracY_uid9_fpHypotTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid14_fpHypotTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid14_fpHypotTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid14_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid16_fpHypotTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid16_fpHypotTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid16_fpHypotTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid18_fpHypotTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid18_fpHypotTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid18_fpHypotTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid19_fpHypotTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid19_fpHypotTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid19_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid30_fpHypotTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid30_fpHypotTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid30_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid32_fpHypotTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid32_fpHypotTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid32_fpHypotTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid34_fpHypotTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid34_fpHypotTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid34_fpHypotTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid35_fpHypotTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid35_fpHypotTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid35_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expCmpGtePQ_uid61_fpHypotTest_a : std_logic_vector(0 downto 0);
signal expCmpGtePQ_uid61_fpHypotTest_b : std_logic_vector(0 downto 0);
signal expCmpGtePQ_uid61_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expDiffPQ_uid62_fpHypotTest_a : std_logic_vector(10 downto 0);
signal expDiffPQ_uid62_fpHypotTest_b : std_logic_vector(10 downto 0);
signal expDiffPQ_uid62_fpHypotTest_o : std_logic_vector (10 downto 0);
signal expDiffPQ_uid62_fpHypotTest_q : std_logic_vector (10 downto 0);
signal expDiffQP_uid63_fpHypotTest_a : std_logic_vector(10 downto 0);
signal expDiffQP_uid63_fpHypotTest_b : std_logic_vector(10 downto 0);
signal expDiffQP_uid63_fpHypotTest_o : std_logic_vector (10 downto 0);
signal expDiffQP_uid63_fpHypotTest_q : std_logic_vector (10 downto 0);
signal mux_uid64_fpHypotTest_s : std_logic_vector (0 downto 0);
signal mux_uid64_fpHypotTest_q : std_logic_vector (10 downto 0);
signal oFracB_uid69_fpHypotTest_s : std_logic_vector (0 downto 0);
signal oFracB_uid69_fpHypotTest_q : std_logic_vector (23 downto 0);
signal expA_uid70_fpHypotTest_s : std_logic_vector (0 downto 0);
signal expA_uid70_fpHypotTest_q : std_logic_vector (9 downto 0);
signal shiftValue_uid73_fpHypotTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid73_fpHypotTest_q : std_logic_vector (4 downto 0);
signal oFracBFlushToZero_uid76_fpHypotTest_a : std_logic_vector(0 downto 0);
signal oFracBFlushToZero_uid76_fpHypotTest_b : std_logic_vector(0 downto 0);
signal oFracBFlushToZero_uid76_fpHypotTest_q : std_logic_vector(0 downto 0);
signal oFracBPostExc_uid78_fpHypotTest_s : std_logic_vector (0 downto 0);
signal oFracBPostExc_uid78_fpHypotTest_q : std_logic_vector (23 downto 0);
signal sumAHighB_uid84_fpHypotTest_a : std_logic_vector(24 downto 0);
signal sumAHighB_uid84_fpHypotTest_b : std_logic_vector(24 downto 0);
signal sumAHighB_uid84_fpHypotTest_o : std_logic_vector (24 downto 0);
signal sumAHighB_uid84_fpHypotTest_q : std_logic_vector (24 downto 0);
signal expFracPostNorm_uid94_fpHypotTest_a : std_logic_vector(35 downto 0);
signal expFracPostNorm_uid94_fpHypotTest_b : std_logic_vector(35 downto 0);
signal expFracPostNorm_uid94_fpHypotTest_o : std_logic_vector (35 downto 0);
signal expFracPostNorm_uid94_fpHypotTest_q : std_logic_vector (34 downto 0);
signal expSumOfSquaresUnbiased_uid97_fpHypotTest_a : std_logic_vector(11 downto 0);
signal expSumOfSquaresUnbiased_uid97_fpHypotTest_b : std_logic_vector(11 downto 0);
signal expSumOfSquaresUnbiased_uid97_fpHypotTest_o : std_logic_vector (11 downto 0);
signal expSumOfSquaresUnbiased_uid97_fpHypotTest_q : std_logic_vector (10 downto 0);
signal expOddSig_uid100_fpHypotTest_a : std_logic_vector(11 downto 0);
signal expOddSig_uid100_fpHypotTest_b : std_logic_vector(11 downto 0);
signal expOddSig_uid100_fpHypotTest_o : std_logic_vector (11 downto 0);
signal expOddSig_uid100_fpHypotTest_q : std_logic_vector (10 downto 0);
signal expRPostInc_uid114_fpHypotTest_a : std_logic_vector(11 downto 0);
signal expRPostInc_uid114_fpHypotTest_b : std_logic_vector(11 downto 0);
signal expRPostInc_uid114_fpHypotTest_o : std_logic_vector (11 downto 0);
signal expRPostInc_uid114_fpHypotTest_q : std_logic_vector (10 downto 0);
signal excXYZ_uid118_fpHypotTest_a : std_logic_vector(0 downto 0);
signal excXYZ_uid118_fpHypotTest_b : std_logic_vector(0 downto 0);
signal excXYZ_uid118_fpHypotTest_q : std_logic_vector(0 downto 0);
signal excXYRUdf_uid119_fpHypotTest_a : std_logic_vector(0 downto 0);
signal excXYRUdf_uid119_fpHypotTest_b : std_logic_vector(0 downto 0);
signal excXYRUdf_uid119_fpHypotTest_c : std_logic_vector(0 downto 0);
signal excXYRUdf_uid119_fpHypotTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid120_fpHypotTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid120_fpHypotTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid120_fpHypotTest_q : std_logic_vector(0 downto 0);
signal xRegOrZeroYRegOvf_uid122_fpHypotTest_a : std_logic_vector(0 downto 0);
signal xRegOrZeroYRegOvf_uid122_fpHypotTest_b : std_logic_vector(0 downto 0);
signal xRegOrZeroYRegOvf_uid122_fpHypotTest_c : std_logic_vector(0 downto 0);
signal xRegOrZeroYRegOvf_uid122_fpHypotTest_q : std_logic_vector(0 downto 0);
signal yRegOrZeroXRegOvf_uid124_fpHypotTest_a : std_logic_vector(0 downto 0);
signal yRegOrZeroXRegOvf_uid124_fpHypotTest_b : std_logic_vector(0 downto 0);
signal yRegOrZeroXRegOvf_uid124_fpHypotTest_c : std_logic_vector(0 downto 0);
signal yRegOrZeroXRegOvf_uid124_fpHypotTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid125_fpHypotTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid125_fpHypotTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid125_fpHypotTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid125_fpHypotTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid125_fpHypotTest_q : std_logic_vector(0 downto 0);
signal outMuxSelEnc_uid132_fpHypotTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid136_fpHypotTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid136_fpHypotTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid141_fpHypotTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid141_fpHypotTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal normBitXSqr_uid48_fpHypotTest_in : std_logic_vector (47 downto 0);
signal normBitXSqr_uid48_fpHypotTest_b : std_logic_vector (0 downto 0);
signal normFracXSqrHigh_uid54_fpHypotTest_in : std_logic_vector (47 downto 0);
signal normFracXSqrHigh_uid54_fpHypotTest_b : std_logic_vector (23 downto 0);
signal normFracXSqrLow_uid55_fpHypotTest_in : std_logic_vector (46 downto 0);
signal normFracXSqrLow_uid55_fpHypotTest_b : std_logic_vector (23 downto 0);
signal normBitYSqr_uid49_fpHypotTest_in : std_logic_vector (47 downto 0);
signal normBitYSqr_uid49_fpHypotTest_b : std_logic_vector (0 downto 0);
signal normFracYSqrHigh_uid57_fpHypotTest_in : std_logic_vector (47 downto 0);
signal normFracYSqrHigh_uid57_fpHypotTest_b : std_logic_vector (23 downto 0);
signal normFracYSqrLow_uid58_fpHypotTest_in : std_logic_vector (46 downto 0);
signal normFracYSqrLow_uid58_fpHypotTest_b : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal soSPreNorm_uid82_uid85_fpHypotTest_q : std_logic_vector (25 downto 0);
signal expXTimes2_uid50_fpHypotTest_q : std_logic_vector (8 downto 0);
signal expYTimes2_uid51_fpHypotTest_q : std_logic_vector (8 downto 0);
signal FracRPreSqrt15dto0_uid108_fpHypotTest_in : std_logic_vector (15 downto 0);
signal FracRPreSqrt15dto0_uid108_fpHypotTest_b : std_logic_vector (15 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_q : std_logic_vector(0 downto 0);
signal excSelBits_uid131_fpHypotTest_q : std_logic_vector (2 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal fracR_uid112_fpHypotTest_in : std_logic_vector (23 downto 0);
signal fracR_uid112_fpHypotTest_b : std_logic_vector (22 downto 0);
signal fracRPostIncMSBU_uid113_fpHypotTest_in : std_logic_vector (25 downto 0);
signal fracRPostIncMSBU_uid113_fpHypotTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid43_uid43_fpHypotTest_q : std_logic_vector (23 downto 0);
signal oFracY_uid44_uid44_fpHypotTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid24_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid24_fpHypotTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid20_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid20_fpHypotTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid23_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid23_fpHypotTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid40_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid40_fpHypotTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid36_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid36_fpHypotTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid39_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid39_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expDiff_uid65_fpHypotTest_in : std_logic_vector (9 downto 0);
signal expDiff_uid65_fpHypotTest_b : std_logic_vector (9 downto 0);
signal rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b : std_logic_vector (0 downto 0);
signal oFracBPostExcG_uid80_fpHypotTest_q : std_logic_vector (24 downto 0);
signal fracRPreSqrt_uid95_fpHypotTest_in : std_logic_vector (23 downto 0);
signal fracRPreSqrt_uid95_fpHypotTest_b : std_logic_vector (22 downto 0);
signal expRPreSqrt_uid96_fpHypotTest_in : std_logic_vector (33 downto 0);
signal expRPreSqrt_uid96_fpHypotTest_b : std_logic_vector (9 downto 0);
signal expREven_uid98_fpHypotTest_in : std_logic_vector (10 downto 0);
signal expREven_uid98_fpHypotTest_b : std_logic_vector (9 downto 0);
signal expROdd_uid101_fpHypotTest_in : std_logic_vector (10 downto 0);
signal expROdd_uid101_fpHypotTest_b : std_logic_vector (9 downto 0);
signal expRPreExc_uid139_fpHypotTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid139_fpHypotTest_b : std_logic_vector (7 downto 0);
signal RHypot_uid142_fpHypotTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b : std_logic_vector (18 downto 0);
signal ofracP_uid56_fpHypotTest_s : std_logic_vector (0 downto 0);
signal ofracP_uid56_fpHypotTest_q : std_logic_vector (23 downto 0);
signal ofracQ_uid59_fpHypotTest_s : std_logic_vector (0 downto 0);
signal ofracQ_uid59_fpHypotTest_q : std_logic_vector (23 downto 0);
signal lowRangeB_uid178_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid178_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid179_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid179_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid184_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid184_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid185_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid185_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest_b : std_logic_vector (23 downto 0);
signal FullSumAB25_uid86_fpHypotTest_in : std_logic_vector (25 downto 0);
signal FullSumAB25_uid86_fpHypotTest_b : std_logic_vector (0 downto 0);
signal soSRangeHigh_uid87_fpHypotTest_in : std_logic_vector (24 downto 0);
signal soSRangeHigh_uid87_fpHypotTest_b : std_logic_vector (23 downto 0);
signal soSRangeLow_uid88_fpHypotTest_in : std_logic_vector (23 downto 0);
signal soSRangeLow_uid88_fpHypotTest_b : std_logic_vector (23 downto 0);
signal expP_uid52_fpHypotTest_a : std_logic_vector(9 downto 0);
signal expP_uid52_fpHypotTest_b : std_logic_vector(9 downto 0);
signal expP_uid52_fpHypotTest_o : std_logic_vector (9 downto 0);
signal expP_uid52_fpHypotTest_q : std_logic_vector (9 downto 0);
signal expQ_uid53_fpHypotTest_a : std_logic_vector(9 downto 0);
signal expQ_uid53_fpHypotTest_b : std_logic_vector(9 downto 0);
signal expQ_uid53_fpHypotTest_o : std_logic_vector (9 downto 0);
signal expQ_uid53_fpHypotTest_q : std_logic_vector (9 downto 0);
signal yT1_uid176_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid176_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal exc_N_uid21_fpHypotTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid21_fpHypotTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid21_fpHypotTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid37_fpHypotTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid37_fpHypotTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid37_fpHypotTest_q : std_logic_vector(0 downto 0);
signal xNaNyNonInf_uid129_fpHypotTest_a : std_logic_vector(0 downto 0);
signal xNaNyNonInf_uid129_fpHypotTest_b : std_logic_vector(0 downto 0);
signal xNaNyNonInf_uid129_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expDiffShiftRange_uid72_fpHypotTest_in : std_logic_vector (4 downto 0);
signal expDiffShiftRange_uid72_fpHypotTest_b : std_logic_vector (4 downto 0);
signal X24dto8_uid145_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid145_alignShift_uid81_fpHypotTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid148_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid148_alignShift_uid81_fpHypotTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid151_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid151_alignShift_uid81_fpHypotTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid106_fpHypotTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid106_fpHypotTest_b : std_logic_vector (6 downto 0);
signal ExpRPreSqrt0_uid102_fpHypotTest_in : std_logic_vector (0 downto 0);
signal ExpRPreSqrt0_uid102_fpHypotTest_b : std_logic_vector (0 downto 0);
signal sumAHighB_uid180_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid180_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid180_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid180_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid186_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid186_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid186_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid186_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal rightShiftStage2Idx1_uid169_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal resFracNorm_uid89_fpHypotTest_s : std_logic_vector (0 downto 0);
signal resFracNorm_uid89_fpHypotTest_q : std_logic_vector (23 downto 0);
signal normCatFracSoS_uid93_uid93_fpHypotTest_q : std_logic_vector (24 downto 0);
signal InvExc_N_uid22_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid22_fpHypotTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid38_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid38_fpHypotTest_q : std_logic_vector(0 downto 0);
signal yNaNxNonInf_uid127_fpHypotTest_a : std_logic_vector(0 downto 0);
signal yNaNxNonInf_uid127_fpHypotTest_b : std_logic_vector(0 downto 0);
signal yNaNxNonInf_uid127_fpHypotTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid130_fpHypotTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid130_fpHypotTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid130_fpHypotTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal expOddSelect_uid103_fpHypotTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid103_fpHypotTest_q : std_logic_vector(0 downto 0);
signal s1_uid178_uid181_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid184_uid187_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal exc_R_uid25_fpHypotTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid25_fpHypotTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid25_fpHypotTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid25_fpHypotTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid41_fpHypotTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid41_fpHypotTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid41_fpHypotTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid41_fpHypotTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid107_fpHypotTest_q : std_logic_vector (7 downto 0);
signal fracRPreInc_uid110_fpHypotTest_in : std_logic_vector (29 downto 0);
signal fracRPreInc_uid110_fpHypotTest_b : std_logic_vector (24 downto 0);
signal lowRangeB_uid82_fpHypotTest_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid82_fpHypotTest_b : std_logic_vector (0 downto 0);
signal highBBits_uid83_fpHypotTest_in : std_logic_vector (24 downto 0);
signal highBBits_uid83_fpHypotTest_b : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid10_fpHypotTest(CONSTANT,9)
cstAllOWE_uid10_fpHypotTest_q <= "11111111";
--VCC(CONSTANT,1)
VCC_q <= "1";
--RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest(BITSELECT,166)@8
RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest_in <= rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q;
RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest_b <= RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest_in(24 downto 1);
--rightShiftStage2Idx1_uid169_alignShift_uid81_fpHypotTest(BITJOIN,168)@8
rightShiftStage2Idx1_uid169_alignShift_uid81_fpHypotTest_q <= GND_q & RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest_b;
--rightShiftStage1Idx3Pad6_uid163_alignShift_uid81_fpHypotTest(CONSTANT,162)
rightShiftStage1Idx3Pad6_uid163_alignShift_uid81_fpHypotTest_q <= "000000";
--zerosWFp1_uid77_fpHypotTest(CONSTANT,76)
zerosWFp1_uid77_fpHypotTest_q <= "000000000000000000000000";
--fracY_uid9_fpHypotTest(BITSELECT,8)@0
fracY_uid9_fpHypotTest_in <= b(22 downto 0);
fracY_uid9_fpHypotTest_b <= fracY_uid9_fpHypotTest_in(22 downto 0);
--oFracY_uid44_uid44_fpHypotTest(BITJOIN,43)@0
oFracY_uid44_uid44_fpHypotTest_q <= VCC_q & fracY_uid9_fpHypotTest_b;
--reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0(REG,199)@0
reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0_q <= oFracY_uid44_uid44_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--oFracYSqr_uid46_fpHypotTest(MULT,45)@1
oFracYSqr_uid46_fpHypotTest_pr <= UNSIGNED(oFracYSqr_uid46_fpHypotTest_a) * UNSIGNED(oFracYSqr_uid46_fpHypotTest_b);
oFracYSqr_uid46_fpHypotTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oFracYSqr_uid46_fpHypotTest_a <= (others => '0');
oFracYSqr_uid46_fpHypotTest_b <= (others => '0');
oFracYSqr_uid46_fpHypotTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
oFracYSqr_uid46_fpHypotTest_a <= reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0_q;
oFracYSqr_uid46_fpHypotTest_b <= reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0_q;
oFracYSqr_uid46_fpHypotTest_s1 <= STD_LOGIC_VECTOR(oFracYSqr_uid46_fpHypotTest_pr);
END IF;
END IF;
END PROCESS;
oFracYSqr_uid46_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oFracYSqr_uid46_fpHypotTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
oFracYSqr_uid46_fpHypotTest_q <= oFracYSqr_uid46_fpHypotTest_s1;
END IF;
END IF;
END PROCESS;
--normFracYSqrHigh_uid57_fpHypotTest(BITSELECT,56)@4
normFracYSqrHigh_uid57_fpHypotTest_in <= oFracYSqr_uid46_fpHypotTest_q;
normFracYSqrHigh_uid57_fpHypotTest_b <= normFracYSqrHigh_uid57_fpHypotTest_in(47 downto 24);
--normFracYSqrLow_uid58_fpHypotTest(BITSELECT,57)@4
normFracYSqrLow_uid58_fpHypotTest_in <= oFracYSqr_uid46_fpHypotTest_q(46 downto 0);
normFracYSqrLow_uid58_fpHypotTest_b <= normFracYSqrLow_uid58_fpHypotTest_in(46 downto 23);
--normBitYSqr_uid49_fpHypotTest(BITSELECT,48)@4
normBitYSqr_uid49_fpHypotTest_in <= oFracYSqr_uid46_fpHypotTest_q;
normBitYSqr_uid49_fpHypotTest_b <= normBitYSqr_uid49_fpHypotTest_in(47 downto 47);
--ofracQ_uid59_fpHypotTest(MUX,58)@4
ofracQ_uid59_fpHypotTest_s <= normBitYSqr_uid49_fpHypotTest_b;
ofracQ_uid59_fpHypotTest: PROCESS (ofracQ_uid59_fpHypotTest_s, en, normFracYSqrLow_uid58_fpHypotTest_b, normFracYSqrHigh_uid57_fpHypotTest_b)
BEGIN
CASE ofracQ_uid59_fpHypotTest_s IS
WHEN "0" => ofracQ_uid59_fpHypotTest_q <= normFracYSqrLow_uid58_fpHypotTest_b;
WHEN "1" => ofracQ_uid59_fpHypotTest_q <= normFracYSqrHigh_uid57_fpHypotTest_b;
WHEN OTHERS => ofracQ_uid59_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c(DELAY,305)@4
ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => ofracQ_uid59_fpHypotTest_q, xout => ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c_q, ena => en(0), clk => clk, aclr => areset );
--fracX_uid8_fpHypotTest(BITSELECT,7)@0
fracX_uid8_fpHypotTest_in <= a(22 downto 0);
fracX_uid8_fpHypotTest_b <= fracX_uid8_fpHypotTest_in(22 downto 0);
--oFracX_uid43_uid43_fpHypotTest(BITJOIN,42)@0
oFracX_uid43_uid43_fpHypotTest_q <= VCC_q & fracX_uid8_fpHypotTest_b;
--reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0(REG,197)@0
reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0_q <= oFracX_uid43_uid43_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--oFracXSqr_uid45_fpHypotTest(MULT,44)@1
oFracXSqr_uid45_fpHypotTest_pr <= UNSIGNED(oFracXSqr_uid45_fpHypotTest_a) * UNSIGNED(oFracXSqr_uid45_fpHypotTest_b);
oFracXSqr_uid45_fpHypotTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oFracXSqr_uid45_fpHypotTest_a <= (others => '0');
oFracXSqr_uid45_fpHypotTest_b <= (others => '0');
oFracXSqr_uid45_fpHypotTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
oFracXSqr_uid45_fpHypotTest_a <= reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0_q;
oFracXSqr_uid45_fpHypotTest_b <= reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0_q;
oFracXSqr_uid45_fpHypotTest_s1 <= STD_LOGIC_VECTOR(oFracXSqr_uid45_fpHypotTest_pr);
END IF;
END IF;
END PROCESS;
oFracXSqr_uid45_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oFracXSqr_uid45_fpHypotTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
oFracXSqr_uid45_fpHypotTest_q <= oFracXSqr_uid45_fpHypotTest_s1;
END IF;
END IF;
END PROCESS;
--normFracXSqrHigh_uid54_fpHypotTest(BITSELECT,53)@4
normFracXSqrHigh_uid54_fpHypotTest_in <= oFracXSqr_uid45_fpHypotTest_q;
normFracXSqrHigh_uid54_fpHypotTest_b <= normFracXSqrHigh_uid54_fpHypotTest_in(47 downto 24);
--normFracXSqrLow_uid55_fpHypotTest(BITSELECT,54)@4
normFracXSqrLow_uid55_fpHypotTest_in <= oFracXSqr_uid45_fpHypotTest_q(46 downto 0);
normFracXSqrLow_uid55_fpHypotTest_b <= normFracXSqrLow_uid55_fpHypotTest_in(46 downto 23);
--normBitXSqr_uid48_fpHypotTest(BITSELECT,47)@4
normBitXSqr_uid48_fpHypotTest_in <= oFracXSqr_uid45_fpHypotTest_q;
normBitXSqr_uid48_fpHypotTest_b <= normBitXSqr_uid48_fpHypotTest_in(47 downto 47);
--ofracP_uid56_fpHypotTest(MUX,55)@4
ofracP_uid56_fpHypotTest_s <= normBitXSqr_uid48_fpHypotTest_b;
ofracP_uid56_fpHypotTest: PROCESS (ofracP_uid56_fpHypotTest_s, en, normFracXSqrLow_uid55_fpHypotTest_b, normFracXSqrHigh_uid54_fpHypotTest_b)
BEGIN
CASE ofracP_uid56_fpHypotTest_s IS
WHEN "0" => ofracP_uid56_fpHypotTest_q <= normFracXSqrLow_uid55_fpHypotTest_b;
WHEN "1" => ofracP_uid56_fpHypotTest_q <= normFracXSqrHigh_uid54_fpHypotTest_b;
WHEN OTHERS => ofracP_uid56_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d(DELAY,306)@4
ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => ofracP_uid56_fpHypotTest_q, xout => ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d_q, ena => en(0), clk => clk, aclr => areset );
--expY_uid7_fpHypotTest(BITSELECT,6)@0
expY_uid7_fpHypotTest_in <= b(30 downto 0);
expY_uid7_fpHypotTest_b <= expY_uid7_fpHypotTest_in(30 downto 23);
--expXIsZero_uid30_fpHypotTest(LOGICAL,29)@0
expXIsZero_uid30_fpHypotTest_a <= expY_uid7_fpHypotTest_b;
expXIsZero_uid30_fpHypotTest_b <= cstAllZWE_uid12_fpHypotTest_q;
expXIsZero_uid30_fpHypotTest_q <= "1" when expXIsZero_uid30_fpHypotTest_a = expXIsZero_uid30_fpHypotTest_b else "0";
--ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b(DELAY,294)@0
ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => expXIsZero_uid30_fpHypotTest_q, xout => ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--bias_uid47_fpHypotTest(CONSTANT,46)
bias_uid47_fpHypotTest_q <= "1111111";
--ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_inputreg(DELAY,497)
ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid7_fpHypotTest_b, xout => ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b(DELAY,278)@0
ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_inputreg_q, xout => ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expYTimes2_uid51_fpHypotTest(BITJOIN,50)@4
expYTimes2_uid51_fpHypotTest_q <= ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_q & normBitYSqr_uid49_fpHypotTest_b;
--expQ_uid53_fpHypotTest(SUB,52)@4
expQ_uid53_fpHypotTest_a <= STD_LOGIC_VECTOR("0" & expYTimes2_uid51_fpHypotTest_q);
expQ_uid53_fpHypotTest_b <= STD_LOGIC_VECTOR("000" & bias_uid47_fpHypotTest_q);
expQ_uid53_fpHypotTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expQ_uid53_fpHypotTest_a) - UNSIGNED(expQ_uid53_fpHypotTest_b));
expQ_uid53_fpHypotTest_q <= expQ_uid53_fpHypotTest_o(9 downto 0);
--ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b(DELAY,292)@4
ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 10, depth => 1 )
PORT MAP ( xin => expQ_uid53_fpHypotTest_q, xout => ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expX_uid6_fpHypotTest(BITSELECT,5)@0
expX_uid6_fpHypotTest_in <= a(30 downto 0);
expX_uid6_fpHypotTest_b <= expX_uid6_fpHypotTest_in(30 downto 23);
--ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_inputreg(DELAY,496)
ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpHypotTest_b, xout => ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b(DELAY,276)@0
ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_inputreg_q, xout => ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXTimes2_uid50_fpHypotTest(BITJOIN,49)@4
expXTimes2_uid50_fpHypotTest_q <= ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_q & normBitXSqr_uid48_fpHypotTest_b;
--expP_uid52_fpHypotTest(SUB,51)@4
expP_uid52_fpHypotTest_a <= STD_LOGIC_VECTOR("0" & expXTimes2_uid50_fpHypotTest_q);
expP_uid52_fpHypotTest_b <= STD_LOGIC_VECTOR("000" & bias_uid47_fpHypotTest_q);
expP_uid52_fpHypotTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expP_uid52_fpHypotTest_a) - UNSIGNED(expP_uid52_fpHypotTest_b));
expP_uid52_fpHypotTest_q <= expP_uid52_fpHypotTest_o(9 downto 0);
--reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0(REG,201)@4
reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q <= expP_uid52_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--pGTEq_uid60_fpHypotTest(COMPARE,59)@5
pGTEq_uid60_fpHypotTest_cin <= GND_q;
pGTEq_uid60_fpHypotTest_a <= STD_LOGIC_VECTOR((11 downto 10 => reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q(9)) & reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q) & '0';
pGTEq_uid60_fpHypotTest_b <= STD_LOGIC_VECTOR((11 downto 10 => ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q(9)) & ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q) & pGTEq_uid60_fpHypotTest_cin(0);
pGTEq_uid60_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(pGTEq_uid60_fpHypotTest_a) - SIGNED(pGTEq_uid60_fpHypotTest_b));
pGTEq_uid60_fpHypotTest_n(0) <= not pGTEq_uid60_fpHypotTest_o(12);
--expCmpGtePQ_uid61_fpHypotTest(LOGICAL,60)@5
expCmpGtePQ_uid61_fpHypotTest_a <= pGTEq_uid60_fpHypotTest_n;
expCmpGtePQ_uid61_fpHypotTest_b <= ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b_q;
expCmpGtePQ_uid61_fpHypotTest_q <= expCmpGtePQ_uid61_fpHypotTest_a or expCmpGtePQ_uid61_fpHypotTest_b;
--oFracB_uid69_fpHypotTest(MUX,68)@5
oFracB_uid69_fpHypotTest_s <= expCmpGtePQ_uid61_fpHypotTest_q;
oFracB_uid69_fpHypotTest: PROCESS (oFracB_uid69_fpHypotTest_s, en, ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d_q, ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c_q)
BEGIN
CASE oFracB_uid69_fpHypotTest_s IS
WHEN "0" => oFracB_uid69_fpHypotTest_q <= ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d_q;
WHEN "1" => oFracB_uid69_fpHypotTest_q <= ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c_q;
WHEN OTHERS => oFracB_uid69_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracB_uid69_fpHypotTest_q_to_oFracBPostExc_uid78_fpHypotTest_c(DELAY,325)@5
ld_oFracB_uid69_fpHypotTest_q_to_oFracBPostExc_uid78_fpHypotTest_c : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracB_uid69_fpHypotTest_q, xout => ld_oFracB_uid69_fpHypotTest_q_to_oFracBPostExc_uid78_fpHypotTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cWFP2_uid66_fpHypotTest(CONSTANT,65)
cWFP2_uid66_fpHypotTest_q <= "11001";
--expDiffPQ_uid62_fpHypotTest(SUB,61)@5
expDiffPQ_uid62_fpHypotTest_a <= STD_LOGIC_VECTOR((10 downto 10 => reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q(9)) & reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q);
expDiffPQ_uid62_fpHypotTest_b <= STD_LOGIC_VECTOR((10 downto 10 => ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q(9)) & ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q);
expDiffPQ_uid62_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(expDiffPQ_uid62_fpHypotTest_a) - SIGNED(expDiffPQ_uid62_fpHypotTest_b));
expDiffPQ_uid62_fpHypotTest_q <= expDiffPQ_uid62_fpHypotTest_o(10 downto 0);
--ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b(DELAY,298)@4
ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 10, depth => 1 )
PORT MAP ( xin => expP_uid52_fpHypotTest_q, xout => ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0(REG,202)@4
reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0_q <= expQ_uid53_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--expDiffQP_uid63_fpHypotTest(SUB,62)@5
expDiffQP_uid63_fpHypotTest_a <= STD_LOGIC_VECTOR((10 downto 10 => reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0_q(9)) & reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0_q);
expDiffQP_uid63_fpHypotTest_b <= STD_LOGIC_VECTOR((10 downto 10 => ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b_q(9)) & ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b_q);
expDiffQP_uid63_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(expDiffQP_uid63_fpHypotTest_a) - SIGNED(expDiffQP_uid63_fpHypotTest_b));
expDiffQP_uid63_fpHypotTest_q <= expDiffQP_uid63_fpHypotTest_o(10 downto 0);
--mux_uid64_fpHypotTest(MUX,63)@5
mux_uid64_fpHypotTest_s <= expCmpGtePQ_uid61_fpHypotTest_q;
mux_uid64_fpHypotTest: PROCESS (mux_uid64_fpHypotTest_s, en, expDiffQP_uid63_fpHypotTest_q, expDiffPQ_uid62_fpHypotTest_q)
BEGIN
CASE mux_uid64_fpHypotTest_s IS
WHEN "0" => mux_uid64_fpHypotTest_q <= expDiffQP_uid63_fpHypotTest_q;
WHEN "1" => mux_uid64_fpHypotTest_q <= expDiffPQ_uid62_fpHypotTest_q;
WHEN OTHERS => mux_uid64_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--expDiff_uid65_fpHypotTest(BITSELECT,64)@5
expDiff_uid65_fpHypotTest_in <= mux_uid64_fpHypotTest_q(9 downto 0);
expDiff_uid65_fpHypotTest_b <= expDiff_uid65_fpHypotTest_in(9 downto 0);
--reg_expDiff_uid65_fpHypotTest_0_to_shiftedOut_uid67_fpHypotTest_0(REG,204)@5
reg_expDiff_uid65_fpHypotTest_0_to_shiftedOut_uid67_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expDiff_uid65_fpHypotTest_0_to_shiftedOut_uid67_fpHypotTest_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expDiff_uid65_fpHypotTest_0_to_shiftedOut_uid67_fpHypotTest_0_q <= expDiff_uid65_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--shiftedOut_uid67_fpHypotTest(COMPARE,66)@6
shiftedOut_uid67_fpHypotTest_cin <= GND_q;
shiftedOut_uid67_fpHypotTest_a <= STD_LOGIC_VECTOR("00" & reg_expDiff_uid65_fpHypotTest_0_to_shiftedOut_uid67_fpHypotTest_0_q) & '0';
shiftedOut_uid67_fpHypotTest_b <= STD_LOGIC_VECTOR("0000000" & cWFP2_uid66_fpHypotTest_q) & shiftedOut_uid67_fpHypotTest_cin(0);
shiftedOut_uid67_fpHypotTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftedOut_uid67_fpHypotTest_a) - UNSIGNED(shiftedOut_uid67_fpHypotTest_b));
shiftedOut_uid67_fpHypotTest_n(0) <= not shiftedOut_uid67_fpHypotTest_o(12);
--expXIsZero_uid14_fpHypotTest(LOGICAL,13)@0
expXIsZero_uid14_fpHypotTest_a <= expX_uid6_fpHypotTest_b;
expXIsZero_uid14_fpHypotTest_b <= cstAllZWE_uid12_fpHypotTest_q;
expXIsZero_uid14_fpHypotTest_q <= "1" when expXIsZero_uid14_fpHypotTest_a = expXIsZero_uid14_fpHypotTest_b else "0";
--ld_expXIsZero_uid14_fpHypotTest_q_to_excAZero_uid74_fpHypotTest_d(DELAY,318)@0
ld_expXIsZero_uid14_fpHypotTest_q_to_excAZero_uid74_fpHypotTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => expXIsZero_uid14_fpHypotTest_q, xout => ld_expXIsZero_uid14_fpHypotTest_q_to_excAZero_uid74_fpHypotTest_d_q, ena => en(0), clk => clk, aclr => areset );
--excBZero_uid75_fpHypotTest(MUX,74)@5
excBZero_uid75_fpHypotTest_s <= expCmpGtePQ_uid61_fpHypotTest_q;
excBZero_uid75_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excBZero_uid75_fpHypotTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE excBZero_uid75_fpHypotTest_s IS
WHEN "0" => excBZero_uid75_fpHypotTest_q <= ld_expXIsZero_uid14_fpHypotTest_q_to_excAZero_uid74_fpHypotTest_d_q;
WHEN "1" => excBZero_uid75_fpHypotTest_q <= ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b_q;
WHEN OTHERS => excBZero_uid75_fpHypotTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--oFracBFlushToZero_uid76_fpHypotTest(LOGICAL,75)@6
oFracBFlushToZero_uid76_fpHypotTest_a <= excBZero_uid75_fpHypotTest_q;
oFracBFlushToZero_uid76_fpHypotTest_b <= shiftedOut_uid67_fpHypotTest_n;
oFracBFlushToZero_uid76_fpHypotTest_q <= oFracBFlushToZero_uid76_fpHypotTest_a or oFracBFlushToZero_uid76_fpHypotTest_b;
--oFracBPostExc_uid78_fpHypotTest(MUX,77)@6
oFracBPostExc_uid78_fpHypotTest_s <= oFracBFlushToZero_uid76_fpHypotTest_q;
oFracBPostExc_uid78_fpHypotTest: PROCESS (oFracBPostExc_uid78_fpHypotTest_s, en, ld_oFracB_uid69_fpHypotTest_q_to_oFracBPostExc_uid78_fpHypotTest_c_q, zerosWFp1_uid77_fpHypotTest_q)
BEGIN
CASE oFracBPostExc_uid78_fpHypotTest_s IS
WHEN "0" => oFracBPostExc_uid78_fpHypotTest_q <= ld_oFracB_uid69_fpHypotTest_q_to_oFracBPostExc_uid78_fpHypotTest_c_q;
WHEN "1" => oFracBPostExc_uid78_fpHypotTest_q <= zerosWFp1_uid77_fpHypotTest_q;
WHEN OTHERS => oFracBPostExc_uid78_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--oFracBPostExcG_uid80_fpHypotTest(BITJOIN,79)@6
oFracBPostExcG_uid80_fpHypotTest_q <= oFracBPostExc_uid78_fpHypotTest_q & GND_q;
--X24dto24_uid151_alignShift_uid81_fpHypotTest(BITSELECT,150)@6
X24dto24_uid151_alignShift_uid81_fpHypotTest_in <= oFracBPostExcG_uid80_fpHypotTest_q;
X24dto24_uid151_alignShift_uid81_fpHypotTest_b <= X24dto24_uid151_alignShift_uid81_fpHypotTest_in(24 downto 24);
--rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest(BITJOIN,152)@6
rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_q <= zerosWFp1_uid77_fpHypotTest_q & X24dto24_uid151_alignShift_uid81_fpHypotTest_b;
--reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5(REG,210)@6
reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5_q <= rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage0Idx2Pad16_uid149_alignShift_uid81_fpHypotTest(CONSTANT,148)
rightShiftStage0Idx2Pad16_uid149_alignShift_uid81_fpHypotTest_q <= "0000000000000000";
--X24dto16_uid148_alignShift_uid81_fpHypotTest(BITSELECT,147)@6
X24dto16_uid148_alignShift_uid81_fpHypotTest_in <= oFracBPostExcG_uid80_fpHypotTest_q;
X24dto16_uid148_alignShift_uid81_fpHypotTest_b <= X24dto16_uid148_alignShift_uid81_fpHypotTest_in(24 downto 16);
--rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest(BITJOIN,149)@6
rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_q <= rightShiftStage0Idx2Pad16_uid149_alignShift_uid81_fpHypotTest_q & X24dto16_uid148_alignShift_uid81_fpHypotTest_b;
--reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4(REG,209)@6
reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4_q <= rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--X24dto8_uid145_alignShift_uid81_fpHypotTest(BITSELECT,144)@6
X24dto8_uid145_alignShift_uid81_fpHypotTest_in <= oFracBPostExcG_uid80_fpHypotTest_q;
X24dto8_uid145_alignShift_uid81_fpHypotTest_b <= X24dto8_uid145_alignShift_uid81_fpHypotTest_in(24 downto 8);
--rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest(BITJOIN,146)@6
rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_q <= cstAllZWE_uid12_fpHypotTest_q & X24dto8_uid145_alignShift_uid81_fpHypotTest_b;
--reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3(REG,208)@6
reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3_q <= rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2(REG,207)@6
reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2_q <= oFracBPostExcG_uid80_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--z_uid71_fpHypotTest(CONSTANT,70)
z_uid71_fpHypotTest_q <= "00000";
--expDiffShiftRange_uid72_fpHypotTest(BITSELECT,71)@5
expDiffShiftRange_uid72_fpHypotTest_in <= expDiff_uid65_fpHypotTest_b(4 downto 0);
expDiffShiftRange_uid72_fpHypotTest_b <= expDiffShiftRange_uid72_fpHypotTest_in(4 downto 0);
--reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2(REG,205)@5
reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2_q <= expDiffShiftRange_uid72_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid73_fpHypotTest(MUX,72)@6
shiftValue_uid73_fpHypotTest_s <= shiftedOut_uid67_fpHypotTest_n;
shiftValue_uid73_fpHypotTest: PROCESS (shiftValue_uid73_fpHypotTest_s, en, reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2_q, z_uid71_fpHypotTest_q)
BEGIN
CASE shiftValue_uid73_fpHypotTest_s IS
WHEN "0" => shiftValue_uid73_fpHypotTest_q <= reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2_q;
WHEN "1" => shiftValue_uid73_fpHypotTest_q <= z_uid71_fpHypotTest_q;
WHEN OTHERS => shiftValue_uid73_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest(BITSELECT,153)@6
rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_in <= shiftValue_uid73_fpHypotTest_q;
rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_b <= rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_1(REG,206)@6
reg_rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_1_q <= rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid155_alignShift_uid81_fpHypotTest(MUX,154)@7
rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_s <= reg_rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_1_q;
rightShiftStage0_uid155_alignShift_uid81_fpHypotTest: PROCESS (rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_s, en, reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2_q, reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3_q, reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4_q, reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5_q)
BEGIN
CASE rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_s IS
WHEN "00" => rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q <= reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2_q;
WHEN "01" => rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q <= reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3_q;
WHEN "10" => rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q <= reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4_q;
WHEN "11" => rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q <= reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5_q;
WHEN OTHERS => rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest(BITSELECT,161)@7
RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_in <= rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q;
RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b <= RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_a(DELAY,424)@7
ld_RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b, xout => ld_RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest(BITJOIN,163)@8
rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_q <= rightShiftStage1Idx3Pad6_uid163_alignShift_uid81_fpHypotTest_q & ld_RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_a_q;
--rightShiftStage1Idx2Pad4_uid160_alignShift_uid81_fpHypotTest(CONSTANT,159)
rightShiftStage1Idx2Pad4_uid160_alignShift_uid81_fpHypotTest_q <= "0000";
--RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest(BITSELECT,158)@7
RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_in <= rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q;
RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b <= RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_a(DELAY,422)@7
ld_RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b, xout => ld_RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest(BITJOIN,160)@8
rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_q <= rightShiftStage1Idx2Pad4_uid160_alignShift_uid81_fpHypotTest_q & ld_RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_a_q;
--rightShiftStage1Idx1Pad2_uid157_alignShift_uid81_fpHypotTest(CONSTANT,156)
rightShiftStage1Idx1Pad2_uid157_alignShift_uid81_fpHypotTest_q <= "00";
--RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest(BITSELECT,155)@7
RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_in <= rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q;
RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b <= RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_a(DELAY,420)@7
ld_RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b, xout => ld_RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest(BITJOIN,157)@8
rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_q <= rightShiftStage1Idx1Pad2_uid157_alignShift_uid81_fpHypotTest_q & ld_RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_a_q;
--reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2(REG,212)@7
reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2_q <= rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest(BITSELECT,164)@6
rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_in <= shiftValue_uid73_fpHypotTest_q(2 downto 0);
rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_b <= rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1(REG,211)@6
reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q <= rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_b(DELAY,426)@7
ld_reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid166_alignShift_uid81_fpHypotTest(MUX,165)@8
rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_s <= ld_reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_b_q;
rightShiftStage1_uid166_alignShift_uid81_fpHypotTest: PROCESS (rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_s, en, reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2_q, rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_q, rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_q, rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_q)
BEGIN
CASE rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_s IS
WHEN "00" => rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q <= reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2_q;
WHEN "01" => rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q <= rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_q;
WHEN "10" => rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q <= rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_q;
WHEN "11" => rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q <= rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_q;
WHEN OTHERS => rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest(BITSELECT,169)@6
rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_in <= shiftValue_uid73_fpHypotTest_q(0 downto 0);
rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b <= rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_in(0 downto 0);
--ld_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b_to_reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_a(DELAY,475)@6
ld_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b_to_reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b, xout => ld_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b_to_reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1(REG,213)@7
reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_q <= ld_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b_to_reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid171_alignShift_uid81_fpHypotTest(MUX,170)@8
rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_s <= reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_q;
rightShiftStage2_uid171_alignShift_uid81_fpHypotTest: PROCESS (rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_s, en, rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q, rightShiftStage2Idx1_uid169_alignShift_uid81_fpHypotTest_q)
BEGIN
CASE rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_s IS
WHEN "0" => rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_q <= rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q;
WHEN "1" => rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_q <= rightShiftStage2Idx1_uid169_alignShift_uid81_fpHypotTest_q;
WHEN OTHERS => rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--highBBits_uid83_fpHypotTest(BITSELECT,82)@8
highBBits_uid83_fpHypotTest_in <= rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_q;
highBBits_uid83_fpHypotTest_b <= highBBits_uid83_fpHypotTest_in(24 downto 1);
--reg_highBBits_uid83_fpHypotTest_0_to_sumAHighB_uid84_fpHypotTest_1(REG,214)@8
reg_highBBits_uid83_fpHypotTest_0_to_sumAHighB_uid84_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid83_fpHypotTest_0_to_sumAHighB_uid84_fpHypotTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid83_fpHypotTest_0_to_sumAHighB_uid84_fpHypotTest_1_q <= highBBits_uid83_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--oFracA_uid68_fpHypotTest(MUX,67)@5
oFracA_uid68_fpHypotTest_s <= expCmpGtePQ_uid61_fpHypotTest_q;
oFracA_uid68_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oFracA_uid68_fpHypotTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oFracA_uid68_fpHypotTest_s IS
WHEN "0" => oFracA_uid68_fpHypotTest_q <= ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c_q;
WHEN "1" => oFracA_uid68_fpHypotTest_q <= ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d_q;
WHEN OTHERS => oFracA_uid68_fpHypotTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--excAZero_uid74_fpHypotTest(MUX,73)@5
excAZero_uid74_fpHypotTest_s <= expCmpGtePQ_uid61_fpHypotTest_q;
excAZero_uid74_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excAZero_uid74_fpHypotTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE excAZero_uid74_fpHypotTest_s IS
WHEN "0" => excAZero_uid74_fpHypotTest_q <= ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b_q;
WHEN "1" => excAZero_uid74_fpHypotTest_q <= ld_expXIsZero_uid14_fpHypotTest_q_to_excAZero_uid74_fpHypotTest_d_q;
WHEN OTHERS => excAZero_uid74_fpHypotTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--oFracAPostExc_uid79_fpHypotTest(MUX,78)@6
oFracAPostExc_uid79_fpHypotTest_s <= excAZero_uid74_fpHypotTest_q;
oFracAPostExc_uid79_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oFracAPostExc_uid79_fpHypotTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oFracAPostExc_uid79_fpHypotTest_s IS
WHEN "0" => oFracAPostExc_uid79_fpHypotTest_q <= oFracA_uid68_fpHypotTest_q;
WHEN "1" => oFracAPostExc_uid79_fpHypotTest_q <= zerosWFp1_uid77_fpHypotTest_q;
WHEN OTHERS => oFracAPostExc_uid79_fpHypotTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracAPostExc_uid79_fpHypotTest_q_to_sumAHighB_uid84_fpHypotTest_a(DELAY,331)@7
ld_oFracAPostExc_uid79_fpHypotTest_q_to_sumAHighB_uid84_fpHypotTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => oFracAPostExc_uid79_fpHypotTest_q, xout => ld_oFracAPostExc_uid79_fpHypotTest_q_to_sumAHighB_uid84_fpHypotTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid84_fpHypotTest(ADD,83)@9
sumAHighB_uid84_fpHypotTest_a <= STD_LOGIC_VECTOR("0" & ld_oFracAPostExc_uid79_fpHypotTest_q_to_sumAHighB_uid84_fpHypotTest_a_q);
sumAHighB_uid84_fpHypotTest_b <= STD_LOGIC_VECTOR("0" & reg_highBBits_uid83_fpHypotTest_0_to_sumAHighB_uid84_fpHypotTest_1_q);
sumAHighB_uid84_fpHypotTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sumAHighB_uid84_fpHypotTest_a) + UNSIGNED(sumAHighB_uid84_fpHypotTest_b));
sumAHighB_uid84_fpHypotTest_q <= sumAHighB_uid84_fpHypotTest_o(24 downto 0);
--lowRangeB_uid82_fpHypotTest(BITSELECT,81)@8
lowRangeB_uid82_fpHypotTest_in <= rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_q(0 downto 0);
lowRangeB_uid82_fpHypotTest_b <= lowRangeB_uid82_fpHypotTest_in(0 downto 0);
--reg_lowRangeB_uid82_fpHypotTest_0_to_soSPreNorm_uid82_uid85_fpHypotTest_0(REG,215)@8
reg_lowRangeB_uid82_fpHypotTest_0_to_soSPreNorm_uid82_uid85_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid82_fpHypotTest_0_to_soSPreNorm_uid82_uid85_fpHypotTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid82_fpHypotTest_0_to_soSPreNorm_uid82_uid85_fpHypotTest_0_q <= lowRangeB_uid82_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--soSPreNorm_uid82_uid85_fpHypotTest(BITJOIN,84)@9
soSPreNorm_uid82_uid85_fpHypotTest_q <= sumAHighB_uid84_fpHypotTest_q & reg_lowRangeB_uid82_fpHypotTest_0_to_soSPreNorm_uid82_uid85_fpHypotTest_0_q;
--FullSumAB25_uid86_fpHypotTest(BITSELECT,85)@9
FullSumAB25_uid86_fpHypotTest_in <= soSPreNorm_uid82_uid85_fpHypotTest_q;
FullSumAB25_uid86_fpHypotTest_b <= FullSumAB25_uid86_fpHypotTest_in(25 downto 25);
--soSRangeHigh_uid87_fpHypotTest(BITSELECT,86)@9
soSRangeHigh_uid87_fpHypotTest_in <= soSPreNorm_uid82_uid85_fpHypotTest_q(24 downto 0);
soSRangeHigh_uid87_fpHypotTest_b <= soSRangeHigh_uid87_fpHypotTest_in(24 downto 1);
--soSRangeLow_uid88_fpHypotTest(BITSELECT,87)@9
soSRangeLow_uid88_fpHypotTest_in <= soSPreNorm_uid82_uid85_fpHypotTest_q(23 downto 0);
soSRangeLow_uid88_fpHypotTest_b <= soSRangeLow_uid88_fpHypotTest_in(23 downto 0);
--resFracNorm_uid89_fpHypotTest(MUX,88)@9
resFracNorm_uid89_fpHypotTest_s <= FullSumAB25_uid86_fpHypotTest_b;
resFracNorm_uid89_fpHypotTest: PROCESS (resFracNorm_uid89_fpHypotTest_s, en, soSRangeLow_uid88_fpHypotTest_b, soSRangeHigh_uid87_fpHypotTest_b)
BEGIN
CASE resFracNorm_uid89_fpHypotTest_s IS
WHEN "0" => resFracNorm_uid89_fpHypotTest_q <= soSRangeLow_uid88_fpHypotTest_b;
WHEN "1" => resFracNorm_uid89_fpHypotTest_q <= soSRangeHigh_uid87_fpHypotTest_b;
WHEN OTHERS => resFracNorm_uid89_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--normCatFracSoS_uid93_uid93_fpHypotTest(BITJOIN,92)@9
normCatFracSoS_uid93_uid93_fpHypotTest_q <= FullSumAB25_uid86_fpHypotTest_b & resFracNorm_uid89_fpHypotTest_q;
--reg_normCatFracSoS_uid93_uid93_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_1(REG,217)@9
reg_normCatFracSoS_uid93_uid93_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_normCatFracSoS_uid93_uid93_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_normCatFracSoS_uid93_uid93_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_1_q <= normCatFracSoS_uid93_uid93_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable(LOGICAL,505)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_a <= en;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q <= not ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_a;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor(LOGICAL,506)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_b <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena_q;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_q <= not (ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_a or ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_b);
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg(REG,504)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena(REG,507)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_q = "1") THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd(LOGICAL,508)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena_q;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_b <= en;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_a and ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_b;
--expA_uid70_fpHypotTest(MUX,69)@5
expA_uid70_fpHypotTest_s <= expCmpGtePQ_uid61_fpHypotTest_q;
expA_uid70_fpHypotTest: PROCESS (expA_uid70_fpHypotTest_s, en, ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q, ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b_q)
BEGIN
CASE expA_uid70_fpHypotTest_s IS
WHEN "0" => expA_uid70_fpHypotTest_q <= ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q;
WHEN "1" => expA_uid70_fpHypotTest_q <= ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b_q;
WHEN OTHERS => expA_uid70_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_inputreg(DELAY,498)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 10, depth => 1 )
PORT MAP ( xin => expA_uid70_fpHypotTest_q, xout => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt(COUNTER,500)
-- every=1, low=0, high=1, step=1, init=1
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_i <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_i,1));
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg(REG,501)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux(MUX,502)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_s <= en;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux: PROCESS (ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_s, ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q, ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_q)
BEGIN
CASE ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_s IS
WHEN "0" => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q;
WHEN "1" => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem(DUALMEM,499)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_ia <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_inputreg_q;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_aa <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_ab <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_q;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 1,
numwords_a => 2,
width_b => 10,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_iq,
address_a => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_aa,
data_a => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_ia
);
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_reset0 <= areset;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_iq(9 downto 0);
--cstAllZWF_uid11_fpHypotTest(CONSTANT,10)
cstAllZWF_uid11_fpHypotTest_q <= "00000000000000000000000";
--expCatRndBit_uid91_uid92_fpHypotTest(BITJOIN,91)@9
expCatRndBit_uid91_uid92_fpHypotTest_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_q & cstAllZWF_uid11_fpHypotTest_q & VCC_q;
--reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0(REG,216)@9
reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0_q <= expCatRndBit_uid91_uid92_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostNorm_uid94_fpHypotTest(ADD,93)@10
expFracPostNorm_uid94_fpHypotTest_a <= STD_LOGIC_VECTOR((35 downto 34 => reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0_q(33)) & reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0_q);
expFracPostNorm_uid94_fpHypotTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_normCatFracSoS_uid93_uid93_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_1_q);
expFracPostNorm_uid94_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracPostNorm_uid94_fpHypotTest_a) + SIGNED(expFracPostNorm_uid94_fpHypotTest_b));
expFracPostNorm_uid94_fpHypotTest_q <= expFracPostNorm_uid94_fpHypotTest_o(34 downto 0);
--expRPreSqrt_uid96_fpHypotTest(BITSELECT,95)@10
expRPreSqrt_uid96_fpHypotTest_in <= expFracPostNorm_uid94_fpHypotTest_q(33 downto 0);
expRPreSqrt_uid96_fpHypotTest_b <= expRPreSqrt_uid96_fpHypotTest_in(33 downto 24);
--ExpRPreSqrt0_uid102_fpHypotTest(BITSELECT,101)@10
ExpRPreSqrt0_uid102_fpHypotTest_in <= expRPreSqrt_uid96_fpHypotTest_b(0 downto 0);
ExpRPreSqrt0_uid102_fpHypotTest_b <= ExpRPreSqrt0_uid102_fpHypotTest_in(0 downto 0);
--expOddSelect_uid103_fpHypotTest(LOGICAL,102)@10
expOddSelect_uid103_fpHypotTest_a <= ExpRPreSqrt0_uid102_fpHypotTest_b;
expOddSelect_uid103_fpHypotTest_q <= not expOddSelect_uid103_fpHypotTest_a;
--fracRPreSqrt_uid95_fpHypotTest(BITSELECT,94)@10
fracRPreSqrt_uid95_fpHypotTest_in <= expFracPostNorm_uid94_fpHypotTest_q(23 downto 0);
fracRPreSqrt_uid95_fpHypotTest_b <= fracRPreSqrt_uid95_fpHypotTest_in(23 downto 1);
--fracXAddr_uid106_fpHypotTest(BITSELECT,105)@10
fracXAddr_uid106_fpHypotTest_in <= fracRPreSqrt_uid95_fpHypotTest_b;
fracXAddr_uid106_fpHypotTest_b <= fracXAddr_uid106_fpHypotTest_in(22 downto 16);
--addrTable_uid107_fpHypotTest(BITJOIN,106)@10
addrTable_uid107_fpHypotTest_q <= expOddSelect_uid103_fpHypotTest_q & fracXAddr_uid106_fpHypotTest_b;
--reg_addrTable_uid107_fpHypotTest_0_to_memoryC2_uid175_sqrtTableGenerator_lutmem_0(REG,220)@10
reg_addrTable_uid107_fpHypotTest_0_to_memoryC2_uid175_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid107_fpHypotTest_0_to_memoryC2_uid175_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid107_fpHypotTest_0_to_memoryC2_uid175_sqrtTableGenerator_lutmem_0_q <= addrTable_uid107_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid175_sqrtTableGenerator_lutmem(DUALMEM,196)@11
memoryC2_uid175_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid175_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid175_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid107_fpHypotTest_0_to_memoryC2_uid175_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid175_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_hypot_s5_memoryC2_uid175_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid175_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid175_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid175_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid175_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid175_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid175_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid175_sqrtTableGenerator_lutmem_q <= memoryC2_uid175_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid175_sqrtTableGenerator_lutmem_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_1(REG,222)@13
reg_memoryC2_uid175_sqrtTableGenerator_lutmem_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid175_sqrtTableGenerator_lutmem_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid175_sqrtTableGenerator_lutmem_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_1_q <= memoryC2_uid175_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_inputreg(DELAY,509)
ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracRPreSqrt_uid95_fpHypotTest_b, xout => ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a(DELAY,360)@10
ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_inputreg_q, xout => ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracRPreSqrt15dto0_uid108_fpHypotTest(BITSELECT,107)@13
FracRPreSqrt15dto0_uid108_fpHypotTest_in <= ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_q(15 downto 0);
FracRPreSqrt15dto0_uid108_fpHypotTest_b <= FracRPreSqrt15dto0_uid108_fpHypotTest_in(15 downto 0);
--yT1_uid176_sqrtPolynomialEvaluator(BITSELECT,175)@13
yT1_uid176_sqrtPolynomialEvaluator_in <= FracRPreSqrt15dto0_uid108_fpHypotTest_b;
yT1_uid176_sqrtPolynomialEvaluator_b <= yT1_uid176_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid176_sqrtPolynomialEvaluator_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_0(REG,221)@13
reg_yT1_uid176_sqrtPolynomialEvaluator_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid176_sqrtPolynomialEvaluator_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid176_sqrtPolynomialEvaluator_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_0_q <= yT1_uid176_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator(MULT,188)@14
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_b);
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_a <= reg_yT1_uid176_sqrtPolynomialEvaluator_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_0_q;
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid175_sqrtTableGenerator_lutmem_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_1_q;
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_q <= prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator(BITSELECT,189)@17
prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_in <= prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid179_sqrtPolynomialEvaluator(BITSELECT,178)@17
highBBits_uid179_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_b;
highBBits_uid179_sqrtPolynomialEvaluator_b <= highBBits_uid179_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_a(DELAY,485)@10
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addrTable_uid107_fpHypotTest_q, xout => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0(REG,223)@13
reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid174_sqrtTableGenerator_lutmem(DUALMEM,195)@14
memoryC1_uid174_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid174_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid174_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid174_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_hypot_s5_memoryC1_uid174_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid174_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid174_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid174_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid174_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid174_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid174_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid174_sqrtTableGenerator_lutmem_q <= memoryC1_uid174_sqrtTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0(REG,224)@16
reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0_q <= memoryC1_uid174_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid180_sqrtPolynomialEvaluator(ADD,179)@17
sumAHighB_uid180_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0_q(20)) & reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid180_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid179_sqrtPolynomialEvaluator_b(11)) & highBBits_uid179_sqrtPolynomialEvaluator_b);
sumAHighB_uid180_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid180_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid180_sqrtPolynomialEvaluator_b));
sumAHighB_uid180_sqrtPolynomialEvaluator_q <= sumAHighB_uid180_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid178_sqrtPolynomialEvaluator(BITSELECT,177)@17
lowRangeB_uid178_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid178_sqrtPolynomialEvaluator_b <= lowRangeB_uid178_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid178_uid181_sqrtPolynomialEvaluator(BITJOIN,180)@17
s1_uid178_uid181_sqrtPolynomialEvaluator_q <= sumAHighB_uid180_sqrtPolynomialEvaluator_q & lowRangeB_uid178_sqrtPolynomialEvaluator_b;
--reg_s1_uid178_uid181_sqrtPolynomialEvaluator_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_1(REG,226)@17
reg_s1_uid178_uid181_sqrtPolynomialEvaluator_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid178_uid181_sqrtPolynomialEvaluator_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid178_uid181_sqrtPolynomialEvaluator_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_1_q <= s1_uid178_uid181_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor(LOGICAL,636)
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_b);
--ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena(REG,637)
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,638)
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0(REG,225)@13
reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q <= FracRPreSqrt15dto0_uid108_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_inputreg(DELAY,628)
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q, xout => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,629)
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_inputreg_q;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_q;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 1,
numwords_a => 2,
width_b => 16,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator(MULT,191)@18
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_b);
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a <= ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_b <= reg_s1_uid178_uid181_sqrtPolynomialEvaluator_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_1_q;
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_q <= prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator(BITSELECT,192)@21
prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_in <= prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid185_sqrtPolynomialEvaluator(BITSELECT,184)@21
highBBits_uid185_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_b;
highBBits_uid185_sqrtPolynomialEvaluator_b <= highBBits_uid185_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,649)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,645)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "0100";
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,646)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_mem_top_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q);
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_b else "0";
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,647)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,650)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,651)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,639)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid107_fpHypotTest_q, xout => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=4, step=1, init=1
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 3 THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 4;
ELSE
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,3));
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,642)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,643)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,640)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0(REG,227)@17
reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid173_sqrtTableGenerator_lutmem(DUALMEM,194)@18
memoryC0_uid173_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid173_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid173_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_q;
memoryC0_uid173_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_hypot_s5_memoryC0_uid173_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid173_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid173_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid173_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid173_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid173_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid173_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid173_sqrtTableGenerator_lutmem_q <= memoryC0_uid173_sqrtTableGenerator_lutmem_iq(28 downto 0);
--reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0(REG,228)@20
reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0_q <= memoryC0_uid173_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid186_sqrtPolynomialEvaluator(ADD,185)@21
sumAHighB_uid186_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0_q(28)) & reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid186_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid185_sqrtPolynomialEvaluator_b(21)) & highBBits_uid185_sqrtPolynomialEvaluator_b);
sumAHighB_uid186_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid186_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid186_sqrtPolynomialEvaluator_b));
sumAHighB_uid186_sqrtPolynomialEvaluator_q <= sumAHighB_uid186_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid184_sqrtPolynomialEvaluator(BITSELECT,183)@21
lowRangeB_uid184_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid184_sqrtPolynomialEvaluator_b <= lowRangeB_uid184_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid184_uid187_sqrtPolynomialEvaluator(BITJOIN,186)@21
s2_uid184_uid187_sqrtPolynomialEvaluator_q <= sumAHighB_uid186_sqrtPolynomialEvaluator_q & lowRangeB_uid184_sqrtPolynomialEvaluator_b;
--fracRPreInc_uid110_fpHypotTest(BITSELECT,109)@21
fracRPreInc_uid110_fpHypotTest_in <= s2_uid184_uid187_sqrtPolynomialEvaluator_q(29 downto 0);
fracRPreInc_uid110_fpHypotTest_b <= fracRPreInc_uid110_fpHypotTest_in(29 downto 5);
--reg_fracRPreInc_uid110_fpHypotTest_0_to_fracRPostInc_uid111_fpHypotTest_0(REG,229)@21
reg_fracRPreInc_uid110_fpHypotTest_0_to_fracRPostInc_uid111_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreInc_uid110_fpHypotTest_0_to_fracRPostInc_uid111_fpHypotTest_0_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreInc_uid110_fpHypotTest_0_to_fracRPostInc_uid111_fpHypotTest_0_q <= fracRPreInc_uid110_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostInc_uid111_fpHypotTest(ADD,110)@22
fracRPostInc_uid111_fpHypotTest_a <= STD_LOGIC_VECTOR("0" & reg_fracRPreInc_uid110_fpHypotTest_0_to_fracRPostInc_uid111_fpHypotTest_0_q);
fracRPostInc_uid111_fpHypotTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000" & VCC_q);
fracRPostInc_uid111_fpHypotTest_o <= STD_LOGIC_VECTOR(UNSIGNED(fracRPostInc_uid111_fpHypotTest_a) + UNSIGNED(fracRPostInc_uid111_fpHypotTest_b));
fracRPostInc_uid111_fpHypotTest_q <= fracRPostInc_uid111_fpHypotTest_o(25 downto 0);
--fracRPostIncMSBU_uid113_fpHypotTest(BITSELECT,112)@22
fracRPostIncMSBU_uid113_fpHypotTest_in <= fracRPostInc_uid111_fpHypotTest_q;
fracRPostIncMSBU_uid113_fpHypotTest_b <= fracRPostIncMSBU_uid113_fpHypotTest_in(25 downto 25);
--reg_fracRPostIncMSBU_uid113_fpHypotTest_0_to_expRPostInc_uid114_fpHypotTest_1(REG,230)@22
reg_fracRPostIncMSBU_uid113_fpHypotTest_0_to_expRPostInc_uid114_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPostIncMSBU_uid113_fpHypotTest_0_to_expRPostInc_uid114_fpHypotTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPostIncMSBU_uid113_fpHypotTest_0_to_expRPostInc_uid114_fpHypotTest_1_q <= fracRPostIncMSBU_uid113_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor(LOGICAL,520)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_b <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_q <= not (ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_a or ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_b);
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_mem_top(CONSTANT,516)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_mem_top_q <= "01000";
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp(LOGICAL,517)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_a <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_mem_top_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_q);
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_q <= "1" when ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_a = ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_b else "0";
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmpReg(REG,518)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmpReg_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena(REG,521)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_q = "1") THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd(LOGICAL,522)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_a <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_b <= en;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_a and ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_b;
--biasP1Signal_uid99_fpHypotTest(CONSTANT,98)
biasP1Signal_uid99_fpHypotTest_q <= "1111110";
--reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0(REG,218)@10
reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q <= expRPreSqrt_uid96_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid100_fpHypotTest(ADD,99)@11
expOddSig_uid100_fpHypotTest_a <= STD_LOGIC_VECTOR((11 downto 10 => reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q(9)) & reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q);
expOddSig_uid100_fpHypotTest_b <= STD_LOGIC_VECTOR('0' & "0000" & biasP1Signal_uid99_fpHypotTest_q);
expOddSig_uid100_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(expOddSig_uid100_fpHypotTest_a) + SIGNED(expOddSig_uid100_fpHypotTest_b));
expOddSig_uid100_fpHypotTest_q <= expOddSig_uid100_fpHypotTest_o(10 downto 0);
--expROdd_uid101_fpHypotTest(BITSELECT,100)@11
expROdd_uid101_fpHypotTest_in <= expOddSig_uid100_fpHypotTest_q;
expROdd_uid101_fpHypotTest_b <= expROdd_uid101_fpHypotTest_in(10 downto 1);
--expSumOfSquaresUnbiased_uid97_fpHypotTest(ADD,96)@11
expSumOfSquaresUnbiased_uid97_fpHypotTest_a <= STD_LOGIC_VECTOR((11 downto 10 => reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q(9)) & reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q);
expSumOfSquaresUnbiased_uid97_fpHypotTest_b <= STD_LOGIC_VECTOR('0' & "0000" & bias_uid47_fpHypotTest_q);
expSumOfSquaresUnbiased_uid97_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumOfSquaresUnbiased_uid97_fpHypotTest_a) + SIGNED(expSumOfSquaresUnbiased_uid97_fpHypotTest_b));
expSumOfSquaresUnbiased_uid97_fpHypotTest_q <= expSumOfSquaresUnbiased_uid97_fpHypotTest_o(10 downto 0);
--expREven_uid98_fpHypotTest(BITSELECT,97)@11
expREven_uid98_fpHypotTest_in <= expSumOfSquaresUnbiased_uid97_fpHypotTest_q;
expREven_uid98_fpHypotTest_b <= expREven_uid98_fpHypotTest_in(10 downto 1);
--ld_expOddSelect_uid103_fpHypotTest_q_to_expRMux_uid104_fpHypotTest_b(DELAY,354)@10
ld_expOddSelect_uid103_fpHypotTest_q_to_expRMux_uid104_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid103_fpHypotTest_q, xout => ld_expOddSelect_uid103_fpHypotTest_q_to_expRMux_uid104_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid104_fpHypotTest(MUX,103)@11
expRMux_uid104_fpHypotTest_s <= ld_expOddSelect_uid103_fpHypotTest_q_to_expRMux_uid104_fpHypotTest_b_q;
expRMux_uid104_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid104_fpHypotTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid104_fpHypotTest_s IS
WHEN "0" => expRMux_uid104_fpHypotTest_q <= expREven_uid98_fpHypotTest_b;
WHEN "1" => expRMux_uid104_fpHypotTest_q <= expROdd_uid101_fpHypotTest_b;
WHEN OTHERS => expRMux_uid104_fpHypotTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_inputreg(DELAY,510)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 10, depth => 1 )
PORT MAP ( xin => expRMux_uid104_fpHypotTest_q, xout => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt(COUNTER,512)
-- every=1, low=0, high=8, step=1, init=1
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i = 7 THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_eq = '1') THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i - 8;
ELSE
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i,4));
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg(REG,513)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux(MUX,514)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_s <= en;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux: PROCESS (ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_s, ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg_q, ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_s IS
WHEN "0" => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg_q;
WHEN "1" => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem(DUALMEM,511)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_ia <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_inputreg_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_aa <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_ab <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 4,
numwords_a => 9,
width_b => 10,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_iq,
address_a => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_aa,
data_a => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_ia
);
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_reset0 <= areset;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_iq(9 downto 0);
--expRPostInc_uid114_fpHypotTest(ADD,113)@23
expRPostInc_uid114_fpHypotTest_a <= STD_LOGIC_VECTOR((11 downto 10 => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_q(9)) & ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_q);
expRPostInc_uid114_fpHypotTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_fracRPostIncMSBU_uid113_fpHypotTest_0_to_expRPostInc_uid114_fpHypotTest_1_q);
expRPostInc_uid114_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(expRPostInc_uid114_fpHypotTest_a) + SIGNED(expRPostInc_uid114_fpHypotTest_b));
expRPostInc_uid114_fpHypotTest_q <= expRPostInc_uid114_fpHypotTest_o(10 downto 0);
--expRPreExc_uid139_fpHypotTest(BITSELECT,138)@23
expRPreExc_uid139_fpHypotTest_in <= expRPostInc_uid114_fpHypotTest_q(7 downto 0);
expRPreExc_uid139_fpHypotTest_b <= expRPreExc_uid139_fpHypotTest_in(7 downto 0);
--ld_expRPreExc_uid139_fpHypotTest_b_to_expRPostExc_uid141_fpHypotTest_d(DELAY,404)@23
ld_expRPreExc_uid139_fpHypotTest_b_to_expRPostExc_uid141_fpHypotTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid139_fpHypotTest_b, xout => ld_expRPreExc_uid139_fpHypotTest_b_to_expRPostExc_uid141_fpHypotTest_d_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid12_fpHypotTest(CONSTANT,11)
cstAllZWE_uid12_fpHypotTest_q <= "00000000";
--ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor(LOGICAL,624)
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_b <= ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena_q;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_q <= not (ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_a or ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_b);
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_mem_top(CONSTANT,529)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_mem_top_q <= "010101";
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp(LOGICAL,530)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_a <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_mem_top_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q);
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_q <= "1" when ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_a = ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_b else "0";
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg(REG,531)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena(REG,625)
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_q = "1") THEN
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd(LOGICAL,626)
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_a <= ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena_q;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_b <= en;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_q <= ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_a and ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_b;
--fracXIsZero_uid18_fpHypotTest(LOGICAL,17)@0
fracXIsZero_uid18_fpHypotTest_a <= fracX_uid8_fpHypotTest_b;
fracXIsZero_uid18_fpHypotTest_b <= cstAllZWF_uid11_fpHypotTest_q;
fracXIsZero_uid18_fpHypotTest_q <= "1" when fracXIsZero_uid18_fpHypotTest_a = fracXIsZero_uid18_fpHypotTest_b else "0";
--expXIsMax_uid16_fpHypotTest(LOGICAL,15)@0
expXIsMax_uid16_fpHypotTest_a <= expX_uid6_fpHypotTest_b;
expXIsMax_uid16_fpHypotTest_b <= cstAllOWE_uid10_fpHypotTest_q;
expXIsMax_uid16_fpHypotTest_q <= "1" when expXIsMax_uid16_fpHypotTest_a = expXIsMax_uid16_fpHypotTest_b else "0";
--exc_I_uid19_fpHypotTest(LOGICAL,18)@0
exc_I_uid19_fpHypotTest_a <= expXIsMax_uid16_fpHypotTest_q;
exc_I_uid19_fpHypotTest_b <= fracXIsZero_uid18_fpHypotTest_q;
exc_I_uid19_fpHypotTest_q <= exc_I_uid19_fpHypotTest_a and exc_I_uid19_fpHypotTest_b;
--InvExc_I_uid23_fpHypotTest(LOGICAL,22)@0
InvExc_I_uid23_fpHypotTest_a <= exc_I_uid19_fpHypotTest_q;
InvExc_I_uid23_fpHypotTest_q <= not InvExc_I_uid23_fpHypotTest_a;
--fracXIsZero_uid34_fpHypotTest(LOGICAL,33)@0
fracXIsZero_uid34_fpHypotTest_a <= fracY_uid9_fpHypotTest_b;
fracXIsZero_uid34_fpHypotTest_b <= cstAllZWF_uid11_fpHypotTest_q;
fracXIsZero_uid34_fpHypotTest_q <= "1" when fracXIsZero_uid34_fpHypotTest_a = fracXIsZero_uid34_fpHypotTest_b else "0";
--InvFracXIsZero_uid36_fpHypotTest(LOGICAL,35)@0
InvFracXIsZero_uid36_fpHypotTest_a <= fracXIsZero_uid34_fpHypotTest_q;
InvFracXIsZero_uid36_fpHypotTest_q <= not InvFracXIsZero_uid36_fpHypotTest_a;
--expXIsMax_uid32_fpHypotTest(LOGICAL,31)@0
expXIsMax_uid32_fpHypotTest_a <= expY_uid7_fpHypotTest_b;
expXIsMax_uid32_fpHypotTest_b <= cstAllOWE_uid10_fpHypotTest_q;
expXIsMax_uid32_fpHypotTest_q <= "1" when expXIsMax_uid32_fpHypotTest_a = expXIsMax_uid32_fpHypotTest_b else "0";
--exc_N_uid37_fpHypotTest(LOGICAL,36)@0
exc_N_uid37_fpHypotTest_a <= expXIsMax_uid32_fpHypotTest_q;
exc_N_uid37_fpHypotTest_b <= InvFracXIsZero_uid36_fpHypotTest_q;
exc_N_uid37_fpHypotTest_q <= exc_N_uid37_fpHypotTest_a and exc_N_uid37_fpHypotTest_b;
--yNaNxNonInf_uid127_fpHypotTest(LOGICAL,126)@0
yNaNxNonInf_uid127_fpHypotTest_a <= exc_N_uid37_fpHypotTest_q;
yNaNxNonInf_uid127_fpHypotTest_b <= InvExc_I_uid23_fpHypotTest_q;
yNaNxNonInf_uid127_fpHypotTest_q <= yNaNxNonInf_uid127_fpHypotTest_a and yNaNxNonInf_uid127_fpHypotTest_b;
--exc_I_uid35_fpHypotTest(LOGICAL,34)@0
exc_I_uid35_fpHypotTest_a <= expXIsMax_uid32_fpHypotTest_q;
exc_I_uid35_fpHypotTest_b <= fracXIsZero_uid34_fpHypotTest_q;
exc_I_uid35_fpHypotTest_q <= exc_I_uid35_fpHypotTest_a and exc_I_uid35_fpHypotTest_b;
--InvExc_I_uid39_fpHypotTest(LOGICAL,38)@0
InvExc_I_uid39_fpHypotTest_a <= exc_I_uid35_fpHypotTest_q;
InvExc_I_uid39_fpHypotTest_q <= not InvExc_I_uid39_fpHypotTest_a;
--InvFracXIsZero_uid20_fpHypotTest(LOGICAL,19)@0
InvFracXIsZero_uid20_fpHypotTest_a <= fracXIsZero_uid18_fpHypotTest_q;
InvFracXIsZero_uid20_fpHypotTest_q <= not InvFracXIsZero_uid20_fpHypotTest_a;
--exc_N_uid21_fpHypotTest(LOGICAL,20)@0
exc_N_uid21_fpHypotTest_a <= expXIsMax_uid16_fpHypotTest_q;
exc_N_uid21_fpHypotTest_b <= InvFracXIsZero_uid20_fpHypotTest_q;
exc_N_uid21_fpHypotTest_q <= exc_N_uid21_fpHypotTest_a and exc_N_uid21_fpHypotTest_b;
--xNaNyNonInf_uid129_fpHypotTest(LOGICAL,128)@0
xNaNyNonInf_uid129_fpHypotTest_a <= exc_N_uid21_fpHypotTest_q;
xNaNyNonInf_uid129_fpHypotTest_b <= InvExc_I_uid39_fpHypotTest_q;
xNaNyNonInf_uid129_fpHypotTest_q <= xNaNyNonInf_uid129_fpHypotTest_a and xNaNyNonInf_uid129_fpHypotTest_b;
--excRNaN_uid130_fpHypotTest(LOGICAL,129)@0
excRNaN_uid130_fpHypotTest_a <= xNaNyNonInf_uid129_fpHypotTest_q;
excRNaN_uid130_fpHypotTest_b <= yNaNxNonInf_uid127_fpHypotTest_q;
excRNaN_uid130_fpHypotTest_q <= excRNaN_uid130_fpHypotTest_a or excRNaN_uid130_fpHypotTest_b;
--ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_inputreg(DELAY,614)
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid130_fpHypotTest_q, xout => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt(COUNTER,525)
-- every=1, low=0, high=21, step=1, init=1
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i = 20 THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_eq = '1') THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i - 21;
ELSE
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i,5));
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg(REG,526)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux(MUX,527)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_s <= en;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux: PROCESS (ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_s, ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q, ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_q)
BEGIN
CASE ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_s IS
WHEN "0" => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
WHEN "1" => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem(DUALMEM,615)
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_ia <= ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_inputreg_q;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_aa <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_ab <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_ia
);
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_q <= ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_iq(0 downto 0);
--reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1(REG,231)@23
reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q <= expRPostInc_uid114_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--sqrtOverflow_uid117_fpHypotTest(COMPARE,116)@24
sqrtOverflow_uid117_fpHypotTest_cin <= GND_q;
sqrtOverflow_uid117_fpHypotTest_a <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q(10)) & reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q) & '0';
sqrtOverflow_uid117_fpHypotTest_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid10_fpHypotTest_q) & sqrtOverflow_uid117_fpHypotTest_cin(0);
sqrtOverflow_uid117_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(sqrtOverflow_uid117_fpHypotTest_a) - SIGNED(sqrtOverflow_uid117_fpHypotTest_b));
sqrtOverflow_uid117_fpHypotTest_n(0) <= not sqrtOverflow_uid117_fpHypotTest_o(13);
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor(LOGICAL,533)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_b <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_q <= not (ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_a or ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_b);
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena(REG,534)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_q = "1") THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd(LOGICAL,535)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_a <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_b <= en;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_a and ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_b;
--InvExc_N_uid22_fpHypotTest(LOGICAL,21)@0
InvExc_N_uid22_fpHypotTest_a <= exc_N_uid21_fpHypotTest_q;
InvExc_N_uid22_fpHypotTest_q <= not InvExc_N_uid22_fpHypotTest_a;
--InvExpXIsZero_uid24_fpHypotTest(LOGICAL,23)@0
InvExpXIsZero_uid24_fpHypotTest_a <= expXIsZero_uid14_fpHypotTest_q;
InvExpXIsZero_uid24_fpHypotTest_q <= not InvExpXIsZero_uid24_fpHypotTest_a;
--exc_R_uid25_fpHypotTest(LOGICAL,24)@0
exc_R_uid25_fpHypotTest_a <= InvExpXIsZero_uid24_fpHypotTest_q;
exc_R_uid25_fpHypotTest_b <= InvExc_I_uid23_fpHypotTest_q;
exc_R_uid25_fpHypotTest_c <= InvExc_N_uid22_fpHypotTest_q;
exc_R_uid25_fpHypotTest_q <= exc_R_uid25_fpHypotTest_a and exc_R_uid25_fpHypotTest_b and exc_R_uid25_fpHypotTest_c;
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_inputreg(DELAY,523)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid25_fpHypotTest_q, xout => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem(DUALMEM,524)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_ia <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_inputreg_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_aa <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_ab <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_iq,
address_a => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_aa,
data_a => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_ia
);
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_reset0 <= areset;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_iq(0 downto 0);
--ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor(LOGICAL,585)
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_b <= ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena_q;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_q <= not (ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_a or ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_b);
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_mem_top(CONSTANT,568)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_mem_top_q <= "010100";
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp(LOGICAL,569)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_a <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_mem_top_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q);
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_q <= "1" when ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_a = ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_b else "0";
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg(REG,570)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena(REG,586)
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_q = "1") THEN
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd(LOGICAL,587)
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_a <= ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena_q;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_b <= en;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_q <= ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_a and ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_b;
--InvExc_N_uid38_fpHypotTest(LOGICAL,37)@0
InvExc_N_uid38_fpHypotTest_a <= exc_N_uid37_fpHypotTest_q;
InvExc_N_uid38_fpHypotTest_q <= not InvExc_N_uid38_fpHypotTest_a;
--InvExpXIsZero_uid40_fpHypotTest(LOGICAL,39)@0
InvExpXIsZero_uid40_fpHypotTest_a <= expXIsZero_uid30_fpHypotTest_q;
InvExpXIsZero_uid40_fpHypotTest_q <= not InvExpXIsZero_uid40_fpHypotTest_a;
--exc_R_uid41_fpHypotTest(LOGICAL,40)@0
exc_R_uid41_fpHypotTest_a <= InvExpXIsZero_uid40_fpHypotTest_q;
exc_R_uid41_fpHypotTest_b <= InvExc_I_uid39_fpHypotTest_q;
exc_R_uid41_fpHypotTest_c <= InvExc_N_uid38_fpHypotTest_q;
exc_R_uid41_fpHypotTest_q <= exc_R_uid41_fpHypotTest_a and exc_R_uid41_fpHypotTest_b and exc_R_uid41_fpHypotTest_c;
--yRegOrZero_uid123_fpHypotTest(LOGICAL,122)@0
yRegOrZero_uid123_fpHypotTest_a <= exc_R_uid41_fpHypotTest_q;
yRegOrZero_uid123_fpHypotTest_b <= expXIsZero_uid30_fpHypotTest_q;
yRegOrZero_uid123_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
yRegOrZero_uid123_fpHypotTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
yRegOrZero_uid123_fpHypotTest_q <= yRegOrZero_uid123_fpHypotTest_a or yRegOrZero_uid123_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_inputreg(DELAY,575)
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yRegOrZero_uid123_fpHypotTest_q, xout => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt(COUNTER,564)
-- every=1, low=0, high=20, step=1, init=1
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i = 19 THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_eq = '1') THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i - 20;
ELSE
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i,5));
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg(REG,565)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux(MUX,566)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_s <= en;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux: PROCESS (ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_s, ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q, ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_q)
BEGIN
CASE ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_s IS
WHEN "0" => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q;
WHEN "1" => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem(DUALMEM,576)
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_ia <= ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_inputreg_q;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_aa <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_ab <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 21,
width_b => 1,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_iq,
address_a => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_aa,
data_a => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_ia
);
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_reset0 <= areset;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_q <= ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_iq(0 downto 0);
--yRegOrZeroXRegOvf_uid124_fpHypotTest(LOGICAL,123)@24
yRegOrZeroXRegOvf_uid124_fpHypotTest_a <= ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_q;
yRegOrZeroXRegOvf_uid124_fpHypotTest_b <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_q;
yRegOrZeroXRegOvf_uid124_fpHypotTest_c <= sqrtOverflow_uid117_fpHypotTest_n;
yRegOrZeroXRegOvf_uid124_fpHypotTest_q <= yRegOrZeroXRegOvf_uid124_fpHypotTest_a and yRegOrZeroXRegOvf_uid124_fpHypotTest_b and yRegOrZeroXRegOvf_uid124_fpHypotTest_c;
--ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor(LOGICAL,546)
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_b <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena_q;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_q <= not (ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_a or ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_b);
--ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena(REG,547)
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_q = "1") THEN
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd(LOGICAL,548)
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_a <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena_q;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_b <= en;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_q <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_a and ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_b;
--ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_inputreg(DELAY,536)
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid41_fpHypotTest_q, xout => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem(DUALMEM,537)
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_ia <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_inputreg_q;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_aa <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_ab <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_iq,
address_a => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_aa,
data_a => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_ia
);
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_reset0 <= areset;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_q <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_iq(0 downto 0);
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor(LOGICAL,572)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_b <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_q <= not (ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_a or ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_b);
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena(REG,573)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_q = "1") THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd(LOGICAL,574)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_a <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_b <= en;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_a and ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_b;
--xRegOrZero_uid121_fpHypotTest(LOGICAL,120)@0
xRegOrZero_uid121_fpHypotTest_a <= exc_R_uid25_fpHypotTest_q;
xRegOrZero_uid121_fpHypotTest_b <= expXIsZero_uid14_fpHypotTest_q;
xRegOrZero_uid121_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xRegOrZero_uid121_fpHypotTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xRegOrZero_uid121_fpHypotTest_q <= xRegOrZero_uid121_fpHypotTest_a or xRegOrZero_uid121_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_inputreg(DELAY,562)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xRegOrZero_uid121_fpHypotTest_q, xout => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem(DUALMEM,563)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_ia <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_inputreg_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_aa <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_ab <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 21,
width_b => 1,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_iq,
address_a => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_aa,
data_a => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_ia
);
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_reset0 <= areset;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_iq(0 downto 0);
--xRegOrZeroYRegOvf_uid122_fpHypotTest(LOGICAL,121)@24
xRegOrZeroYRegOvf_uid122_fpHypotTest_a <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_q;
xRegOrZeroYRegOvf_uid122_fpHypotTest_b <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_q;
xRegOrZeroYRegOvf_uid122_fpHypotTest_c <= sqrtOverflow_uid117_fpHypotTest_n;
xRegOrZeroYRegOvf_uid122_fpHypotTest_q <= xRegOrZeroYRegOvf_uid122_fpHypotTest_a and xRegOrZeroYRegOvf_uid122_fpHypotTest_b and xRegOrZeroYRegOvf_uid122_fpHypotTest_c;
--ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor(LOGICAL,611)
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_b <= ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena_q;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_q <= not (ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_a or ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_b);
--ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena(REG,612)
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_q = "1") THEN
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd(LOGICAL,613)
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_a <= ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena_q;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_b <= en;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_q <= ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_a and ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_b;
--ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_inputreg(DELAY,601)
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid35_fpHypotTest_q, xout => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem(DUALMEM,602)
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_ia <= ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_inputreg_q;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_aa <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_ab <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_iq,
address_a => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_aa,
data_a => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_ia
);
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_q <= ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_iq(0 downto 0);
--ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor(LOGICAL,598)
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_b <= ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena_q;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_q <= not (ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_a or ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_b);
--ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena(REG,599)
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_q = "1") THEN
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd(LOGICAL,600)
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_a <= ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena_q;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_b <= en;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_q <= ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_a and ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_b;
--ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_inputreg(DELAY,588)
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid19_fpHypotTest_q, xout => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem(DUALMEM,589)
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_ia <= ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_inputreg_q;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_aa <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_ab <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_iq,
address_a => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_aa,
data_a => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_ia
);
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_reset0 <= areset;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_q <= ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_iq(0 downto 0);
--excRInf_uid125_fpHypotTest(LOGICAL,124)@24
excRInf_uid125_fpHypotTest_a <= ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_q;
excRInf_uid125_fpHypotTest_b <= ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_q;
excRInf_uid125_fpHypotTest_c <= xRegOrZeroYRegOvf_uid122_fpHypotTest_q;
excRInf_uid125_fpHypotTest_d <= yRegOrZeroXRegOvf_uid124_fpHypotTest_q;
excRInf_uid125_fpHypotTest_q <= excRInf_uid125_fpHypotTest_a or excRInf_uid125_fpHypotTest_b or excRInf_uid125_fpHypotTest_c or excRInf_uid125_fpHypotTest_d;
--sqrtUnderflow_uid115_fpHypotTest(COMPARE,114)@24
sqrtUnderflow_uid115_fpHypotTest_cin <= GND_q;
sqrtUnderflow_uid115_fpHypotTest_a <= STD_LOGIC_VECTOR('0' & "00000000000" & GND_q) & '0';
sqrtUnderflow_uid115_fpHypotTest_b <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q(10)) & reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q) & sqrtUnderflow_uid115_fpHypotTest_cin(0);
sqrtUnderflow_uid115_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(sqrtUnderflow_uid115_fpHypotTest_a) - SIGNED(sqrtUnderflow_uid115_fpHypotTest_b));
sqrtUnderflow_uid115_fpHypotTest_n(0) <= not sqrtUnderflow_uid115_fpHypotTest_o(13);
--excXYRUdf_uid119_fpHypotTest(LOGICAL,118)@24
excXYRUdf_uid119_fpHypotTest_a <= sqrtUnderflow_uid115_fpHypotTest_n;
excXYRUdf_uid119_fpHypotTest_b <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_q;
excXYRUdf_uid119_fpHypotTest_c <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_q;
excXYRUdf_uid119_fpHypotTest_q <= excXYRUdf_uid119_fpHypotTest_a and excXYRUdf_uid119_fpHypotTest_b and excXYRUdf_uid119_fpHypotTest_c;
--ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor(LOGICAL,559)
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_b <= ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena_q;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_q <= not (ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_a or ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_b);
--ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena(REG,560)
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_q = "1") THEN
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd(LOGICAL,561)
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_a <= ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena_q;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_b <= en;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_q <= ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_a and ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_b;
--excXYZ_uid118_fpHypotTest(LOGICAL,117)@0
excXYZ_uid118_fpHypotTest_a <= expXIsZero_uid14_fpHypotTest_q;
excXYZ_uid118_fpHypotTest_b <= expXIsZero_uid30_fpHypotTest_q;
excXYZ_uid118_fpHypotTest_q <= excXYZ_uid118_fpHypotTest_a and excXYZ_uid118_fpHypotTest_b;
--ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_inputreg(DELAY,549)
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excXYZ_uid118_fpHypotTest_q, xout => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem(DUALMEM,550)
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_ia <= ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_inputreg_q;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_aa <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_ab <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_iq,
address_a => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_aa,
data_a => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_ia
);
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_reset0 <= areset;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_q <= ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_iq(0 downto 0);
--excRZero_uid120_fpHypotTest(LOGICAL,119)@24
excRZero_uid120_fpHypotTest_a <= ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_q;
excRZero_uid120_fpHypotTest_b <= excXYRUdf_uid119_fpHypotTest_q;
excRZero_uid120_fpHypotTest_q <= excRZero_uid120_fpHypotTest_a or excRZero_uid120_fpHypotTest_b;
--excSelBits_uid131_fpHypotTest(BITJOIN,130)@24
excSelBits_uid131_fpHypotTest_q <= ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_q & excRInf_uid125_fpHypotTest_q & excRZero_uid120_fpHypotTest_q;
--reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0(REG,233)@24
reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0_q <= excSelBits_uid131_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid132_fpHypotTest(LOOKUP,131)@25
outMuxSelEnc_uid132_fpHypotTest: PROCESS (reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid132_fpHypotTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid132_fpHypotTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid132_fpHypotTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid132_fpHypotTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid132_fpHypotTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid132_fpHypotTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid132_fpHypotTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid132_fpHypotTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid132_fpHypotTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid141_fpHypotTest(MUX,140)@25
expRPostExc_uid141_fpHypotTest_s <= outMuxSelEnc_uid132_fpHypotTest_q;
expRPostExc_uid141_fpHypotTest: PROCESS (expRPostExc_uid141_fpHypotTest_s, en, cstAllZWE_uid12_fpHypotTest_q, ld_expRPreExc_uid139_fpHypotTest_b_to_expRPostExc_uid141_fpHypotTest_d_q, cstAllOWE_uid10_fpHypotTest_q, cstAllOWE_uid10_fpHypotTest_q)
BEGIN
CASE expRPostExc_uid141_fpHypotTest_s IS
WHEN "00" => expRPostExc_uid141_fpHypotTest_q <= cstAllZWE_uid12_fpHypotTest_q;
WHEN "01" => expRPostExc_uid141_fpHypotTest_q <= ld_expRPreExc_uid139_fpHypotTest_b_to_expRPostExc_uid141_fpHypotTest_d_q;
WHEN "10" => expRPostExc_uid141_fpHypotTest_q <= cstAllOWE_uid10_fpHypotTest_q;
WHEN "11" => expRPostExc_uid141_fpHypotTest_q <= cstAllOWE_uid10_fpHypotTest_q;
WHEN OTHERS => expRPostExc_uid141_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--NaNFracRPostExc_uid133_fpHypotTest(CONSTANT,132)
NaNFracRPostExc_uid133_fpHypotTest_q <= "00000000000000000000001";
--fracR_uid112_fpHypotTest(BITSELECT,111)@22
fracR_uid112_fpHypotTest_in <= fracRPostInc_uid111_fpHypotTest_q(23 downto 0);
fracR_uid112_fpHypotTest_b <= fracR_uid112_fpHypotTest_in(23 downto 1);
--ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_inputreg(DELAY,627)
ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracR_uid112_fpHypotTest_b, xout => ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d(DELAY,401)@22
ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_inputreg_q, xout => ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid136_fpHypotTest(MUX,135)@25
fracRPostExc_uid136_fpHypotTest_s <= outMuxSelEnc_uid132_fpHypotTest_q;
fracRPostExc_uid136_fpHypotTest: PROCESS (fracRPostExc_uid136_fpHypotTest_s, en, cstAllZWF_uid11_fpHypotTest_q, ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_q, cstAllZWF_uid11_fpHypotTest_q, NaNFracRPostExc_uid133_fpHypotTest_q)
BEGIN
CASE fracRPostExc_uid136_fpHypotTest_s IS
WHEN "00" => fracRPostExc_uid136_fpHypotTest_q <= cstAllZWF_uid11_fpHypotTest_q;
WHEN "01" => fracRPostExc_uid136_fpHypotTest_q <= ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_q;
WHEN "10" => fracRPostExc_uid136_fpHypotTest_q <= cstAllZWF_uid11_fpHypotTest_q;
WHEN "11" => fracRPostExc_uid136_fpHypotTest_q <= NaNFracRPostExc_uid133_fpHypotTest_q;
WHEN OTHERS => fracRPostExc_uid136_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--RHypot_uid142_fpHypotTest(BITJOIN,141)@25
RHypot_uid142_fpHypotTest_q <= GND_q & expRPostExc_uid141_fpHypotTest_q & fracRPostExc_uid136_fpHypotTest_q;
--xOut(GPOUT,4)@25
q <= RHypot_uid142_fpHypotTest_q;
end normal;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fpc_library_cmd.vhd | 10 | 105191 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal_v31 ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_addsub_sInternalSM_2_sInternal_v31 IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal_v31;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal_v31 IS
BEGIN
cmp: hcc_aludot_v2
GENERIC MAP (
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aasign => dataa(42),
aaexponent => dataa(41 DOWNTO 32),
aamantissa => dataa(31 DOWNTO 0),
aasat => dataa(43),
aazip => dataa(44),
aanan => dataa(45),
bbsign => datab(42),
bbexponent => datab(41 DOWNTO 32),
bbmantissa => datab(31 DOWNTO 0),
bbsat => datab(43),
bbzip => datab(44),
bbnan => dataa(45),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM _v31 ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_sIEEE_2_sInternalSM_v31 IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM_v31;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM_v31 IS
BEGIN
cmp: hcc_muldot_v1
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
ccsign => result(42),
ccexponent => result(41 DOWNTO 32),
ccmantissa => result(31 DOWNTO 0),
ccsat => result(43),
cczip => result(44),
ccnan => result(45)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal oneOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
signal resPreExcHandling: std_logic_vector(31 downto 0);
signal excBits : std_logic_vector(3 downto 0);
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => resPreExcHandling(31),
exponentout => resPreExcHandling(30 downto 23),
mantissaout => resPreExcHandling(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut,
oneOut => oneOut
);
excBits <= nanOut & overflowOut & underflowOut & oneOut;
with excBits select
result <= "01111111100000000000000000000001" when "1000"|"1001"|"1100",
"01111111100000000000000000000000" when "0100",
"00000000000000000000000000000000" when "0010",
"00111111100000000000000000000000" when "0001"|"0011"|"0101",
resPreExcHandling when others;
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_lsft23.vhd | 10 | 4244 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT23.VHD ***
--*** ***
--*** Function: 23 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft23 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_lsft23;
ARCHITECTURE sft OF fp_lsft23 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (23 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 23 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 23 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 23 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END sft;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/hcc_castxtod.vhd | 10 | 3498 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_castxtod.vhd | 10 | 3498 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/fpc_library_package_cmd.vhd | 10 | 48869 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_mulfp1_dot_sv.vhd | 10 | 14347 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/hcc_rsftcomb64.vhd | 10 | 4574 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/hcc_castdtol.vhd | 10 | 3430 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtol IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castdtol;
ARCHITECTURE rtl OF hcc_castdtol IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,outputpipe=>1,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytol
GENERIC MAP (normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_rsft56x20.vhd | 10 | 3434 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT56X20.VHD ***
--*** ***
--*** Function: 56 bit Unsigned Right Shift ***
--*** (Maximum 20 bit Shift) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft56x20 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (56 DOWNTO 1)
);
END fp_rsft56x20;
ARCHITECTURE rtl OF fp_rsft56x20 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (56 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 53 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(54) <= (levzip(54) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(55) AND NOT(shift(2)) AND shift(1)) OR
(levzip(56) AND shift(2) AND NOT(shift(1)));
levone(55) <= (levzip(55) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(56) AND NOT(shift(2)) AND shift(1));
levone(56) <= levzip(56) AND NOT(shift(2)) AND NOT(shift(1));
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 44 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 45 TO 48 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbc: FOR k IN 49 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbd: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gca: FOR k IN 1 TO 40 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k+16) AND shift(5));
END GENERATE;
gcc: FOR k IN 41 TO 56 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/hcc_alufp2x.vhd | 10 | 10713 |
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/hcc_neg2x.vhd | 10 | 2843 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NEG2X.VHD ***
--*** ***
--*** Function: Negation (for unary -ve) ***
--*** ***
--*** 13/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_neg2x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_neg2x;
ARCHITECTURE rtl OF hcc_neg2x IS
signal aaff : STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC;
BEGIN
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64+13*xoutput+3*funcoutput LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
goa: IF (ieeeoutput = 1) GENERATE
cc(64) <= NOT(aaff(64));
cc(63 DOWNTO 1) <= aaff(63 DOWNTO 1);
ccsat <= '0';
cczip <= '0';
END GENERATE;
gob: IF (xoutput = 1) GENERATE
gxa: FOR k IN 14 TO 77 GENERATE
cc(k) <= NOT(aaff(k));
END GENERATE;
cc(13 DOWNTO 1) <= aaff(13 DOWNTO 1);
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
goc: IF (funcoutput = 1) GENERATE
cc(67) <= NOT(aaff(67));
cc(66 DOWNTO 1) <= aaff(66 DOWNTO 1);
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/hcc_delay.vhd | 10 | 3399 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_invsqr_lut1.vhd | 10 | 35784 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_INVSQR_LUT1.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse Root ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_invsqr_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END fp_invsqr_lut1;
ARCHITECTURE rtl OF fp_invsqr_lut1 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1023,11);
WHEN "000000001" => data <= conv_std_logic_vector(1020,11);
WHEN "000000010" => data <= conv_std_logic_vector(1017,11);
WHEN "000000011" => data <= conv_std_logic_vector(1014,11);
WHEN "000000100" => data <= conv_std_logic_vector(1011,11);
WHEN "000000101" => data <= conv_std_logic_vector(1008,11);
WHEN "000000110" => data <= conv_std_logic_vector(1005,11);
WHEN "000000111" => data <= conv_std_logic_vector(1002,11);
WHEN "000001000" => data <= conv_std_logic_vector(999,11);
WHEN "000001001" => data <= conv_std_logic_vector(996,11);
WHEN "000001010" => data <= conv_std_logic_vector(993,11);
WHEN "000001011" => data <= conv_std_logic_vector(990,11);
WHEN "000001100" => data <= conv_std_logic_vector(988,11);
WHEN "000001101" => data <= conv_std_logic_vector(985,11);
WHEN "000001110" => data <= conv_std_logic_vector(982,11);
WHEN "000001111" => data <= conv_std_logic_vector(979,11);
WHEN "000010000" => data <= conv_std_logic_vector(976,11);
WHEN "000010001" => data <= conv_std_logic_vector(974,11);
WHEN "000010010" => data <= conv_std_logic_vector(971,11);
WHEN "000010011" => data <= conv_std_logic_vector(968,11);
WHEN "000010100" => data <= conv_std_logic_vector(965,11);
WHEN "000010101" => data <= conv_std_logic_vector(963,11);
WHEN "000010110" => data <= conv_std_logic_vector(960,11);
WHEN "000010111" => data <= conv_std_logic_vector(957,11);
WHEN "000011000" => data <= conv_std_logic_vector(955,11);
WHEN "000011001" => data <= conv_std_logic_vector(952,11);
WHEN "000011010" => data <= conv_std_logic_vector(949,11);
WHEN "000011011" => data <= conv_std_logic_vector(947,11);
WHEN "000011100" => data <= conv_std_logic_vector(944,11);
WHEN "000011101" => data <= conv_std_logic_vector(941,11);
WHEN "000011110" => data <= conv_std_logic_vector(939,11);
WHEN "000011111" => data <= conv_std_logic_vector(936,11);
WHEN "000100000" => data <= conv_std_logic_vector(934,11);
WHEN "000100001" => data <= conv_std_logic_vector(931,11);
WHEN "000100010" => data <= conv_std_logic_vector(929,11);
WHEN "000100011" => data <= conv_std_logic_vector(926,11);
WHEN "000100100" => data <= conv_std_logic_vector(924,11);
WHEN "000100101" => data <= conv_std_logic_vector(921,11);
WHEN "000100110" => data <= conv_std_logic_vector(918,11);
WHEN "000100111" => data <= conv_std_logic_vector(916,11);
WHEN "000101000" => data <= conv_std_logic_vector(913,11);
WHEN "000101001" => data <= conv_std_logic_vector(911,11);
WHEN "000101010" => data <= conv_std_logic_vector(909,11);
WHEN "000101011" => data <= conv_std_logic_vector(906,11);
WHEN "000101100" => data <= conv_std_logic_vector(904,11);
WHEN "000101101" => data <= conv_std_logic_vector(901,11);
WHEN "000101110" => data <= conv_std_logic_vector(899,11);
WHEN "000101111" => data <= conv_std_logic_vector(896,11);
WHEN "000110000" => data <= conv_std_logic_vector(894,11);
WHEN "000110001" => data <= conv_std_logic_vector(892,11);
WHEN "000110010" => data <= conv_std_logic_vector(889,11);
WHEN "000110011" => data <= conv_std_logic_vector(887,11);
WHEN "000110100" => data <= conv_std_logic_vector(885,11);
WHEN "000110101" => data <= conv_std_logic_vector(882,11);
WHEN "000110110" => data <= conv_std_logic_vector(880,11);
WHEN "000110111" => data <= conv_std_logic_vector(878,11);
WHEN "000111000" => data <= conv_std_logic_vector(875,11);
WHEN "000111001" => data <= conv_std_logic_vector(873,11);
WHEN "000111010" => data <= conv_std_logic_vector(871,11);
WHEN "000111011" => data <= conv_std_logic_vector(868,11);
WHEN "000111100" => data <= conv_std_logic_vector(866,11);
WHEN "000111101" => data <= conv_std_logic_vector(864,11);
WHEN "000111110" => data <= conv_std_logic_vector(862,11);
WHEN "000111111" => data <= conv_std_logic_vector(859,11);
WHEN "001000000" => data <= conv_std_logic_vector(857,11);
WHEN "001000001" => data <= conv_std_logic_vector(855,11);
WHEN "001000010" => data <= conv_std_logic_vector(853,11);
WHEN "001000011" => data <= conv_std_logic_vector(850,11);
WHEN "001000100" => data <= conv_std_logic_vector(848,11);
WHEN "001000101" => data <= conv_std_logic_vector(846,11);
WHEN "001000110" => data <= conv_std_logic_vector(844,11);
WHEN "001000111" => data <= conv_std_logic_vector(842,11);
WHEN "001001000" => data <= conv_std_logic_vector(840,11);
WHEN "001001001" => data <= conv_std_logic_vector(837,11);
WHEN "001001010" => data <= conv_std_logic_vector(835,11);
WHEN "001001011" => data <= conv_std_logic_vector(833,11);
WHEN "001001100" => data <= conv_std_logic_vector(831,11);
WHEN "001001101" => data <= conv_std_logic_vector(829,11);
WHEN "001001110" => data <= conv_std_logic_vector(827,11);
WHEN "001001111" => data <= conv_std_logic_vector(825,11);
WHEN "001010000" => data <= conv_std_logic_vector(823,11);
WHEN "001010001" => data <= conv_std_logic_vector(820,11);
WHEN "001010010" => data <= conv_std_logic_vector(818,11);
WHEN "001010011" => data <= conv_std_logic_vector(816,11);
WHEN "001010100" => data <= conv_std_logic_vector(814,11);
WHEN "001010101" => data <= conv_std_logic_vector(812,11);
WHEN "001010110" => data <= conv_std_logic_vector(810,11);
WHEN "001010111" => data <= conv_std_logic_vector(808,11);
WHEN "001011000" => data <= conv_std_logic_vector(806,11);
WHEN "001011001" => data <= conv_std_logic_vector(804,11);
WHEN "001011010" => data <= conv_std_logic_vector(802,11);
WHEN "001011011" => data <= conv_std_logic_vector(800,11);
WHEN "001011100" => data <= conv_std_logic_vector(798,11);
WHEN "001011101" => data <= conv_std_logic_vector(796,11);
WHEN "001011110" => data <= conv_std_logic_vector(794,11);
WHEN "001011111" => data <= conv_std_logic_vector(792,11);
WHEN "001100000" => data <= conv_std_logic_vector(790,11);
WHEN "001100001" => data <= conv_std_logic_vector(788,11);
WHEN "001100010" => data <= conv_std_logic_vector(786,11);
WHEN "001100011" => data <= conv_std_logic_vector(785,11);
WHEN "001100100" => data <= conv_std_logic_vector(783,11);
WHEN "001100101" => data <= conv_std_logic_vector(781,11);
WHEN "001100110" => data <= conv_std_logic_vector(779,11);
WHEN "001100111" => data <= conv_std_logic_vector(777,11);
WHEN "001101000" => data <= conv_std_logic_vector(775,11);
WHEN "001101001" => data <= conv_std_logic_vector(773,11);
WHEN "001101010" => data <= conv_std_logic_vector(771,11);
WHEN "001101011" => data <= conv_std_logic_vector(769,11);
WHEN "001101100" => data <= conv_std_logic_vector(768,11);
WHEN "001101101" => data <= conv_std_logic_vector(766,11);
WHEN "001101110" => data <= conv_std_logic_vector(764,11);
WHEN "001101111" => data <= conv_std_logic_vector(762,11);
WHEN "001110000" => data <= conv_std_logic_vector(760,11);
WHEN "001110001" => data <= conv_std_logic_vector(758,11);
WHEN "001110010" => data <= conv_std_logic_vector(757,11);
WHEN "001110011" => data <= conv_std_logic_vector(755,11);
WHEN "001110100" => data <= conv_std_logic_vector(753,11);
WHEN "001110101" => data <= conv_std_logic_vector(751,11);
WHEN "001110110" => data <= conv_std_logic_vector(749,11);
WHEN "001110111" => data <= conv_std_logic_vector(748,11);
WHEN "001111000" => data <= conv_std_logic_vector(746,11);
WHEN "001111001" => data <= conv_std_logic_vector(744,11);
WHEN "001111010" => data <= conv_std_logic_vector(742,11);
WHEN "001111011" => data <= conv_std_logic_vector(741,11);
WHEN "001111100" => data <= conv_std_logic_vector(739,11);
WHEN "001111101" => data <= conv_std_logic_vector(737,11);
WHEN "001111110" => data <= conv_std_logic_vector(735,11);
WHEN "001111111" => data <= conv_std_logic_vector(734,11);
WHEN "010000000" => data <= conv_std_logic_vector(732,11);
WHEN "010000001" => data <= conv_std_logic_vector(730,11);
WHEN "010000010" => data <= conv_std_logic_vector(728,11);
WHEN "010000011" => data <= conv_std_logic_vector(727,11);
WHEN "010000100" => data <= conv_std_logic_vector(725,11);
WHEN "010000101" => data <= conv_std_logic_vector(723,11);
WHEN "010000110" => data <= conv_std_logic_vector(722,11);
WHEN "010000111" => data <= conv_std_logic_vector(720,11);
WHEN "010001000" => data <= conv_std_logic_vector(718,11);
WHEN "010001001" => data <= conv_std_logic_vector(717,11);
WHEN "010001010" => data <= conv_std_logic_vector(715,11);
WHEN "010001011" => data <= conv_std_logic_vector(713,11);
WHEN "010001100" => data <= conv_std_logic_vector(712,11);
WHEN "010001101" => data <= conv_std_logic_vector(710,11);
WHEN "010001110" => data <= conv_std_logic_vector(709,11);
WHEN "010001111" => data <= conv_std_logic_vector(707,11);
WHEN "010010000" => data <= conv_std_logic_vector(705,11);
WHEN "010010001" => data <= conv_std_logic_vector(704,11);
WHEN "010010010" => data <= conv_std_logic_vector(702,11);
WHEN "010010011" => data <= conv_std_logic_vector(700,11);
WHEN "010010100" => data <= conv_std_logic_vector(699,11);
WHEN "010010101" => data <= conv_std_logic_vector(697,11);
WHEN "010010110" => data <= conv_std_logic_vector(696,11);
WHEN "010010111" => data <= conv_std_logic_vector(694,11);
WHEN "010011000" => data <= conv_std_logic_vector(693,11);
WHEN "010011001" => data <= conv_std_logic_vector(691,11);
WHEN "010011010" => data <= conv_std_logic_vector(689,11);
WHEN "010011011" => data <= conv_std_logic_vector(688,11);
WHEN "010011100" => data <= conv_std_logic_vector(686,11);
WHEN "010011101" => data <= conv_std_logic_vector(685,11);
WHEN "010011110" => data <= conv_std_logic_vector(683,11);
WHEN "010011111" => data <= conv_std_logic_vector(682,11);
WHEN "010100000" => data <= conv_std_logic_vector(680,11);
WHEN "010100001" => data <= conv_std_logic_vector(679,11);
WHEN "010100010" => data <= conv_std_logic_vector(677,11);
WHEN "010100011" => data <= conv_std_logic_vector(676,11);
WHEN "010100100" => data <= conv_std_logic_vector(674,11);
WHEN "010100101" => data <= conv_std_logic_vector(673,11);
WHEN "010100110" => data <= conv_std_logic_vector(671,11);
WHEN "010100111" => data <= conv_std_logic_vector(670,11);
WHEN "010101000" => data <= conv_std_logic_vector(668,11);
WHEN "010101001" => data <= conv_std_logic_vector(667,11);
WHEN "010101010" => data <= conv_std_logic_vector(665,11);
WHEN "010101011" => data <= conv_std_logic_vector(664,11);
WHEN "010101100" => data <= conv_std_logic_vector(662,11);
WHEN "010101101" => data <= conv_std_logic_vector(661,11);
WHEN "010101110" => data <= conv_std_logic_vector(660,11);
WHEN "010101111" => data <= conv_std_logic_vector(658,11);
WHEN "010110000" => data <= conv_std_logic_vector(657,11);
WHEN "010110001" => data <= conv_std_logic_vector(655,11);
WHEN "010110010" => data <= conv_std_logic_vector(654,11);
WHEN "010110011" => data <= conv_std_logic_vector(652,11);
WHEN "010110100" => data <= conv_std_logic_vector(651,11);
WHEN "010110101" => data <= conv_std_logic_vector(650,11);
WHEN "010110110" => data <= conv_std_logic_vector(648,11);
WHEN "010110111" => data <= conv_std_logic_vector(647,11);
WHEN "010111000" => data <= conv_std_logic_vector(645,11);
WHEN "010111001" => data <= conv_std_logic_vector(644,11);
WHEN "010111010" => data <= conv_std_logic_vector(643,11);
WHEN "010111011" => data <= conv_std_logic_vector(641,11);
WHEN "010111100" => data <= conv_std_logic_vector(640,11);
WHEN "010111101" => data <= conv_std_logic_vector(639,11);
WHEN "010111110" => data <= conv_std_logic_vector(637,11);
WHEN "010111111" => data <= conv_std_logic_vector(636,11);
WHEN "011000000" => data <= conv_std_logic_vector(634,11);
WHEN "011000001" => data <= conv_std_logic_vector(633,11);
WHEN "011000010" => data <= conv_std_logic_vector(632,11);
WHEN "011000011" => data <= conv_std_logic_vector(630,11);
WHEN "011000100" => data <= conv_std_logic_vector(629,11);
WHEN "011000101" => data <= conv_std_logic_vector(628,11);
WHEN "011000110" => data <= conv_std_logic_vector(626,11);
WHEN "011000111" => data <= conv_std_logic_vector(625,11);
WHEN "011001000" => data <= conv_std_logic_vector(624,11);
WHEN "011001001" => data <= conv_std_logic_vector(622,11);
WHEN "011001010" => data <= conv_std_logic_vector(621,11);
WHEN "011001011" => data <= conv_std_logic_vector(620,11);
WHEN "011001100" => data <= conv_std_logic_vector(619,11);
WHEN "011001101" => data <= conv_std_logic_vector(617,11);
WHEN "011001110" => data <= conv_std_logic_vector(616,11);
WHEN "011001111" => data <= conv_std_logic_vector(615,11);
WHEN "011010000" => data <= conv_std_logic_vector(613,11);
WHEN "011010001" => data <= conv_std_logic_vector(612,11);
WHEN "011010010" => data <= conv_std_logic_vector(611,11);
WHEN "011010011" => data <= conv_std_logic_vector(610,11);
WHEN "011010100" => data <= conv_std_logic_vector(608,11);
WHEN "011010101" => data <= conv_std_logic_vector(607,11);
WHEN "011010110" => data <= conv_std_logic_vector(606,11);
WHEN "011010111" => data <= conv_std_logic_vector(605,11);
WHEN "011011000" => data <= conv_std_logic_vector(603,11);
WHEN "011011001" => data <= conv_std_logic_vector(602,11);
WHEN "011011010" => data <= conv_std_logic_vector(601,11);
WHEN "011011011" => data <= conv_std_logic_vector(600,11);
WHEN "011011100" => data <= conv_std_logic_vector(598,11);
WHEN "011011101" => data <= conv_std_logic_vector(597,11);
WHEN "011011110" => data <= conv_std_logic_vector(596,11);
WHEN "011011111" => data <= conv_std_logic_vector(595,11);
WHEN "011100000" => data <= conv_std_logic_vector(594,11);
WHEN "011100001" => data <= conv_std_logic_vector(592,11);
WHEN "011100010" => data <= conv_std_logic_vector(591,11);
WHEN "011100011" => data <= conv_std_logic_vector(590,11);
WHEN "011100100" => data <= conv_std_logic_vector(589,11);
WHEN "011100101" => data <= conv_std_logic_vector(588,11);
WHEN "011100110" => data <= conv_std_logic_vector(586,11);
WHEN "011100111" => data <= conv_std_logic_vector(585,11);
WHEN "011101000" => data <= conv_std_logic_vector(584,11);
WHEN "011101001" => data <= conv_std_logic_vector(583,11);
WHEN "011101010" => data <= conv_std_logic_vector(582,11);
WHEN "011101011" => data <= conv_std_logic_vector(580,11);
WHEN "011101100" => data <= conv_std_logic_vector(579,11);
WHEN "011101101" => data <= conv_std_logic_vector(578,11);
WHEN "011101110" => data <= conv_std_logic_vector(577,11);
WHEN "011101111" => data <= conv_std_logic_vector(576,11);
WHEN "011110000" => data <= conv_std_logic_vector(575,11);
WHEN "011110001" => data <= conv_std_logic_vector(574,11);
WHEN "011110010" => data <= conv_std_logic_vector(572,11);
WHEN "011110011" => data <= conv_std_logic_vector(571,11);
WHEN "011110100" => data <= conv_std_logic_vector(570,11);
WHEN "011110101" => data <= conv_std_logic_vector(569,11);
WHEN "011110110" => data <= conv_std_logic_vector(568,11);
WHEN "011110111" => data <= conv_std_logic_vector(567,11);
WHEN "011111000" => data <= conv_std_logic_vector(566,11);
WHEN "011111001" => data <= conv_std_logic_vector(565,11);
WHEN "011111010" => data <= conv_std_logic_vector(563,11);
WHEN "011111011" => data <= conv_std_logic_vector(562,11);
WHEN "011111100" => data <= conv_std_logic_vector(561,11);
WHEN "011111101" => data <= conv_std_logic_vector(560,11);
WHEN "011111110" => data <= conv_std_logic_vector(559,11);
WHEN "011111111" => data <= conv_std_logic_vector(558,11);
WHEN "100000000" => data <= conv_std_logic_vector(557,11);
WHEN "100000001" => data <= conv_std_logic_vector(556,11);
WHEN "100000010" => data <= conv_std_logic_vector(555,11);
WHEN "100000011" => data <= conv_std_logic_vector(554,11);
WHEN "100000100" => data <= conv_std_logic_vector(553,11);
WHEN "100000101" => data <= conv_std_logic_vector(551,11);
WHEN "100000110" => data <= conv_std_logic_vector(550,11);
WHEN "100000111" => data <= conv_std_logic_vector(549,11);
WHEN "100001000" => data <= conv_std_logic_vector(548,11);
WHEN "100001001" => data <= conv_std_logic_vector(547,11);
WHEN "100001010" => data <= conv_std_logic_vector(546,11);
WHEN "100001011" => data <= conv_std_logic_vector(545,11);
WHEN "100001100" => data <= conv_std_logic_vector(544,11);
WHEN "100001101" => data <= conv_std_logic_vector(543,11);
WHEN "100001110" => data <= conv_std_logic_vector(542,11);
WHEN "100001111" => data <= conv_std_logic_vector(541,11);
WHEN "100010000" => data <= conv_std_logic_vector(540,11);
WHEN "100010001" => data <= conv_std_logic_vector(539,11);
WHEN "100010010" => data <= conv_std_logic_vector(538,11);
WHEN "100010011" => data <= conv_std_logic_vector(537,11);
WHEN "100010100" => data <= conv_std_logic_vector(536,11);
WHEN "100010101" => data <= conv_std_logic_vector(535,11);
WHEN "100010110" => data <= conv_std_logic_vector(534,11);
WHEN "100010111" => data <= conv_std_logic_vector(533,11);
WHEN "100011000" => data <= conv_std_logic_vector(532,11);
WHEN "100011001" => data <= conv_std_logic_vector(531,11);
WHEN "100011010" => data <= conv_std_logic_vector(530,11);
WHEN "100011011" => data <= conv_std_logic_vector(529,11);
WHEN "100011100" => data <= conv_std_logic_vector(528,11);
WHEN "100011101" => data <= conv_std_logic_vector(527,11);
WHEN "100011110" => data <= conv_std_logic_vector(526,11);
WHEN "100011111" => data <= conv_std_logic_vector(525,11);
WHEN "100100000" => data <= conv_std_logic_vector(524,11);
WHEN "100100001" => data <= conv_std_logic_vector(523,11);
WHEN "100100010" => data <= conv_std_logic_vector(522,11);
WHEN "100100011" => data <= conv_std_logic_vector(521,11);
WHEN "100100100" => data <= conv_std_logic_vector(520,11);
WHEN "100100101" => data <= conv_std_logic_vector(519,11);
WHEN "100100110" => data <= conv_std_logic_vector(518,11);
WHEN "100100111" => data <= conv_std_logic_vector(517,11);
WHEN "100101000" => data <= conv_std_logic_vector(516,11);
WHEN "100101001" => data <= conv_std_logic_vector(515,11);
WHEN "100101010" => data <= conv_std_logic_vector(514,11);
WHEN "100101011" => data <= conv_std_logic_vector(513,11);
WHEN "100101100" => data <= conv_std_logic_vector(512,11);
WHEN "100101101" => data <= conv_std_logic_vector(511,11);
WHEN "100101110" => data <= conv_std_logic_vector(510,11);
WHEN "100101111" => data <= conv_std_logic_vector(509,11);
WHEN "100110000" => data <= conv_std_logic_vector(508,11);
WHEN "100110001" => data <= conv_std_logic_vector(508,11);
WHEN "100110010" => data <= conv_std_logic_vector(507,11);
WHEN "100110011" => data <= conv_std_logic_vector(506,11);
WHEN "100110100" => data <= conv_std_logic_vector(505,11);
WHEN "100110101" => data <= conv_std_logic_vector(504,11);
WHEN "100110110" => data <= conv_std_logic_vector(503,11);
WHEN "100110111" => data <= conv_std_logic_vector(502,11);
WHEN "100111000" => data <= conv_std_logic_vector(501,11);
WHEN "100111001" => data <= conv_std_logic_vector(500,11);
WHEN "100111010" => data <= conv_std_logic_vector(499,11);
WHEN "100111011" => data <= conv_std_logic_vector(498,11);
WHEN "100111100" => data <= conv_std_logic_vector(497,11);
WHEN "100111101" => data <= conv_std_logic_vector(497,11);
WHEN "100111110" => data <= conv_std_logic_vector(496,11);
WHEN "100111111" => data <= conv_std_logic_vector(495,11);
WHEN "101000000" => data <= conv_std_logic_vector(494,11);
WHEN "101000001" => data <= conv_std_logic_vector(493,11);
WHEN "101000010" => data <= conv_std_logic_vector(492,11);
WHEN "101000011" => data <= conv_std_logic_vector(491,11);
WHEN "101000100" => data <= conv_std_logic_vector(490,11);
WHEN "101000101" => data <= conv_std_logic_vector(489,11);
WHEN "101000110" => data <= conv_std_logic_vector(489,11);
WHEN "101000111" => data <= conv_std_logic_vector(488,11);
WHEN "101001000" => data <= conv_std_logic_vector(487,11);
WHEN "101001001" => data <= conv_std_logic_vector(486,11);
WHEN "101001010" => data <= conv_std_logic_vector(485,11);
WHEN "101001011" => data <= conv_std_logic_vector(484,11);
WHEN "101001100" => data <= conv_std_logic_vector(483,11);
WHEN "101001101" => data <= conv_std_logic_vector(483,11);
WHEN "101001110" => data <= conv_std_logic_vector(482,11);
WHEN "101001111" => data <= conv_std_logic_vector(481,11);
WHEN "101010000" => data <= conv_std_logic_vector(480,11);
WHEN "101010001" => data <= conv_std_logic_vector(479,11);
WHEN "101010010" => data <= conv_std_logic_vector(478,11);
WHEN "101010011" => data <= conv_std_logic_vector(477,11);
WHEN "101010100" => data <= conv_std_logic_vector(477,11);
WHEN "101010101" => data <= conv_std_logic_vector(476,11);
WHEN "101010110" => data <= conv_std_logic_vector(475,11);
WHEN "101010111" => data <= conv_std_logic_vector(474,11);
WHEN "101011000" => data <= conv_std_logic_vector(473,11);
WHEN "101011001" => data <= conv_std_logic_vector(472,11);
WHEN "101011010" => data <= conv_std_logic_vector(472,11);
WHEN "101011011" => data <= conv_std_logic_vector(471,11);
WHEN "101011100" => data <= conv_std_logic_vector(470,11);
WHEN "101011101" => data <= conv_std_logic_vector(469,11);
WHEN "101011110" => data <= conv_std_logic_vector(468,11);
WHEN "101011111" => data <= conv_std_logic_vector(468,11);
WHEN "101100000" => data <= conv_std_logic_vector(467,11);
WHEN "101100001" => data <= conv_std_logic_vector(466,11);
WHEN "101100010" => data <= conv_std_logic_vector(465,11);
WHEN "101100011" => data <= conv_std_logic_vector(464,11);
WHEN "101100100" => data <= conv_std_logic_vector(464,11);
WHEN "101100101" => data <= conv_std_logic_vector(463,11);
WHEN "101100110" => data <= conv_std_logic_vector(462,11);
WHEN "101100111" => data <= conv_std_logic_vector(461,11);
WHEN "101101000" => data <= conv_std_logic_vector(460,11);
WHEN "101101001" => data <= conv_std_logic_vector(460,11);
WHEN "101101010" => data <= conv_std_logic_vector(459,11);
WHEN "101101011" => data <= conv_std_logic_vector(458,11);
WHEN "101101100" => data <= conv_std_logic_vector(457,11);
WHEN "101101101" => data <= conv_std_logic_vector(456,11);
WHEN "101101110" => data <= conv_std_logic_vector(456,11);
WHEN "101101111" => data <= conv_std_logic_vector(455,11);
WHEN "101110000" => data <= conv_std_logic_vector(454,11);
WHEN "101110001" => data <= conv_std_logic_vector(453,11);
WHEN "101110010" => data <= conv_std_logic_vector(453,11);
WHEN "101110011" => data <= conv_std_logic_vector(452,11);
WHEN "101110100" => data <= conv_std_logic_vector(451,11);
WHEN "101110101" => data <= conv_std_logic_vector(450,11);
WHEN "101110110" => data <= conv_std_logic_vector(449,11);
WHEN "101110111" => data <= conv_std_logic_vector(449,11);
WHEN "101111000" => data <= conv_std_logic_vector(448,11);
WHEN "101111001" => data <= conv_std_logic_vector(447,11);
WHEN "101111010" => data <= conv_std_logic_vector(446,11);
WHEN "101111011" => data <= conv_std_logic_vector(446,11);
WHEN "101111100" => data <= conv_std_logic_vector(445,11);
WHEN "101111101" => data <= conv_std_logic_vector(444,11);
WHEN "101111110" => data <= conv_std_logic_vector(443,11);
WHEN "101111111" => data <= conv_std_logic_vector(443,11);
WHEN "110000000" => data <= conv_std_logic_vector(442,11);
WHEN "110000001" => data <= conv_std_logic_vector(441,11);
WHEN "110000010" => data <= conv_std_logic_vector(440,11);
WHEN "110000011" => data <= conv_std_logic_vector(440,11);
WHEN "110000100" => data <= conv_std_logic_vector(439,11);
WHEN "110000101" => data <= conv_std_logic_vector(438,11);
WHEN "110000110" => data <= conv_std_logic_vector(438,11);
WHEN "110000111" => data <= conv_std_logic_vector(437,11);
WHEN "110001000" => data <= conv_std_logic_vector(436,11);
WHEN "110001001" => data <= conv_std_logic_vector(435,11);
WHEN "110001010" => data <= conv_std_logic_vector(435,11);
WHEN "110001011" => data <= conv_std_logic_vector(434,11);
WHEN "110001100" => data <= conv_std_logic_vector(433,11);
WHEN "110001101" => data <= conv_std_logic_vector(433,11);
WHEN "110001110" => data <= conv_std_logic_vector(432,11);
WHEN "110001111" => data <= conv_std_logic_vector(431,11);
WHEN "110010000" => data <= conv_std_logic_vector(430,11);
WHEN "110010001" => data <= conv_std_logic_vector(430,11);
WHEN "110010010" => data <= conv_std_logic_vector(429,11);
WHEN "110010011" => data <= conv_std_logic_vector(428,11);
WHEN "110010100" => data <= conv_std_logic_vector(428,11);
WHEN "110010101" => data <= conv_std_logic_vector(427,11);
WHEN "110010110" => data <= conv_std_logic_vector(426,11);
WHEN "110010111" => data <= conv_std_logic_vector(425,11);
WHEN "110011000" => data <= conv_std_logic_vector(425,11);
WHEN "110011001" => data <= conv_std_logic_vector(424,11);
WHEN "110011010" => data <= conv_std_logic_vector(423,11);
WHEN "110011011" => data <= conv_std_logic_vector(423,11);
WHEN "110011100" => data <= conv_std_logic_vector(422,11);
WHEN "110011101" => data <= conv_std_logic_vector(421,11);
WHEN "110011110" => data <= conv_std_logic_vector(421,11);
WHEN "110011111" => data <= conv_std_logic_vector(420,11);
WHEN "110100000" => data <= conv_std_logic_vector(419,11);
WHEN "110100001" => data <= conv_std_logic_vector(419,11);
WHEN "110100010" => data <= conv_std_logic_vector(418,11);
WHEN "110100011" => data <= conv_std_logic_vector(417,11);
WHEN "110100100" => data <= conv_std_logic_vector(417,11);
WHEN "110100101" => data <= conv_std_logic_vector(416,11);
WHEN "110100110" => data <= conv_std_logic_vector(415,11);
WHEN "110100111" => data <= conv_std_logic_vector(415,11);
WHEN "110101000" => data <= conv_std_logic_vector(414,11);
WHEN "110101001" => data <= conv_std_logic_vector(413,11);
WHEN "110101010" => data <= conv_std_logic_vector(413,11);
WHEN "110101011" => data <= conv_std_logic_vector(412,11);
WHEN "110101100" => data <= conv_std_logic_vector(411,11);
WHEN "110101101" => data <= conv_std_logic_vector(411,11);
WHEN "110101110" => data <= conv_std_logic_vector(410,11);
WHEN "110101111" => data <= conv_std_logic_vector(409,11);
WHEN "110110000" => data <= conv_std_logic_vector(409,11);
WHEN "110110001" => data <= conv_std_logic_vector(408,11);
WHEN "110110010" => data <= conv_std_logic_vector(407,11);
WHEN "110110011" => data <= conv_std_logic_vector(407,11);
WHEN "110110100" => data <= conv_std_logic_vector(406,11);
WHEN "110110101" => data <= conv_std_logic_vector(405,11);
WHEN "110110110" => data <= conv_std_logic_vector(405,11);
WHEN "110110111" => data <= conv_std_logic_vector(404,11);
WHEN "110111000" => data <= conv_std_logic_vector(404,11);
WHEN "110111001" => data <= conv_std_logic_vector(403,11);
WHEN "110111010" => data <= conv_std_logic_vector(402,11);
WHEN "110111011" => data <= conv_std_logic_vector(402,11);
WHEN "110111100" => data <= conv_std_logic_vector(401,11);
WHEN "110111101" => data <= conv_std_logic_vector(400,11);
WHEN "110111110" => data <= conv_std_logic_vector(400,11);
WHEN "110111111" => data <= conv_std_logic_vector(399,11);
WHEN "111000000" => data <= conv_std_logic_vector(399,11);
WHEN "111000001" => data <= conv_std_logic_vector(398,11);
WHEN "111000010" => data <= conv_std_logic_vector(397,11);
WHEN "111000011" => data <= conv_std_logic_vector(397,11);
WHEN "111000100" => data <= conv_std_logic_vector(396,11);
WHEN "111000101" => data <= conv_std_logic_vector(395,11);
WHEN "111000110" => data <= conv_std_logic_vector(395,11);
WHEN "111000111" => data <= conv_std_logic_vector(394,11);
WHEN "111001000" => data <= conv_std_logic_vector(394,11);
WHEN "111001001" => data <= conv_std_logic_vector(393,11);
WHEN "111001010" => data <= conv_std_logic_vector(392,11);
WHEN "111001011" => data <= conv_std_logic_vector(392,11);
WHEN "111001100" => data <= conv_std_logic_vector(391,11);
WHEN "111001101" => data <= conv_std_logic_vector(391,11);
WHEN "111001110" => data <= conv_std_logic_vector(390,11);
WHEN "111001111" => data <= conv_std_logic_vector(389,11);
WHEN "111010000" => data <= conv_std_logic_vector(389,11);
WHEN "111010001" => data <= conv_std_logic_vector(388,11);
WHEN "111010010" => data <= conv_std_logic_vector(388,11);
WHEN "111010011" => data <= conv_std_logic_vector(387,11);
WHEN "111010100" => data <= conv_std_logic_vector(386,11);
WHEN "111010101" => data <= conv_std_logic_vector(386,11);
WHEN "111010110" => data <= conv_std_logic_vector(385,11);
WHEN "111010111" => data <= conv_std_logic_vector(385,11);
WHEN "111011000" => data <= conv_std_logic_vector(384,11);
WHEN "111011001" => data <= conv_std_logic_vector(383,11);
WHEN "111011010" => data <= conv_std_logic_vector(383,11);
WHEN "111011011" => data <= conv_std_logic_vector(382,11);
WHEN "111011100" => data <= conv_std_logic_vector(382,11);
WHEN "111011101" => data <= conv_std_logic_vector(381,11);
WHEN "111011110" => data <= conv_std_logic_vector(381,11);
WHEN "111011111" => data <= conv_std_logic_vector(380,11);
WHEN "111100000" => data <= conv_std_logic_vector(379,11);
WHEN "111100001" => data <= conv_std_logic_vector(379,11);
WHEN "111100010" => data <= conv_std_logic_vector(378,11);
WHEN "111100011" => data <= conv_std_logic_vector(378,11);
WHEN "111100100" => data <= conv_std_logic_vector(377,11);
WHEN "111100101" => data <= conv_std_logic_vector(377,11);
WHEN "111100110" => data <= conv_std_logic_vector(376,11);
WHEN "111100111" => data <= conv_std_logic_vector(375,11);
WHEN "111101000" => data <= conv_std_logic_vector(375,11);
WHEN "111101001" => data <= conv_std_logic_vector(374,11);
WHEN "111101010" => data <= conv_std_logic_vector(374,11);
WHEN "111101011" => data <= conv_std_logic_vector(373,11);
WHEN "111101100" => data <= conv_std_logic_vector(373,11);
WHEN "111101101" => data <= conv_std_logic_vector(372,11);
WHEN "111101110" => data <= conv_std_logic_vector(372,11);
WHEN "111101111" => data <= conv_std_logic_vector(371,11);
WHEN "111110000" => data <= conv_std_logic_vector(370,11);
WHEN "111110001" => data <= conv_std_logic_vector(370,11);
WHEN "111110010" => data <= conv_std_logic_vector(369,11);
WHEN "111110011" => data <= conv_std_logic_vector(369,11);
WHEN "111110100" => data <= conv_std_logic_vector(368,11);
WHEN "111110101" => data <= conv_std_logic_vector(368,11);
WHEN "111110110" => data <= conv_std_logic_vector(367,11);
WHEN "111110111" => data <= conv_std_logic_vector(367,11);
WHEN "111111000" => data <= conv_std_logic_vector(366,11);
WHEN "111111001" => data <= conv_std_logic_vector(366,11);
WHEN "111111010" => data <= conv_std_logic_vector(365,11);
WHEN "111111011" => data <= conv_std_logic_vector(364,11);
WHEN "111111100" => data <= conv_std_logic_vector(364,11);
WHEN "111111101" => data <= conv_std_logic_vector(363,11);
WHEN "111111110" => data <= conv_std_logic_vector(363,11);
WHEN "111111111" => data <= conv_std_logic_vector(362,11);
WHEN others => data <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/fp_invsqr_lut1.vhd | 10 | 35784 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_INVSQR_LUT1.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse Root ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_invsqr_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END fp_invsqr_lut1;
ARCHITECTURE rtl OF fp_invsqr_lut1 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1023,11);
WHEN "000000001" => data <= conv_std_logic_vector(1020,11);
WHEN "000000010" => data <= conv_std_logic_vector(1017,11);
WHEN "000000011" => data <= conv_std_logic_vector(1014,11);
WHEN "000000100" => data <= conv_std_logic_vector(1011,11);
WHEN "000000101" => data <= conv_std_logic_vector(1008,11);
WHEN "000000110" => data <= conv_std_logic_vector(1005,11);
WHEN "000000111" => data <= conv_std_logic_vector(1002,11);
WHEN "000001000" => data <= conv_std_logic_vector(999,11);
WHEN "000001001" => data <= conv_std_logic_vector(996,11);
WHEN "000001010" => data <= conv_std_logic_vector(993,11);
WHEN "000001011" => data <= conv_std_logic_vector(990,11);
WHEN "000001100" => data <= conv_std_logic_vector(988,11);
WHEN "000001101" => data <= conv_std_logic_vector(985,11);
WHEN "000001110" => data <= conv_std_logic_vector(982,11);
WHEN "000001111" => data <= conv_std_logic_vector(979,11);
WHEN "000010000" => data <= conv_std_logic_vector(976,11);
WHEN "000010001" => data <= conv_std_logic_vector(974,11);
WHEN "000010010" => data <= conv_std_logic_vector(971,11);
WHEN "000010011" => data <= conv_std_logic_vector(968,11);
WHEN "000010100" => data <= conv_std_logic_vector(965,11);
WHEN "000010101" => data <= conv_std_logic_vector(963,11);
WHEN "000010110" => data <= conv_std_logic_vector(960,11);
WHEN "000010111" => data <= conv_std_logic_vector(957,11);
WHEN "000011000" => data <= conv_std_logic_vector(955,11);
WHEN "000011001" => data <= conv_std_logic_vector(952,11);
WHEN "000011010" => data <= conv_std_logic_vector(949,11);
WHEN "000011011" => data <= conv_std_logic_vector(947,11);
WHEN "000011100" => data <= conv_std_logic_vector(944,11);
WHEN "000011101" => data <= conv_std_logic_vector(941,11);
WHEN "000011110" => data <= conv_std_logic_vector(939,11);
WHEN "000011111" => data <= conv_std_logic_vector(936,11);
WHEN "000100000" => data <= conv_std_logic_vector(934,11);
WHEN "000100001" => data <= conv_std_logic_vector(931,11);
WHEN "000100010" => data <= conv_std_logic_vector(929,11);
WHEN "000100011" => data <= conv_std_logic_vector(926,11);
WHEN "000100100" => data <= conv_std_logic_vector(924,11);
WHEN "000100101" => data <= conv_std_logic_vector(921,11);
WHEN "000100110" => data <= conv_std_logic_vector(918,11);
WHEN "000100111" => data <= conv_std_logic_vector(916,11);
WHEN "000101000" => data <= conv_std_logic_vector(913,11);
WHEN "000101001" => data <= conv_std_logic_vector(911,11);
WHEN "000101010" => data <= conv_std_logic_vector(909,11);
WHEN "000101011" => data <= conv_std_logic_vector(906,11);
WHEN "000101100" => data <= conv_std_logic_vector(904,11);
WHEN "000101101" => data <= conv_std_logic_vector(901,11);
WHEN "000101110" => data <= conv_std_logic_vector(899,11);
WHEN "000101111" => data <= conv_std_logic_vector(896,11);
WHEN "000110000" => data <= conv_std_logic_vector(894,11);
WHEN "000110001" => data <= conv_std_logic_vector(892,11);
WHEN "000110010" => data <= conv_std_logic_vector(889,11);
WHEN "000110011" => data <= conv_std_logic_vector(887,11);
WHEN "000110100" => data <= conv_std_logic_vector(885,11);
WHEN "000110101" => data <= conv_std_logic_vector(882,11);
WHEN "000110110" => data <= conv_std_logic_vector(880,11);
WHEN "000110111" => data <= conv_std_logic_vector(878,11);
WHEN "000111000" => data <= conv_std_logic_vector(875,11);
WHEN "000111001" => data <= conv_std_logic_vector(873,11);
WHEN "000111010" => data <= conv_std_logic_vector(871,11);
WHEN "000111011" => data <= conv_std_logic_vector(868,11);
WHEN "000111100" => data <= conv_std_logic_vector(866,11);
WHEN "000111101" => data <= conv_std_logic_vector(864,11);
WHEN "000111110" => data <= conv_std_logic_vector(862,11);
WHEN "000111111" => data <= conv_std_logic_vector(859,11);
WHEN "001000000" => data <= conv_std_logic_vector(857,11);
WHEN "001000001" => data <= conv_std_logic_vector(855,11);
WHEN "001000010" => data <= conv_std_logic_vector(853,11);
WHEN "001000011" => data <= conv_std_logic_vector(850,11);
WHEN "001000100" => data <= conv_std_logic_vector(848,11);
WHEN "001000101" => data <= conv_std_logic_vector(846,11);
WHEN "001000110" => data <= conv_std_logic_vector(844,11);
WHEN "001000111" => data <= conv_std_logic_vector(842,11);
WHEN "001001000" => data <= conv_std_logic_vector(840,11);
WHEN "001001001" => data <= conv_std_logic_vector(837,11);
WHEN "001001010" => data <= conv_std_logic_vector(835,11);
WHEN "001001011" => data <= conv_std_logic_vector(833,11);
WHEN "001001100" => data <= conv_std_logic_vector(831,11);
WHEN "001001101" => data <= conv_std_logic_vector(829,11);
WHEN "001001110" => data <= conv_std_logic_vector(827,11);
WHEN "001001111" => data <= conv_std_logic_vector(825,11);
WHEN "001010000" => data <= conv_std_logic_vector(823,11);
WHEN "001010001" => data <= conv_std_logic_vector(820,11);
WHEN "001010010" => data <= conv_std_logic_vector(818,11);
WHEN "001010011" => data <= conv_std_logic_vector(816,11);
WHEN "001010100" => data <= conv_std_logic_vector(814,11);
WHEN "001010101" => data <= conv_std_logic_vector(812,11);
WHEN "001010110" => data <= conv_std_logic_vector(810,11);
WHEN "001010111" => data <= conv_std_logic_vector(808,11);
WHEN "001011000" => data <= conv_std_logic_vector(806,11);
WHEN "001011001" => data <= conv_std_logic_vector(804,11);
WHEN "001011010" => data <= conv_std_logic_vector(802,11);
WHEN "001011011" => data <= conv_std_logic_vector(800,11);
WHEN "001011100" => data <= conv_std_logic_vector(798,11);
WHEN "001011101" => data <= conv_std_logic_vector(796,11);
WHEN "001011110" => data <= conv_std_logic_vector(794,11);
WHEN "001011111" => data <= conv_std_logic_vector(792,11);
WHEN "001100000" => data <= conv_std_logic_vector(790,11);
WHEN "001100001" => data <= conv_std_logic_vector(788,11);
WHEN "001100010" => data <= conv_std_logic_vector(786,11);
WHEN "001100011" => data <= conv_std_logic_vector(785,11);
WHEN "001100100" => data <= conv_std_logic_vector(783,11);
WHEN "001100101" => data <= conv_std_logic_vector(781,11);
WHEN "001100110" => data <= conv_std_logic_vector(779,11);
WHEN "001100111" => data <= conv_std_logic_vector(777,11);
WHEN "001101000" => data <= conv_std_logic_vector(775,11);
WHEN "001101001" => data <= conv_std_logic_vector(773,11);
WHEN "001101010" => data <= conv_std_logic_vector(771,11);
WHEN "001101011" => data <= conv_std_logic_vector(769,11);
WHEN "001101100" => data <= conv_std_logic_vector(768,11);
WHEN "001101101" => data <= conv_std_logic_vector(766,11);
WHEN "001101110" => data <= conv_std_logic_vector(764,11);
WHEN "001101111" => data <= conv_std_logic_vector(762,11);
WHEN "001110000" => data <= conv_std_logic_vector(760,11);
WHEN "001110001" => data <= conv_std_logic_vector(758,11);
WHEN "001110010" => data <= conv_std_logic_vector(757,11);
WHEN "001110011" => data <= conv_std_logic_vector(755,11);
WHEN "001110100" => data <= conv_std_logic_vector(753,11);
WHEN "001110101" => data <= conv_std_logic_vector(751,11);
WHEN "001110110" => data <= conv_std_logic_vector(749,11);
WHEN "001110111" => data <= conv_std_logic_vector(748,11);
WHEN "001111000" => data <= conv_std_logic_vector(746,11);
WHEN "001111001" => data <= conv_std_logic_vector(744,11);
WHEN "001111010" => data <= conv_std_logic_vector(742,11);
WHEN "001111011" => data <= conv_std_logic_vector(741,11);
WHEN "001111100" => data <= conv_std_logic_vector(739,11);
WHEN "001111101" => data <= conv_std_logic_vector(737,11);
WHEN "001111110" => data <= conv_std_logic_vector(735,11);
WHEN "001111111" => data <= conv_std_logic_vector(734,11);
WHEN "010000000" => data <= conv_std_logic_vector(732,11);
WHEN "010000001" => data <= conv_std_logic_vector(730,11);
WHEN "010000010" => data <= conv_std_logic_vector(728,11);
WHEN "010000011" => data <= conv_std_logic_vector(727,11);
WHEN "010000100" => data <= conv_std_logic_vector(725,11);
WHEN "010000101" => data <= conv_std_logic_vector(723,11);
WHEN "010000110" => data <= conv_std_logic_vector(722,11);
WHEN "010000111" => data <= conv_std_logic_vector(720,11);
WHEN "010001000" => data <= conv_std_logic_vector(718,11);
WHEN "010001001" => data <= conv_std_logic_vector(717,11);
WHEN "010001010" => data <= conv_std_logic_vector(715,11);
WHEN "010001011" => data <= conv_std_logic_vector(713,11);
WHEN "010001100" => data <= conv_std_logic_vector(712,11);
WHEN "010001101" => data <= conv_std_logic_vector(710,11);
WHEN "010001110" => data <= conv_std_logic_vector(709,11);
WHEN "010001111" => data <= conv_std_logic_vector(707,11);
WHEN "010010000" => data <= conv_std_logic_vector(705,11);
WHEN "010010001" => data <= conv_std_logic_vector(704,11);
WHEN "010010010" => data <= conv_std_logic_vector(702,11);
WHEN "010010011" => data <= conv_std_logic_vector(700,11);
WHEN "010010100" => data <= conv_std_logic_vector(699,11);
WHEN "010010101" => data <= conv_std_logic_vector(697,11);
WHEN "010010110" => data <= conv_std_logic_vector(696,11);
WHEN "010010111" => data <= conv_std_logic_vector(694,11);
WHEN "010011000" => data <= conv_std_logic_vector(693,11);
WHEN "010011001" => data <= conv_std_logic_vector(691,11);
WHEN "010011010" => data <= conv_std_logic_vector(689,11);
WHEN "010011011" => data <= conv_std_logic_vector(688,11);
WHEN "010011100" => data <= conv_std_logic_vector(686,11);
WHEN "010011101" => data <= conv_std_logic_vector(685,11);
WHEN "010011110" => data <= conv_std_logic_vector(683,11);
WHEN "010011111" => data <= conv_std_logic_vector(682,11);
WHEN "010100000" => data <= conv_std_logic_vector(680,11);
WHEN "010100001" => data <= conv_std_logic_vector(679,11);
WHEN "010100010" => data <= conv_std_logic_vector(677,11);
WHEN "010100011" => data <= conv_std_logic_vector(676,11);
WHEN "010100100" => data <= conv_std_logic_vector(674,11);
WHEN "010100101" => data <= conv_std_logic_vector(673,11);
WHEN "010100110" => data <= conv_std_logic_vector(671,11);
WHEN "010100111" => data <= conv_std_logic_vector(670,11);
WHEN "010101000" => data <= conv_std_logic_vector(668,11);
WHEN "010101001" => data <= conv_std_logic_vector(667,11);
WHEN "010101010" => data <= conv_std_logic_vector(665,11);
WHEN "010101011" => data <= conv_std_logic_vector(664,11);
WHEN "010101100" => data <= conv_std_logic_vector(662,11);
WHEN "010101101" => data <= conv_std_logic_vector(661,11);
WHEN "010101110" => data <= conv_std_logic_vector(660,11);
WHEN "010101111" => data <= conv_std_logic_vector(658,11);
WHEN "010110000" => data <= conv_std_logic_vector(657,11);
WHEN "010110001" => data <= conv_std_logic_vector(655,11);
WHEN "010110010" => data <= conv_std_logic_vector(654,11);
WHEN "010110011" => data <= conv_std_logic_vector(652,11);
WHEN "010110100" => data <= conv_std_logic_vector(651,11);
WHEN "010110101" => data <= conv_std_logic_vector(650,11);
WHEN "010110110" => data <= conv_std_logic_vector(648,11);
WHEN "010110111" => data <= conv_std_logic_vector(647,11);
WHEN "010111000" => data <= conv_std_logic_vector(645,11);
WHEN "010111001" => data <= conv_std_logic_vector(644,11);
WHEN "010111010" => data <= conv_std_logic_vector(643,11);
WHEN "010111011" => data <= conv_std_logic_vector(641,11);
WHEN "010111100" => data <= conv_std_logic_vector(640,11);
WHEN "010111101" => data <= conv_std_logic_vector(639,11);
WHEN "010111110" => data <= conv_std_logic_vector(637,11);
WHEN "010111111" => data <= conv_std_logic_vector(636,11);
WHEN "011000000" => data <= conv_std_logic_vector(634,11);
WHEN "011000001" => data <= conv_std_logic_vector(633,11);
WHEN "011000010" => data <= conv_std_logic_vector(632,11);
WHEN "011000011" => data <= conv_std_logic_vector(630,11);
WHEN "011000100" => data <= conv_std_logic_vector(629,11);
WHEN "011000101" => data <= conv_std_logic_vector(628,11);
WHEN "011000110" => data <= conv_std_logic_vector(626,11);
WHEN "011000111" => data <= conv_std_logic_vector(625,11);
WHEN "011001000" => data <= conv_std_logic_vector(624,11);
WHEN "011001001" => data <= conv_std_logic_vector(622,11);
WHEN "011001010" => data <= conv_std_logic_vector(621,11);
WHEN "011001011" => data <= conv_std_logic_vector(620,11);
WHEN "011001100" => data <= conv_std_logic_vector(619,11);
WHEN "011001101" => data <= conv_std_logic_vector(617,11);
WHEN "011001110" => data <= conv_std_logic_vector(616,11);
WHEN "011001111" => data <= conv_std_logic_vector(615,11);
WHEN "011010000" => data <= conv_std_logic_vector(613,11);
WHEN "011010001" => data <= conv_std_logic_vector(612,11);
WHEN "011010010" => data <= conv_std_logic_vector(611,11);
WHEN "011010011" => data <= conv_std_logic_vector(610,11);
WHEN "011010100" => data <= conv_std_logic_vector(608,11);
WHEN "011010101" => data <= conv_std_logic_vector(607,11);
WHEN "011010110" => data <= conv_std_logic_vector(606,11);
WHEN "011010111" => data <= conv_std_logic_vector(605,11);
WHEN "011011000" => data <= conv_std_logic_vector(603,11);
WHEN "011011001" => data <= conv_std_logic_vector(602,11);
WHEN "011011010" => data <= conv_std_logic_vector(601,11);
WHEN "011011011" => data <= conv_std_logic_vector(600,11);
WHEN "011011100" => data <= conv_std_logic_vector(598,11);
WHEN "011011101" => data <= conv_std_logic_vector(597,11);
WHEN "011011110" => data <= conv_std_logic_vector(596,11);
WHEN "011011111" => data <= conv_std_logic_vector(595,11);
WHEN "011100000" => data <= conv_std_logic_vector(594,11);
WHEN "011100001" => data <= conv_std_logic_vector(592,11);
WHEN "011100010" => data <= conv_std_logic_vector(591,11);
WHEN "011100011" => data <= conv_std_logic_vector(590,11);
WHEN "011100100" => data <= conv_std_logic_vector(589,11);
WHEN "011100101" => data <= conv_std_logic_vector(588,11);
WHEN "011100110" => data <= conv_std_logic_vector(586,11);
WHEN "011100111" => data <= conv_std_logic_vector(585,11);
WHEN "011101000" => data <= conv_std_logic_vector(584,11);
WHEN "011101001" => data <= conv_std_logic_vector(583,11);
WHEN "011101010" => data <= conv_std_logic_vector(582,11);
WHEN "011101011" => data <= conv_std_logic_vector(580,11);
WHEN "011101100" => data <= conv_std_logic_vector(579,11);
WHEN "011101101" => data <= conv_std_logic_vector(578,11);
WHEN "011101110" => data <= conv_std_logic_vector(577,11);
WHEN "011101111" => data <= conv_std_logic_vector(576,11);
WHEN "011110000" => data <= conv_std_logic_vector(575,11);
WHEN "011110001" => data <= conv_std_logic_vector(574,11);
WHEN "011110010" => data <= conv_std_logic_vector(572,11);
WHEN "011110011" => data <= conv_std_logic_vector(571,11);
WHEN "011110100" => data <= conv_std_logic_vector(570,11);
WHEN "011110101" => data <= conv_std_logic_vector(569,11);
WHEN "011110110" => data <= conv_std_logic_vector(568,11);
WHEN "011110111" => data <= conv_std_logic_vector(567,11);
WHEN "011111000" => data <= conv_std_logic_vector(566,11);
WHEN "011111001" => data <= conv_std_logic_vector(565,11);
WHEN "011111010" => data <= conv_std_logic_vector(563,11);
WHEN "011111011" => data <= conv_std_logic_vector(562,11);
WHEN "011111100" => data <= conv_std_logic_vector(561,11);
WHEN "011111101" => data <= conv_std_logic_vector(560,11);
WHEN "011111110" => data <= conv_std_logic_vector(559,11);
WHEN "011111111" => data <= conv_std_logic_vector(558,11);
WHEN "100000000" => data <= conv_std_logic_vector(557,11);
WHEN "100000001" => data <= conv_std_logic_vector(556,11);
WHEN "100000010" => data <= conv_std_logic_vector(555,11);
WHEN "100000011" => data <= conv_std_logic_vector(554,11);
WHEN "100000100" => data <= conv_std_logic_vector(553,11);
WHEN "100000101" => data <= conv_std_logic_vector(551,11);
WHEN "100000110" => data <= conv_std_logic_vector(550,11);
WHEN "100000111" => data <= conv_std_logic_vector(549,11);
WHEN "100001000" => data <= conv_std_logic_vector(548,11);
WHEN "100001001" => data <= conv_std_logic_vector(547,11);
WHEN "100001010" => data <= conv_std_logic_vector(546,11);
WHEN "100001011" => data <= conv_std_logic_vector(545,11);
WHEN "100001100" => data <= conv_std_logic_vector(544,11);
WHEN "100001101" => data <= conv_std_logic_vector(543,11);
WHEN "100001110" => data <= conv_std_logic_vector(542,11);
WHEN "100001111" => data <= conv_std_logic_vector(541,11);
WHEN "100010000" => data <= conv_std_logic_vector(540,11);
WHEN "100010001" => data <= conv_std_logic_vector(539,11);
WHEN "100010010" => data <= conv_std_logic_vector(538,11);
WHEN "100010011" => data <= conv_std_logic_vector(537,11);
WHEN "100010100" => data <= conv_std_logic_vector(536,11);
WHEN "100010101" => data <= conv_std_logic_vector(535,11);
WHEN "100010110" => data <= conv_std_logic_vector(534,11);
WHEN "100010111" => data <= conv_std_logic_vector(533,11);
WHEN "100011000" => data <= conv_std_logic_vector(532,11);
WHEN "100011001" => data <= conv_std_logic_vector(531,11);
WHEN "100011010" => data <= conv_std_logic_vector(530,11);
WHEN "100011011" => data <= conv_std_logic_vector(529,11);
WHEN "100011100" => data <= conv_std_logic_vector(528,11);
WHEN "100011101" => data <= conv_std_logic_vector(527,11);
WHEN "100011110" => data <= conv_std_logic_vector(526,11);
WHEN "100011111" => data <= conv_std_logic_vector(525,11);
WHEN "100100000" => data <= conv_std_logic_vector(524,11);
WHEN "100100001" => data <= conv_std_logic_vector(523,11);
WHEN "100100010" => data <= conv_std_logic_vector(522,11);
WHEN "100100011" => data <= conv_std_logic_vector(521,11);
WHEN "100100100" => data <= conv_std_logic_vector(520,11);
WHEN "100100101" => data <= conv_std_logic_vector(519,11);
WHEN "100100110" => data <= conv_std_logic_vector(518,11);
WHEN "100100111" => data <= conv_std_logic_vector(517,11);
WHEN "100101000" => data <= conv_std_logic_vector(516,11);
WHEN "100101001" => data <= conv_std_logic_vector(515,11);
WHEN "100101010" => data <= conv_std_logic_vector(514,11);
WHEN "100101011" => data <= conv_std_logic_vector(513,11);
WHEN "100101100" => data <= conv_std_logic_vector(512,11);
WHEN "100101101" => data <= conv_std_logic_vector(511,11);
WHEN "100101110" => data <= conv_std_logic_vector(510,11);
WHEN "100101111" => data <= conv_std_logic_vector(509,11);
WHEN "100110000" => data <= conv_std_logic_vector(508,11);
WHEN "100110001" => data <= conv_std_logic_vector(508,11);
WHEN "100110010" => data <= conv_std_logic_vector(507,11);
WHEN "100110011" => data <= conv_std_logic_vector(506,11);
WHEN "100110100" => data <= conv_std_logic_vector(505,11);
WHEN "100110101" => data <= conv_std_logic_vector(504,11);
WHEN "100110110" => data <= conv_std_logic_vector(503,11);
WHEN "100110111" => data <= conv_std_logic_vector(502,11);
WHEN "100111000" => data <= conv_std_logic_vector(501,11);
WHEN "100111001" => data <= conv_std_logic_vector(500,11);
WHEN "100111010" => data <= conv_std_logic_vector(499,11);
WHEN "100111011" => data <= conv_std_logic_vector(498,11);
WHEN "100111100" => data <= conv_std_logic_vector(497,11);
WHEN "100111101" => data <= conv_std_logic_vector(497,11);
WHEN "100111110" => data <= conv_std_logic_vector(496,11);
WHEN "100111111" => data <= conv_std_logic_vector(495,11);
WHEN "101000000" => data <= conv_std_logic_vector(494,11);
WHEN "101000001" => data <= conv_std_logic_vector(493,11);
WHEN "101000010" => data <= conv_std_logic_vector(492,11);
WHEN "101000011" => data <= conv_std_logic_vector(491,11);
WHEN "101000100" => data <= conv_std_logic_vector(490,11);
WHEN "101000101" => data <= conv_std_logic_vector(489,11);
WHEN "101000110" => data <= conv_std_logic_vector(489,11);
WHEN "101000111" => data <= conv_std_logic_vector(488,11);
WHEN "101001000" => data <= conv_std_logic_vector(487,11);
WHEN "101001001" => data <= conv_std_logic_vector(486,11);
WHEN "101001010" => data <= conv_std_logic_vector(485,11);
WHEN "101001011" => data <= conv_std_logic_vector(484,11);
WHEN "101001100" => data <= conv_std_logic_vector(483,11);
WHEN "101001101" => data <= conv_std_logic_vector(483,11);
WHEN "101001110" => data <= conv_std_logic_vector(482,11);
WHEN "101001111" => data <= conv_std_logic_vector(481,11);
WHEN "101010000" => data <= conv_std_logic_vector(480,11);
WHEN "101010001" => data <= conv_std_logic_vector(479,11);
WHEN "101010010" => data <= conv_std_logic_vector(478,11);
WHEN "101010011" => data <= conv_std_logic_vector(477,11);
WHEN "101010100" => data <= conv_std_logic_vector(477,11);
WHEN "101010101" => data <= conv_std_logic_vector(476,11);
WHEN "101010110" => data <= conv_std_logic_vector(475,11);
WHEN "101010111" => data <= conv_std_logic_vector(474,11);
WHEN "101011000" => data <= conv_std_logic_vector(473,11);
WHEN "101011001" => data <= conv_std_logic_vector(472,11);
WHEN "101011010" => data <= conv_std_logic_vector(472,11);
WHEN "101011011" => data <= conv_std_logic_vector(471,11);
WHEN "101011100" => data <= conv_std_logic_vector(470,11);
WHEN "101011101" => data <= conv_std_logic_vector(469,11);
WHEN "101011110" => data <= conv_std_logic_vector(468,11);
WHEN "101011111" => data <= conv_std_logic_vector(468,11);
WHEN "101100000" => data <= conv_std_logic_vector(467,11);
WHEN "101100001" => data <= conv_std_logic_vector(466,11);
WHEN "101100010" => data <= conv_std_logic_vector(465,11);
WHEN "101100011" => data <= conv_std_logic_vector(464,11);
WHEN "101100100" => data <= conv_std_logic_vector(464,11);
WHEN "101100101" => data <= conv_std_logic_vector(463,11);
WHEN "101100110" => data <= conv_std_logic_vector(462,11);
WHEN "101100111" => data <= conv_std_logic_vector(461,11);
WHEN "101101000" => data <= conv_std_logic_vector(460,11);
WHEN "101101001" => data <= conv_std_logic_vector(460,11);
WHEN "101101010" => data <= conv_std_logic_vector(459,11);
WHEN "101101011" => data <= conv_std_logic_vector(458,11);
WHEN "101101100" => data <= conv_std_logic_vector(457,11);
WHEN "101101101" => data <= conv_std_logic_vector(456,11);
WHEN "101101110" => data <= conv_std_logic_vector(456,11);
WHEN "101101111" => data <= conv_std_logic_vector(455,11);
WHEN "101110000" => data <= conv_std_logic_vector(454,11);
WHEN "101110001" => data <= conv_std_logic_vector(453,11);
WHEN "101110010" => data <= conv_std_logic_vector(453,11);
WHEN "101110011" => data <= conv_std_logic_vector(452,11);
WHEN "101110100" => data <= conv_std_logic_vector(451,11);
WHEN "101110101" => data <= conv_std_logic_vector(450,11);
WHEN "101110110" => data <= conv_std_logic_vector(449,11);
WHEN "101110111" => data <= conv_std_logic_vector(449,11);
WHEN "101111000" => data <= conv_std_logic_vector(448,11);
WHEN "101111001" => data <= conv_std_logic_vector(447,11);
WHEN "101111010" => data <= conv_std_logic_vector(446,11);
WHEN "101111011" => data <= conv_std_logic_vector(446,11);
WHEN "101111100" => data <= conv_std_logic_vector(445,11);
WHEN "101111101" => data <= conv_std_logic_vector(444,11);
WHEN "101111110" => data <= conv_std_logic_vector(443,11);
WHEN "101111111" => data <= conv_std_logic_vector(443,11);
WHEN "110000000" => data <= conv_std_logic_vector(442,11);
WHEN "110000001" => data <= conv_std_logic_vector(441,11);
WHEN "110000010" => data <= conv_std_logic_vector(440,11);
WHEN "110000011" => data <= conv_std_logic_vector(440,11);
WHEN "110000100" => data <= conv_std_logic_vector(439,11);
WHEN "110000101" => data <= conv_std_logic_vector(438,11);
WHEN "110000110" => data <= conv_std_logic_vector(438,11);
WHEN "110000111" => data <= conv_std_logic_vector(437,11);
WHEN "110001000" => data <= conv_std_logic_vector(436,11);
WHEN "110001001" => data <= conv_std_logic_vector(435,11);
WHEN "110001010" => data <= conv_std_logic_vector(435,11);
WHEN "110001011" => data <= conv_std_logic_vector(434,11);
WHEN "110001100" => data <= conv_std_logic_vector(433,11);
WHEN "110001101" => data <= conv_std_logic_vector(433,11);
WHEN "110001110" => data <= conv_std_logic_vector(432,11);
WHEN "110001111" => data <= conv_std_logic_vector(431,11);
WHEN "110010000" => data <= conv_std_logic_vector(430,11);
WHEN "110010001" => data <= conv_std_logic_vector(430,11);
WHEN "110010010" => data <= conv_std_logic_vector(429,11);
WHEN "110010011" => data <= conv_std_logic_vector(428,11);
WHEN "110010100" => data <= conv_std_logic_vector(428,11);
WHEN "110010101" => data <= conv_std_logic_vector(427,11);
WHEN "110010110" => data <= conv_std_logic_vector(426,11);
WHEN "110010111" => data <= conv_std_logic_vector(425,11);
WHEN "110011000" => data <= conv_std_logic_vector(425,11);
WHEN "110011001" => data <= conv_std_logic_vector(424,11);
WHEN "110011010" => data <= conv_std_logic_vector(423,11);
WHEN "110011011" => data <= conv_std_logic_vector(423,11);
WHEN "110011100" => data <= conv_std_logic_vector(422,11);
WHEN "110011101" => data <= conv_std_logic_vector(421,11);
WHEN "110011110" => data <= conv_std_logic_vector(421,11);
WHEN "110011111" => data <= conv_std_logic_vector(420,11);
WHEN "110100000" => data <= conv_std_logic_vector(419,11);
WHEN "110100001" => data <= conv_std_logic_vector(419,11);
WHEN "110100010" => data <= conv_std_logic_vector(418,11);
WHEN "110100011" => data <= conv_std_logic_vector(417,11);
WHEN "110100100" => data <= conv_std_logic_vector(417,11);
WHEN "110100101" => data <= conv_std_logic_vector(416,11);
WHEN "110100110" => data <= conv_std_logic_vector(415,11);
WHEN "110100111" => data <= conv_std_logic_vector(415,11);
WHEN "110101000" => data <= conv_std_logic_vector(414,11);
WHEN "110101001" => data <= conv_std_logic_vector(413,11);
WHEN "110101010" => data <= conv_std_logic_vector(413,11);
WHEN "110101011" => data <= conv_std_logic_vector(412,11);
WHEN "110101100" => data <= conv_std_logic_vector(411,11);
WHEN "110101101" => data <= conv_std_logic_vector(411,11);
WHEN "110101110" => data <= conv_std_logic_vector(410,11);
WHEN "110101111" => data <= conv_std_logic_vector(409,11);
WHEN "110110000" => data <= conv_std_logic_vector(409,11);
WHEN "110110001" => data <= conv_std_logic_vector(408,11);
WHEN "110110010" => data <= conv_std_logic_vector(407,11);
WHEN "110110011" => data <= conv_std_logic_vector(407,11);
WHEN "110110100" => data <= conv_std_logic_vector(406,11);
WHEN "110110101" => data <= conv_std_logic_vector(405,11);
WHEN "110110110" => data <= conv_std_logic_vector(405,11);
WHEN "110110111" => data <= conv_std_logic_vector(404,11);
WHEN "110111000" => data <= conv_std_logic_vector(404,11);
WHEN "110111001" => data <= conv_std_logic_vector(403,11);
WHEN "110111010" => data <= conv_std_logic_vector(402,11);
WHEN "110111011" => data <= conv_std_logic_vector(402,11);
WHEN "110111100" => data <= conv_std_logic_vector(401,11);
WHEN "110111101" => data <= conv_std_logic_vector(400,11);
WHEN "110111110" => data <= conv_std_logic_vector(400,11);
WHEN "110111111" => data <= conv_std_logic_vector(399,11);
WHEN "111000000" => data <= conv_std_logic_vector(399,11);
WHEN "111000001" => data <= conv_std_logic_vector(398,11);
WHEN "111000010" => data <= conv_std_logic_vector(397,11);
WHEN "111000011" => data <= conv_std_logic_vector(397,11);
WHEN "111000100" => data <= conv_std_logic_vector(396,11);
WHEN "111000101" => data <= conv_std_logic_vector(395,11);
WHEN "111000110" => data <= conv_std_logic_vector(395,11);
WHEN "111000111" => data <= conv_std_logic_vector(394,11);
WHEN "111001000" => data <= conv_std_logic_vector(394,11);
WHEN "111001001" => data <= conv_std_logic_vector(393,11);
WHEN "111001010" => data <= conv_std_logic_vector(392,11);
WHEN "111001011" => data <= conv_std_logic_vector(392,11);
WHEN "111001100" => data <= conv_std_logic_vector(391,11);
WHEN "111001101" => data <= conv_std_logic_vector(391,11);
WHEN "111001110" => data <= conv_std_logic_vector(390,11);
WHEN "111001111" => data <= conv_std_logic_vector(389,11);
WHEN "111010000" => data <= conv_std_logic_vector(389,11);
WHEN "111010001" => data <= conv_std_logic_vector(388,11);
WHEN "111010010" => data <= conv_std_logic_vector(388,11);
WHEN "111010011" => data <= conv_std_logic_vector(387,11);
WHEN "111010100" => data <= conv_std_logic_vector(386,11);
WHEN "111010101" => data <= conv_std_logic_vector(386,11);
WHEN "111010110" => data <= conv_std_logic_vector(385,11);
WHEN "111010111" => data <= conv_std_logic_vector(385,11);
WHEN "111011000" => data <= conv_std_logic_vector(384,11);
WHEN "111011001" => data <= conv_std_logic_vector(383,11);
WHEN "111011010" => data <= conv_std_logic_vector(383,11);
WHEN "111011011" => data <= conv_std_logic_vector(382,11);
WHEN "111011100" => data <= conv_std_logic_vector(382,11);
WHEN "111011101" => data <= conv_std_logic_vector(381,11);
WHEN "111011110" => data <= conv_std_logic_vector(381,11);
WHEN "111011111" => data <= conv_std_logic_vector(380,11);
WHEN "111100000" => data <= conv_std_logic_vector(379,11);
WHEN "111100001" => data <= conv_std_logic_vector(379,11);
WHEN "111100010" => data <= conv_std_logic_vector(378,11);
WHEN "111100011" => data <= conv_std_logic_vector(378,11);
WHEN "111100100" => data <= conv_std_logic_vector(377,11);
WHEN "111100101" => data <= conv_std_logic_vector(377,11);
WHEN "111100110" => data <= conv_std_logic_vector(376,11);
WHEN "111100111" => data <= conv_std_logic_vector(375,11);
WHEN "111101000" => data <= conv_std_logic_vector(375,11);
WHEN "111101001" => data <= conv_std_logic_vector(374,11);
WHEN "111101010" => data <= conv_std_logic_vector(374,11);
WHEN "111101011" => data <= conv_std_logic_vector(373,11);
WHEN "111101100" => data <= conv_std_logic_vector(373,11);
WHEN "111101101" => data <= conv_std_logic_vector(372,11);
WHEN "111101110" => data <= conv_std_logic_vector(372,11);
WHEN "111101111" => data <= conv_std_logic_vector(371,11);
WHEN "111110000" => data <= conv_std_logic_vector(370,11);
WHEN "111110001" => data <= conv_std_logic_vector(370,11);
WHEN "111110010" => data <= conv_std_logic_vector(369,11);
WHEN "111110011" => data <= conv_std_logic_vector(369,11);
WHEN "111110100" => data <= conv_std_logic_vector(368,11);
WHEN "111110101" => data <= conv_std_logic_vector(368,11);
WHEN "111110110" => data <= conv_std_logic_vector(367,11);
WHEN "111110111" => data <= conv_std_logic_vector(367,11);
WHEN "111111000" => data <= conv_std_logic_vector(366,11);
WHEN "111111001" => data <= conv_std_logic_vector(366,11);
WHEN "111111010" => data <= conv_std_logic_vector(365,11);
WHEN "111111011" => data <= conv_std_logic_vector(364,11);
WHEN "111111100" => data <= conv_std_logic_vector(364,11);
WHEN "111111101" => data <= conv_std_logic_vector(363,11);
WHEN "111111110" => data <= conv_std_logic_vector(363,11);
WHEN "111111111" => data <= conv_std_logic_vector(362,11);
WHEN others => data <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_castftox.vhd | 10 | 6574 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 06/02/08 - divider mantissa aa to aaff ***
--*** 13/07/09 - if zip, then zero '1' in frac ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftox IS
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castftox;
ARCHITECTURE rtl OF hcc_castftox IS
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
signal satff, zipff : STD_LOGIC;
BEGIN
-- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1)
-- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1)
-- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1)
-- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x)
gza: IF (roundconvert = 1) GENERATE
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
END GENERATE;
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
gro: IF ((target = 0 AND outputpipe = 1) OR
(target = 1 AND outputpipe = 1)) GENERATE
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= fractional & exponent;
satff <= satnode;
zipff <= zipnode;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- if exponent = 255 => saturate, if 0 => 0
satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND
aaff(27) AND aaff(26) AND aaff(25) AND aaff(24);
zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR
aaff(27) OR aaff(26) OR aaff(25) OR aaff(24));
gexpa: FOR k IN 1 TO 8 GENERATE
expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode);
END GENERATE;
expnode(9) <= satnode;
expnode(10) <= '0';
--*** internal format ***
gxa: IF (target = 0) GENERATE
fracnode(mantissa) <= aaff(32);
fracnode(mantissa-1) <= aaff(32);
fracnode(mantissa-2) <= aaff(32);
fracnode(mantissa-3) <= aaff(32);
fracnode(mantissa-4) <= aaff(32);
--fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign
-- 13/07/09
fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign
gxb: FOR k IN 1 TO 23 GENERATE
fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32));
END GENERATE;
gxc: FOR k IN 1 TO mantissa-29 GENERATE
fracnode(k)<= aaff(32); -- '0' XOR sign
END GENERATE;
gxd: IF (roundconvert = 0) GENERATE
fractional <= fracnode;
END GENERATE;
gxe: IF (roundconvert = 1) GENERATE
fractional <= fracnode + (zerovec(mantissa-1) & aaff(32));
END GENERATE;
exponent <= expnode;
END GENERATE;
--*** direct to multiplier ***
gma: IF (target = 1) GENERATE
fracnode(mantissa) <= aaff(32);
--fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign
-- 13/07/09
fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode);
gmb: FOR k IN 1 TO 23 GENERATE
fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32));
END GENERATE;
gmc: FOR k IN 1 TO mantissa-25 GENERATE
fracnode(k)<= aaff(32); -- '0' XOR sign
END GENERATE;
gmd: IF (roundconvert = 0) GENERATE
fractional <= fracnode;
END GENERATE;
gme: IF (roundconvert = 1) GENERATE
fractional <= fracnode + (zerovec(mantissa-1) & aaff(32));
END GENERATE;
--***??? adjust ???
exponent <= expnode;
END GENERATE;
-- never register output
--*** direct to divider ***
gda: IF (target = 2) GENERATE
fracnode(mantissa) <= aaff(32);
-- 13/07/09
fracnode(mantissa-1) <= '1' AND NOT(zipnode);
fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1);
gfb: FOR k IN 1 TO mantissa-25 GENERATE
fracnode(k)<= '0';
END GENERATE;
fractional <= fracnode;
--***??? adjust ???
exponent <= expnode;
END GENERATE;
--*** OUTPUTS ***
goa: IF ((target = 0 AND outputpipe = 1) OR
(target = 1 AND outputpipe = 1)) GENERATE
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
END GENERATE;
gob: IF ((target = 0 AND outputpipe = 0) OR
(target = 1 AND outputpipe = 0) OR
(target = 2)) GENERATE
cc <= fractional & exponent;
ccsat <= satnode;
cczip <= zipnode;
END GENERATE;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fp_div_lut0.vhd | 10 | 37328 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_div_lut0;
ARCHITECTURE rtl OF fp_div_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1046531,20);
WHEN "000000010" => data <= conv_std_logic_vector(1044495,20);
WHEN "000000011" => data <= conv_std_logic_vector(1042467,20);
WHEN "000000100" => data <= conv_std_logic_vector(1040447,20);
WHEN "000000101" => data <= conv_std_logic_vector(1038434,20);
WHEN "000000110" => data <= conv_std_logic_vector(1036429,20);
WHEN "000000111" => data <= conv_std_logic_vector(1034432,20);
WHEN "000001000" => data <= conv_std_logic_vector(1032443,20);
WHEN "000001001" => data <= conv_std_logic_vector(1030461,20);
WHEN "000001010" => data <= conv_std_logic_vector(1028487,20);
WHEN "000001011" => data <= conv_std_logic_vector(1026521,20);
WHEN "000001100" => data <= conv_std_logic_vector(1024562,20);
WHEN "000001101" => data <= conv_std_logic_vector(1022610,20);
WHEN "000001110" => data <= conv_std_logic_vector(1020666,20);
WHEN "000001111" => data <= conv_std_logic_vector(1018729,20);
WHEN "000010000" => data <= conv_std_logic_vector(1016800,20);
WHEN "000010001" => data <= conv_std_logic_vector(1014878,20);
WHEN "000010010" => data <= conv_std_logic_vector(1012963,20);
WHEN "000010011" => data <= conv_std_logic_vector(1011055,20);
WHEN "000010100" => data <= conv_std_logic_vector(1009155,20);
WHEN "000010101" => data <= conv_std_logic_vector(1007262,20);
WHEN "000010110" => data <= conv_std_logic_vector(1005375,20);
WHEN "000010111" => data <= conv_std_logic_vector(1003496,20);
WHEN "000011000" => data <= conv_std_logic_vector(1001624,20);
WHEN "000011001" => data <= conv_std_logic_vector(999759,20);
WHEN "000011010" => data <= conv_std_logic_vector(997900,20);
WHEN "000011011" => data <= conv_std_logic_vector(996049,20);
WHEN "000011100" => data <= conv_std_logic_vector(994205,20);
WHEN "000011101" => data <= conv_std_logic_vector(992367,20);
WHEN "000011110" => data <= conv_std_logic_vector(990536,20);
WHEN "000011111" => data <= conv_std_logic_vector(988712,20);
WHEN "000100000" => data <= conv_std_logic_vector(986894,20);
WHEN "000100001" => data <= conv_std_logic_vector(985083,20);
WHEN "000100010" => data <= conv_std_logic_vector(983279,20);
WHEN "000100011" => data <= conv_std_logic_vector(981482,20);
WHEN "000100100" => data <= conv_std_logic_vector(979691,20);
WHEN "000100101" => data <= conv_std_logic_vector(977906,20);
WHEN "000100110" => data <= conv_std_logic_vector(976128,20);
WHEN "000100111" => data <= conv_std_logic_vector(974357,20);
WHEN "000101000" => data <= conv_std_logic_vector(972591,20);
WHEN "000101001" => data <= conv_std_logic_vector(970833,20);
WHEN "000101010" => data <= conv_std_logic_vector(969080,20);
WHEN "000101011" => data <= conv_std_logic_vector(967334,20);
WHEN "000101100" => data <= conv_std_logic_vector(965594,20);
WHEN "000101101" => data <= conv_std_logic_vector(963861,20);
WHEN "000101110" => data <= conv_std_logic_vector(962133,20);
WHEN "000101111" => data <= conv_std_logic_vector(960412,20);
WHEN "000110000" => data <= conv_std_logic_vector(958697,20);
WHEN "000110001" => data <= conv_std_logic_vector(956988,20);
WHEN "000110010" => data <= conv_std_logic_vector(955286,20);
WHEN "000110011" => data <= conv_std_logic_vector(953589,20);
WHEN "000110100" => data <= conv_std_logic_vector(951898,20);
WHEN "000110101" => data <= conv_std_logic_vector(950213,20);
WHEN "000110110" => data <= conv_std_logic_vector(948534,20);
WHEN "000110111" => data <= conv_std_logic_vector(946862,20);
WHEN "000111000" => data <= conv_std_logic_vector(945195,20);
WHEN "000111001" => data <= conv_std_logic_vector(943533,20);
WHEN "000111010" => data <= conv_std_logic_vector(941878,20);
WHEN "000111011" => data <= conv_std_logic_vector(940229,20);
WHEN "000111100" => data <= conv_std_logic_vector(938585,20);
WHEN "000111101" => data <= conv_std_logic_vector(936947,20);
WHEN "000111110" => data <= conv_std_logic_vector(935314,20);
WHEN "000111111" => data <= conv_std_logic_vector(933688,20);
WHEN "001000000" => data <= conv_std_logic_vector(932067,20);
WHEN "001000001" => data <= conv_std_logic_vector(930451,20);
WHEN "001000010" => data <= conv_std_logic_vector(928842,20);
WHEN "001000011" => data <= conv_std_logic_vector(927237,20);
WHEN "001000100" => data <= conv_std_logic_vector(925639,20);
WHEN "001000101" => data <= conv_std_logic_vector(924046,20);
WHEN "001000110" => data <= conv_std_logic_vector(922458,20);
WHEN "001000111" => data <= conv_std_logic_vector(920876,20);
WHEN "001001000" => data <= conv_std_logic_vector(919299,20);
WHEN "001001001" => data <= conv_std_logic_vector(917727,20);
WHEN "001001010" => data <= conv_std_logic_vector(916161,20);
WHEN "001001011" => data <= conv_std_logic_vector(914601,20);
WHEN "001001100" => data <= conv_std_logic_vector(913045,20);
WHEN "001001101" => data <= conv_std_logic_vector(911495,20);
WHEN "001001110" => data <= conv_std_logic_vector(909950,20);
WHEN "001001111" => data <= conv_std_logic_vector(908410,20);
WHEN "001010000" => data <= conv_std_logic_vector(906876,20);
WHEN "001010001" => data <= conv_std_logic_vector(905347,20);
WHEN "001010010" => data <= conv_std_logic_vector(903822,20);
WHEN "001010011" => data <= conv_std_logic_vector(902303,20);
WHEN "001010100" => data <= conv_std_logic_vector(900789,20);
WHEN "001010101" => data <= conv_std_logic_vector(899281,20);
WHEN "001010110" => data <= conv_std_logic_vector(897777,20);
WHEN "001010111" => data <= conv_std_logic_vector(896278,20);
WHEN "001011000" => data <= conv_std_logic_vector(894784,20);
WHEN "001011001" => data <= conv_std_logic_vector(893295,20);
WHEN "001011010" => data <= conv_std_logic_vector(891812,20);
WHEN "001011011" => data <= conv_std_logic_vector(890333,20);
WHEN "001011100" => data <= conv_std_logic_vector(888859,20);
WHEN "001011101" => data <= conv_std_logic_vector(887389,20);
WHEN "001011110" => data <= conv_std_logic_vector(885925,20);
WHEN "001011111" => data <= conv_std_logic_vector(884465,20);
WHEN "001100000" => data <= conv_std_logic_vector(883011,20);
WHEN "001100001" => data <= conv_std_logic_vector(881561,20);
WHEN "001100010" => data <= conv_std_logic_vector(880116,20);
WHEN "001100011" => data <= conv_std_logic_vector(878675,20);
WHEN "001100100" => data <= conv_std_logic_vector(877239,20);
WHEN "001100101" => data <= conv_std_logic_vector(875808,20);
WHEN "001100110" => data <= conv_std_logic_vector(874382,20);
WHEN "001100111" => data <= conv_std_logic_vector(872960,20);
WHEN "001101000" => data <= conv_std_logic_vector(871543,20);
WHEN "001101001" => data <= conv_std_logic_vector(870131,20);
WHEN "001101010" => data <= conv_std_logic_vector(868723,20);
WHEN "001101011" => data <= conv_std_logic_vector(867319,20);
WHEN "001101100" => data <= conv_std_logic_vector(865920,20);
WHEN "001101101" => data <= conv_std_logic_vector(864526,20);
WHEN "001101110" => data <= conv_std_logic_vector(863136,20);
WHEN "001101111" => data <= conv_std_logic_vector(861751,20);
WHEN "001110000" => data <= conv_std_logic_vector(860369,20);
WHEN "001110001" => data <= conv_std_logic_vector(858993,20);
WHEN "001110010" => data <= conv_std_logic_vector(857621,20);
WHEN "001110011" => data <= conv_std_logic_vector(856253,20);
WHEN "001110100" => data <= conv_std_logic_vector(854889,20);
WHEN "001110101" => data <= conv_std_logic_vector(853530,20);
WHEN "001110110" => data <= conv_std_logic_vector(852176,20);
WHEN "001110111" => data <= conv_std_logic_vector(850825,20);
WHEN "001111000" => data <= conv_std_logic_vector(849479,20);
WHEN "001111001" => data <= conv_std_logic_vector(848137,20);
WHEN "001111010" => data <= conv_std_logic_vector(846799,20);
WHEN "001111011" => data <= conv_std_logic_vector(845465,20);
WHEN "001111100" => data <= conv_std_logic_vector(844136,20);
WHEN "001111101" => data <= conv_std_logic_vector(842811,20);
WHEN "001111110" => data <= conv_std_logic_vector(841490,20);
WHEN "001111111" => data <= conv_std_logic_vector(840173,20);
WHEN "010000000" => data <= conv_std_logic_vector(838860,20);
WHEN "010000001" => data <= conv_std_logic_vector(837552,20);
WHEN "010000010" => data <= conv_std_logic_vector(836247,20);
WHEN "010000011" => data <= conv_std_logic_vector(834946,20);
WHEN "010000100" => data <= conv_std_logic_vector(833650,20);
WHEN "010000101" => data <= conv_std_logic_vector(832358,20);
WHEN "010000110" => data <= conv_std_logic_vector(831069,20);
WHEN "010000111" => data <= conv_std_logic_vector(829785,20);
WHEN "010001000" => data <= conv_std_logic_vector(828504,20);
WHEN "010001001" => data <= conv_std_logic_vector(827227,20);
WHEN "010001010" => data <= conv_std_logic_vector(825955,20);
WHEN "010001011" => data <= conv_std_logic_vector(824686,20);
WHEN "010001100" => data <= conv_std_logic_vector(823421,20);
WHEN "010001101" => data <= conv_std_logic_vector(822160,20);
WHEN "010001110" => data <= conv_std_logic_vector(820903,20);
WHEN "010001111" => data <= conv_std_logic_vector(819650,20);
WHEN "010010000" => data <= conv_std_logic_vector(818400,20);
WHEN "010010001" => data <= conv_std_logic_vector(817155,20);
WHEN "010010010" => data <= conv_std_logic_vector(815913,20);
WHEN "010010011" => data <= conv_std_logic_vector(814675,20);
WHEN "010010100" => data <= conv_std_logic_vector(813440,20);
WHEN "010010101" => data <= conv_std_logic_vector(812210,20);
WHEN "010010110" => data <= conv_std_logic_vector(810983,20);
WHEN "010010111" => data <= conv_std_logic_vector(809760,20);
WHEN "010011000" => data <= conv_std_logic_vector(808540,20);
WHEN "010011001" => data <= conv_std_logic_vector(807324,20);
WHEN "010011010" => data <= conv_std_logic_vector(806112,20);
WHEN "010011011" => data <= conv_std_logic_vector(804903,20);
WHEN "010011100" => data <= conv_std_logic_vector(803699,20);
WHEN "010011101" => data <= conv_std_logic_vector(802497,20);
WHEN "010011110" => data <= conv_std_logic_vector(801299,20);
WHEN "010011111" => data <= conv_std_logic_vector(800105,20);
WHEN "010100000" => data <= conv_std_logic_vector(798915,20);
WHEN "010100001" => data <= conv_std_logic_vector(797728,20);
WHEN "010100010" => data <= conv_std_logic_vector(796544,20);
WHEN "010100011" => data <= conv_std_logic_vector(795364,20);
WHEN "010100100" => data <= conv_std_logic_vector(794187,20);
WHEN "010100101" => data <= conv_std_logic_vector(793014,20);
WHEN "010100110" => data <= conv_std_logic_vector(791845,20);
WHEN "010100111" => data <= conv_std_logic_vector(790678,20);
WHEN "010101000" => data <= conv_std_logic_vector(789516,20);
WHEN "010101001" => data <= conv_std_logic_vector(788356,20);
WHEN "010101010" => data <= conv_std_logic_vector(787200,20);
WHEN "010101011" => data <= conv_std_logic_vector(786048,20);
WHEN "010101100" => data <= conv_std_logic_vector(784899,20);
WHEN "010101101" => data <= conv_std_logic_vector(783753,20);
WHEN "010101110" => data <= conv_std_logic_vector(782610,20);
WHEN "010101111" => data <= conv_std_logic_vector(781471,20);
WHEN "010110000" => data <= conv_std_logic_vector(780335,20);
WHEN "010110001" => data <= conv_std_logic_vector(779203,20);
WHEN "010110010" => data <= conv_std_logic_vector(778073,20);
WHEN "010110011" => data <= conv_std_logic_vector(776947,20);
WHEN "010110100" => data <= conv_std_logic_vector(775825,20);
WHEN "010110101" => data <= conv_std_logic_vector(774705,20);
WHEN "010110110" => data <= conv_std_logic_vector(773589,20);
WHEN "010110111" => data <= conv_std_logic_vector(772476,20);
WHEN "010111000" => data <= conv_std_logic_vector(771366,20);
WHEN "010111001" => data <= conv_std_logic_vector(770259,20);
WHEN "010111010" => data <= conv_std_logic_vector(769156,20);
WHEN "010111011" => data <= conv_std_logic_vector(768055,20);
WHEN "010111100" => data <= conv_std_logic_vector(766958,20);
WHEN "010111101" => data <= conv_std_logic_vector(765864,20);
WHEN "010111110" => data <= conv_std_logic_vector(764773,20);
WHEN "010111111" => data <= conv_std_logic_vector(763685,20);
WHEN "011000000" => data <= conv_std_logic_vector(762600,20);
WHEN "011000001" => data <= conv_std_logic_vector(761519,20);
WHEN "011000010" => data <= conv_std_logic_vector(760440,20);
WHEN "011000011" => data <= conv_std_logic_vector(759364,20);
WHEN "011000100" => data <= conv_std_logic_vector(758292,20);
WHEN "011000101" => data <= conv_std_logic_vector(757222,20);
WHEN "011000110" => data <= conv_std_logic_vector(756156,20);
WHEN "011000111" => data <= conv_std_logic_vector(755092,20);
WHEN "011001000" => data <= conv_std_logic_vector(754032,20);
WHEN "011001001" => data <= conv_std_logic_vector(752974,20);
WHEN "011001010" => data <= conv_std_logic_vector(751920,20);
WHEN "011001011" => data <= conv_std_logic_vector(750868,20);
WHEN "011001100" => data <= conv_std_logic_vector(749819,20);
WHEN "011001101" => data <= conv_std_logic_vector(748774,20);
WHEN "011001110" => data <= conv_std_logic_vector(747731,20);
WHEN "011001111" => data <= conv_std_logic_vector(746691,20);
WHEN "011010000" => data <= conv_std_logic_vector(745654,20);
WHEN "011010001" => data <= conv_std_logic_vector(744619,20);
WHEN "011010010" => data <= conv_std_logic_vector(743588,20);
WHEN "011010011" => data <= conv_std_logic_vector(742560,20);
WHEN "011010100" => data <= conv_std_logic_vector(741534,20);
WHEN "011010101" => data <= conv_std_logic_vector(740511,20);
WHEN "011010110" => data <= conv_std_logic_vector(739491,20);
WHEN "011010111" => data <= conv_std_logic_vector(738474,20);
WHEN "011011000" => data <= conv_std_logic_vector(737460,20);
WHEN "011011001" => data <= conv_std_logic_vector(736448,20);
WHEN "011011010" => data <= conv_std_logic_vector(735439,20);
WHEN "011011011" => data <= conv_std_logic_vector(734433,20);
WHEN "011011100" => data <= conv_std_logic_vector(733430,20);
WHEN "011011101" => data <= conv_std_logic_vector(732429,20);
WHEN "011011110" => data <= conv_std_logic_vector(731431,20);
WHEN "011011111" => data <= conv_std_logic_vector(730436,20);
WHEN "011100000" => data <= conv_std_logic_vector(729444,20);
WHEN "011100001" => data <= conv_std_logic_vector(728454,20);
WHEN "011100010" => data <= conv_std_logic_vector(727467,20);
WHEN "011100011" => data <= conv_std_logic_vector(726483,20);
WHEN "011100100" => data <= conv_std_logic_vector(725501,20);
WHEN "011100101" => data <= conv_std_logic_vector(724522,20);
WHEN "011100110" => data <= conv_std_logic_vector(723545,20);
WHEN "011100111" => data <= conv_std_logic_vector(722572,20);
WHEN "011101000" => data <= conv_std_logic_vector(721600,20);
WHEN "011101001" => data <= conv_std_logic_vector(720632,20);
WHEN "011101010" => data <= conv_std_logic_vector(719666,20);
WHEN "011101011" => data <= conv_std_logic_vector(718702,20);
WHEN "011101100" => data <= conv_std_logic_vector(717742,20);
WHEN "011101101" => data <= conv_std_logic_vector(716783,20);
WHEN "011101110" => data <= conv_std_logic_vector(715828,20);
WHEN "011101111" => data <= conv_std_logic_vector(714874,20);
WHEN "011110000" => data <= conv_std_logic_vector(713924,20);
WHEN "011110001" => data <= conv_std_logic_vector(712976,20);
WHEN "011110010" => data <= conv_std_logic_vector(712030,20);
WHEN "011110011" => data <= conv_std_logic_vector(711087,20);
WHEN "011110100" => data <= conv_std_logic_vector(710146,20);
WHEN "011110101" => data <= conv_std_logic_vector(709208,20);
WHEN "011110110" => data <= conv_std_logic_vector(708273,20);
WHEN "011110111" => data <= conv_std_logic_vector(707339,20);
WHEN "011111000" => data <= conv_std_logic_vector(706409,20);
WHEN "011111001" => data <= conv_std_logic_vector(705481,20);
WHEN "011111010" => data <= conv_std_logic_vector(704555,20);
WHEN "011111011" => data <= conv_std_logic_vector(703631,20);
WHEN "011111100" => data <= conv_std_logic_vector(702710,20);
WHEN "011111101" => data <= conv_std_logic_vector(701792,20);
WHEN "011111110" => data <= conv_std_logic_vector(700876,20);
WHEN "011111111" => data <= conv_std_logic_vector(699962,20);
WHEN "100000000" => data <= conv_std_logic_vector(699050,20);
WHEN "100000001" => data <= conv_std_logic_vector(698141,20);
WHEN "100000010" => data <= conv_std_logic_vector(697235,20);
WHEN "100000011" => data <= conv_std_logic_vector(696330,20);
WHEN "100000100" => data <= conv_std_logic_vector(695428,20);
WHEN "100000101" => data <= conv_std_logic_vector(694529,20);
WHEN "100000110" => data <= conv_std_logic_vector(693631,20);
WHEN "100000111" => data <= conv_std_logic_vector(692736,20);
WHEN "100001000" => data <= conv_std_logic_vector(691844,20);
WHEN "100001001" => data <= conv_std_logic_vector(690953,20);
WHEN "100001010" => data <= conv_std_logic_vector(690065,20);
WHEN "100001011" => data <= conv_std_logic_vector(689179,20);
WHEN "100001100" => data <= conv_std_logic_vector(688296,20);
WHEN "100001101" => data <= conv_std_logic_vector(687414,20);
WHEN "100001110" => data <= conv_std_logic_vector(686535,20);
WHEN "100001111" => data <= conv_std_logic_vector(685659,20);
WHEN "100010000" => data <= conv_std_logic_vector(684784,20);
WHEN "100010001" => data <= conv_std_logic_vector(683912,20);
WHEN "100010010" => data <= conv_std_logic_vector(683042,20);
WHEN "100010011" => data <= conv_std_logic_vector(682174,20);
WHEN "100010100" => data <= conv_std_logic_vector(681308,20);
WHEN "100010101" => data <= conv_std_logic_vector(680444,20);
WHEN "100010110" => data <= conv_std_logic_vector(679583,20);
WHEN "100010111" => data <= conv_std_logic_vector(678724,20);
WHEN "100011000" => data <= conv_std_logic_vector(677867,20);
WHEN "100011001" => data <= conv_std_logic_vector(677012,20);
WHEN "100011010" => data <= conv_std_logic_vector(676160,20);
WHEN "100011011" => data <= conv_std_logic_vector(675309,20);
WHEN "100011100" => data <= conv_std_logic_vector(674461,20);
WHEN "100011101" => data <= conv_std_logic_vector(673614,20);
WHEN "100011110" => data <= conv_std_logic_vector(672770,20);
WHEN "100011111" => data <= conv_std_logic_vector(671928,20);
WHEN "100100000" => data <= conv_std_logic_vector(671088,20);
WHEN "100100001" => data <= conv_std_logic_vector(670251,20);
WHEN "100100010" => data <= conv_std_logic_vector(669415,20);
WHEN "100100011" => data <= conv_std_logic_vector(668581,20);
WHEN "100100100" => data <= conv_std_logic_vector(667750,20);
WHEN "100100101" => data <= conv_std_logic_vector(666920,20);
WHEN "100100110" => data <= conv_std_logic_vector(666093,20);
WHEN "100100111" => data <= conv_std_logic_vector(665267,20);
WHEN "100101000" => data <= conv_std_logic_vector(664444,20);
WHEN "100101001" => data <= conv_std_logic_vector(663623,20);
WHEN "100101010" => data <= conv_std_logic_vector(662803,20);
WHEN "100101011" => data <= conv_std_logic_vector(661986,20);
WHEN "100101100" => data <= conv_std_logic_vector(661171,20);
WHEN "100101101" => data <= conv_std_logic_vector(660358,20);
WHEN "100101110" => data <= conv_std_logic_vector(659546,20);
WHEN "100101111" => data <= conv_std_logic_vector(658737,20);
WHEN "100110000" => data <= conv_std_logic_vector(657930,20);
WHEN "100110001" => data <= conv_std_logic_vector(657124,20);
WHEN "100110010" => data <= conv_std_logic_vector(656321,20);
WHEN "100110011" => data <= conv_std_logic_vector(655520,20);
WHEN "100110100" => data <= conv_std_logic_vector(654720,20);
WHEN "100110101" => data <= conv_std_logic_vector(653923,20);
WHEN "100110110" => data <= conv_std_logic_vector(653127,20);
WHEN "100110111" => data <= conv_std_logic_vector(652334,20);
WHEN "100111000" => data <= conv_std_logic_vector(651542,20);
WHEN "100111001" => data <= conv_std_logic_vector(650752,20);
WHEN "100111010" => data <= conv_std_logic_vector(649965,20);
WHEN "100111011" => data <= conv_std_logic_vector(649179,20);
WHEN "100111100" => data <= conv_std_logic_vector(648395,20);
WHEN "100111101" => data <= conv_std_logic_vector(647612,20);
WHEN "100111110" => data <= conv_std_logic_vector(646832,20);
WHEN "100111111" => data <= conv_std_logic_vector(646054,20);
WHEN "101000000" => data <= conv_std_logic_vector(645277,20);
WHEN "101000001" => data <= conv_std_logic_vector(644503,20);
WHEN "101000010" => data <= conv_std_logic_vector(643730,20);
WHEN "101000011" => data <= conv_std_logic_vector(642959,20);
WHEN "101000100" => data <= conv_std_logic_vector(642190,20);
WHEN "101000101" => data <= conv_std_logic_vector(641423,20);
WHEN "101000110" => data <= conv_std_logic_vector(640657,20);
WHEN "101000111" => data <= conv_std_logic_vector(639894,20);
WHEN "101001000" => data <= conv_std_logic_vector(639132,20);
WHEN "101001001" => data <= conv_std_logic_vector(638372,20);
WHEN "101001010" => data <= conv_std_logic_vector(637614,20);
WHEN "101001011" => data <= conv_std_logic_vector(636857,20);
WHEN "101001100" => data <= conv_std_logic_vector(636103,20);
WHEN "101001101" => data <= conv_std_logic_vector(635350,20);
WHEN "101001110" => data <= conv_std_logic_vector(634599,20);
WHEN "101001111" => data <= conv_std_logic_vector(633850,20);
WHEN "101010000" => data <= conv_std_logic_vector(633102,20);
WHEN "101010001" => data <= conv_std_logic_vector(632357,20);
WHEN "101010010" => data <= conv_std_logic_vector(631613,20);
WHEN "101010011" => data <= conv_std_logic_vector(630870,20);
WHEN "101010100" => data <= conv_std_logic_vector(630130,20);
WHEN "101010101" => data <= conv_std_logic_vector(629391,20);
WHEN "101010110" => data <= conv_std_logic_vector(628654,20);
WHEN "101010111" => data <= conv_std_logic_vector(627919,20);
WHEN "101011000" => data <= conv_std_logic_vector(627185,20);
WHEN "101011001" => data <= conv_std_logic_vector(626454,20);
WHEN "101011010" => data <= conv_std_logic_vector(625723,20);
WHEN "101011011" => data <= conv_std_logic_vector(624995,20);
WHEN "101011100" => data <= conv_std_logic_vector(624268,20);
WHEN "101011101" => data <= conv_std_logic_vector(623543,20);
WHEN "101011110" => data <= conv_std_logic_vector(622820,20);
WHEN "101011111" => data <= conv_std_logic_vector(622098,20);
WHEN "101100000" => data <= conv_std_logic_vector(621378,20);
WHEN "101100001" => data <= conv_std_logic_vector(620660,20);
WHEN "101100010" => data <= conv_std_logic_vector(619943,20);
WHEN "101100011" => data <= conv_std_logic_vector(619228,20);
WHEN "101100100" => data <= conv_std_logic_vector(618515,20);
WHEN "101100101" => data <= conv_std_logic_vector(617803,20);
WHEN "101100110" => data <= conv_std_logic_vector(617093,20);
WHEN "101100111" => data <= conv_std_logic_vector(616384,20);
WHEN "101101000" => data <= conv_std_logic_vector(615677,20);
WHEN "101101001" => data <= conv_std_logic_vector(614972,20);
WHEN "101101010" => data <= conv_std_logic_vector(614269,20);
WHEN "101101011" => data <= conv_std_logic_vector(613567,20);
WHEN "101101100" => data <= conv_std_logic_vector(612866,20);
WHEN "101101101" => data <= conv_std_logic_vector(612167,20);
WHEN "101101110" => data <= conv_std_logic_vector(611470,20);
WHEN "101101111" => data <= conv_std_logic_vector(610774,20);
WHEN "101110000" => data <= conv_std_logic_vector(610080,20);
WHEN "101110001" => data <= conv_std_logic_vector(609388,20);
WHEN "101110010" => data <= conv_std_logic_vector(608697,20);
WHEN "101110011" => data <= conv_std_logic_vector(608008,20);
WHEN "101110100" => data <= conv_std_logic_vector(607320,20);
WHEN "101110101" => data <= conv_std_logic_vector(606634,20);
WHEN "101110110" => data <= conv_std_logic_vector(605949,20);
WHEN "101110111" => data <= conv_std_logic_vector(605266,20);
WHEN "101111000" => data <= conv_std_logic_vector(604584,20);
WHEN "101111001" => data <= conv_std_logic_vector(603904,20);
WHEN "101111010" => data <= conv_std_logic_vector(603226,20);
WHEN "101111011" => data <= conv_std_logic_vector(602549,20);
WHEN "101111100" => data <= conv_std_logic_vector(601873,20);
WHEN "101111101" => data <= conv_std_logic_vector(601199,20);
WHEN "101111110" => data <= conv_std_logic_vector(600527,20);
WHEN "101111111" => data <= conv_std_logic_vector(599856,20);
WHEN "110000000" => data <= conv_std_logic_vector(599186,20);
WHEN "110000001" => data <= conv_std_logic_vector(598518,20);
WHEN "110000010" => data <= conv_std_logic_vector(597852,20);
WHEN "110000011" => data <= conv_std_logic_vector(597187,20);
WHEN "110000100" => data <= conv_std_logic_vector(596523,20);
WHEN "110000101" => data <= conv_std_logic_vector(595861,20);
WHEN "110000110" => data <= conv_std_logic_vector(595200,20);
WHEN "110000111" => data <= conv_std_logic_vector(594541,20);
WHEN "110001000" => data <= conv_std_logic_vector(593884,20);
WHEN "110001001" => data <= conv_std_logic_vector(593227,20);
WHEN "110001010" => data <= conv_std_logic_vector(592573,20);
WHEN "110001011" => data <= conv_std_logic_vector(591919,20);
WHEN "110001100" => data <= conv_std_logic_vector(591267,20);
WHEN "110001101" => data <= conv_std_logic_vector(590617,20);
WHEN "110001110" => data <= conv_std_logic_vector(589968,20);
WHEN "110001111" => data <= conv_std_logic_vector(589320,20);
WHEN "110010000" => data <= conv_std_logic_vector(588674,20);
WHEN "110010001" => data <= conv_std_logic_vector(588029,20);
WHEN "110010010" => data <= conv_std_logic_vector(587386,20);
WHEN "110010011" => data <= conv_std_logic_vector(586744,20);
WHEN "110010100" => data <= conv_std_logic_vector(586103,20);
WHEN "110010101" => data <= conv_std_logic_vector(585464,20);
WHEN "110010110" => data <= conv_std_logic_vector(584827,20);
WHEN "110010111" => data <= conv_std_logic_vector(584190,20);
WHEN "110011000" => data <= conv_std_logic_vector(583555,20);
WHEN "110011001" => data <= conv_std_logic_vector(582922,20);
WHEN "110011010" => data <= conv_std_logic_vector(582289,20);
WHEN "110011011" => data <= conv_std_logic_vector(581658,20);
WHEN "110011100" => data <= conv_std_logic_vector(581029,20);
WHEN "110011101" => data <= conv_std_logic_vector(580401,20);
WHEN "110011110" => data <= conv_std_logic_vector(579774,20);
WHEN "110011111" => data <= conv_std_logic_vector(579149,20);
WHEN "110100000" => data <= conv_std_logic_vector(578525,20);
WHEN "110100001" => data <= conv_std_logic_vector(577902,20);
WHEN "110100010" => data <= conv_std_logic_vector(577280,20);
WHEN "110100011" => data <= conv_std_logic_vector(576660,20);
WHEN "110100100" => data <= conv_std_logic_vector(576042,20);
WHEN "110100101" => data <= conv_std_logic_vector(575424,20);
WHEN "110100110" => data <= conv_std_logic_vector(574808,20);
WHEN "110100111" => data <= conv_std_logic_vector(574193,20);
WHEN "110101000" => data <= conv_std_logic_vector(573580,20);
WHEN "110101001" => data <= conv_std_logic_vector(572968,20);
WHEN "110101010" => data <= conv_std_logic_vector(572357,20);
WHEN "110101011" => data <= conv_std_logic_vector(571747,20);
WHEN "110101100" => data <= conv_std_logic_vector(571139,20);
WHEN "110101101" => data <= conv_std_logic_vector(570532,20);
WHEN "110101110" => data <= conv_std_logic_vector(569926,20);
WHEN "110101111" => data <= conv_std_logic_vector(569322,20);
WHEN "110110000" => data <= conv_std_logic_vector(568719,20);
WHEN "110110001" => data <= conv_std_logic_vector(568117,20);
WHEN "110110010" => data <= conv_std_logic_vector(567517,20);
WHEN "110110011" => data <= conv_std_logic_vector(566917,20);
WHEN "110110100" => data <= conv_std_logic_vector(566319,20);
WHEN "110110101" => data <= conv_std_logic_vector(565723,20);
WHEN "110110110" => data <= conv_std_logic_vector(565127,20);
WHEN "110110111" => data <= conv_std_logic_vector(564533,20);
WHEN "110111000" => data <= conv_std_logic_vector(563940,20);
WHEN "110111001" => data <= conv_std_logic_vector(563348,20);
WHEN "110111010" => data <= conv_std_logic_vector(562758,20);
WHEN "110111011" => data <= conv_std_logic_vector(562168,20);
WHEN "110111100" => data <= conv_std_logic_vector(561580,20);
WHEN "110111101" => data <= conv_std_logic_vector(560993,20);
WHEN "110111110" => data <= conv_std_logic_vector(560408,20);
WHEN "110111111" => data <= conv_std_logic_vector(559824,20);
WHEN "111000000" => data <= conv_std_logic_vector(559240,20);
WHEN "111000001" => data <= conv_std_logic_vector(558658,20);
WHEN "111000010" => data <= conv_std_logic_vector(558078,20);
WHEN "111000011" => data <= conv_std_logic_vector(557498,20);
WHEN "111000100" => data <= conv_std_logic_vector(556920,20);
WHEN "111000101" => data <= conv_std_logic_vector(556343,20);
WHEN "111000110" => data <= conv_std_logic_vector(555767,20);
WHEN "111000111" => data <= conv_std_logic_vector(555192,20);
WHEN "111001000" => data <= conv_std_logic_vector(554619,20);
WHEN "111001001" => data <= conv_std_logic_vector(554046,20);
WHEN "111001010" => data <= conv_std_logic_vector(553475,20);
WHEN "111001011" => data <= conv_std_logic_vector(552905,20);
WHEN "111001100" => data <= conv_std_logic_vector(552336,20);
WHEN "111001101" => data <= conv_std_logic_vector(551769,20);
WHEN "111001110" => data <= conv_std_logic_vector(551202,20);
WHEN "111001111" => data <= conv_std_logic_vector(550637,20);
WHEN "111010000" => data <= conv_std_logic_vector(550073,20);
WHEN "111010001" => data <= conv_std_logic_vector(549509,20);
WHEN "111010010" => data <= conv_std_logic_vector(548948,20);
WHEN "111010011" => data <= conv_std_logic_vector(548387,20);
WHEN "111010100" => data <= conv_std_logic_vector(547827,20);
WHEN "111010101" => data <= conv_std_logic_vector(547269,20);
WHEN "111010110" => data <= conv_std_logic_vector(546712,20);
WHEN "111010111" => data <= conv_std_logic_vector(546155,20);
WHEN "111011000" => data <= conv_std_logic_vector(545600,20);
WHEN "111011001" => data <= conv_std_logic_vector(545046,20);
WHEN "111011010" => data <= conv_std_logic_vector(544494,20);
WHEN "111011011" => data <= conv_std_logic_vector(543942,20);
WHEN "111011100" => data <= conv_std_logic_vector(543391,20);
WHEN "111011101" => data <= conv_std_logic_vector(542842,20);
WHEN "111011110" => data <= conv_std_logic_vector(542294,20);
WHEN "111011111" => data <= conv_std_logic_vector(541746,20);
WHEN "111100000" => data <= conv_std_logic_vector(541200,20);
WHEN "111100001" => data <= conv_std_logic_vector(540655,20);
WHEN "111100010" => data <= conv_std_logic_vector(540111,20);
WHEN "111100011" => data <= conv_std_logic_vector(539569,20);
WHEN "111100100" => data <= conv_std_logic_vector(539027,20);
WHEN "111100101" => data <= conv_std_logic_vector(538486,20);
WHEN "111100110" => data <= conv_std_logic_vector(537947,20);
WHEN "111100111" => data <= conv_std_logic_vector(537408,20);
WHEN "111101000" => data <= conv_std_logic_vector(536871,20);
WHEN "111101001" => data <= conv_std_logic_vector(536334,20);
WHEN "111101010" => data <= conv_std_logic_vector(535799,20);
WHEN "111101011" => data <= conv_std_logic_vector(535265,20);
WHEN "111101100" => data <= conv_std_logic_vector(534732,20);
WHEN "111101101" => data <= conv_std_logic_vector(534200,20);
WHEN "111101110" => data <= conv_std_logic_vector(533669,20);
WHEN "111101111" => data <= conv_std_logic_vector(533139,20);
WHEN "111110000" => data <= conv_std_logic_vector(532610,20);
WHEN "111110001" => data <= conv_std_logic_vector(532082,20);
WHEN "111110010" => data <= conv_std_logic_vector(531555,20);
WHEN "111110011" => data <= conv_std_logic_vector(531029,20);
WHEN "111110100" => data <= conv_std_logic_vector(530505,20);
WHEN "111110101" => data <= conv_std_logic_vector(529981,20);
WHEN "111110110" => data <= conv_std_logic_vector(529458,20);
WHEN "111110111" => data <= conv_std_logic_vector(528937,20);
WHEN "111111000" => data <= conv_std_logic_vector(528416,20);
WHEN "111111001" => data <= conv_std_logic_vector(527897,20);
WHEN "111111010" => data <= conv_std_logic_vector(527378,20);
WHEN "111111011" => data <= conv_std_logic_vector(526860,20);
WHEN "111111100" => data <= conv_std_logic_vector(526344,20);
WHEN "111111101" => data <= conv_std_logic_vector(525828,20);
WHEN "111111110" => data <= conv_std_logic_vector(525314,20);
WHEN "111111111" => data <= conv_std_logic_vector(524800,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_cordic_start1.vhd | 10 | 3284 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_range1.vhd | 10 | 12008 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Core. Output as a fraction of 2PI. ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range1 IS
GENERIC (device : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_range1;
ARCHITECTURE rtl of fp_range1 IS
type rangeexponentfftype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal mantissadelff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal mantissamultipliernode : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal mantissamultiplierff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaexponentnode : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal leadnode, leadff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal rangeexponentff : rangeexponentfftype;
signal negrangeexponentff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal tableaddressff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal basefractionnode, basefractionff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal incmantissanode, incmantissaff : STD_LOGIC_VECTOR (56 DOWNTO 1);
signal incexponentnode, incexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal basefractiondelnode, basefractiondelff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (79 DOWNTO 1);
signal multipliernormnode : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal multipliernormff : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal leftrotatenode, rightrotatenode : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal leftrotateff, rightrotateff : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal rotatenode : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal rotateff : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal selectrotateff : STD_LOGIC;
signal circlenode : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal circleff : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal negbasefractiondelnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negbasefractiondelff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negrotatenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcirclenode : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal negcircleff : STD_LOGIC_VECTOR (37 DOWNTO 1);
component fp_clz23
PORT (
mantissa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
component fp_lsft23
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_lsft78
PORT (
inbus : IN STD_LOGIC_VECTOR (78 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (78 DOWNTO 1)
);
end component;
component fp_rsft78
PORT (
inbus : IN STD_LOGIC_VECTOR (78 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (78 DOWNTO 1)
);
end component;
component fp_range_table1
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
end component;
component fp_mul23x56 IS
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= '0';
mantissadelff(k) <= '0';
mantissamultiplierff(k) <= '0';
END LOOP;
exponentff <= "00000000";
FOR k IN 1 TO 6 LOOP
rangeexponentff(k)(9 DOWNTO 1) <= "000000000";
END LOOP;
negrangeexponentff(9 DOWNTO 1) <= "000000000";
leadff <= "00000";
tableaddressff <= "00000000";
FOR k IN 1 TO 36 LOOP
basefractionff(k) <= '0';
END LOOP;
FOR k IN 1 TO 56 LOOP
incmantissaff(k) <= '0';
END LOOP;
incexponentff <= "00000000";
FOR k IN 1 TO 78 LOOP
multipliernormff(k) <= '0';
leftrotateff(k) <= '0';
rightrotateff(k) <= '0';
END LOOP;
selectrotateff <= '0';
FOR k IN 1 TO 37 LOOP
circleff(k) <= '0';
negcircleff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mantissaff <= mantissain; -- level 1
mantissadelff <= mantissaff; -- level 2
exponentff <= exponentin; -- level 1
leadff <= leadnode; -- level 2
mantissamultiplierff <= mantissamultipliernode; -- level 3
tableaddressff <= exponentff; -- level 2
basefractionff <= basefractionnode; -- level 3
incmantissaff <= incmantissanode; -- level 3
incexponentff <= incexponentnode; -- level 3
rangeexponentff(1)(9 DOWNTO 1) <= mantissaexponentnode; -- levels 3,4,5,6,7, and 8
rangeexponentff(2)(9 DOWNTO 1) <= rangeexponentff(1)(9 DOWNTO 1) - ('0' & incexponentff);
rangeexponentff(3)(9 DOWNTO 1) <= rangeexponentff(2)(9 DOWNTO 1);
rangeexponentff(4)(9 DOWNTO 1) <= rangeexponentff(3)(9 DOWNTO 1);
rangeexponentff(5)(9 DOWNTO 1) <= rangeexponentff(4)(9 DOWNTO 1);
rangeexponentff(6)(9 DOWNTO 1) <= rangeexponentff(5)(9 DOWNTO 1) - ("00000000" & NOT(multipliernode(79)));
negrangeexponentff <= "100000000" -
(rangeexponentff(5)(9 DOWNTO 1) -
("00000000" & NOT(multipliernode(79)))); -- level 8
multipliernormff <= multipliernormnode;
leftrotateff <= leftrotatenode;
rightrotateff <= rightrotatenode;
rotateff <= rotatenode;
selectrotateff <= negrangeexponentff(9);
basefractiondelff <= basefractiondelnode;
negbasefractiondelff <= negbasefractiondelnode;
circleff <= circlenode;
negcircleff <= negcirclenode;
END IF;
END IF;
END PROCESS;
cbfd: fp_del
GENERIC MAP (width=>36,pipes=>6)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>basefractionff,
cc=>basefractiondelnode);
--turn mantissa fractional part into floating point number
-- level 1 in
cclzin: fp_clz23
PORT MAP (mantissa=>mantissaff,leading=>leadnode);
-- need to do this shift so that both mult inputs normalized, so we can see
-- if 1 bit mult output normalization required
-- level 2 in
csftin: fp_lsft23
PORT MAP (inbus=>mantissadelff,shift=>leadff,
outbus=>mantissamultipliernode);
-- exponents (expin, baseexp, incexp) reversed
-- exponents show shift from 0.9999 posisition
-- ex: 0.111e3 = 0.000111, 0.111e5 = 0.00000111
-- if no shift, expin = 23
-- ex: mantissain = 123, after shift = 0.1111011 (0.96), same as 7
-- level 2 in
mantissaexponentnode <= "000010111" - ("0000" & leadff); -- 23 - shift
-- level 2 in
clut: fp_range_table1
PORT MAP (address=>tableaddressff,
basefraction=>basefractionnode,
incmantissa=>incmantissanode,
incexponent=>incexponentnode);
-- 23 x 56 = 79 bits
-- mantissamulin, incman both in range 0.5 to 0.9999, so result is range 0.25 to 0.999
-- if < 0.5, shift left and add 1 to exponent
-- levels 4,5,6,7
cmul: fp_mul23x56
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mantissamultiplierff,databb=>incmantissaff,
result=>multipliernode);
-- level 7 in
gma: FOR k IN 1 TO 78 GENERATE
multipliernormnode(k) <= (multipliernode(k+1) AND multipliernode(79)) OR
(multipliernode(k) AND NOT(multipliernode(79)));
END GENERATE;
lftsft: fp_lsft78
PORT MAP (inbus=>multipliernormff,shift=>rangeexponentff(6)(6 DOWNTO 1),
outbus=>leftrotatenode);
rgtsft: fp_rsft78
PORT MAP (inbus=>multipliernormff,shift=>negrangeexponentff(6 DOWNTO 1),
outbus=>rightrotatenode);
gra: FOR k IN 1 TO 78 GENERATE
rotatenode(k) <= (leftrotateff(k) AND NOT(selectrotateff)) OR
(rightrotateff(k) AND selectrotateff);
END GENERATE;
-- use 3-1 adder to round as well?
-- max will be 1.9999, but only interested in fractional part
circlenode <= ('0' & basefractiondelff) + ('0' & rotateff(78 DOWNTO 43));
negbasefractiondelnode <= 0 - (basefractiondelnode(36 DOWNTO 1));
gnra: FOR k IN 1 TO 36 GENERATE
negrotatenode(k) <= NOT(rotateff(k+42));
END GENERATE;
negcirclenode <= ('1' & negbasefractiondelff) + ('1' & negrotatenode) + 1;
-- fractional part of 2pi will be circle(36 DOWNTO 1)
circle <= circleff(36 DOWNTO 1);
negcircle <= negcircleff(36 DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_atan_s5.vhd | 10 | 384322 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atan_s5
-- VHDL created on Tue Mar 12 11:23:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atan_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atan_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpArctanXTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid11_fpArctanXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid13_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid15_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid16_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal piO2_uid37_fpArctanXTest_q : std_logic_vector (25 downto 0);
signal piO4_uid38_fpArctanXTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid46_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid46_fpArctanXTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid46_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid53_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid55_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal zS_uid58_fpArctanXTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid60_fpArctanXTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid70_fpArctanXTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid70_fpArctanXTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid70_fpArctanXTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid70_fpArctanXTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid70_fpArctanXTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid100_fpArctanXTest_q : std_logic_vector(1 downto 0);
signal cst2BiasM1_uid120_z_uid48_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid121_z_uid48_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid153_z_uid48_fpArctanXTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid153_z_uid48_fpArctanXTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid154_z_uid48_fpArctanXTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid154_z_uid48_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid160_z_uid48_fpArctanXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid160_z_uid48_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid166_fxpU_uid63_fpArctanXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid172_fxpU_uid63_fpArctanXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid180_fxpU_uid63_fpArctanXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid183_fxpU_uid63_fpArctanXTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid210_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid213_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid224_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid250_pT1_uid193_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid250_pT1_uid193_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid250_pT1_uid193_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid250_pT1_uid193_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid250_pT1_uid193_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid253_pT2_uid199_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid253_pT2_uid199_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid253_pT2_uid199_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid253_pT2_uid199_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid253_pT2_uid199_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid256_pT1_uid238_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid256_pT1_uid238_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid256_pT1_uid238_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid256_pT1_uid238_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid256_pT1_uid238_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid259_pT2_uid244_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid259_pT2_uid244_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid259_pT2_uid244_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid259_pT2_uid244_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid259_pT2_uid244_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid189_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid189_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid189_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid189_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid189_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid189_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid190_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid190_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid190_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid190_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid190_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid190_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid191_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid191_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid191_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid191_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid191_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid191_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid234_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid234_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid234_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid234_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid234_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid234_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid235_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid235_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid235_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid235_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid235_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid235_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid236_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid236_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid236_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid236_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid236_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid236_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid105_fpArctanXTest_0_to_outMuxSelEnc_uid106_fpArctanXTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid157_z_uid48_fpArctanXTest_0_to_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC2_uid236_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid237_invPolyEval_0_to_prodXY_uid256_pT1_uid238_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid236_invTabGen_lutmem_0_to_prodXY_uid256_pT1_uid238_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid235_invTabGen_lutmem_0_to_sumAHighB_uid241_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid239_uid242_invPolyEval_0_to_prodXY_uid259_pT2_uid244_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid234_invTabGen_lutmem_0_to_sumAHighB_uid247_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid110_fpArctanXTest_0_to_R_uid163_z_uid48_fpArctanXTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid47_fpArctanXTest_2_to_u_uid49_fpArctanXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid50_fpArctanXTest_0_to_atanUIsU_uid54_fpArctanXTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid61_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid168_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid171_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid174_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid66_fpArctanXTest_0_to_memoryC2_uid191_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid191_atanXOXTabGen_lutmem_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid190_atanXOXTabGen_lutmem_0_to_sumAHighB_uid196_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid194_uid197_atanXOXPolyEval_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid189_atanXOXTabGen_lutmem_0_to_sumAHighB_uid202_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid69_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid76_fpArctanXTest_0_to_shiftValPath2PreSub_uid81_fpArctanXTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid87_uid88_fpArctanXTest_0_to_path2Diff_uid88_fpArctanXTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid95_uid95_fpArctanXTest_0_to_expFracRPath2PostRnd_uid96_fpArctanXTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid77_fpArctanXTest_0_to_expfracRPath3PostRnd_uid78_fpArctanXTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid97_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid101_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid98_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid103_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_5_q : std_logic_vector (7 downto 0);
signal ld_reg_path2_uid47_fpArctanXTest_2_to_u_uid49_fpArctanXTest_1_q_to_u_uid49_fpArctanXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid51_fpArctanXTest_b_to_oFracU_uid52_uid52_fpArctanXTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid82_fpArctanXTest_c_to_sValPostSOut_uid84_fpArctanXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid74_fpArctanXTest_q_to_oFracRPath2_uid85_uid85_fpArctanXTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid47_fpArctanXTest_n_to_pathSelBits_uid99_fpArctanXTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid46_fpArctanXTest_q_to_pathSelBits_uid99_fpArctanXTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid141_z_uid48_fpArctanXTest_b_to_yPPolyEval_uid144_z_uid48_fpArctanXTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid140_z_uid48_fpArctanXTest_q_to_fracRCalc_uid153_z_uid48_fpArctanXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_1_q_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage035dto0_uid178_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx1_uid179_fxpU_uid63_fpArctanXTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid181_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx2_uid182_fxpU_uid63_fpArctanXTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid184_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx3_uid185_fxpU_uid63_fpArctanXTest_b_q : std_logic_vector (33 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_1_q_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_b_q : std_logic_vector (1 downto 0);
signal ld_RightShiftStage024dto2_uid217_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx1_uid219_fxpOp2Path2_uid87_fpArctanXTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid220_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx2_uid222_fxpOp2Path2_uid87_fpArctanXTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid223_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx3_uid225_fxpOp2Path2_uid87_fpArctanXTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_1_q_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC1_uid190_atanXOXTabGen_lutmem_0_q_to_memoryC1_uid190_atanXOXTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC1_uid235_invTabGen_lutmem_0_q_to_memoryC1_uid235_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_reg_signR_uid110_fpArctanXTest_0_to_R_uid163_z_uid48_fpArctanXTest_2_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid192_atanXOXPolyEval_b_to_reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_b_to_reg_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_expRPath3_uid80_fpArctanXTest_b_to_reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_a_q : std_logic_vector (7 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid49_fpArctanXTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_sticky_ena_q : signal is true;
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_sticky_ena_q : signal is true;
signal ld_y_uid141_z_uid48_fpArctanXTest_b_to_yPPolyEval_uid144_z_uid48_fpArctanXTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid192_atanXOXPolyEval_b_to_reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_reset0 : std_logic;
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_sticky_ena_q : signal is true;
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_reset0 : std_logic;
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_sticky_ena_q : signal is true;
signal ld_expRPath3_uid80_fpArctanXTest_b_to_reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_a_inputreg_q : std_logic_vector (7 downto 0);
signal atanUIsU_uid54_fpArctanXTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid54_fpArctanXTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid54_fpArctanXTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid54_fpArctanXTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid54_fpArctanXTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid82_fpArctanXTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid82_fpArctanXTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid82_fpArctanXTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid82_fpArctanXTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid82_fpArctanXTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid105_fpArctanXTest_q : std_logic_vector (2 downto 0);
signal leftShiftStage1Idx1_uid179_fxpU_uid63_fpArctanXTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid78_fpArctanXTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid78_fpArctanXTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid78_fpArctanXTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid78_fpArctanXTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid96_fpArctanXTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid96_fpArctanXTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid96_fpArctanXTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid96_fpArctanXTest_q : std_logic_vector (32 downto 0);
signal oFracU_uid52_uid52_fpArctanXTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid85_uid85_fpArctanXTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal expX_uid6_fpArctanXTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpArctanXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpArctanXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpArctanXTest_b : std_logic_vector (22 downto 0);
signal singX_uid8_fpArctanXTest_in : std_logic_vector (31 downto 0);
signal singX_uid8_fpArctanXTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid22_fpArctanXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid22_fpArctanXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid22_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid24_fpArctanXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid24_fpArctanXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid24_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid26_fpArctanXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid26_fpArctanXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid26_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid27_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid27_fpArctanXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid27_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid35_fpArctanXTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid35_fpArctanXTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid35_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid36_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid36_fpArctanXTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid36_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal path2_uid47_fpArctanXTest_a : std_logic_vector(10 downto 0);
signal path2_uid47_fpArctanXTest_b : std_logic_vector(10 downto 0);
signal path2_uid47_fpArctanXTest_o : std_logic_vector (10 downto 0);
signal path2_uid47_fpArctanXTest_cin : std_logic_vector (0 downto 0);
signal path2_uid47_fpArctanXTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid56_fpArctanXTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid56_fpArctanXTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid56_fpArctanXTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid56_fpArctanXTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid81_fpArctanXTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid81_fpArctanXTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid81_fpArctanXTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid81_fpArctanXTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid88_fpArctanXTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid88_fpArctanXTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid88_fpArctanXTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid88_fpArctanXTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid102_fpArctanXTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid102_fpArctanXTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid104_fpArctanXTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid104_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid106_fpArctanXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid107_fpArctanXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid107_fpArctanXTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid108_fpArctanXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid108_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal fracXIsZero_uid140_z_uid48_fpArctanXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid140_z_uid48_fpArctanXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid140_z_uid48_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid147_z_uid48_fpArctanXTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid147_z_uid48_fpArctanXTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid147_z_uid48_fpArctanXTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid147_z_uid48_fpArctanXTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid158_z_uid48_fpArctanXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid159_z_uid48_fpArctanXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid159_z_uid48_fpArctanXTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal cstPiO2_uid39_fpArctanXTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid39_fpArctanXTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid42_fpArctanXTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid42_fpArctanXTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid61_fpArctanXTest_q : std_logic_vector (36 downto 0);
signal normBit_uid71_fpArctanXTest_in : std_logic_vector (49 downto 0);
signal normBit_uid71_fpArctanXTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid72_fpArctanXTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid72_fpArctanXTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid73_fpArctanXTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid73_fpArctanXTest_b : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid222_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid182_fxpU_uid63_fpArctanXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid219_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid185_fxpU_uid63_fpArctanXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid225_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid251_pT1_uid193_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid251_pT1_uid193_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid254_pT2_uid199_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid254_pT2_uid199_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid257_pT1_uid238_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid257_pT1_uid238_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid260_pT2_uid244_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid260_pT2_uid244_invPolyEval_b : std_logic_vector (22 downto 0);
signal R_uid163_z_uid48_fpArctanXTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (24 downto 0);
signal u_uid49_fpArctanXTest_s : std_logic_vector (0 downto 0);
signal u_uid49_fpArctanXTest_q : std_logic_vector (31 downto 0);
signal pathSelBits_uid99_fpArctanXTest_q : std_logic_vector (2 downto 0);
signal yPPolyEval_uid144_z_uid48_fpArctanXTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid144_z_uid48_fpArctanXTest_b : std_logic_vector (14 downto 0);
signal fpPiO2C_uid40_fpArctanXTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid43_fpArctanXTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid45_fpArctanXTest_s : std_logic_vector (0 downto 0);
signal constOut_uid45_fpArctanXTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid49_fpArctanXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid111_fpArctanXTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid79_fpArctanXTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid79_fpArctanXTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid80_fpArctanXTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid80_fpArctanXTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid97_fpArctanXTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid97_fpArctanXTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid98_fpArctanXTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid98_fpArctanXTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid206_fxpOp2Path2_uid87_fpArctanXTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid206_fxpOp2Path2_uid87_fpArctanXTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid209_fxpOp2Path2_uid87_fpArctanXTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid209_fxpOp2Path2_uid87_fpArctanXTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid212_fxpOp2Path2_uid87_fpArctanXTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid212_fxpOp2Path2_uid87_fpArctanXTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid139_uid139_z_uid48_fpArctanXTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid137_z_uid48_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid137_z_uid48_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid28_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid28_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid136_z_uid48_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid136_z_uid48_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid57_fpArctanXTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid57_fpArctanXTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid59_fpArctanXTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid59_fpArctanXTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid83_fpArctanXTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid83_fpArctanXTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid90_fpArctanXTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid90_fpArctanXTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid91_fpArctanXTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid91_fpArctanXTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid92_fpArctanXTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid92_fpArctanXTest_b : std_logic_vector (23 downto 0);
signal expRComp_uid148_z_uid48_fpArctanXTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid148_z_uid48_fpArctanXTest_b : std_logic_vector (7 downto 0);
signal udf_uid149_z_uid48_fpArctanXTest_in : std_logic_vector (9 downto 0);
signal udf_uid149_z_uid48_fpArctanXTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid151_z_uid48_fpArctanXTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid151_z_uid48_fpArctanXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid178_fxpU_uid63_fpArctanXTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid178_fxpU_uid63_fpArctanXTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid181_fxpU_uid63_fpArctanXTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid181_fxpU_uid63_fpArctanXTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid184_fxpU_uid63_fpArctanXTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid184_fxpU_uid63_fpArctanXTest_b : std_logic_vector (33 downto 0);
signal X32dto0_uid167_fxpU_uid63_fpArctanXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid167_fxpU_uid63_fpArctanXTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid170_fxpU_uid63_fpArctanXTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid170_fxpU_uid63_fpArctanXTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid173_fxpU_uid63_fpArctanXTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid173_fxpU_uid63_fpArctanXTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid74_fpArctanXTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid74_fpArctanXTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid75_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid75_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal lowRangeB_uid194_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid194_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid195_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid195_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid200_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid200_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid201_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid201_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid239_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid239_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid240_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid240_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid245_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid245_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid246_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid246_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid64_fpArctanXTest_in : std_logic_vector (35 downto 0);
signal y_uid64_fpArctanXTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid228_fxpOp2Path2_uid87_fpArctanXTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid228_fxpOp2Path2_uid87_fpArctanXTest_b : std_logic_vector (23 downto 0);
signal expU_uid50_fpArctanXTest_in : std_logic_vector (30 downto 0);
signal expU_uid50_fpArctanXTest_b : std_logic_vector (7 downto 0);
signal fracU_uid51_fpArctanXTest_in : std_logic_vector (22 downto 0);
signal fracU_uid51_fpArctanXTest_b : std_logic_vector (22 downto 0);
signal yT1_uid237_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid237_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid101_fpArctanXTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid101_fpArctanXTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid103_fpArctanXTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid103_fpArctanXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid208_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid211_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid214_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (24 downto 0);
signal y_uid141_z_uid48_fpArctanXTest_in : std_logic_vector (22 downto 0);
signal y_uid141_z_uid48_fpArctanXTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid29_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid29_fpArctanXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid29_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid62_fpArctanXTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid62_fpArctanXTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid84_fpArctanXTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid84_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid93_fpArctanXTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid93_fpArctanXTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid94_fpArctanXTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid94_fpArctanXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1_uid168_fxpU_uid63_fpArctanXTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid171_fxpU_uid63_fpArctanXTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid174_fxpU_uid63_fpArctanXTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid76_fpArctanXTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid76_fpArctanXTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid76_fpArctanXTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid76_fpArctanXTest_q : std_logic_vector (8 downto 0);
signal sumAHighB_uid196_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid196_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid196_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid196_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid202_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid202_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid202_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid202_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid241_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid241_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid241_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid241_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid247_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid247_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid247_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid247_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid66_fpArctanXTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid66_fpArctanXTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid67_fpArctanXTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid67_fpArctanXTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid230_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid143_z_uid48_fpArctanXTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid143_z_uid48_fpArctanXTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid109_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid109_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid86_fpArctanXTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid86_fpArctanXTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid95_uid95_fpArctanXTest_q : std_logic_vector (31 downto 0);
signal expFracPreRnd_uid77_fpArctanXTest_q : std_logic_vector (32 downto 0);
signal s1_uid194_uid197_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid200_uid203_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid239_uid242_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid245_uid248_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid192_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid192_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid217_fxpOp2Path2_uid87_fpArctanXTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid217_fxpOp2Path2_uid87_fpArctanXTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid220_fxpOp2Path2_uid87_fpArctanXTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid220_fxpOp2Path2_uid87_fpArctanXTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid223_fxpOp2Path2_uid87_fpArctanXTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid223_fxpOp2Path2_uid87_fpArctanXTest_b : std_logic_vector (18 downto 0);
signal signR_uid110_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpArctanXTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid138_z_uid48_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid138_z_uid48_fpArctanXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid138_z_uid48_fpArctanXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid138_z_uid48_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_b : std_logic_vector (0 downto 0);
signal fxpAtanXOXRes_uid69_fpArctanXTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid69_fpArctanXTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid146_z_uid48_fpArctanXTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid146_z_uid48_fpArctanXTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid87_uid88_fpArctanXTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid155_z_uid48_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid155_z_uid48_fpArctanXTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid155_z_uid48_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid152_z_uid48_fpArctanXTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid152_z_uid48_fpArctanXTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid156_z_uid48_fpArctanXTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid156_z_uid48_fpArctanXTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid156_z_uid48_fpArctanXTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid157_z_uid48_fpArctanXTest_q : std_logic_vector (2 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable(LOGICAL,623)
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_a <= en;
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q <= not ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_a;
--ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_nor(LOGICAL,715)
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_nor_b <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_sticky_ena_q;
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_nor_q <= not (ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_nor_a or ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_nor_b);
--ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_mem_top(CONSTANT,711)
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_mem_top_q <= "0100001";
--ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmp(LOGICAL,712)
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmp_a <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_mem_top_q;
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdmux_q);
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmp_q <= "1" when ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmp_a = ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmp_b else "0";
--ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmpReg(REG,713)
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmpReg_q <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_sticky_ena(REG,716)
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_nor_q = "1") THEN
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_sticky_ena_q <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_enaAnd(LOGICAL,717)
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_enaAnd_a <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_sticky_ena_q;
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_enaAnd_b <= en;
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_enaAnd_q <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_enaAnd_a and ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_enaAnd_b;
--cstAllZWF_uid10_fpArctanXTest(CONSTANT,9)
cstAllZWF_uid10_fpArctanXTest_q <= "00000000000000000000000";
--fracX_uid7_fpArctanXTest(BITSELECT,6)@0
fracX_uid7_fpArctanXTest_in <= a(22 downto 0);
fracX_uid7_fpArctanXTest_b <= fracX_uid7_fpArctanXTest_in(22 downto 0);
--fracXIsZero_uid26_fpArctanXTest(LOGICAL,25)@0
fracXIsZero_uid26_fpArctanXTest_a <= fracX_uid7_fpArctanXTest_b;
fracXIsZero_uid26_fpArctanXTest_b <= cstAllZWF_uid10_fpArctanXTest_q;
fracXIsZero_uid26_fpArctanXTest_q <= "1" when fracXIsZero_uid26_fpArctanXTest_a = fracXIsZero_uid26_fpArctanXTest_b else "0";
--InvFracXIsZero_uid28_fpArctanXTest(LOGICAL,27)@0
InvFracXIsZero_uid28_fpArctanXTest_a <= fracXIsZero_uid26_fpArctanXTest_q;
InvFracXIsZero_uid28_fpArctanXTest_q <= not InvFracXIsZero_uid28_fpArctanXTest_a;
--cstAllOWE_uid9_fpArctanXTest(CONSTANT,8)
cstAllOWE_uid9_fpArctanXTest_q <= "11111111";
--expX_uid6_fpArctanXTest(BITSELECT,5)@0
expX_uid6_fpArctanXTest_in <= a(30 downto 0);
expX_uid6_fpArctanXTest_b <= expX_uid6_fpArctanXTest_in(30 downto 23);
--expXIsMax_uid24_fpArctanXTest(LOGICAL,23)@0
expXIsMax_uid24_fpArctanXTest_a <= expX_uid6_fpArctanXTest_b;
expXIsMax_uid24_fpArctanXTest_b <= cstAllOWE_uid9_fpArctanXTest_q;
expXIsMax_uid24_fpArctanXTest_q <= "1" when expXIsMax_uid24_fpArctanXTest_a = expXIsMax_uid24_fpArctanXTest_b else "0";
--exc_N_uid29_fpArctanXTest(LOGICAL,28)@0
exc_N_uid29_fpArctanXTest_a <= expXIsMax_uid24_fpArctanXTest_q;
exc_N_uid29_fpArctanXTest_b <= InvFracXIsZero_uid28_fpArctanXTest_q;
exc_N_uid29_fpArctanXTest_q <= exc_N_uid29_fpArctanXTest_a and exc_N_uid29_fpArctanXTest_b;
--InvExc_N_uid109_fpArctanXTest(LOGICAL,108)@0
InvExc_N_uid109_fpArctanXTest_a <= exc_N_uid29_fpArctanXTest_q;
InvExc_N_uid109_fpArctanXTest_q <= not InvExc_N_uid109_fpArctanXTest_a;
--singX_uid8_fpArctanXTest(BITSELECT,7)@0
singX_uid8_fpArctanXTest_in <= a;
singX_uid8_fpArctanXTest_b <= singX_uid8_fpArctanXTest_in(31 downto 31);
--signR_uid110_fpArctanXTest(LOGICAL,109)@0
signR_uid110_fpArctanXTest_a <= singX_uid8_fpArctanXTest_b;
signR_uid110_fpArctanXTest_b <= InvExc_N_uid109_fpArctanXTest_q;
signR_uid110_fpArctanXTest_q <= signR_uid110_fpArctanXTest_a and signR_uid110_fpArctanXTest_b;
--ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_inputreg(DELAY,705)
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid110_fpArctanXTest_q, xout => ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt(COUNTER,707)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_i <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_i <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_i,6));
--ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdreg(REG,708)
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdreg_q <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdmux(MUX,709)
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdmux_s <= en;
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdmux: PROCESS (ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdmux_s, ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdreg_q, ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdmux_q <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdmux_q <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem(DUALMEM,706)
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_ia <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_inputreg_q;
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_aa <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdreg_q;
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_ab <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_rdmux_q;
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_iq,
address_a => ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_aa,
data_a => ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_ia
);
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_reset0 <= areset;
ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_q <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_nor(LOGICAL,624)
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_nor_b <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_sticky_ena_q;
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_nor_q <= not (ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_nor_a or ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_nor_b);
--ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_mem_top(CONSTANT,620)
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_mem_top_q <= "0100000";
--ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmp(LOGICAL,621)
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmp_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_mem_top_q;
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_q);
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmp_q <= "1" when ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmp_a = ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmp_b else "0";
--ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmpReg(REG,622)
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmpReg_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_sticky_ena(REG,625)
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_nor_q = "1") THEN
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_sticky_ena_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_enaAnd(LOGICAL,626)
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_enaAnd_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_sticky_ena_q;
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_enaAnd_b <= en;
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_enaAnd_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_enaAnd_a and ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_enaAnd_b;
--ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_inputreg(DELAY,614)
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid8_fpArctanXTest_b, xout => ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt(COUNTER,616)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_i <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_i <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_i,6));
--ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg(REG,617)
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux(MUX,618)
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_s <= en;
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux: PROCESS (ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_s, ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg_q, ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem(DUALMEM,615)
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_ia <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_inputreg_q;
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_aa <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg_q;
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_ab <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_q;
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_iq,
address_a => ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_aa,
data_a => ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_ia
);
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_reset0 <= areset;
ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid13_fpArctanXTest(CONSTANT,12)
cstBias_uid13_fpArctanXTest_q <= "01111111";
--piO2_uid37_fpArctanXTest(CONSTANT,36)
piO2_uid37_fpArctanXTest_q <= "11001001000011111101101011";
--cstPiO2_uid39_fpArctanXTest(BITSELECT,38)@35
cstPiO2_uid39_fpArctanXTest_in <= piO2_uid37_fpArctanXTest_q(24 downto 0);
cstPiO2_uid39_fpArctanXTest_b <= cstPiO2_uid39_fpArctanXTest_in(24 downto 2);
--fpPiO2C_uid40_fpArctanXTest(BITJOIN,39)@35
fpPiO2C_uid40_fpArctanXTest_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_q & cstBias_uid13_fpArctanXTest_q & cstPiO2_uid39_fpArctanXTest_b;
--cstBiasM1_uid14_fpArctanXTest(CONSTANT,13)
cstBiasM1_uid14_fpArctanXTest_q <= "01111110";
--piO4_uid38_fpArctanXTest(CONSTANT,37)
piO4_uid38_fpArctanXTest_q <= "110010010000111111011011";
--cstPiO4_uid42_fpArctanXTest(BITSELECT,41)@35
cstPiO4_uid42_fpArctanXTest_in <= piO4_uid38_fpArctanXTest_q(22 downto 0);
cstPiO4_uid42_fpArctanXTest_b <= cstPiO4_uid42_fpArctanXTest_in(22 downto 0);
--fpPiO4C_uid43_fpArctanXTest(BITJOIN,42)@35
fpPiO4C_uid43_fpArctanXTest_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_mem_q & cstBiasM1_uid14_fpArctanXTest_q & cstPiO4_uid42_fpArctanXTest_b;
--ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_nor(LOGICAL,637)
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_nor_b <= ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_sticky_ena_q;
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_nor_q <= not (ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_nor_a or ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_nor_b);
--ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_sticky_ena(REG,638)
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_nor_q = "1") THEN
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_sticky_ena_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_enaAnd(LOGICAL,639)
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_enaAnd_a <= ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_sticky_ena_q;
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_enaAnd_b <= en;
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_enaAnd_q <= ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_enaAnd_a and ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_enaAnd_b;
--exc_I_uid27_fpArctanXTest(LOGICAL,26)@0
exc_I_uid27_fpArctanXTest_a <= expXIsMax_uid24_fpArctanXTest_q;
exc_I_uid27_fpArctanXTest_b <= fracXIsZero_uid26_fpArctanXTest_q;
exc_I_uid27_fpArctanXTest_q <= exc_I_uid27_fpArctanXTest_a and exc_I_uid27_fpArctanXTest_b;
--ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_inputreg(DELAY,627)
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid27_fpArctanXTest_q, xout => ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem(DUALMEM,628)
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_ia <= ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_inputreg_q;
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_aa <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg_q;
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_ab <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_q;
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_iq,
address_a => ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_aa,
data_a => ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_ia
);
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_q <= ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_iq(0 downto 0);
--constOut_uid45_fpArctanXTest(MUX,44)@35
constOut_uid45_fpArctanXTest_s <= ld_exc_I_uid27_fpArctanXTest_q_to_constOut_uid45_fpArctanXTest_b_replace_mem_q;
constOut_uid45_fpArctanXTest: PROCESS (constOut_uid45_fpArctanXTest_s, en, fpPiO4C_uid43_fpArctanXTest_q, fpPiO2C_uid40_fpArctanXTest_q)
BEGIN
CASE constOut_uid45_fpArctanXTest_s IS
WHEN "0" => constOut_uid45_fpArctanXTest_q <= fpPiO4C_uid43_fpArctanXTest_q;
WHEN "1" => constOut_uid45_fpArctanXTest_q <= fpPiO2C_uid40_fpArctanXTest_q;
WHEN OTHERS => constOut_uid45_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid103_fpArctanXTest(BITSELECT,102)@35
expOutCst_uid103_fpArctanXTest_in <= constOut_uid45_fpArctanXTest_q(30 downto 0);
expOutCst_uid103_fpArctanXTest_b <= expOutCst_uid103_fpArctanXTest_in(30 downto 23);
--reg_expOutCst_uid103_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_5(REG,318)@35
reg_expOutCst_uid103_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid103_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid103_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_5_q <= expOutCst_uid103_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid60_fpArctanXTest(CONSTANT,59)
cst01pWShift_uid60_fpArctanXTest_q <= "0000000000000";
--ld_signR_uid110_fpArctanXTest_q_to_reg_signR_uid110_fpArctanXTest_0_to_R_uid163_z_uid48_fpArctanXTest_2_a(DELAY,574)@0
ld_signR_uid110_fpArctanXTest_q_to_reg_signR_uid110_fpArctanXTest_0_to_R_uid163_z_uid48_fpArctanXTest_2_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid110_fpArctanXTest_q, xout => ld_signR_uid110_fpArctanXTest_q_to_reg_signR_uid110_fpArctanXTest_0_to_R_uid163_z_uid48_fpArctanXTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_signR_uid110_fpArctanXTest_0_to_R_uid163_z_uid48_fpArctanXTest_2(REG,279)@11
reg_signR_uid110_fpArctanXTest_0_to_R_uid163_z_uid48_fpArctanXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid110_fpArctanXTest_0_to_R_uid163_z_uid48_fpArctanXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid110_fpArctanXTest_0_to_R_uid163_z_uid48_fpArctanXTest_2_q <= ld_signR_uid110_fpArctanXTest_q_to_reg_signR_uid110_fpArctanXTest_0_to_R_uid163_z_uid48_fpArctanXTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_nor(LOGICAL,729)
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_nor_b <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_sticky_ena_q;
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_nor_q <= not (ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_nor_a or ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_nor_b);
--ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_mem_top(CONSTANT,725)
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmp(LOGICAL,726)
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmp_a <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_mem_top_q;
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdmux_q);
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmp_q <= "1" when ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmp_a = ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmp_b else "0";
--ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmpReg(REG,727)
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmpReg_q <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_sticky_ena(REG,730)
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_nor_q = "1") THEN
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_sticky_ena_q <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_enaAnd(LOGICAL,731)
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_enaAnd_a <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_sticky_ena_q;
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_enaAnd_b <= en;
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_enaAnd_q <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_enaAnd_a and ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_enaAnd_b;
--cst2Bias_uid121_z_uid48_fpArctanXTest(CONSTANT,120)
cst2Bias_uid121_z_uid48_fpArctanXTest_q <= "11111110";
--expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest(SUB,149)@0
expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid121_z_uid48_fpArctanXTest_q);
expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArctanXTest_b);
expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest_a) - UNSIGNED(expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest_b));
expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest_q <= expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest_o(8 downto 0);
--expRCompYIsOne_uid151_z_uid48_fpArctanXTest(BITSELECT,150)@0
expRCompYIsOne_uid151_z_uid48_fpArctanXTest_in <= expRCompYIsOneExt_uid150_z_uid48_fpArctanXTest_q(7 downto 0);
expRCompYIsOne_uid151_z_uid48_fpArctanXTest_b <= expRCompYIsOne_uid151_z_uid48_fpArctanXTest_in(7 downto 0);
--cst2BiasM1_uid120_z_uid48_fpArctanXTest(CONSTANT,119)
cst2BiasM1_uid120_z_uid48_fpArctanXTest_q <= "11111101";
--expRCompExt_uid147_z_uid48_fpArctanXTest(SUB,146)@0
expRCompExt_uid147_z_uid48_fpArctanXTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid120_z_uid48_fpArctanXTest_q);
expRCompExt_uid147_z_uid48_fpArctanXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArctanXTest_b);
expRCompExt_uid147_z_uid48_fpArctanXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid147_z_uid48_fpArctanXTest_a) - UNSIGNED(expRCompExt_uid147_z_uid48_fpArctanXTest_b));
expRCompExt_uid147_z_uid48_fpArctanXTest_q <= expRCompExt_uid147_z_uid48_fpArctanXTest_o(8 downto 0);
--expRComp_uid148_z_uid48_fpArctanXTest(BITSELECT,147)@0
expRComp_uid148_z_uid48_fpArctanXTest_in <= expRCompExt_uid147_z_uid48_fpArctanXTest_q(7 downto 0);
expRComp_uid148_z_uid48_fpArctanXTest_b <= expRComp_uid148_z_uid48_fpArctanXTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid140_z_uid48_fpArctanXTest(LOGICAL,139)@0
fracXIsZero_uid140_z_uid48_fpArctanXTest_a <= fracX_uid7_fpArctanXTest_b;
fracXIsZero_uid140_z_uid48_fpArctanXTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid140_z_uid48_fpArctanXTest_q <= "1" when fracXIsZero_uid140_z_uid48_fpArctanXTest_a = fracXIsZero_uid140_z_uid48_fpArctanXTest_b else "0";
--expRCalc_uid154_z_uid48_fpArctanXTest(MUX,153)@0
expRCalc_uid154_z_uid48_fpArctanXTest_s <= fracXIsZero_uid140_z_uid48_fpArctanXTest_q;
expRCalc_uid154_z_uid48_fpArctanXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid154_z_uid48_fpArctanXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid154_z_uid48_fpArctanXTest_s IS
WHEN "0" => expRCalc_uid154_z_uid48_fpArctanXTest_q <= expRComp_uid148_z_uid48_fpArctanXTest_b;
WHEN "1" => expRCalc_uid154_z_uid48_fpArctanXTest_q <= expRCompYIsOne_uid151_z_uid48_fpArctanXTest_b;
WHEN OTHERS => expRCalc_uid154_z_uid48_fpArctanXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid22_fpArctanXTest(LOGICAL,21)@0
expXIsZero_uid22_fpArctanXTest_a <= expX_uid6_fpArctanXTest_b;
expXIsZero_uid22_fpArctanXTest_b <= cstAllZWE_uid12_fpArctanXTest_q;
expXIsZero_uid22_fpArctanXTest_q <= "1" when expXIsZero_uid22_fpArctanXTest_a = expXIsZero_uid22_fpArctanXTest_b else "0";
--udf_uid149_z_uid48_fpArctanXTest(BITSELECT,148)@0
udf_uid149_z_uid48_fpArctanXTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid147_z_uid48_fpArctanXTest_q(8)) & expRCompExt_uid147_z_uid48_fpArctanXTest_q);
udf_uid149_z_uid48_fpArctanXTest_b <= udf_uid149_z_uid48_fpArctanXTest_in(9 downto 9);
--InvExc_I_uid136_z_uid48_fpArctanXTest(LOGICAL,135)@0
InvExc_I_uid136_z_uid48_fpArctanXTest_a <= exc_I_uid27_fpArctanXTest_q;
InvExc_I_uid136_z_uid48_fpArctanXTest_q <= not InvExc_I_uid136_z_uid48_fpArctanXTest_a;
--InvExpXIsZero_uid137_z_uid48_fpArctanXTest(LOGICAL,136)@0
InvExpXIsZero_uid137_z_uid48_fpArctanXTest_a <= expXIsZero_uid22_fpArctanXTest_q;
InvExpXIsZero_uid137_z_uid48_fpArctanXTest_q <= not InvExpXIsZero_uid137_z_uid48_fpArctanXTest_a;
--exc_R_uid138_z_uid48_fpArctanXTest(LOGICAL,137)@0
exc_R_uid138_z_uid48_fpArctanXTest_a <= InvExpXIsZero_uid137_z_uid48_fpArctanXTest_q;
exc_R_uid138_z_uid48_fpArctanXTest_b <= InvExc_I_uid136_z_uid48_fpArctanXTest_q;
exc_R_uid138_z_uid48_fpArctanXTest_c <= InvExc_N_uid109_fpArctanXTest_q;
exc_R_uid138_z_uid48_fpArctanXTest_q <= exc_R_uid138_z_uid48_fpArctanXTest_a and exc_R_uid138_z_uid48_fpArctanXTest_b and exc_R_uid138_z_uid48_fpArctanXTest_c;
--xRegAndUdf_uid155_z_uid48_fpArctanXTest(LOGICAL,154)@0
xRegAndUdf_uid155_z_uid48_fpArctanXTest_a <= exc_R_uid138_z_uid48_fpArctanXTest_q;
xRegAndUdf_uid155_z_uid48_fpArctanXTest_b <= udf_uid149_z_uid48_fpArctanXTest_b;
xRegAndUdf_uid155_z_uid48_fpArctanXTest_q <= xRegAndUdf_uid155_z_uid48_fpArctanXTest_a and xRegAndUdf_uid155_z_uid48_fpArctanXTest_b;
--xIOrXRUdf_uid156_z_uid48_fpArctanXTest(LOGICAL,155)@0
xIOrXRUdf_uid156_z_uid48_fpArctanXTest_a <= exc_I_uid27_fpArctanXTest_q;
xIOrXRUdf_uid156_z_uid48_fpArctanXTest_b <= xRegAndUdf_uid155_z_uid48_fpArctanXTest_q;
xIOrXRUdf_uid156_z_uid48_fpArctanXTest_q <= xIOrXRUdf_uid156_z_uid48_fpArctanXTest_a or xIOrXRUdf_uid156_z_uid48_fpArctanXTest_b;
--excSelBits_uid157_z_uid48_fpArctanXTest(BITJOIN,156)@0
excSelBits_uid157_z_uid48_fpArctanXTest_q <= exc_N_uid29_fpArctanXTest_q & expXIsZero_uid22_fpArctanXTest_q & xIOrXRUdf_uid156_z_uid48_fpArctanXTest_q;
--reg_excSelBits_uid157_z_uid48_fpArctanXTest_0_to_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0(REG,268)@0
reg_excSelBits_uid157_z_uid48_fpArctanXTest_0_to_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid157_z_uid48_fpArctanXTest_0_to_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid157_z_uid48_fpArctanXTest_0_to_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_q <= excSelBits_uid157_z_uid48_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid158_z_uid48_fpArctanXTest(LOOKUP,157)@1
outMuxSelEnc_uid158_z_uid48_fpArctanXTest: PROCESS (reg_excSelBits_uid157_z_uid48_fpArctanXTest_0_to_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid157_z_uid48_fpArctanXTest_0_to_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid158_z_uid48_fpArctanXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid158_z_uid48_fpArctanXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid158_z_uid48_fpArctanXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid158_z_uid48_fpArctanXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid158_z_uid48_fpArctanXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid158_z_uid48_fpArctanXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid158_z_uid48_fpArctanXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid158_z_uid48_fpArctanXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid158_z_uid48_fpArctanXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid160_z_uid48_fpArctanXTest(MUX,159)@1
expRPostExc_uid160_z_uid48_fpArctanXTest_s <= outMuxSelEnc_uid158_z_uid48_fpArctanXTest_q;
expRPostExc_uid160_z_uid48_fpArctanXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid160_z_uid48_fpArctanXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid160_z_uid48_fpArctanXTest_s IS
WHEN "00" => expRPostExc_uid160_z_uid48_fpArctanXTest_q <= cstAllZWE_uid12_fpArctanXTest_q;
WHEN "01" => expRPostExc_uid160_z_uid48_fpArctanXTest_q <= expRCalc_uid154_z_uid48_fpArctanXTest_q;
WHEN "10" => expRPostExc_uid160_z_uid48_fpArctanXTest_q <= cstAllOWE_uid9_fpArctanXTest_q;
WHEN "11" => expRPostExc_uid160_z_uid48_fpArctanXTest_q <= cstAllOWE_uid9_fpArctanXTest_q;
WHEN OTHERS => expRPostExc_uid160_z_uid48_fpArctanXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_inputreg(DELAY,719)
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid160_z_uid48_fpArctanXTest_q, xout => ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdcnt(COUNTER,721)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdreg(REG,722)
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdreg_q <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdmux(MUX,723)
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdmux_s, ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdreg_q, ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdmux_q <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdmux_q <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem(DUALMEM,720)
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_ia <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_inputreg_q;
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_aa <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdreg_q;
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_ab <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_rdmux_q;
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_ia
);
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_q <= ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid11_fpArctanXTest(CONSTANT,10)
cstNaNWF_uid11_fpArctanXTest_q <= "00000000000000000000001";
--oFracX_uid139_uid139_z_uid48_fpArctanXTest(BITJOIN,138)@0
oFracX_uid139_uid139_z_uid48_fpArctanXTest_q <= VCC_q & fracX_uid7_fpArctanXTest_b;
--y_uid141_z_uid48_fpArctanXTest(BITSELECT,140)@0
y_uid141_z_uid48_fpArctanXTest_in <= oFracX_uid139_uid139_z_uid48_fpArctanXTest_q(22 downto 0);
y_uid141_z_uid48_fpArctanXTest_b <= y_uid141_z_uid48_fpArctanXTest_in(22 downto 0);
--yAddr_uid143_z_uid48_fpArctanXTest(BITSELECT,142)@0
yAddr_uid143_z_uid48_fpArctanXTest_in <= y_uid141_z_uid48_fpArctanXTest_b;
yAddr_uid143_z_uid48_fpArctanXTest_b <= yAddr_uid143_z_uid48_fpArctanXTest_in(22 downto 15);
--reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC2_uid236_invTabGen_lutmem_0(REG,269)@0
reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC2_uid236_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC2_uid236_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC2_uid236_invTabGen_lutmem_0_q <= yAddr_uid143_z_uid48_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid236_invTabGen_lutmem(DUALMEM,266)@1
memoryC2_uid236_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid236_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid236_invTabGen_lutmem_ab <= reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC2_uid236_invTabGen_lutmem_0_q;
memoryC2_uid236_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan_s5_memoryC2_uid236_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid236_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid236_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid236_invTabGen_lutmem_iq,
address_a => memoryC2_uid236_invTabGen_lutmem_aa,
data_a => memoryC2_uid236_invTabGen_lutmem_ia
);
memoryC2_uid236_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid236_invTabGen_lutmem_q <= memoryC2_uid236_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid236_invTabGen_lutmem_0_to_prodXY_uid256_pT1_uid238_invPolyEval_1(REG,271)@3
reg_memoryC2_uid236_invTabGen_lutmem_0_to_prodXY_uid256_pT1_uid238_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid236_invTabGen_lutmem_0_to_prodXY_uid256_pT1_uid238_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid236_invTabGen_lutmem_0_to_prodXY_uid256_pT1_uid238_invPolyEval_1_q <= memoryC2_uid236_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid141_z_uid48_fpArctanXTest_b_to_yPPolyEval_uid144_z_uid48_fpArctanXTest_a_inputreg(DELAY,718)
ld_y_uid141_z_uid48_fpArctanXTest_b_to_yPPolyEval_uid144_z_uid48_fpArctanXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid141_z_uid48_fpArctanXTest_b, xout => ld_y_uid141_z_uid48_fpArctanXTest_b_to_yPPolyEval_uid144_z_uid48_fpArctanXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid141_z_uid48_fpArctanXTest_b_to_yPPolyEval_uid144_z_uid48_fpArctanXTest_a(DELAY,436)@0
ld_y_uid141_z_uid48_fpArctanXTest_b_to_yPPolyEval_uid144_z_uid48_fpArctanXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid141_z_uid48_fpArctanXTest_b_to_yPPolyEval_uid144_z_uid48_fpArctanXTest_a_inputreg_q, xout => ld_y_uid141_z_uid48_fpArctanXTest_b_to_yPPolyEval_uid144_z_uid48_fpArctanXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid144_z_uid48_fpArctanXTest(BITSELECT,143)@3
yPPolyEval_uid144_z_uid48_fpArctanXTest_in <= ld_y_uid141_z_uid48_fpArctanXTest_b_to_yPPolyEval_uid144_z_uid48_fpArctanXTest_a_q(14 downto 0);
yPPolyEval_uid144_z_uid48_fpArctanXTest_b <= yPPolyEval_uid144_z_uid48_fpArctanXTest_in(14 downto 0);
--yT1_uid237_invPolyEval(BITSELECT,236)@3
yT1_uid237_invPolyEval_in <= yPPolyEval_uid144_z_uid48_fpArctanXTest_b;
yT1_uid237_invPolyEval_b <= yT1_uid237_invPolyEval_in(14 downto 3);
--reg_yT1_uid237_invPolyEval_0_to_prodXY_uid256_pT1_uid238_invPolyEval_0(REG,270)@3
reg_yT1_uid237_invPolyEval_0_to_prodXY_uid256_pT1_uid238_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid237_invPolyEval_0_to_prodXY_uid256_pT1_uid238_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid237_invPolyEval_0_to_prodXY_uid256_pT1_uid238_invPolyEval_0_q <= yT1_uid237_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid256_pT1_uid238_invPolyEval(MULT,255)@4
prodXY_uid256_pT1_uid238_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid256_pT1_uid238_invPolyEval_a),13)) * SIGNED(prodXY_uid256_pT1_uid238_invPolyEval_b);
prodXY_uid256_pT1_uid238_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid256_pT1_uid238_invPolyEval_a <= (others => '0');
prodXY_uid256_pT1_uid238_invPolyEval_b <= (others => '0');
prodXY_uid256_pT1_uid238_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid256_pT1_uid238_invPolyEval_a <= reg_yT1_uid237_invPolyEval_0_to_prodXY_uid256_pT1_uid238_invPolyEval_0_q;
prodXY_uid256_pT1_uid238_invPolyEval_b <= reg_memoryC2_uid236_invTabGen_lutmem_0_to_prodXY_uid256_pT1_uid238_invPolyEval_1_q;
prodXY_uid256_pT1_uid238_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid256_pT1_uid238_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid256_pT1_uid238_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid256_pT1_uid238_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid256_pT1_uid238_invPolyEval_q <= prodXY_uid256_pT1_uid238_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid257_pT1_uid238_invPolyEval(BITSELECT,256)@7
prodXYTruncFR_uid257_pT1_uid238_invPolyEval_in <= prodXY_uid256_pT1_uid238_invPolyEval_q;
prodXYTruncFR_uid257_pT1_uid238_invPolyEval_b <= prodXYTruncFR_uid257_pT1_uid238_invPolyEval_in(23 downto 11);
--highBBits_uid240_invPolyEval(BITSELECT,239)@7
highBBits_uid240_invPolyEval_in <= prodXYTruncFR_uid257_pT1_uid238_invPolyEval_b;
highBBits_uid240_invPolyEval_b <= highBBits_uid240_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC1_uid235_invTabGen_lutmem_0_q_to_memoryC1_uid235_invTabGen_lutmem_a(DELAY,560)@1
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC1_uid235_invTabGen_lutmem_0_q_to_memoryC1_uid235_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC2_uid236_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC1_uid235_invTabGen_lutmem_0_q_to_memoryC1_uid235_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid235_invTabGen_lutmem(DUALMEM,265)@4
memoryC1_uid235_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid235_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid235_invTabGen_lutmem_ab <= ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC1_uid235_invTabGen_lutmem_0_q_to_memoryC1_uid235_invTabGen_lutmem_a_q;
memoryC1_uid235_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan_s5_memoryC1_uid235_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid235_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid235_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid235_invTabGen_lutmem_iq,
address_a => memoryC1_uid235_invTabGen_lutmem_aa,
data_a => memoryC1_uid235_invTabGen_lutmem_ia
);
memoryC1_uid235_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid235_invTabGen_lutmem_q <= memoryC1_uid235_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid235_invTabGen_lutmem_0_to_sumAHighB_uid241_invPolyEval_0(REG,273)@6
reg_memoryC1_uid235_invTabGen_lutmem_0_to_sumAHighB_uid241_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid235_invTabGen_lutmem_0_to_sumAHighB_uid241_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid235_invTabGen_lutmem_0_to_sumAHighB_uid241_invPolyEval_0_q <= memoryC1_uid235_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid241_invPolyEval(ADD,240)@7
sumAHighB_uid241_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid235_invTabGen_lutmem_0_to_sumAHighB_uid241_invPolyEval_0_q(19)) & reg_memoryC1_uid235_invTabGen_lutmem_0_to_sumAHighB_uid241_invPolyEval_0_q);
sumAHighB_uid241_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid240_invPolyEval_b(11)) & highBBits_uid240_invPolyEval_b);
sumAHighB_uid241_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid241_invPolyEval_a) + SIGNED(sumAHighB_uid241_invPolyEval_b));
sumAHighB_uid241_invPolyEval_q <= sumAHighB_uid241_invPolyEval_o(20 downto 0);
--lowRangeB_uid239_invPolyEval(BITSELECT,238)@7
lowRangeB_uid239_invPolyEval_in <= prodXYTruncFR_uid257_pT1_uid238_invPolyEval_b(0 downto 0);
lowRangeB_uid239_invPolyEval_b <= lowRangeB_uid239_invPolyEval_in(0 downto 0);
--s1_uid239_uid242_invPolyEval(BITJOIN,241)@7
s1_uid239_uid242_invPolyEval_q <= sumAHighB_uid241_invPolyEval_q & lowRangeB_uid239_invPolyEval_b;
--reg_s1_uid239_uid242_invPolyEval_0_to_prodXY_uid259_pT2_uid244_invPolyEval_1(REG,275)@7
reg_s1_uid239_uid242_invPolyEval_0_to_prodXY_uid259_pT2_uid244_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid239_uid242_invPolyEval_0_to_prodXY_uid259_pT2_uid244_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid239_uid242_invPolyEval_0_to_prodXY_uid259_pT2_uid244_invPolyEval_1_q <= s1_uid239_uid242_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_nor(LOGICAL,753)
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_nor_a or ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_cmpReg(REG,751)
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_sticky_ena(REG,754)
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_enaAnd(LOGICAL,755)
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0(REG,274)@3
reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q <= yPPolyEval_uid144_z_uid48_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_inputreg(DELAY,745)
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q, xout => ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdcnt(COUNTER,747)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdcnt_i,1));
--ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdreg(REG,748)
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdmux(MUX,749)
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem(DUALMEM,746)
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_iq(14 downto 0);
--prodXY_uid259_pT2_uid244_invPolyEval(MULT,258)@8
prodXY_uid259_pT2_uid244_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid259_pT2_uid244_invPolyEval_a),16)) * SIGNED(prodXY_uid259_pT2_uid244_invPolyEval_b);
prodXY_uid259_pT2_uid244_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid259_pT2_uid244_invPolyEval_a <= (others => '0');
prodXY_uid259_pT2_uid244_invPolyEval_b <= (others => '0');
prodXY_uid259_pT2_uid244_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid259_pT2_uid244_invPolyEval_a <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_mem_q;
prodXY_uid259_pT2_uid244_invPolyEval_b <= reg_s1_uid239_uid242_invPolyEval_0_to_prodXY_uid259_pT2_uid244_invPolyEval_1_q;
prodXY_uid259_pT2_uid244_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid259_pT2_uid244_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid259_pT2_uid244_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid259_pT2_uid244_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid259_pT2_uid244_invPolyEval_q <= prodXY_uid259_pT2_uid244_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid260_pT2_uid244_invPolyEval(BITSELECT,259)@11
prodXYTruncFR_uid260_pT2_uid244_invPolyEval_in <= prodXY_uid259_pT2_uid244_invPolyEval_q;
prodXYTruncFR_uid260_pT2_uid244_invPolyEval_b <= prodXYTruncFR_uid260_pT2_uid244_invPolyEval_in(36 downto 14);
--highBBits_uid246_invPolyEval(BITSELECT,245)@11
highBBits_uid246_invPolyEval_in <= prodXYTruncFR_uid260_pT2_uid244_invPolyEval_b;
highBBits_uid246_invPolyEval_b <= highBBits_uid246_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_nor(LOGICAL,766)
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_mem_top(CONSTANT,738)
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmp(LOGICAL,739)
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmpReg(REG,740)
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_sticky_ena(REG,767)
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_enaAnd(LOGICAL,768)
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_inputreg(DELAY,756)
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC2_uid236_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt(COUNTER,734)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdreg(REG,735)
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux(MUX,736)
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem(DUALMEM,757)
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid234_invTabGen_lutmem(DUALMEM,264)@8
memoryC0_uid234_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid234_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid234_invTabGen_lutmem_ab <= ld_reg_yAddr_uid143_z_uid48_fpArctanXTest_0_to_memoryC0_uid234_invTabGen_lutmem_0_q_to_memoryC0_uid234_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid234_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan_s5_memoryC0_uid234_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid234_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid234_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid234_invTabGen_lutmem_iq,
address_a => memoryC0_uid234_invTabGen_lutmem_aa,
data_a => memoryC0_uid234_invTabGen_lutmem_ia
);
memoryC0_uid234_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid234_invTabGen_lutmem_q <= memoryC0_uid234_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid234_invTabGen_lutmem_0_to_sumAHighB_uid247_invPolyEval_0(REG,277)@10
reg_memoryC0_uid234_invTabGen_lutmem_0_to_sumAHighB_uid247_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid234_invTabGen_lutmem_0_to_sumAHighB_uid247_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid234_invTabGen_lutmem_0_to_sumAHighB_uid247_invPolyEval_0_q <= memoryC0_uid234_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid247_invPolyEval(ADD,246)@11
sumAHighB_uid247_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid234_invTabGen_lutmem_0_to_sumAHighB_uid247_invPolyEval_0_q(28)) & reg_memoryC0_uid234_invTabGen_lutmem_0_to_sumAHighB_uid247_invPolyEval_0_q);
sumAHighB_uid247_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid246_invPolyEval_b(20)) & highBBits_uid246_invPolyEval_b);
sumAHighB_uid247_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid247_invPolyEval_a) + SIGNED(sumAHighB_uid247_invPolyEval_b));
sumAHighB_uid247_invPolyEval_q <= sumAHighB_uid247_invPolyEval_o(29 downto 0);
--lowRangeB_uid245_invPolyEval(BITSELECT,244)@11
lowRangeB_uid245_invPolyEval_in <= prodXYTruncFR_uid260_pT2_uid244_invPolyEval_b(1 downto 0);
lowRangeB_uid245_invPolyEval_b <= lowRangeB_uid245_invPolyEval_in(1 downto 0);
--s2_uid245_uid248_invPolyEval(BITJOIN,247)@11
s2_uid245_uid248_invPolyEval_q <= sumAHighB_uid247_invPolyEval_q & lowRangeB_uid245_invPolyEval_b;
--fxpInverseRes_uid146_z_uid48_fpArctanXTest(BITSELECT,145)@11
fxpInverseRes_uid146_z_uid48_fpArctanXTest_in <= s2_uid245_uid248_invPolyEval_q(28 downto 0);
fxpInverseRes_uid146_z_uid48_fpArctanXTest_b <= fxpInverseRes_uid146_z_uid48_fpArctanXTest_in(28 downto 5);
--fxpInverseResFrac_uid152_z_uid48_fpArctanXTest(BITSELECT,151)@11
fxpInverseResFrac_uid152_z_uid48_fpArctanXTest_in <= fxpInverseRes_uid146_z_uid48_fpArctanXTest_b(22 downto 0);
fxpInverseResFrac_uid152_z_uid48_fpArctanXTest_b <= fxpInverseResFrac_uid152_z_uid48_fpArctanXTest_in(22 downto 0);
--ld_fracXIsZero_uid140_z_uid48_fpArctanXTest_q_to_fracRCalc_uid153_z_uid48_fpArctanXTest_b(DELAY,444)@0
ld_fracXIsZero_uid140_z_uid48_fpArctanXTest_q_to_fracRCalc_uid153_z_uid48_fpArctanXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid140_z_uid48_fpArctanXTest_q, xout => ld_fracXIsZero_uid140_z_uid48_fpArctanXTest_q_to_fracRCalc_uid153_z_uid48_fpArctanXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid153_z_uid48_fpArctanXTest(MUX,152)@11
fracRCalc_uid153_z_uid48_fpArctanXTest_s <= ld_fracXIsZero_uid140_z_uid48_fpArctanXTest_q_to_fracRCalc_uid153_z_uid48_fpArctanXTest_b_q;
fracRCalc_uid153_z_uid48_fpArctanXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid153_z_uid48_fpArctanXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid153_z_uid48_fpArctanXTest_s IS
WHEN "0" => fracRCalc_uid153_z_uid48_fpArctanXTest_q <= fxpInverseResFrac_uid152_z_uid48_fpArctanXTest_b;
WHEN "1" => fracRCalc_uid153_z_uid48_fpArctanXTest_q <= cstAllZWF_uid10_fpArctanXTest_q;
WHEN OTHERS => fracRCalc_uid153_z_uid48_fpArctanXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_1(REG,278)@1
reg_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_1_q <= outMuxSelEnc_uid158_z_uid48_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_1_q_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_b(DELAY,457)@2
ld_reg_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_1_q_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_1_q, xout => ld_reg_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_1_q_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid159_z_uid48_fpArctanXTest(MUX,158)@12
fracRPostExc_uid159_z_uid48_fpArctanXTest_s <= ld_reg_outMuxSelEnc_uid158_z_uid48_fpArctanXTest_0_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_1_q_to_fracRPostExc_uid159_z_uid48_fpArctanXTest_b_q;
fracRPostExc_uid159_z_uid48_fpArctanXTest: PROCESS (fracRPostExc_uid159_z_uid48_fpArctanXTest_s, en, cstAllZWF_uid10_fpArctanXTest_q, fracRCalc_uid153_z_uid48_fpArctanXTest_q, cstAllZWF_uid10_fpArctanXTest_q, cstNaNWF_uid11_fpArctanXTest_q)
BEGIN
CASE fracRPostExc_uid159_z_uid48_fpArctanXTest_s IS
WHEN "00" => fracRPostExc_uid159_z_uid48_fpArctanXTest_q <= cstAllZWF_uid10_fpArctanXTest_q;
WHEN "01" => fracRPostExc_uid159_z_uid48_fpArctanXTest_q <= fracRCalc_uid153_z_uid48_fpArctanXTest_q;
WHEN "10" => fracRPostExc_uid159_z_uid48_fpArctanXTest_q <= cstAllZWF_uid10_fpArctanXTest_q;
WHEN "11" => fracRPostExc_uid159_z_uid48_fpArctanXTest_q <= cstNaNWF_uid11_fpArctanXTest_q;
WHEN OTHERS => fracRPostExc_uid159_z_uid48_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid163_z_uid48_fpArctanXTest(BITJOIN,162)@12
R_uid163_z_uid48_fpArctanXTest_q <= reg_signR_uid110_fpArctanXTest_0_to_R_uid163_z_uid48_fpArctanXTest_2_q & ld_expRPostExc_uid160_z_uid48_fpArctanXTest_q_to_R_uid163_z_uid48_fpArctanXTest_b_replace_mem_q & fracRPostExc_uid159_z_uid48_fpArctanXTest_q;
--ld_xIn_a_to_u_uid49_fpArctanXTest_c_nor(LOGICAL,650)
ld_xIn_a_to_u_uid49_fpArctanXTest_c_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_xIn_a_to_u_uid49_fpArctanXTest_c_nor_b <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid49_fpArctanXTest_c_nor_q <= not (ld_xIn_a_to_u_uid49_fpArctanXTest_c_nor_a or ld_xIn_a_to_u_uid49_fpArctanXTest_c_nor_b);
--ld_xIn_a_to_u_uid49_fpArctanXTest_c_mem_top(CONSTANT,646)
ld_xIn_a_to_u_uid49_fpArctanXTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmp(LOGICAL,647)
ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmp_a <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_mem_top_q;
ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmp_a = ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmpReg(REG,648)
ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmpReg_q <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid49_fpArctanXTest_c_sticky_ena(REG,651)
ld_xIn_a_to_u_uid49_fpArctanXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid49_fpArctanXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid49_fpArctanXTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid49_fpArctanXTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid49_fpArctanXTest_c_enaAnd(LOGICAL,652)
ld_xIn_a_to_u_uid49_fpArctanXTest_c_enaAnd_a <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid49_fpArctanXTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid49_fpArctanXTest_c_enaAnd_q <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_enaAnd_a and ld_xIn_a_to_u_uid49_fpArctanXTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid49_fpArctanXTest_c_inputreg(DELAY,640)
ld_xIn_a_to_u_uid49_fpArctanXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid49_fpArctanXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt(COUNTER,642)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdreg(REG,643)
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdmux(MUX,644)
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem(DUALMEM,641)
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_inputreg_q;
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid49_fpArctanXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_q <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_iq(31 downto 0);
--path2_uid47_fpArctanXTest(COMPARE,46)@0
path2_uid47_fpArctanXTest_cin <= GND_q;
path2_uid47_fpArctanXTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpArctanXTest_b) & '0';
path2_uid47_fpArctanXTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid13_fpArctanXTest_q) & path2_uid47_fpArctanXTest_cin(0);
path2_uid47_fpArctanXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid47_fpArctanXTest_a) - UNSIGNED(path2_uid47_fpArctanXTest_b));
path2_uid47_fpArctanXTest_n(0) <= not path2_uid47_fpArctanXTest_o(10);
--reg_path2_uid47_fpArctanXTest_2_to_u_uid49_fpArctanXTest_1(REG,280)@0
reg_path2_uid47_fpArctanXTest_2_to_u_uid49_fpArctanXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid47_fpArctanXTest_2_to_u_uid49_fpArctanXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid47_fpArctanXTest_2_to_u_uid49_fpArctanXTest_1_q <= path2_uid47_fpArctanXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid47_fpArctanXTest_2_to_u_uid49_fpArctanXTest_1_q_to_u_uid49_fpArctanXTest_b(DELAY,344)@1
ld_reg_path2_uid47_fpArctanXTest_2_to_u_uid49_fpArctanXTest_1_q_to_u_uid49_fpArctanXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid47_fpArctanXTest_2_to_u_uid49_fpArctanXTest_1_q, xout => ld_reg_path2_uid47_fpArctanXTest_2_to_u_uid49_fpArctanXTest_1_q_to_u_uid49_fpArctanXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid49_fpArctanXTest(MUX,48)@12
u_uid49_fpArctanXTest_s <= ld_reg_path2_uid47_fpArctanXTest_2_to_u_uid49_fpArctanXTest_1_q_to_u_uid49_fpArctanXTest_b_q;
u_uid49_fpArctanXTest: PROCESS (u_uid49_fpArctanXTest_s, en, ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_q, R_uid163_z_uid48_fpArctanXTest_q)
BEGIN
CASE u_uid49_fpArctanXTest_s IS
WHEN "0" => u_uid49_fpArctanXTest_q <= ld_xIn_a_to_u_uid49_fpArctanXTest_c_replace_mem_q;
WHEN "1" => u_uid49_fpArctanXTest_q <= R_uid163_z_uid48_fpArctanXTest_q;
WHEN OTHERS => u_uid49_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid51_fpArctanXTest(BITSELECT,50)@12
fracU_uid51_fpArctanXTest_in <= u_uid49_fpArctanXTest_q(22 downto 0);
fracU_uid51_fpArctanXTest_b <= fracU_uid51_fpArctanXTest_in(22 downto 0);
--ld_fracU_uid51_fpArctanXTest_b_to_oFracU_uid52_uid52_fpArctanXTest_a(DELAY,349)@12
ld_fracU_uid51_fpArctanXTest_b_to_oFracU_uid52_uid52_fpArctanXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid51_fpArctanXTest_b, xout => ld_fracU_uid51_fpArctanXTest_b_to_oFracU_uid52_uid52_fpArctanXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid52_uid52_fpArctanXTest(BITJOIN,51)@13
oFracU_uid52_uid52_fpArctanXTest_q <= VCC_q & ld_fracU_uid51_fpArctanXTest_b_to_oFracU_uid52_uid52_fpArctanXTest_a_q;
--oFracUExt_uid61_fpArctanXTest(BITJOIN,60)@13
oFracUExt_uid61_fpArctanXTest_q <= cst01pWShift_uid60_fpArctanXTest_q & oFracU_uid52_uid52_fpArctanXTest_q;
--X24dto0_uid173_fxpU_uid63_fpArctanXTest(BITSELECT,172)@13
X24dto0_uid173_fxpU_uid63_fpArctanXTest_in <= oFracUExt_uid61_fpArctanXTest_q(24 downto 0);
X24dto0_uid173_fxpU_uid63_fpArctanXTest_b <= X24dto0_uid173_fxpU_uid63_fpArctanXTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid172_fxpU_uid63_fpArctanXTest(CONSTANT,171)
leftShiftStage0Idx3Pad12_uid172_fxpU_uid63_fpArctanXTest_q <= "000000000000";
--leftShiftStage0Idx3_uid174_fxpU_uid63_fpArctanXTest(BITJOIN,173)@13
leftShiftStage0Idx3_uid174_fxpU_uid63_fpArctanXTest_q <= X24dto0_uid173_fxpU_uid63_fpArctanXTest_b & leftShiftStage0Idx3Pad12_uid172_fxpU_uid63_fpArctanXTest_q;
--reg_leftShiftStage0Idx3_uid174_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_5(REG,289)@13
reg_leftShiftStage0Idx3_uid174_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid174_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid174_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_5_q <= leftShiftStage0Idx3_uid174_fxpU_uid63_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid170_fxpU_uid63_fpArctanXTest(BITSELECT,169)@13
X28dto0_uid170_fxpU_uid63_fpArctanXTest_in <= oFracUExt_uid61_fpArctanXTest_q(28 downto 0);
X28dto0_uid170_fxpU_uid63_fpArctanXTest_b <= X28dto0_uid170_fxpU_uid63_fpArctanXTest_in(28 downto 0);
--leftShiftStage0Idx2_uid171_fxpU_uid63_fpArctanXTest(BITJOIN,170)@13
leftShiftStage0Idx2_uid171_fxpU_uid63_fpArctanXTest_q <= X28dto0_uid170_fxpU_uid63_fpArctanXTest_b & cstAllZWE_uid12_fpArctanXTest_q;
--reg_leftShiftStage0Idx2_uid171_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_4(REG,288)@13
reg_leftShiftStage0Idx2_uid171_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid171_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid171_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_4_q <= leftShiftStage0Idx2_uid171_fxpU_uid63_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid167_fxpU_uid63_fpArctanXTest(BITSELECT,166)@13
X32dto0_uid167_fxpU_uid63_fpArctanXTest_in <= oFracUExt_uid61_fpArctanXTest_q(32 downto 0);
X32dto0_uid167_fxpU_uid63_fpArctanXTest_b <= X32dto0_uid167_fxpU_uid63_fpArctanXTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid166_fxpU_uid63_fpArctanXTest(CONSTANT,165)
leftShiftStage0Idx1Pad4_uid166_fxpU_uid63_fpArctanXTest_q <= "0000";
--leftShiftStage0Idx1_uid168_fxpU_uid63_fpArctanXTest(BITJOIN,167)@13
leftShiftStage0Idx1_uid168_fxpU_uid63_fpArctanXTest_q <= X32dto0_uid167_fxpU_uid63_fpArctanXTest_b & leftShiftStage0Idx1Pad4_uid166_fxpU_uid63_fpArctanXTest_q;
--reg_leftShiftStage0Idx1_uid168_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_3(REG,287)@13
reg_leftShiftStage0Idx1_uid168_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid168_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid168_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_3_q <= leftShiftStage0Idx1_uid168_fxpU_uid63_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid61_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_2(REG,286)@13
reg_oFracUExt_uid61_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid61_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid61_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_2_q <= oFracUExt_uid61_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid58_fpArctanXTest(CONSTANT,57)
zS_uid58_fpArctanXTest_q <= "000000000";
--shiftBias_uid55_fpArctanXTest(CONSTANT,54)
shiftBias_uid55_fpArctanXTest_q <= "01110010";
--expU_uid50_fpArctanXTest(BITSELECT,49)@12
expU_uid50_fpArctanXTest_in <= u_uid49_fpArctanXTest_q(30 downto 0);
expU_uid50_fpArctanXTest_b <= expU_uid50_fpArctanXTest_in(30 downto 23);
--reg_expU_uid50_fpArctanXTest_0_to_atanUIsU_uid54_fpArctanXTest_1(REG,281)@12
reg_expU_uid50_fpArctanXTest_0_to_atanUIsU_uid54_fpArctanXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid50_fpArctanXTest_0_to_atanUIsU_uid54_fpArctanXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid50_fpArctanXTest_0_to_atanUIsU_uid54_fpArctanXTest_1_q <= expU_uid50_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid56_fpArctanXTest(SUB,55)@13
shiftValue_uid56_fpArctanXTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid50_fpArctanXTest_0_to_atanUIsU_uid54_fpArctanXTest_1_q);
shiftValue_uid56_fpArctanXTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid55_fpArctanXTest_q);
shiftValue_uid56_fpArctanXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid56_fpArctanXTest_a) - UNSIGNED(shiftValue_uid56_fpArctanXTest_b));
shiftValue_uid56_fpArctanXTest_q <= shiftValue_uid56_fpArctanXTest_o(8 downto 0);
--ShiftValue8_uid57_fpArctanXTest(BITSELECT,56)@13
ShiftValue8_uid57_fpArctanXTest_in <= shiftValue_uid56_fpArctanXTest_q;
ShiftValue8_uid57_fpArctanXTest_b <= ShiftValue8_uid57_fpArctanXTest_in(8 downto 8);
--shiftValuePostNeg_uid59_fpArctanXTest(MUX,58)@13
shiftValuePostNeg_uid59_fpArctanXTest_s <= ShiftValue8_uid57_fpArctanXTest_b;
shiftValuePostNeg_uid59_fpArctanXTest: PROCESS (shiftValuePostNeg_uid59_fpArctanXTest_s, en, shiftValue_uid56_fpArctanXTest_q, zS_uid58_fpArctanXTest_q)
BEGIN
CASE shiftValuePostNeg_uid59_fpArctanXTest_s IS
WHEN "0" => shiftValuePostNeg_uid59_fpArctanXTest_q <= shiftValue_uid56_fpArctanXTest_q;
WHEN "1" => shiftValuePostNeg_uid59_fpArctanXTest_q <= zS_uid58_fpArctanXTest_q;
WHEN OTHERS => shiftValuePostNeg_uid59_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid62_fpArctanXTest(BITSELECT,61)@13
fxpShifterBits_uid62_fpArctanXTest_in <= shiftValuePostNeg_uid59_fpArctanXTest_q(3 downto 0);
fxpShifterBits_uid62_fpArctanXTest_b <= fxpShifterBits_uid62_fpArctanXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest(BITSELECT,174)@13
leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest_in <= fxpShifterBits_uid62_fpArctanXTest_b;
leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest_b <= leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_1(REG,285)@13
reg_leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_1_q <= leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest(MUX,175)@14
leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_s <= reg_leftShiftStageSel3Dto2_uid175_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_1_q;
leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest: PROCESS (leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_s, en, reg_oFracUExt_uid61_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_2_q, reg_leftShiftStage0Idx1_uid168_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_3_q, reg_leftShiftStage0Idx2_uid171_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_4_q, reg_leftShiftStage0Idx3_uid174_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_5_q)
BEGIN
CASE leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_s IS
WHEN "00" => leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_q <= reg_oFracUExt_uid61_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_2_q;
WHEN "01" => leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_q <= reg_leftShiftStage0Idx1_uid168_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_3_q;
WHEN "10" => leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_q <= reg_leftShiftStage0Idx2_uid171_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_4_q;
WHEN "11" => leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_q <= reg_leftShiftStage0Idx3_uid174_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid184_fxpU_uid63_fpArctanXTest(BITSELECT,183)@14
LeftShiftStage033dto0_uid184_fxpU_uid63_fpArctanXTest_in <= leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_q(33 downto 0);
LeftShiftStage033dto0_uid184_fxpU_uid63_fpArctanXTest_b <= LeftShiftStage033dto0_uid184_fxpU_uid63_fpArctanXTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid184_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx3_uid185_fxpU_uid63_fpArctanXTest_b(DELAY,481)@14
ld_LeftShiftStage033dto0_uid184_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx3_uid185_fxpU_uid63_fpArctanXTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid184_fxpU_uid63_fpArctanXTest_b, xout => ld_LeftShiftStage033dto0_uid184_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx3_uid185_fxpU_uid63_fpArctanXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid183_fxpU_uid63_fpArctanXTest(CONSTANT,182)
leftShiftStage1Idx3Pad3_uid183_fxpU_uid63_fpArctanXTest_q <= "000";
--leftShiftStage1Idx3_uid185_fxpU_uid63_fpArctanXTest(BITJOIN,184)@15
leftShiftStage1Idx3_uid185_fxpU_uid63_fpArctanXTest_q <= ld_LeftShiftStage033dto0_uid184_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx3_uid185_fxpU_uid63_fpArctanXTest_b_q & leftShiftStage1Idx3Pad3_uid183_fxpU_uid63_fpArctanXTest_q;
--LeftShiftStage034dto0_uid181_fxpU_uid63_fpArctanXTest(BITSELECT,180)@14
LeftShiftStage034dto0_uid181_fxpU_uid63_fpArctanXTest_in <= leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_q(34 downto 0);
LeftShiftStage034dto0_uid181_fxpU_uid63_fpArctanXTest_b <= LeftShiftStage034dto0_uid181_fxpU_uid63_fpArctanXTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid181_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx2_uid182_fxpU_uid63_fpArctanXTest_b(DELAY,479)@14
ld_LeftShiftStage034dto0_uid181_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx2_uid182_fxpU_uid63_fpArctanXTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid181_fxpU_uid63_fpArctanXTest_b, xout => ld_LeftShiftStage034dto0_uid181_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx2_uid182_fxpU_uid63_fpArctanXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid180_fxpU_uid63_fpArctanXTest(CONSTANT,179)
leftShiftStage1Idx2Pad2_uid180_fxpU_uid63_fpArctanXTest_q <= "00";
--leftShiftStage1Idx2_uid182_fxpU_uid63_fpArctanXTest(BITJOIN,181)@15
leftShiftStage1Idx2_uid182_fxpU_uid63_fpArctanXTest_q <= ld_LeftShiftStage034dto0_uid181_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx2_uid182_fxpU_uid63_fpArctanXTest_b_q & leftShiftStage1Idx2Pad2_uid180_fxpU_uid63_fpArctanXTest_q;
--LeftShiftStage035dto0_uid178_fxpU_uid63_fpArctanXTest(BITSELECT,177)@14
LeftShiftStage035dto0_uid178_fxpU_uid63_fpArctanXTest_in <= leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_q(35 downto 0);
LeftShiftStage035dto0_uid178_fxpU_uid63_fpArctanXTest_b <= LeftShiftStage035dto0_uid178_fxpU_uid63_fpArctanXTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid178_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx1_uid179_fxpU_uid63_fpArctanXTest_b(DELAY,477)@14
ld_LeftShiftStage035dto0_uid178_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx1_uid179_fxpU_uid63_fpArctanXTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid178_fxpU_uid63_fpArctanXTest_b, xout => ld_LeftShiftStage035dto0_uid178_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx1_uid179_fxpU_uid63_fpArctanXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid179_fxpU_uid63_fpArctanXTest(BITJOIN,178)@15
leftShiftStage1Idx1_uid179_fxpU_uid63_fpArctanXTest_q <= ld_LeftShiftStage035dto0_uid178_fxpU_uid63_fpArctanXTest_b_to_leftShiftStage1Idx1_uid179_fxpU_uid63_fpArctanXTest_b_q & GND_q;
--reg_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_2(REG,291)@14
reg_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_2_q <= leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest(BITSELECT,185)@13
leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_in <= fxpShifterBits_uid62_fpArctanXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_b <= leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_1(REG,290)@13
reg_leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_1_q <= leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_1_q_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_b(DELAY,483)@14
ld_reg_leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_1_q_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_1_q_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest(MUX,186)@15
leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_s <= ld_reg_leftShiftStageSel1Dto0_uid186_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_1_q_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_b_q;
leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest: PROCESS (leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_s, en, reg_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_2_q, leftShiftStage1Idx1_uid179_fxpU_uid63_fpArctanXTest_q, leftShiftStage1Idx2_uid182_fxpU_uid63_fpArctanXTest_q, leftShiftStage1Idx3_uid185_fxpU_uid63_fpArctanXTest_q)
BEGIN
CASE leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_s IS
WHEN "00" => leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_q <= reg_leftShiftStage0_uid176_fxpU_uid63_fpArctanXTest_0_to_leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_2_q;
WHEN "01" => leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_q <= leftShiftStage1Idx1_uid179_fxpU_uid63_fpArctanXTest_q;
WHEN "10" => leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_q <= leftShiftStage1Idx2_uid182_fxpU_uid63_fpArctanXTest_q;
WHEN "11" => leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_q <= leftShiftStage1Idx3_uid185_fxpU_uid63_fpArctanXTest_q;
WHEN OTHERS => leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid64_fpArctanXTest(BITSELECT,63)@15
y_uid64_fpArctanXTest_in <= leftShiftStage1_uid187_fxpU_uid63_fpArctanXTest_q(35 downto 0);
y_uid64_fpArctanXTest_b <= y_uid64_fpArctanXTest_in(35 downto 1);
--yAddr_uid66_fpArctanXTest(BITSELECT,65)@15
yAddr_uid66_fpArctanXTest_in <= y_uid64_fpArctanXTest_b;
yAddr_uid66_fpArctanXTest_b <= yAddr_uid66_fpArctanXTest_in(34 downto 27);
--reg_yAddr_uid66_fpArctanXTest_0_to_memoryC2_uid191_atanXOXTabGen_lutmem_0(REG,292)@15
reg_yAddr_uid66_fpArctanXTest_0_to_memoryC2_uid191_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid66_fpArctanXTest_0_to_memoryC2_uid191_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid66_fpArctanXTest_0_to_memoryC2_uid191_atanXOXTabGen_lutmem_0_q <= yAddr_uid66_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid191_atanXOXTabGen_lutmem(DUALMEM,263)@16
memoryC2_uid191_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid191_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid191_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid66_fpArctanXTest_0_to_memoryC2_uid191_atanXOXTabGen_lutmem_0_q;
memoryC2_uid191_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan_s5_memoryC2_uid191_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid191_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid191_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid191_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid191_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid191_atanXOXTabGen_lutmem_ia
);
memoryC2_uid191_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid191_atanXOXTabGen_lutmem_q <= memoryC2_uid191_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid191_atanXOXTabGen_lutmem_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_1(REG,294)@18
reg_memoryC2_uid191_atanXOXTabGen_lutmem_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid191_atanXOXTabGen_lutmem_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid191_atanXOXTabGen_lutmem_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_1_q <= memoryC2_uid191_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid67_fpArctanXTest(BITSELECT,66)@15
yPPolyEval_uid67_fpArctanXTest_in <= y_uid64_fpArctanXTest_b(26 downto 0);
yPPolyEval_uid67_fpArctanXTest_b <= yPPolyEval_uid67_fpArctanXTest_in(26 downto 9);
--yT1_uid192_atanXOXPolyEval(BITSELECT,191)@15
yT1_uid192_atanXOXPolyEval_in <= yPPolyEval_uid67_fpArctanXTest_b;
yT1_uid192_atanXOXPolyEval_b <= yT1_uid192_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid192_atanXOXPolyEval_b_to_reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_a_inputreg(DELAY,782)
ld_yT1_uid192_atanXOXPolyEval_b_to_reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid192_atanXOXPolyEval_b, xout => ld_yT1_uid192_atanXOXPolyEval_b_to_reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid192_atanXOXPolyEval_b_to_reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_a(DELAY,588)@15
ld_yT1_uid192_atanXOXPolyEval_b_to_reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid192_atanXOXPolyEval_b_to_reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid192_atanXOXPolyEval_b_to_reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0(REG,293)@18
reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_q <= ld_yT1_uid192_atanXOXPolyEval_b_to_reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid250_pT1_uid193_atanXOXPolyEval(MULT,249)@19
prodXY_uid250_pT1_uid193_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid250_pT1_uid193_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid250_pT1_uid193_atanXOXPolyEval_b);
prodXY_uid250_pT1_uid193_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid250_pT1_uid193_atanXOXPolyEval_a <= (others => '0');
prodXY_uid250_pT1_uid193_atanXOXPolyEval_b <= (others => '0');
prodXY_uid250_pT1_uid193_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid250_pT1_uid193_atanXOXPolyEval_a <= reg_yT1_uid192_atanXOXPolyEval_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_0_q;
prodXY_uid250_pT1_uid193_atanXOXPolyEval_b <= reg_memoryC2_uid191_atanXOXTabGen_lutmem_0_to_prodXY_uid250_pT1_uid193_atanXOXPolyEval_1_q;
prodXY_uid250_pT1_uid193_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid250_pT1_uid193_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid250_pT1_uid193_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid250_pT1_uid193_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid250_pT1_uid193_atanXOXPolyEval_q <= prodXY_uid250_pT1_uid193_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid251_pT1_uid193_atanXOXPolyEval(BITSELECT,250)@22
prodXYTruncFR_uid251_pT1_uid193_atanXOXPolyEval_in <= prodXY_uid250_pT1_uid193_atanXOXPolyEval_q;
prodXYTruncFR_uid251_pT1_uid193_atanXOXPolyEval_b <= prodXYTruncFR_uid251_pT1_uid193_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid195_atanXOXPolyEval(BITSELECT,194)@22
highBBits_uid195_atanXOXPolyEval_in <= prodXYTruncFR_uid251_pT1_uid193_atanXOXPolyEval_b;
highBBits_uid195_atanXOXPolyEval_b <= highBBits_uid195_atanXOXPolyEval_in(13 downto 1);
--ld_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC1_uid190_atanXOXTabGen_lutmem_0_q_to_memoryC1_uid190_atanXOXTabGen_lutmem_a(DELAY,557)@16
ld_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC1_uid190_atanXOXTabGen_lutmem_0_q_to_memoryC1_uid190_atanXOXTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid66_fpArctanXTest_0_to_memoryC2_uid191_atanXOXTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC1_uid190_atanXOXTabGen_lutmem_0_q_to_memoryC1_uid190_atanXOXTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid190_atanXOXTabGen_lutmem(DUALMEM,262)@19
memoryC1_uid190_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid190_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid190_atanXOXTabGen_lutmem_ab <= ld_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC1_uid190_atanXOXTabGen_lutmem_0_q_to_memoryC1_uid190_atanXOXTabGen_lutmem_a_q;
memoryC1_uid190_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan_s5_memoryC1_uid190_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid190_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid190_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid190_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid190_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid190_atanXOXTabGen_lutmem_ia
);
memoryC1_uid190_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid190_atanXOXTabGen_lutmem_q <= memoryC1_uid190_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid190_atanXOXTabGen_lutmem_0_to_sumAHighB_uid196_atanXOXPolyEval_0(REG,296)@21
reg_memoryC1_uid190_atanXOXTabGen_lutmem_0_to_sumAHighB_uid196_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid190_atanXOXTabGen_lutmem_0_to_sumAHighB_uid196_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid190_atanXOXTabGen_lutmem_0_to_sumAHighB_uid196_atanXOXPolyEval_0_q <= memoryC1_uid190_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid196_atanXOXPolyEval(ADD,195)@22
sumAHighB_uid196_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid190_atanXOXTabGen_lutmem_0_to_sumAHighB_uid196_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid190_atanXOXTabGen_lutmem_0_to_sumAHighB_uid196_atanXOXPolyEval_0_q);
sumAHighB_uid196_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid195_atanXOXPolyEval_b(12)) & highBBits_uid195_atanXOXPolyEval_b);
sumAHighB_uid196_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid196_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid196_atanXOXPolyEval_b));
sumAHighB_uid196_atanXOXPolyEval_q <= sumAHighB_uid196_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid194_atanXOXPolyEval(BITSELECT,193)@22
lowRangeB_uid194_atanXOXPolyEval_in <= prodXYTruncFR_uid251_pT1_uid193_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid194_atanXOXPolyEval_b <= lowRangeB_uid194_atanXOXPolyEval_in(0 downto 0);
--s1_uid194_uid197_atanXOXPolyEval(BITJOIN,196)@22
s1_uid194_uid197_atanXOXPolyEval_q <= sumAHighB_uid196_atanXOXPolyEval_q & lowRangeB_uid194_atanXOXPolyEval_b;
--reg_s1_uid194_uid197_atanXOXPolyEval_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_1(REG,298)@22
reg_s1_uid194_uid197_atanXOXPolyEval_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid194_uid197_atanXOXPolyEval_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid194_uid197_atanXOXPolyEval_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_1_q <= s1_uid194_uid197_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_nor(LOGICAL,742)
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_sticky_ena(REG,743)
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_enaAnd(LOGICAL,744)
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0(REG,297)@15
reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q <= yPPolyEval_uid67_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_inputreg(DELAY,732)
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem(DUALMEM,733)
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid253_pT2_uid199_atanXOXPolyEval(MULT,252)@23
prodXY_uid253_pT2_uid199_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid253_pT2_uid199_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid253_pT2_uid199_atanXOXPolyEval_b);
prodXY_uid253_pT2_uid199_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid253_pT2_uid199_atanXOXPolyEval_a <= (others => '0');
prodXY_uid253_pT2_uid199_atanXOXPolyEval_b <= (others => '0');
prodXY_uid253_pT2_uid199_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid253_pT2_uid199_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid253_pT2_uid199_atanXOXPolyEval_b <= reg_s1_uid194_uid197_atanXOXPolyEval_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_1_q;
prodXY_uid253_pT2_uid199_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid253_pT2_uid199_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid253_pT2_uid199_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid253_pT2_uid199_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid253_pT2_uid199_atanXOXPolyEval_q <= prodXY_uid253_pT2_uid199_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid254_pT2_uid199_atanXOXPolyEval(BITSELECT,253)@26
prodXYTruncFR_uid254_pT2_uid199_atanXOXPolyEval_in <= prodXY_uid253_pT2_uid199_atanXOXPolyEval_q;
prodXYTruncFR_uid254_pT2_uid199_atanXOXPolyEval_b <= prodXYTruncFR_uid254_pT2_uid199_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid201_atanXOXPolyEval(BITSELECT,200)@26
highBBits_uid201_atanXOXPolyEval_in <= prodXYTruncFR_uid254_pT2_uid199_atanXOXPolyEval_b;
highBBits_uid201_atanXOXPolyEval_b <= highBBits_uid201_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,793)
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,794)
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,795)
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,783)
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid66_fpArctanXTest_b, xout => ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,784)
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid67_fpArctanXTest_0_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_0_q_to_prodXY_uid253_pT2_uid199_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0(REG,299)@22
reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid66_fpArctanXTest_b_to_reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid189_atanXOXTabGen_lutmem(DUALMEM,261)@23
memoryC0_uid189_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid189_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid189_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid66_fpArctanXTest_0_to_memoryC0_uid189_atanXOXTabGen_lutmem_0_q;
memoryC0_uid189_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atan_s5_memoryC0_uid189_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid189_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid189_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid189_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid189_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid189_atanXOXTabGen_lutmem_ia
);
memoryC0_uid189_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid189_atanXOXTabGen_lutmem_q <= memoryC0_uid189_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid189_atanXOXTabGen_lutmem_0_to_sumAHighB_uid202_atanXOXPolyEval_0(REG,300)@25
reg_memoryC0_uid189_atanXOXTabGen_lutmem_0_to_sumAHighB_uid202_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid189_atanXOXTabGen_lutmem_0_to_sumAHighB_uid202_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid189_atanXOXTabGen_lutmem_0_to_sumAHighB_uid202_atanXOXPolyEval_0_q <= memoryC0_uid189_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid202_atanXOXPolyEval(ADD,201)@26
sumAHighB_uid202_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid189_atanXOXTabGen_lutmem_0_to_sumAHighB_uid202_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid189_atanXOXTabGen_lutmem_0_to_sumAHighB_uid202_atanXOXPolyEval_0_q);
sumAHighB_uid202_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid201_atanXOXPolyEval_b(21)) & highBBits_uid201_atanXOXPolyEval_b);
sumAHighB_uid202_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid202_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid202_atanXOXPolyEval_b));
sumAHighB_uid202_atanXOXPolyEval_q <= sumAHighB_uid202_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid200_atanXOXPolyEval(BITSELECT,199)@26
lowRangeB_uid200_atanXOXPolyEval_in <= prodXYTruncFR_uid254_pT2_uid199_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid200_atanXOXPolyEval_b <= lowRangeB_uid200_atanXOXPolyEval_in(1 downto 0);
--s2_uid200_uid203_atanXOXPolyEval(BITJOIN,202)@26
s2_uid200_uid203_atanXOXPolyEval_q <= sumAHighB_uid202_atanXOXPolyEval_q & lowRangeB_uid200_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid69_fpArctanXTest(BITSELECT,68)@26
fxpAtanXOXRes_uid69_fpArctanXTest_in <= s2_uid200_uid203_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid69_fpArctanXTest_b <= fxpAtanXOXRes_uid69_fpArctanXTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid69_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_1(REG,302)@26
reg_fxpAtanXOXRes_uid69_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid69_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid69_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_1_q <= fxpAtanXOXRes_uid69_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_nor(LOGICAL,663)
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_nor_b <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_sticky_ena_q;
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_nor_q <= not (ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_nor_a or ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_nor_b);
--ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_mem_top(CONSTANT,659)
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmp(LOGICAL,660)
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmp_a <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_mem_top_q;
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdmux_q);
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmp_q <= "1" when ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmp_a = ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmp_b else "0";
--ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmpReg(REG,661)
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmpReg_q <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_sticky_ena(REG,664)
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_sticky_ena_q <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_enaAnd(LOGICAL,665)
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_enaAnd_a <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_sticky_ena_q;
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_enaAnd_q <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_enaAnd_a and ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_enaAnd_b;
--reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0(REG,301)@13
reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q <= oFracU_uid52_uid52_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_inputreg(DELAY,653)
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q, xout => ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt(COUNTER,655)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdreg(REG,656)
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdreg_q <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdmux(MUX,657)
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdmux_s, ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdreg_q, ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdmux_q <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdmux_q <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem(DUALMEM,654)
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_ia <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_inputreg_q;
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_aa <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdreg_q;
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_ab <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_rdmux_q;
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_ia
);
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_q <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid70_fpArctanXTest(MULT,69)@27
mulXAtanXOXRes_uid70_fpArctanXTest_pr <= UNSIGNED(mulXAtanXOXRes_uid70_fpArctanXTest_a) * UNSIGNED(mulXAtanXOXRes_uid70_fpArctanXTest_b);
mulXAtanXOXRes_uid70_fpArctanXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid70_fpArctanXTest_a <= (others => '0');
mulXAtanXOXRes_uid70_fpArctanXTest_b <= (others => '0');
mulXAtanXOXRes_uid70_fpArctanXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid70_fpArctanXTest_a <= ld_reg_oFracU_uid52_uid52_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_0_q_to_mulXAtanXOXRes_uid70_fpArctanXTest_a_replace_mem_q;
mulXAtanXOXRes_uid70_fpArctanXTest_b <= reg_fxpAtanXOXRes_uid69_fpArctanXTest_0_to_mulXAtanXOXRes_uid70_fpArctanXTest_1_q;
mulXAtanXOXRes_uid70_fpArctanXTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid70_fpArctanXTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid70_fpArctanXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid70_fpArctanXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid70_fpArctanXTest_q <= mulXAtanXOXRes_uid70_fpArctanXTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid71_fpArctanXTest(BITSELECT,70)@30
normBit_uid71_fpArctanXTest_in <= mulXAtanXOXRes_uid70_fpArctanXTest_q(49 downto 0);
normBit_uid71_fpArctanXTest_b <= normBit_uid71_fpArctanXTest_in(49 downto 49);
--InvNormBit_uid75_fpArctanXTest(LOGICAL,74)@30
InvNormBit_uid75_fpArctanXTest_a <= normBit_uid71_fpArctanXTest_b;
InvNormBit_uid75_fpArctanXTest_q <= not InvNormBit_uid75_fpArctanXTest_a;
--ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_nor(LOGICAL,676)
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_nor_b <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_sticky_ena_q;
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_nor_q <= not (ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_nor_a or ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_nor_b);
--ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_mem_top(CONSTANT,672)
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_mem_top_q <= "01111";
--ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmp(LOGICAL,673)
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmp_a <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_mem_top_q;
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdmux_q);
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmp_q <= "1" when ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmp_a = ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmp_b else "0";
--ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmpReg(REG,674)
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmpReg_q <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_sticky_ena(REG,677)
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_nor_q = "1") THEN
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_sticky_ena_q <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_enaAnd(LOGICAL,678)
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_enaAnd_a <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_sticky_ena_q;
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_enaAnd_b <= en;
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_enaAnd_q <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_enaAnd_a and ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_enaAnd_b;
--ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_inputreg(DELAY,666)
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid50_fpArctanXTest_b, xout => ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdcnt(COUNTER,668)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdcnt_i <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdcnt_i,4));
--ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdreg(REG,669)
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdreg_q <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdmux(MUX,670)
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdmux_s <= en;
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdmux: PROCESS (ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdmux_s, ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdreg_q, ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdmux_q <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdmux_q <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem(DUALMEM,667)
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_ia <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_inputreg_q;
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_aa <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdreg_q;
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_ab <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_rdmux_q;
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_iq,
address_a => ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_aa,
data_a => ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_ia
);
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_reset0 <= areset;
ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_q <= ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid76_fpArctanXTest(SUB,75)@30
expRPath3Ext_uid76_fpArctanXTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid50_fpArctanXTest_b_to_expRPath3Ext_uid76_fpArctanXTest_a_replace_mem_q);
expRPath3Ext_uid76_fpArctanXTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid75_fpArctanXTest_q);
expRPath3Ext_uid76_fpArctanXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid76_fpArctanXTest_a) - UNSIGNED(expRPath3Ext_uid76_fpArctanXTest_b));
expRPath3Ext_uid76_fpArctanXTest_q <= expRPath3Ext_uid76_fpArctanXTest_o(8 downto 0);
--fracRPath3High_uid72_fpArctanXTest(BITSELECT,71)@30
fracRPath3High_uid72_fpArctanXTest_in <= mulXAtanXOXRes_uid70_fpArctanXTest_q(48 downto 0);
fracRPath3High_uid72_fpArctanXTest_b <= fracRPath3High_uid72_fpArctanXTest_in(48 downto 25);
--fracRPath3Low_uid73_fpArctanXTest(BITSELECT,72)@30
fracRPath3Low_uid73_fpArctanXTest_in <= mulXAtanXOXRes_uid70_fpArctanXTest_q(47 downto 0);
fracRPath3Low_uid73_fpArctanXTest_b <= fracRPath3Low_uid73_fpArctanXTest_in(47 downto 24);
--fracRPath3Pre_uid74_fpArctanXTest(MUX,73)@30
fracRPath3Pre_uid74_fpArctanXTest_s <= normBit_uid71_fpArctanXTest_b;
fracRPath3Pre_uid74_fpArctanXTest: PROCESS (fracRPath3Pre_uid74_fpArctanXTest_s, en, fracRPath3Low_uid73_fpArctanXTest_b, fracRPath3High_uid72_fpArctanXTest_b)
BEGIN
CASE fracRPath3Pre_uid74_fpArctanXTest_s IS
WHEN "0" => fracRPath3Pre_uid74_fpArctanXTest_q <= fracRPath3Low_uid73_fpArctanXTest_b;
WHEN "1" => fracRPath3Pre_uid74_fpArctanXTest_q <= fracRPath3High_uid72_fpArctanXTest_b;
WHEN OTHERS => fracRPath3Pre_uid74_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid77_fpArctanXTest(BITJOIN,76)@30
expFracPreRnd_uid77_fpArctanXTest_q <= expRPath3Ext_uid76_fpArctanXTest_q & fracRPath3Pre_uid74_fpArctanXTest_q;
--reg_expFracPreRnd_uid77_fpArctanXTest_0_to_expfracRPath3PostRnd_uid78_fpArctanXTest_0(REG,310)@30
reg_expFracPreRnd_uid77_fpArctanXTest_0_to_expfracRPath3PostRnd_uid78_fpArctanXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid77_fpArctanXTest_0_to_expfracRPath3PostRnd_uid78_fpArctanXTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid77_fpArctanXTest_0_to_expfracRPath3PostRnd_uid78_fpArctanXTest_0_q <= expFracPreRnd_uid77_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid78_fpArctanXTest(ADD,77)@31
expfracRPath3PostRnd_uid78_fpArctanXTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid77_fpArctanXTest_0_to_expfracRPath3PostRnd_uid78_fpArctanXTest_0_q);
expfracRPath3PostRnd_uid78_fpArctanXTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid78_fpArctanXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid78_fpArctanXTest_a) + UNSIGNED(expfracRPath3PostRnd_uid78_fpArctanXTest_b));
expfracRPath3PostRnd_uid78_fpArctanXTest_q <= expfracRPath3PostRnd_uid78_fpArctanXTest_o(33 downto 0);
--expRPath3_uid80_fpArctanXTest(BITSELECT,79)@31
expRPath3_uid80_fpArctanXTest_in <= expfracRPath3PostRnd_uid78_fpArctanXTest_q(31 downto 0);
expRPath3_uid80_fpArctanXTest_b <= expRPath3_uid80_fpArctanXTest_in(31 downto 24);
--ld_expRPath3_uid80_fpArctanXTest_b_to_reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_a_inputreg(DELAY,833)
ld_expRPath3_uid80_fpArctanXTest_b_to_reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPath3_uid80_fpArctanXTest_b, xout => ld_expRPath3_uid80_fpArctanXTest_b_to_reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPath3_uid80_fpArctanXTest_b_to_reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_a(DELAY,612)@31
ld_expRPath3_uid80_fpArctanXTest_b_to_reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_expRPath3_uid80_fpArctanXTest_b_to_reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_a_inputreg_q, xout => ld_expRPath3_uid80_fpArctanXTest_b_to_reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4(REG,317)@35
reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_q <= ld_expRPath3_uid80_fpArctanXTest_b_to_reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_a_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage124dto1_uid228_fxpOp2Path2_uid87_fpArctanXTest(BITSELECT,227)@33
RightShiftStage124dto1_uid228_fxpOp2Path2_uid87_fpArctanXTest_in <= rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_q;
RightShiftStage124dto1_uid228_fxpOp2Path2_uid87_fpArctanXTest_b <= RightShiftStage124dto1_uid228_fxpOp2Path2_uid87_fpArctanXTest_in(24 downto 1);
--rightShiftStage2Idx1_uid230_fxpOp2Path2_uid87_fpArctanXTest(BITJOIN,229)@33
rightShiftStage2Idx1_uid230_fxpOp2Path2_uid87_fpArctanXTest_q <= GND_q & RightShiftStage124dto1_uid228_fxpOp2Path2_uid87_fpArctanXTest_b;
--rightShiftStage1Idx3Pad6_uid224_fxpOp2Path2_uid87_fpArctanXTest(CONSTANT,223)
rightShiftStage1Idx3Pad6_uid224_fxpOp2Path2_uid87_fpArctanXTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid213_fxpOp2Path2_uid87_fpArctanXTest(CONSTANT,212)
rightShiftStage0Idx3Pad24_uid213_fxpOp2Path2_uid87_fpArctanXTest_q <= "000000000000000000000000";
--X24dto24_uid212_fxpOp2Path2_uid87_fpArctanXTest(BITSELECT,211)@32
X24dto24_uid212_fxpOp2Path2_uid87_fpArctanXTest_in <= oFracRPath2_uid85_uid85_fpArctanXTest_q;
X24dto24_uid212_fxpOp2Path2_uid87_fpArctanXTest_b <= X24dto24_uid212_fxpOp2Path2_uid87_fpArctanXTest_in(24 downto 24);
--rightShiftStage0Idx3_uid214_fxpOp2Path2_uid87_fpArctanXTest(BITJOIN,213)@32
rightShiftStage0Idx3_uid214_fxpOp2Path2_uid87_fpArctanXTest_q <= rightShiftStage0Idx3Pad24_uid213_fxpOp2Path2_uid87_fpArctanXTest_q & X24dto24_uid212_fxpOp2Path2_uid87_fpArctanXTest_b;
--rightShiftStage0Idx2Pad16_uid210_fxpOp2Path2_uid87_fpArctanXTest(CONSTANT,209)
rightShiftStage0Idx2Pad16_uid210_fxpOp2Path2_uid87_fpArctanXTest_q <= "0000000000000000";
--X24dto16_uid209_fxpOp2Path2_uid87_fpArctanXTest(BITSELECT,208)@32
X24dto16_uid209_fxpOp2Path2_uid87_fpArctanXTest_in <= oFracRPath2_uid85_uid85_fpArctanXTest_q;
X24dto16_uid209_fxpOp2Path2_uid87_fpArctanXTest_b <= X24dto16_uid209_fxpOp2Path2_uid87_fpArctanXTest_in(24 downto 16);
--rightShiftStage0Idx2_uid211_fxpOp2Path2_uid87_fpArctanXTest(BITJOIN,210)@32
rightShiftStage0Idx2_uid211_fxpOp2Path2_uid87_fpArctanXTest_q <= rightShiftStage0Idx2Pad16_uid210_fxpOp2Path2_uid87_fpArctanXTest_q & X24dto16_uid209_fxpOp2Path2_uid87_fpArctanXTest_b;
--X24dto8_uid206_fxpOp2Path2_uid87_fpArctanXTest(BITSELECT,205)@32
X24dto8_uid206_fxpOp2Path2_uid87_fpArctanXTest_in <= oFracRPath2_uid85_uid85_fpArctanXTest_q;
X24dto8_uid206_fxpOp2Path2_uid87_fpArctanXTest_b <= X24dto8_uid206_fxpOp2Path2_uid87_fpArctanXTest_in(24 downto 8);
--rightShiftStage0Idx1_uid208_fxpOp2Path2_uid87_fpArctanXTest(BITJOIN,207)@32
rightShiftStage0Idx1_uid208_fxpOp2Path2_uid87_fpArctanXTest_q <= cstAllZWE_uid12_fpArctanXTest_q & X24dto8_uid206_fxpOp2Path2_uid87_fpArctanXTest_b;
--ld_fracRPath3Pre_uid74_fpArctanXTest_q_to_oFracRPath2_uid85_uid85_fpArctanXTest_a(DELAY,382)@30
ld_fracRPath3Pre_uid74_fpArctanXTest_q_to_oFracRPath2_uid85_uid85_fpArctanXTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid74_fpArctanXTest_q, xout => ld_fracRPath3Pre_uid74_fpArctanXTest_q_to_oFracRPath2_uid85_uid85_fpArctanXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid85_uid85_fpArctanXTest(BITJOIN,84)@32
oFracRPath2_uid85_uid85_fpArctanXTest_q <= VCC_q & ld_fracRPath3Pre_uid74_fpArctanXTest_q_to_oFracRPath2_uid85_uid85_fpArctanXTest_a_q;
--cstWFP2_uid16_fpArctanXTest(CONSTANT,15)
cstWFP2_uid16_fpArctanXTest_q <= "00011001";
--reg_expRPath3Ext_uid76_fpArctanXTest_0_to_shiftValPath2PreSub_uid81_fpArctanXTest_1(REG,303)@30
reg_expRPath3Ext_uid76_fpArctanXTest_0_to_shiftValPath2PreSub_uid81_fpArctanXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid76_fpArctanXTest_0_to_shiftValPath2PreSub_uid81_fpArctanXTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid76_fpArctanXTest_0_to_shiftValPath2PreSub_uid81_fpArctanXTest_1_q <= expRPath3Ext_uid76_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid81_fpArctanXTest(SUB,80)@31
shiftValPath2PreSub_uid81_fpArctanXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid13_fpArctanXTest_q);
shiftValPath2PreSub_uid81_fpArctanXTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid76_fpArctanXTest_0_to_shiftValPath2PreSub_uid81_fpArctanXTest_1_q(8)) & reg_expRPath3Ext_uid76_fpArctanXTest_0_to_shiftValPath2PreSub_uid81_fpArctanXTest_1_q);
shiftValPath2PreSub_uid81_fpArctanXTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid81_fpArctanXTest_a) - SIGNED(shiftValPath2PreSub_uid81_fpArctanXTest_b));
shiftValPath2PreSub_uid81_fpArctanXTest_q <= shiftValPath2PreSub_uid81_fpArctanXTest_o(9 downto 0);
--shiftValPath2PreSubR_uid83_fpArctanXTest(BITSELECT,82)@31
shiftValPath2PreSubR_uid83_fpArctanXTest_in <= shiftValPath2PreSub_uid81_fpArctanXTest_q(7 downto 0);
shiftValPath2PreSubR_uid83_fpArctanXTest_b <= shiftValPath2PreSubR_uid83_fpArctanXTest_in(7 downto 0);
--cstBiasMWF_uid15_fpArctanXTest(CONSTANT,14)
cstBiasMWF_uid15_fpArctanXTest_q <= "01101000";
--shiftOut_uid82_fpArctanXTest(COMPARE,81)@13
shiftOut_uid82_fpArctanXTest_cin <= GND_q;
shiftOut_uid82_fpArctanXTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid50_fpArctanXTest_0_to_atanUIsU_uid54_fpArctanXTest_1_q) & '0';
shiftOut_uid82_fpArctanXTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid15_fpArctanXTest_q) & shiftOut_uid82_fpArctanXTest_cin(0);
shiftOut_uid82_fpArctanXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid82_fpArctanXTest_a) - UNSIGNED(shiftOut_uid82_fpArctanXTest_b));
shiftOut_uid82_fpArctanXTest_c(0) <= shiftOut_uid82_fpArctanXTest_o(10);
--ld_shiftOut_uid82_fpArctanXTest_c_to_sValPostSOut_uid84_fpArctanXTest_b(DELAY,380)@13
ld_shiftOut_uid82_fpArctanXTest_c_to_sValPostSOut_uid84_fpArctanXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid82_fpArctanXTest_c, xout => ld_shiftOut_uid82_fpArctanXTest_c_to_sValPostSOut_uid84_fpArctanXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid84_fpArctanXTest(MUX,83)@31
sValPostSOut_uid84_fpArctanXTest_s <= ld_shiftOut_uid82_fpArctanXTest_c_to_sValPostSOut_uid84_fpArctanXTest_b_q;
sValPostSOut_uid84_fpArctanXTest: PROCESS (sValPostSOut_uid84_fpArctanXTest_s, en, shiftValPath2PreSubR_uid83_fpArctanXTest_b, cstWFP2_uid16_fpArctanXTest_q)
BEGIN
CASE sValPostSOut_uid84_fpArctanXTest_s IS
WHEN "0" => sValPostSOut_uid84_fpArctanXTest_q <= shiftValPath2PreSubR_uid83_fpArctanXTest_b;
WHEN "1" => sValPostSOut_uid84_fpArctanXTest_q <= cstWFP2_uid16_fpArctanXTest_q;
WHEN OTHERS => sValPostSOut_uid84_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid86_fpArctanXTest(BITSELECT,85)@31
sValPostSOutR_uid86_fpArctanXTest_in <= sValPostSOut_uid84_fpArctanXTest_q(4 downto 0);
sValPostSOutR_uid86_fpArctanXTest_b <= sValPostSOutR_uid86_fpArctanXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest(BITSELECT,214)@31
rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest_in <= sValPostSOutR_uid86_fpArctanXTest_b;
rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest_b <= rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_1(REG,304)@31
reg_rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_1_q <= rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest(MUX,215)@32
rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_s <= reg_rightShiftStageSel4Dto3_uid215_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_1_q;
rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest: PROCESS (rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_s, en, oFracRPath2_uid85_uid85_fpArctanXTest_q, rightShiftStage0Idx1_uid208_fxpOp2Path2_uid87_fpArctanXTest_q, rightShiftStage0Idx2_uid211_fxpOp2Path2_uid87_fpArctanXTest_q, rightShiftStage0Idx3_uid214_fxpOp2Path2_uid87_fpArctanXTest_q)
BEGIN
CASE rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_s IS
WHEN "00" => rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_q <= oFracRPath2_uid85_uid85_fpArctanXTest_q;
WHEN "01" => rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_q <= rightShiftStage0Idx1_uid208_fxpOp2Path2_uid87_fpArctanXTest_q;
WHEN "10" => rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_q <= rightShiftStage0Idx2_uid211_fxpOp2Path2_uid87_fpArctanXTest_q;
WHEN "11" => rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_q <= rightShiftStage0Idx3_uid214_fxpOp2Path2_uid87_fpArctanXTest_q;
WHEN OTHERS => rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid223_fxpOp2Path2_uid87_fpArctanXTest(BITSELECT,222)@32
RightShiftStage024dto6_uid223_fxpOp2Path2_uid87_fpArctanXTest_in <= rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_q;
RightShiftStage024dto6_uid223_fxpOp2Path2_uid87_fpArctanXTest_b <= RightShiftStage024dto6_uid223_fxpOp2Path2_uid87_fpArctanXTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid223_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx3_uid225_fxpOp2Path2_uid87_fpArctanXTest_a(DELAY,518)@32
ld_RightShiftStage024dto6_uid223_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx3_uid225_fxpOp2Path2_uid87_fpArctanXTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid223_fxpOp2Path2_uid87_fpArctanXTest_b, xout => ld_RightShiftStage024dto6_uid223_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx3_uid225_fxpOp2Path2_uid87_fpArctanXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid225_fxpOp2Path2_uid87_fpArctanXTest(BITJOIN,224)@33
rightShiftStage1Idx3_uid225_fxpOp2Path2_uid87_fpArctanXTest_q <= rightShiftStage1Idx3Pad6_uid224_fxpOp2Path2_uid87_fpArctanXTest_q & ld_RightShiftStage024dto6_uid223_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx3_uid225_fxpOp2Path2_uid87_fpArctanXTest_a_q;
--RightShiftStage024dto4_uid220_fxpOp2Path2_uid87_fpArctanXTest(BITSELECT,219)@32
RightShiftStage024dto4_uid220_fxpOp2Path2_uid87_fpArctanXTest_in <= rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_q;
RightShiftStage024dto4_uid220_fxpOp2Path2_uid87_fpArctanXTest_b <= RightShiftStage024dto4_uid220_fxpOp2Path2_uid87_fpArctanXTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid220_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx2_uid222_fxpOp2Path2_uid87_fpArctanXTest_a(DELAY,516)@32
ld_RightShiftStage024dto4_uid220_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx2_uid222_fxpOp2Path2_uid87_fpArctanXTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid220_fxpOp2Path2_uid87_fpArctanXTest_b, xout => ld_RightShiftStage024dto4_uid220_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx2_uid222_fxpOp2Path2_uid87_fpArctanXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid222_fxpOp2Path2_uid87_fpArctanXTest(BITJOIN,221)@33
rightShiftStage1Idx2_uid222_fxpOp2Path2_uid87_fpArctanXTest_q <= leftShiftStage0Idx1Pad4_uid166_fxpU_uid63_fpArctanXTest_q & ld_RightShiftStage024dto4_uid220_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx2_uid222_fxpOp2Path2_uid87_fpArctanXTest_a_q;
--RightShiftStage024dto2_uid217_fxpOp2Path2_uid87_fpArctanXTest(BITSELECT,216)@32
RightShiftStage024dto2_uid217_fxpOp2Path2_uid87_fpArctanXTest_in <= rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_q;
RightShiftStage024dto2_uid217_fxpOp2Path2_uid87_fpArctanXTest_b <= RightShiftStage024dto2_uid217_fxpOp2Path2_uid87_fpArctanXTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid217_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx1_uid219_fxpOp2Path2_uid87_fpArctanXTest_a(DELAY,514)@32
ld_RightShiftStage024dto2_uid217_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx1_uid219_fxpOp2Path2_uid87_fpArctanXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid217_fxpOp2Path2_uid87_fpArctanXTest_b, xout => ld_RightShiftStage024dto2_uid217_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx1_uid219_fxpOp2Path2_uid87_fpArctanXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid219_fxpOp2Path2_uid87_fpArctanXTest(BITJOIN,218)@33
rightShiftStage1Idx1_uid219_fxpOp2Path2_uid87_fpArctanXTest_q <= leftShiftStage1Idx2Pad2_uid180_fxpU_uid63_fpArctanXTest_q & ld_RightShiftStage024dto2_uid217_fxpOp2Path2_uid87_fpArctanXTest_b_to_rightShiftStage1Idx1_uid219_fxpOp2Path2_uid87_fpArctanXTest_a_q;
--reg_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_2(REG,306)@32
reg_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_2_q <= rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest(BITSELECT,225)@31
rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_in <= sValPostSOutR_uid86_fpArctanXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_b <= rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_1(REG,305)@31
reg_rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_1_q <= rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_1_q_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_b(DELAY,520)@32
ld_reg_rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_1_q_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_1_q_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest(MUX,226)@33
rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_s <= ld_reg_rightShiftStageSel2Dto1_uid226_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_1_q_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_b_q;
rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest: PROCESS (rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_s, en, reg_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_2_q, rightShiftStage1Idx1_uid219_fxpOp2Path2_uid87_fpArctanXTest_q, rightShiftStage1Idx2_uid222_fxpOp2Path2_uid87_fpArctanXTest_q, rightShiftStage1Idx3_uid225_fxpOp2Path2_uid87_fpArctanXTest_q)
BEGIN
CASE rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_s IS
WHEN "00" => rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_q <= reg_rightShiftStage0_uid216_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_2_q;
WHEN "01" => rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_q <= rightShiftStage1Idx1_uid219_fxpOp2Path2_uid87_fpArctanXTest_q;
WHEN "10" => rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_q <= rightShiftStage1Idx2_uid222_fxpOp2Path2_uid87_fpArctanXTest_q;
WHEN "11" => rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_q <= rightShiftStage1Idx3_uid225_fxpOp2Path2_uid87_fpArctanXTest_q;
WHEN OTHERS => rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest(BITSELECT,230)@31
rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_in <= sValPostSOutR_uid86_fpArctanXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_b <= rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_in(0 downto 0);
--ld_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_b_to_reg_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_1_a(DELAY,602)@31
ld_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_b_to_reg_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_b, xout => ld_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_b_to_reg_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_1(REG,307)@32
reg_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_1_q <= ld_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_b_to_reg_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest(MUX,231)@33
rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_s <= reg_rightShiftStageSel0Dto0_uid231_fxpOp2Path2_uid87_fpArctanXTest_0_to_rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_1_q;
rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest: PROCESS (rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_s, en, rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_q, rightShiftStage2Idx1_uid230_fxpOp2Path2_uid87_fpArctanXTest_q)
BEGIN
CASE rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_s IS
WHEN "0" => rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_q <= rightShiftStage1_uid227_fxpOp2Path2_uid87_fpArctanXTest_q;
WHEN "1" => rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_q <= rightShiftStage2Idx1_uid230_fxpOp2Path2_uid87_fpArctanXTest_q;
WHEN OTHERS => rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid87_uid88_fpArctanXTest(BITJOIN,87)@33
pad_fxpOp2Path2_uid87_uid88_fpArctanXTest_q <= rightShiftStage2_uid232_fxpOp2Path2_uid87_fpArctanXTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid87_uid88_fpArctanXTest_0_to_path2Diff_uid88_fpArctanXTest_1(REG,308)@33
reg_pad_fxpOp2Path2_uid87_uid88_fpArctanXTest_0_to_path2Diff_uid88_fpArctanXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid87_uid88_fpArctanXTest_0_to_path2Diff_uid88_fpArctanXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid87_uid88_fpArctanXTest_0_to_path2Diff_uid88_fpArctanXTest_1_q <= pad_fxpOp2Path2_uid87_uid88_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid88_fpArctanXTest(SUB,88)@34
path2Diff_uid88_fpArctanXTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid37_fpArctanXTest_q);
path2Diff_uid88_fpArctanXTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid87_uid88_fpArctanXTest_0_to_path2Diff_uid88_fpArctanXTest_1_q);
path2Diff_uid88_fpArctanXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid88_fpArctanXTest_a) - UNSIGNED(path2Diff_uid88_fpArctanXTest_b));
path2Diff_uid88_fpArctanXTest_q <= path2Diff_uid88_fpArctanXTest_o(26 downto 0);
--normBitPath2Diff_uid90_fpArctanXTest(BITSELECT,89)@34
normBitPath2Diff_uid90_fpArctanXTest_in <= path2Diff_uid88_fpArctanXTest_q(25 downto 0);
normBitPath2Diff_uid90_fpArctanXTest_b <= normBitPath2Diff_uid90_fpArctanXTest_in(25 downto 25);
--expRPath2_uid94_fpArctanXTest(MUX,93)@34
expRPath2_uid94_fpArctanXTest_s <= normBitPath2Diff_uid90_fpArctanXTest_b;
expRPath2_uid94_fpArctanXTest: PROCESS (expRPath2_uid94_fpArctanXTest_s, en, cstBiasM1_uid14_fpArctanXTest_q, cstBias_uid13_fpArctanXTest_q)
BEGIN
CASE expRPath2_uid94_fpArctanXTest_s IS
WHEN "0" => expRPath2_uid94_fpArctanXTest_q <= cstBiasM1_uid14_fpArctanXTest_q;
WHEN "1" => expRPath2_uid94_fpArctanXTest_q <= cstBias_uid13_fpArctanXTest_q;
WHEN OTHERS => expRPath2_uid94_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid91_fpArctanXTest(BITSELECT,90)@34
path2DiffHigh_uid91_fpArctanXTest_in <= path2Diff_uid88_fpArctanXTest_q(24 downto 0);
path2DiffHigh_uid91_fpArctanXTest_b <= path2DiffHigh_uid91_fpArctanXTest_in(24 downto 1);
--path2DiffLow_uid92_fpArctanXTest(BITSELECT,91)@34
path2DiffLow_uid92_fpArctanXTest_in <= path2Diff_uid88_fpArctanXTest_q(23 downto 0);
path2DiffLow_uid92_fpArctanXTest_b <= path2DiffLow_uid92_fpArctanXTest_in(23 downto 0);
--fracRPath2_uid93_fpArctanXTest(MUX,92)@34
fracRPath2_uid93_fpArctanXTest_s <= normBitPath2Diff_uid90_fpArctanXTest_b;
fracRPath2_uid93_fpArctanXTest: PROCESS (fracRPath2_uid93_fpArctanXTest_s, en, path2DiffLow_uid92_fpArctanXTest_b, path2DiffHigh_uid91_fpArctanXTest_b)
BEGIN
CASE fracRPath2_uid93_fpArctanXTest_s IS
WHEN "0" => fracRPath2_uid93_fpArctanXTest_q <= path2DiffLow_uid92_fpArctanXTest_b;
WHEN "1" => fracRPath2_uid93_fpArctanXTest_q <= path2DiffHigh_uid91_fpArctanXTest_b;
WHEN OTHERS => fracRPath2_uid93_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid95_uid95_fpArctanXTest(BITJOIN,94)@34
expFracConc_uid95_uid95_fpArctanXTest_q <= expRPath2_uid94_fpArctanXTest_q & fracRPath2_uid93_fpArctanXTest_q;
--reg_expFracConc_uid95_uid95_fpArctanXTest_0_to_expFracRPath2PostRnd_uid96_fpArctanXTest_0(REG,309)@34
reg_expFracConc_uid95_uid95_fpArctanXTest_0_to_expFracRPath2PostRnd_uid96_fpArctanXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid95_uid95_fpArctanXTest_0_to_expFracRPath2PostRnd_uid96_fpArctanXTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid95_uid95_fpArctanXTest_0_to_expFracRPath2PostRnd_uid96_fpArctanXTest_0_q <= expFracConc_uid95_uid95_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid96_fpArctanXTest(ADD,95)@35
expFracRPath2PostRnd_uid96_fpArctanXTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid95_uid95_fpArctanXTest_0_to_expFracRPath2PostRnd_uid96_fpArctanXTest_0_q);
expFracRPath2PostRnd_uid96_fpArctanXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid96_fpArctanXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid96_fpArctanXTest_a) + UNSIGNED(expFracRPath2PostRnd_uid96_fpArctanXTest_b));
expFracRPath2PostRnd_uid96_fpArctanXTest_q <= expFracRPath2PostRnd_uid96_fpArctanXTest_o(32 downto 0);
--expRPath2_uid98_fpArctanXTest(BITSELECT,97)@35
expRPath2_uid98_fpArctanXTest_in <= expFracRPath2PostRnd_uid96_fpArctanXTest_q(31 downto 0);
expRPath2_uid98_fpArctanXTest_b <= expRPath2_uid98_fpArctanXTest_in(31 downto 24);
--reg_expRPath2_uid98_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_3(REG,316)@35
reg_expRPath2_uid98_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid98_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid98_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_3_q <= expRPath2_uid98_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_nor(LOGICAL,830)
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_nor_b <= ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_sticky_ena_q;
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_nor_q <= not (ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_nor_a or ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_nor_b);
--ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_sticky_ena(REG,831)
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_sticky_ena_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_enaAnd(LOGICAL,832)
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_enaAnd_a <= ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_sticky_ena_q;
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_enaAnd_q <= ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_enaAnd_a and ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_enaAnd_b;
--ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_inputreg(DELAY,820)
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpArctanXTest_b, xout => ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem(DUALMEM,821)
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_ia <= ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_inputreg_q;
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_aa <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg_q;
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_ab <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_q;
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_q <= ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2(REG,315)@35
reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_q <= ld_expX_uid6_fpArctanXTest_b_to_reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_nor(LOGICAL,779)
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_nor_b <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_sticky_ena_q;
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_nor_q <= not (ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_nor_a or ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_nor_b);
--ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_mem_top(CONSTANT,775)
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_mem_top_q <= "010010";
--ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmp(LOGICAL,776)
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmp_a <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_mem_top_q;
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdmux_q);
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmp_q <= "1" when ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmp_a = ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmp_b else "0";
--ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmpReg(REG,777)
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmpReg_q <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_sticky_ena(REG,780)
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_nor_q = "1") THEN
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_sticky_ena_q <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_enaAnd(LOGICAL,781)
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_enaAnd_a <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_sticky_ena_q;
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_enaAnd_b <= en;
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_enaAnd_q <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_enaAnd_a and ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_enaAnd_b;
--expXIsBias_uid35_fpArctanXTest(LOGICAL,34)@0
expXIsBias_uid35_fpArctanXTest_a <= expX_uid6_fpArctanXTest_b;
expXIsBias_uid35_fpArctanXTest_b <= cstBias_uid13_fpArctanXTest_q;
expXIsBias_uid35_fpArctanXTest_q <= "1" when expXIsBias_uid35_fpArctanXTest_a = expXIsBias_uid35_fpArctanXTest_b else "0";
--inIsOne_uid36_fpArctanXTest(LOGICAL,35)@0
inIsOne_uid36_fpArctanXTest_a <= fracXIsZero_uid26_fpArctanXTest_q;
inIsOne_uid36_fpArctanXTest_b <= expXIsBias_uid35_fpArctanXTest_q;
inIsOne_uid36_fpArctanXTest_q <= inIsOne_uid36_fpArctanXTest_a and inIsOne_uid36_fpArctanXTest_b;
--arctanIsConst_uid46_fpArctanXTest(LOGICAL,45)@0
arctanIsConst_uid46_fpArctanXTest_a <= exc_I_uid27_fpArctanXTest_q;
arctanIsConst_uid46_fpArctanXTest_b <= inIsOne_uid36_fpArctanXTest_q;
arctanIsConst_uid46_fpArctanXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid46_fpArctanXTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid46_fpArctanXTest_q <= arctanIsConst_uid46_fpArctanXTest_a or arctanIsConst_uid46_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid46_fpArctanXTest_q_to_pathSelBits_uid99_fpArctanXTest_c(DELAY,400)@1
ld_arctanIsConst_uid46_fpArctanXTest_q_to_pathSelBits_uid99_fpArctanXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid46_fpArctanXTest_q, xout => ld_arctanIsConst_uid46_fpArctanXTest_q_to_pathSelBits_uid99_fpArctanXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid53_fpArctanXTest(CONSTANT,52)
biasMwShift_uid53_fpArctanXTest_q <= "01110011";
--atanUIsU_uid54_fpArctanXTest(COMPARE,53)@13
atanUIsU_uid54_fpArctanXTest_cin <= GND_q;
atanUIsU_uid54_fpArctanXTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid53_fpArctanXTest_q) & '0';
atanUIsU_uid54_fpArctanXTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid50_fpArctanXTest_0_to_atanUIsU_uid54_fpArctanXTest_1_q) & atanUIsU_uid54_fpArctanXTest_cin(0);
atanUIsU_uid54_fpArctanXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid54_fpArctanXTest_a) - UNSIGNED(atanUIsU_uid54_fpArctanXTest_b));
atanUIsU_uid54_fpArctanXTest_n(0) <= not atanUIsU_uid54_fpArctanXTest_o(10);
--ld_path2_uid47_fpArctanXTest_n_to_pathSelBits_uid99_fpArctanXTest_a(DELAY,398)@0
ld_path2_uid47_fpArctanXTest_n_to_pathSelBits_uid99_fpArctanXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid47_fpArctanXTest_n, xout => ld_path2_uid47_fpArctanXTest_n_to_pathSelBits_uid99_fpArctanXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid99_fpArctanXTest(BITJOIN,98)@13
pathSelBits_uid99_fpArctanXTest_q <= ld_arctanIsConst_uid46_fpArctanXTest_q_to_pathSelBits_uid99_fpArctanXTest_c_q & atanUIsU_uid54_fpArctanXTest_n & ld_path2_uid47_fpArctanXTest_n_to_pathSelBits_uid99_fpArctanXTest_a_q;
--ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_inputreg(DELAY,769)
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid99_fpArctanXTest_q, xout => ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt(COUNTER,771)
-- every=1, low=0, high=18, step=1, init=1
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_i = 17 THEN
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_i <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_i - 18;
ELSE
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_i <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_i,5));
--ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdreg(REG,772)
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdreg_q <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdmux(MUX,773)
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdmux_s <= en;
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdmux: PROCESS (ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdmux_s, ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdreg_q, ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdmux_q <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdmux_q <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem(DUALMEM,770)
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_ia <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_inputreg_q;
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_aa <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdreg_q;
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_ab <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_rdmux_q;
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_iq,
address_a => ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_aa,
data_a => ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_ia
);
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_q <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_iq(2 downto 0);
--reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0(REG,282)@34
reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_q <= ld_pathSelBits_uid99_fpArctanXTest_q_to_reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracOutMuxSelEnc_uid100_fpArctanXTest(LOOKUP,99)@35
fracOutMuxSelEnc_uid100_fpArctanXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid100_fpArctanXTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_pathSelBits_uid99_fpArctanXTest_0_to_fracOutMuxSelEnc_uid100_fpArctanXTest_0_q) IS
WHEN "000" => fracOutMuxSelEnc_uid100_fpArctanXTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid100_fpArctanXTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid100_fpArctanXTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid100_fpArctanXTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid100_fpArctanXTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid100_fpArctanXTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid100_fpArctanXTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid100_fpArctanXTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid100_fpArctanXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid104_fpArctanXTest(MUX,103)@36
expRCalc_uid104_fpArctanXTest_s <= fracOutMuxSelEnc_uid100_fpArctanXTest_q;
expRCalc_uid104_fpArctanXTest: PROCESS (expRCalc_uid104_fpArctanXTest_s, en, reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_q, reg_expRPath2_uid98_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_3_q, reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_q, reg_expOutCst_uid103_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_5_q)
BEGIN
CASE expRCalc_uid104_fpArctanXTest_s IS
WHEN "00" => expRCalc_uid104_fpArctanXTest_q <= reg_expX_uid6_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_2_q;
WHEN "01" => expRCalc_uid104_fpArctanXTest_q <= reg_expRPath2_uid98_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_3_q;
WHEN "10" => expRCalc_uid104_fpArctanXTest_q <= reg_expRPath3_uid80_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_4_q;
WHEN "11" => expRCalc_uid104_fpArctanXTest_q <= reg_expOutCst_uid103_fpArctanXTest_0_to_expRCalc_uid104_fpArctanXTest_5_q;
WHEN OTHERS => expRCalc_uid104_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid12_fpArctanXTest(CONSTANT,11)
cstAllZWE_uid12_fpArctanXTest_q <= "00000000";
--ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_nor(LOGICAL,702)
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_nor_b <= ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_sticky_ena_q;
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_nor_q <= not (ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_nor_a or ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_nor_b);
--ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_sticky_ena(REG,703)
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_nor_q = "1") THEN
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_sticky_ena_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_enaAnd(LOGICAL,704)
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_enaAnd_a <= ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_sticky_ena_q;
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_enaAnd_b <= en;
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_enaAnd_q <= ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_enaAnd_a and ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_enaAnd_b;
--ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_inputreg(DELAY,692)
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid29_fpArctanXTest_q, xout => ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem(DUALMEM,693)
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_ia <= ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_inputreg_q;
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_aa <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg_q;
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_ab <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_q;
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_iq,
address_a => ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_aa,
data_a => ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_ia
);
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_q <= ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_nor(LOGICAL,689)
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_nor_b <= ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_sticky_ena_q;
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_nor_q <= not (ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_nor_a or ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_nor_b);
--ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_sticky_ena(REG,690)
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_nor_q = "1") THEN
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_sticky_ena_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_enaAnd(LOGICAL,691)
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_enaAnd_a <= ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_sticky_ena_q;
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_enaAnd_b <= en;
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_enaAnd_q <= ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_enaAnd_a and ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_enaAnd_b;
--ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_inputreg(DELAY,679)
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid22_fpArctanXTest_q, xout => ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem(DUALMEM,680)
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_ia <= ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_inputreg_q;
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_aa <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg_q;
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_ab <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_q;
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_ia
);
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_q <= ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid105_fpArctanXTest(BITJOIN,104)@35
excSelBits_uid105_fpArctanXTest_q <= ld_exc_N_uid29_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid22_fpArctanXTest_q_to_excSelBits_uid105_fpArctanXTest_a_replace_mem_q;
--reg_excSelBits_uid105_fpArctanXTest_0_to_outMuxSelEnc_uid106_fpArctanXTest_0(REG,267)@35
reg_excSelBits_uid105_fpArctanXTest_0_to_outMuxSelEnc_uid106_fpArctanXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid105_fpArctanXTest_0_to_outMuxSelEnc_uid106_fpArctanXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid105_fpArctanXTest_0_to_outMuxSelEnc_uid106_fpArctanXTest_0_q <= excSelBits_uid105_fpArctanXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid106_fpArctanXTest(LOOKUP,105)@36
outMuxSelEnc_uid106_fpArctanXTest: PROCESS (reg_excSelBits_uid105_fpArctanXTest_0_to_outMuxSelEnc_uid106_fpArctanXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid105_fpArctanXTest_0_to_outMuxSelEnc_uid106_fpArctanXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid106_fpArctanXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid106_fpArctanXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid106_fpArctanXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid106_fpArctanXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid106_fpArctanXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid106_fpArctanXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid106_fpArctanXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid106_fpArctanXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid106_fpArctanXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid108_fpArctanXTest(MUX,107)@36
expRPostExc_uid108_fpArctanXTest_s <= outMuxSelEnc_uid106_fpArctanXTest_q;
expRPostExc_uid108_fpArctanXTest: PROCESS (expRPostExc_uid108_fpArctanXTest_s, en, cstAllZWE_uid12_fpArctanXTest_q, expRCalc_uid104_fpArctanXTest_q, cstAllOWE_uid9_fpArctanXTest_q, cstAllOWE_uid9_fpArctanXTest_q)
BEGIN
CASE expRPostExc_uid108_fpArctanXTest_s IS
WHEN "00" => expRPostExc_uid108_fpArctanXTest_q <= cstAllZWE_uid12_fpArctanXTest_q;
WHEN "01" => expRPostExc_uid108_fpArctanXTest_q <= expRCalc_uid104_fpArctanXTest_q;
WHEN "10" => expRPostExc_uid108_fpArctanXTest_q <= cstAllOWE_uid9_fpArctanXTest_q;
WHEN "11" => expRPostExc_uid108_fpArctanXTest_q <= cstAllOWE_uid9_fpArctanXTest_q;
WHEN OTHERS => expRPostExc_uid108_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid101_fpArctanXTest(BITSELECT,100)@35
fracOutCst_uid101_fpArctanXTest_in <= constOut_uid45_fpArctanXTest_q(22 downto 0);
fracOutCst_uid101_fpArctanXTest_b <= fracOutCst_uid101_fpArctanXTest_in(22 downto 0);
--reg_fracOutCst_uid101_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_5(REG,314)@35
reg_fracOutCst_uid101_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid101_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid101_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_5_q <= fracOutCst_uid101_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_nor(LOGICAL,817)
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_nor_b <= ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_sticky_ena_q;
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_nor_q <= not (ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_nor_a or ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_nor_b);
--ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_sticky_ena(REG,818)
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_nor_q = "1") THEN
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_sticky_ena_q <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_enaAnd(LOGICAL,819)
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_enaAnd_a <= ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_sticky_ena_q;
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_enaAnd_b <= en;
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_enaAnd_q <= ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_enaAnd_a and ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_enaAnd_b;
--fracRPath3_uid79_fpArctanXTest(BITSELECT,78)@31
fracRPath3_uid79_fpArctanXTest_in <= expfracRPath3PostRnd_uid78_fpArctanXTest_q(23 downto 0);
fracRPath3_uid79_fpArctanXTest_b <= fracRPath3_uid79_fpArctanXTest_in(23 downto 1);
--ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_inputreg(DELAY,809)
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracRPath3_uid79_fpArctanXTest_b, xout => ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem(DUALMEM,810)
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_ia <= ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_inputreg_q;
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_aa <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdreg_q;
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_ab <= ld_reg_yPPolyEval_uid144_z_uid48_fpArctanXTest_0_to_prodXY_uid259_pT2_uid244_invPolyEval_0_q_to_prodXY_uid259_pT2_uid244_invPolyEval_a_replace_rdmux_q;
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_iq,
address_a => ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_aa,
data_a => ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_ia
);
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_reset0 <= areset;
ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_q <= ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_iq(22 downto 0);
--reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4(REG,313)@35
reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_q <= ld_fracRPath3_uid79_fpArctanXTest_b_to_reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRPath2_uid97_fpArctanXTest(BITSELECT,96)@35
fracRPath2_uid97_fpArctanXTest_in <= expFracRPath2PostRnd_uid96_fpArctanXTest_q(23 downto 0);
fracRPath2_uid97_fpArctanXTest_b <= fracRPath2_uid97_fpArctanXTest_in(23 downto 1);
--reg_fracRPath2_uid97_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_3(REG,312)@35
reg_fracRPath2_uid97_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid97_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid97_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_3_q <= fracRPath2_uid97_fpArctanXTest_b;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_nor(LOGICAL,806)
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_nor_a <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_notEnable_q;
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_nor_b <= ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_sticky_ena_q;
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_nor_q <= not (ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_nor_a or ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_nor_b);
--ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_sticky_ena(REG,807)
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_nor_q = "1") THEN
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_sticky_ena_q <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_enaAnd(LOGICAL,808)
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_enaAnd_a <= ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_sticky_ena_q;
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_enaAnd_b <= en;
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_enaAnd_q <= ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_enaAnd_a and ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_enaAnd_b;
--ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_inputreg(DELAY,796)
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpArctanXTest_b, xout => ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem(DUALMEM,797)
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_ia <= ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_inputreg_q;
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_aa <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdreg_q;
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_ab <= ld_singX_uid8_fpArctanXTest_b_to_fpPiO2C_uid40_fpArctanXTest_c_replace_rdmux_q;
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_iq,
address_a => ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_aa,
data_a => ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_ia
);
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_reset0 <= areset;
ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_q <= ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_iq(22 downto 0);
--reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2(REG,311)@35
reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_q <= ld_fracX_uid7_fpArctanXTest_b_to_reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid102_fpArctanXTest(MUX,101)@36
fracRCalc_uid102_fpArctanXTest_s <= fracOutMuxSelEnc_uid100_fpArctanXTest_q;
fracRCalc_uid102_fpArctanXTest: PROCESS (fracRCalc_uid102_fpArctanXTest_s, en, reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_q, reg_fracRPath2_uid97_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_3_q, reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_q, reg_fracOutCst_uid101_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_5_q)
BEGIN
CASE fracRCalc_uid102_fpArctanXTest_s IS
WHEN "00" => fracRCalc_uid102_fpArctanXTest_q <= reg_fracX_uid7_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_2_q;
WHEN "01" => fracRCalc_uid102_fpArctanXTest_q <= reg_fracRPath2_uid97_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_3_q;
WHEN "10" => fracRCalc_uid102_fpArctanXTest_q <= reg_fracRPath3_uid79_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_4_q;
WHEN "11" => fracRCalc_uid102_fpArctanXTest_q <= reg_fracOutCst_uid101_fpArctanXTest_0_to_fracRCalc_uid102_fpArctanXTest_5_q;
WHEN OTHERS => fracRCalc_uid102_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid107_fpArctanXTest(MUX,106)@36
fracRPostExc_uid107_fpArctanXTest_s <= outMuxSelEnc_uid106_fpArctanXTest_q;
fracRPostExc_uid107_fpArctanXTest: PROCESS (fracRPostExc_uid107_fpArctanXTest_s, en, cstAllZWF_uid10_fpArctanXTest_q, fracRCalc_uid102_fpArctanXTest_q, cstAllZWF_uid10_fpArctanXTest_q, cstNaNWF_uid11_fpArctanXTest_q)
BEGIN
CASE fracRPostExc_uid107_fpArctanXTest_s IS
WHEN "00" => fracRPostExc_uid107_fpArctanXTest_q <= cstAllZWF_uid10_fpArctanXTest_q;
WHEN "01" => fracRPostExc_uid107_fpArctanXTest_q <= fracRCalc_uid102_fpArctanXTest_q;
WHEN "10" => fracRPostExc_uid107_fpArctanXTest_q <= cstAllZWF_uid10_fpArctanXTest_q;
WHEN "11" => fracRPostExc_uid107_fpArctanXTest_q <= cstNaNWF_uid11_fpArctanXTest_q;
WHEN OTHERS => fracRPostExc_uid107_fpArctanXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpArctanXTest(BITJOIN,110)@36
R_uid111_fpArctanXTest_q <= ld_signR_uid110_fpArctanXTest_q_to_R_uid111_fpArctanXTest_c_replace_mem_q & expRPostExc_uid108_fpArctanXTest_q & fracRPostExc_uid107_fpArctanXTest_q;
--xOut(GPOUT,4)@36
q <= R_uid111_fpArctanXTest_q;
end normal;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_normusgn3236_sv.vhd | 10 | 4902 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/dp_rsftpipe64x64.vhd | 10 | 5777 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsftpipe64x64;
ARCHITECTURE rtl of dp_rsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k+48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shift(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shift(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shift(5))) OR
(levtwoff(116) AND shiftff(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(116) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(116) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(116) AND (shiftff(6) OR shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_fabs.vhd | 10 | 3173 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_fabs;
ARCHITECTURE rtl OF fp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 8 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(8));
expmax <= expmaxchk(8);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(23));
mannonzero <= manzerochk(23);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_cbrt_s5.vhd | 10 | 110806 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cbrt_s5
-- VHDL created on Thu Mar 7 15:10:45 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cbrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cbrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCbrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCbrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid10_fpCbrtTest_q : std_logic_vector (7 downto 0);
signal oneFracRPostExc2_uid34_fpCbrtTest_q : std_logic_vector (22 downto 0);
signal prodXY_uid60_pT1_uid48_cbrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid60_pT1_uid48_cbrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid60_pT1_uid48_cbrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid60_pT1_uid48_cbrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid60_pT1_uid48_cbrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid63_pT2_uid54_cbrtPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid63_pT2_uid54_cbrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid63_pT2_uid54_cbrtPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid63_pT2_uid54_cbrtPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid63_pT2_uid54_cbrtPolyEval_q : std_logic_vector (38 downto 0);
signal divBy3Rem_uid24_fpCbrtTest_lutmem_reset0 : std_logic;
signal divBy3Rem_uid24_fpCbrtTest_lutmem_ia : std_logic_vector (1 downto 0);
signal divBy3Rem_uid24_fpCbrtTest_lutmem_aa : std_logic_vector (7 downto 0);
signal divBy3Rem_uid24_fpCbrtTest_lutmem_ab : std_logic_vector (7 downto 0);
signal divBy3Rem_uid24_fpCbrtTest_lutmem_iq : std_logic_vector (1 downto 0);
signal divBy3Rem_uid24_fpCbrtTest_lutmem_q : std_logic_vector (1 downto 0);
signal divBy3DivRes_uid25_fpCbrtTest_lutmem_reset0 : std_logic;
signal divBy3DivRes_uid25_fpCbrtTest_lutmem_ia : std_logic_vector (7 downto 0);
signal divBy3DivRes_uid25_fpCbrtTest_lutmem_aa : std_logic_vector (7 downto 0);
signal divBy3DivRes_uid25_fpCbrtTest_lutmem_ab : std_logic_vector (7 downto 0);
signal divBy3DivRes_uid25_fpCbrtTest_lutmem_iq : std_logic_vector (7 downto 0);
signal divBy3DivRes_uid25_fpCbrtTest_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC0_uid44_cbrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid44_cbrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid44_cbrtTableGenerator_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid44_cbrtTableGenerator_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid44_cbrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid44_cbrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid45_cbrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid45_cbrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid45_cbrtTableGenerator_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid45_cbrtTableGenerator_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid45_cbrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid45_cbrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid46_cbrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid46_cbrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid46_cbrtTableGenerator_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid46_cbrtTableGenerator_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid46_cbrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid46_cbrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_q : std_logic_vector (6 downto 0);
signal reg_divBy3Rem_uid24_fpCbrtTest_lutmem_0_to_addrTable_uid28_fpCbrtTest_1_q : std_logic_vector (1 downto 0);
signal reg_addrTable_uid28_fpCbrtTest_0_to_memoryC2_uid46_cbrtTableGenerator_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid46_cbrtTableGenerator_lutmem_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid49_uid52_cbrtPolyEval_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_excREnc_uid33_fpCbrtTest_0_to_expRPostExc_uid41_fpCbrtTest_1_q : std_logic_vector (1 downto 0);
signal reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3_q : std_logic_vector (7 downto 0);
signal ld_reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q_to_excREnc_uid33_fpCbrtTest_a_q : std_logic_vector (2 downto 0);
signal ld_signX_uid7_fpCbrtTest_b_to_RCbrt_uid42_fpCbrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracXAddr_uid27_fpCbrtTest_b_to_reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_a_q : std_logic_vector (6 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_a_q : std_logic_vector (8 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_reset0 : std_logic;
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_eq : std_logic;
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpCbrtTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCbrtTest_b : std_logic_vector (7 downto 0);
signal signX_uid7_fpCbrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid7_fpCbrtTest_b : std_logic_vector (0 downto 0);
signal frac_uid15_fpCbrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid15_fpCbrtTest_b : std_logic_vector (22 downto 0);
signal fracXAddr_uid27_fpCbrtTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid27_fpCbrtTest_b : std_logic_vector (6 downto 0);
signal X15dto0_uid29_fpCbrtTest_in : std_logic_vector (15 downto 0);
signal X15dto0_uid29_fpCbrtTest_b : std_logic_vector (15 downto 0);
signal expXIsZero_uid12_fpCbrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid12_fpCbrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid12_fpCbrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid14_fpCbrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid14_fpCbrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid14_fpCbrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid16_fpCbrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid16_fpCbrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid16_fpCbrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid17_fpCbrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid17_fpCbrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid17_fpCbrtTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid33_fpCbrtTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid41_fpCbrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid41_fpCbrtTest_q : std_logic_vector (7 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_b : std_logic_vector (23 downto 0);
signal addrTable_uid28_fpCbrtTest_q : std_logic_vector (8 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal yT1_uid47_cbrtPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid47_cbrtPolyEval_b : std_logic_vector (11 downto 0);
signal InvFracXIsZero_uid18_fpCbrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid18_fpCbrtTest_q : std_logic_vector(0 downto 0);
signal lowRangeB_uid49_cbrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid49_cbrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid50_cbrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid50_cbrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid55_cbrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid55_cbrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid56_cbrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid56_cbrtPolyEval_b : std_logic_vector (21 downto 0);
signal exc_N_uid19_fpCbrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid19_fpCbrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid19_fpCbrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid51_cbrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid51_cbrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid51_cbrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid51_cbrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid57_cbrtPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid57_cbrtPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid57_cbrtPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid57_cbrtPolyEval_q : std_logic_vector (29 downto 0);
signal concExc_uid32_fpCbrtTest_q : std_logic_vector (2 downto 0);
signal s1_uid49_uid52_cbrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid55_uid58_cbrtPolyEval_q : std_logic_vector (31 downto 0);
signal fracR_uid31_fpCbrtTest_in : std_logic_vector (28 downto 0);
signal fracR_uid31_fpCbrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid37_fpCbrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid37_fpCbrtTest_q : std_logic_vector (22 downto 0);
signal RCbrt_uid42_fpCbrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid7_fpCbrtTest(BITSELECT,6)@0
signX_uid7_fpCbrtTest_in <= a;
signX_uid7_fpCbrtTest_b <= signX_uid7_fpCbrtTest_in(31 downto 31);
--ld_signX_uid7_fpCbrtTest_b_to_RCbrt_uid42_fpCbrtTest_c(DELAY,113)@0
ld_signX_uid7_fpCbrtTest_b_to_RCbrt_uid42_fpCbrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signX_uid7_fpCbrtTest_b, xout => ld_signX_uid7_fpCbrtTest_b_to_RCbrt_uid42_fpCbrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable(LOGICAL,163)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_a <= en;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q <= not ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_a;
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor(LOGICAL,177)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_b <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_q <= not (ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_a or ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_b);
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_mem_top(CONSTANT,173)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_mem_top_q <= "01000";
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp(LOGICAL,174)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_a <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_mem_top_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_a = ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg(REG,175)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena(REG,178)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd(LOGICAL,179)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_a <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_a and ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_b;
--cstAllOWE_uid8_fpCbrtTest(CONSTANT,7)
cstAllOWE_uid8_fpCbrtTest_q <= "11111111";
--expX_uid6_fpCbrtTest(BITSELECT,5)@0
expX_uid6_fpCbrtTest_in <= a(30 downto 0);
expX_uid6_fpCbrtTest_b <= expX_uid6_fpCbrtTest_in(30 downto 23);
--reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0(REG,71)@0
reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0_q <= expX_uid6_fpCbrtTest_b;
END IF;
END IF;
END PROCESS;
--divBy3DivRes_uid25_fpCbrtTest_lutmem(DUALMEM,66)@1
divBy3DivRes_uid25_fpCbrtTest_lutmem_ia <= (others => '0');
divBy3DivRes_uid25_fpCbrtTest_lutmem_aa <= (others => '0');
divBy3DivRes_uid25_fpCbrtTest_lutmem_ab <= reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0_q;
divBy3DivRes_uid25_fpCbrtTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 8,
numwords_a => 255,
width_b => 8,
widthad_b => 8,
numwords_b => 255,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cbrt_s5_divBy3DivRes_uid25_fpCbrtTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => divBy3DivRes_uid25_fpCbrtTest_lutmem_reset0,
clock0 => clk,
address_b => divBy3DivRes_uid25_fpCbrtTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => divBy3DivRes_uid25_fpCbrtTest_lutmem_iq,
address_a => divBy3DivRes_uid25_fpCbrtTest_lutmem_aa,
data_a => divBy3DivRes_uid25_fpCbrtTest_lutmem_ia
);
divBy3DivRes_uid25_fpCbrtTest_lutmem_reset0 <= areset;
divBy3DivRes_uid25_fpCbrtTest_lutmem_q <= divBy3DivRes_uid25_fpCbrtTest_lutmem_iq(7 downto 0);
--reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3(REG,85)@3
reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3_q <= divBy3DivRes_uid25_fpCbrtTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--cstAllZWE_uid10_fpCbrtTest(CONSTANT,9)
cstAllZWE_uid10_fpCbrtTest_q <= "00000000";
--cstAllZWF_uid9_fpCbrtTest(CONSTANT,8)
cstAllZWF_uid9_fpCbrtTest_q <= "00000000000000000000000";
--frac_uid15_fpCbrtTest(BITSELECT,14)@0
frac_uid15_fpCbrtTest_in <= a(22 downto 0);
frac_uid15_fpCbrtTest_b <= frac_uid15_fpCbrtTest_in(22 downto 0);
--fracXIsZero_uid16_fpCbrtTest(LOGICAL,15)@0
fracXIsZero_uid16_fpCbrtTest_a <= frac_uid15_fpCbrtTest_b;
fracXIsZero_uid16_fpCbrtTest_b <= cstAllZWF_uid9_fpCbrtTest_q;
fracXIsZero_uid16_fpCbrtTest_q <= "1" when fracXIsZero_uid16_fpCbrtTest_a = fracXIsZero_uid16_fpCbrtTest_b else "0";
--InvFracXIsZero_uid18_fpCbrtTest(LOGICAL,17)@0
InvFracXIsZero_uid18_fpCbrtTest_a <= fracXIsZero_uid16_fpCbrtTest_q;
InvFracXIsZero_uid18_fpCbrtTest_q <= not InvFracXIsZero_uid18_fpCbrtTest_a;
--expXIsMax_uid14_fpCbrtTest(LOGICAL,13)@0
expXIsMax_uid14_fpCbrtTest_a <= expX_uid6_fpCbrtTest_b;
expXIsMax_uid14_fpCbrtTest_b <= cstAllOWE_uid8_fpCbrtTest_q;
expXIsMax_uid14_fpCbrtTest_q <= "1" when expXIsMax_uid14_fpCbrtTest_a = expXIsMax_uid14_fpCbrtTest_b else "0";
--exc_N_uid19_fpCbrtTest(LOGICAL,18)@0
exc_N_uid19_fpCbrtTest_a <= expXIsMax_uid14_fpCbrtTest_q;
exc_N_uid19_fpCbrtTest_b <= InvFracXIsZero_uid18_fpCbrtTest_q;
exc_N_uid19_fpCbrtTest_q <= exc_N_uid19_fpCbrtTest_a and exc_N_uid19_fpCbrtTest_b;
--exc_I_uid17_fpCbrtTest(LOGICAL,16)@0
exc_I_uid17_fpCbrtTest_a <= expXIsMax_uid14_fpCbrtTest_q;
exc_I_uid17_fpCbrtTest_b <= fracXIsZero_uid16_fpCbrtTest_q;
exc_I_uid17_fpCbrtTest_q <= exc_I_uid17_fpCbrtTest_a and exc_I_uid17_fpCbrtTest_b;
--expXIsZero_uid12_fpCbrtTest(LOGICAL,11)@0
expXIsZero_uid12_fpCbrtTest_a <= expX_uid6_fpCbrtTest_b;
expXIsZero_uid12_fpCbrtTest_b <= cstAllZWE_uid10_fpCbrtTest_q;
expXIsZero_uid12_fpCbrtTest_q <= "1" when expXIsZero_uid12_fpCbrtTest_a = expXIsZero_uid12_fpCbrtTest_b else "0";
--concExc_uid32_fpCbrtTest(BITJOIN,31)@0
concExc_uid32_fpCbrtTest_q <= exc_N_uid19_fpCbrtTest_q & exc_I_uid17_fpCbrtTest_q & expXIsZero_uid12_fpCbrtTest_q;
--reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0(REG,70)@0
reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q <= concExc_uid32_fpCbrtTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q_to_excREnc_uid33_fpCbrtTest_a(DELAY,106)@1
ld_reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q_to_excREnc_uid33_fpCbrtTest_a : dspba_delay
GENERIC MAP ( width => 3, depth => 2 )
PORT MAP ( xin => reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q, xout => ld_reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q_to_excREnc_uid33_fpCbrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excREnc_uid33_fpCbrtTest(LOOKUP,32)@3
excREnc_uid33_fpCbrtTest: PROCESS (ld_reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q_to_excREnc_uid33_fpCbrtTest_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q_to_excREnc_uid33_fpCbrtTest_a_q) IS
WHEN "000" => excREnc_uid33_fpCbrtTest_q <= "01";
WHEN "001" => excREnc_uid33_fpCbrtTest_q <= "00";
WHEN "010" => excREnc_uid33_fpCbrtTest_q <= "10";
WHEN "011" => excREnc_uid33_fpCbrtTest_q <= "00";
WHEN "100" => excREnc_uid33_fpCbrtTest_q <= "11";
WHEN "101" => excREnc_uid33_fpCbrtTest_q <= "00";
WHEN "110" => excREnc_uid33_fpCbrtTest_q <= "00";
WHEN "111" => excREnc_uid33_fpCbrtTest_q <= "00";
WHEN OTHERS =>
excREnc_uid33_fpCbrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_excREnc_uid33_fpCbrtTest_0_to_expRPostExc_uid41_fpCbrtTest_1(REG,84)@3
reg_excREnc_uid33_fpCbrtTest_0_to_expRPostExc_uid41_fpCbrtTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid33_fpCbrtTest_0_to_expRPostExc_uid41_fpCbrtTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid33_fpCbrtTest_0_to_expRPostExc_uid41_fpCbrtTest_1_q <= excREnc_uid33_fpCbrtTest_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid41_fpCbrtTest(MUX,40)@4
expRPostExc_uid41_fpCbrtTest_s <= reg_excREnc_uid33_fpCbrtTest_0_to_expRPostExc_uid41_fpCbrtTest_1_q;
expRPostExc_uid41_fpCbrtTest: PROCESS (expRPostExc_uid41_fpCbrtTest_s, en, cstAllZWE_uid10_fpCbrtTest_q, reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3_q, cstAllOWE_uid8_fpCbrtTest_q, cstAllOWE_uid8_fpCbrtTest_q)
BEGIN
CASE expRPostExc_uid41_fpCbrtTest_s IS
WHEN "00" => expRPostExc_uid41_fpCbrtTest_q <= cstAllZWE_uid10_fpCbrtTest_q;
WHEN "01" => expRPostExc_uid41_fpCbrtTest_q <= reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3_q;
WHEN "10" => expRPostExc_uid41_fpCbrtTest_q <= cstAllOWE_uid8_fpCbrtTest_q;
WHEN "11" => expRPostExc_uid41_fpCbrtTest_q <= cstAllOWE_uid8_fpCbrtTest_q;
WHEN OTHERS => expRPostExc_uid41_fpCbrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_inputreg(DELAY,167)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid41_fpCbrtTest_q, xout => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt(COUNTER,169)
-- every=1, low=0, high=8, step=1, init=1
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i = 7 THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i - 8;
ELSE
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i,4));
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg(REG,170)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux(MUX,171)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_s, ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q, ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem(DUALMEM,168)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_ia <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_inputreg_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_aa <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_ab <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_iq(7 downto 0);
--oneFracRPostExc2_uid34_fpCbrtTest(CONSTANT,33)
oneFracRPostExc2_uid34_fpCbrtTest_q <= "00000000000000000000001";
--divBy3Rem_uid24_fpCbrtTest_lutmem(DUALMEM,65)@1
divBy3Rem_uid24_fpCbrtTest_lutmem_ia <= (others => '0');
divBy3Rem_uid24_fpCbrtTest_lutmem_aa <= (others => '0');
divBy3Rem_uid24_fpCbrtTest_lutmem_ab <= reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0_q;
divBy3Rem_uid24_fpCbrtTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 8,
numwords_a => 255,
width_b => 2,
widthad_b => 8,
numwords_b => 255,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cbrt_s5_divBy3Rem_uid24_fpCbrtTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => divBy3Rem_uid24_fpCbrtTest_lutmem_reset0,
clock0 => clk,
address_b => divBy3Rem_uid24_fpCbrtTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => divBy3Rem_uid24_fpCbrtTest_lutmem_iq,
address_a => divBy3Rem_uid24_fpCbrtTest_lutmem_aa,
data_a => divBy3Rem_uid24_fpCbrtTest_lutmem_ia
);
divBy3Rem_uid24_fpCbrtTest_lutmem_reset0 <= areset;
divBy3Rem_uid24_fpCbrtTest_lutmem_q <= divBy3Rem_uid24_fpCbrtTest_lutmem_iq(1 downto 0);
--reg_divBy3Rem_uid24_fpCbrtTest_lutmem_0_to_addrTable_uid28_fpCbrtTest_1(REG,73)@3
reg_divBy3Rem_uid24_fpCbrtTest_lutmem_0_to_addrTable_uid28_fpCbrtTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_divBy3Rem_uid24_fpCbrtTest_lutmem_0_to_addrTable_uid28_fpCbrtTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_divBy3Rem_uid24_fpCbrtTest_lutmem_0_to_addrTable_uid28_fpCbrtTest_1_q <= divBy3Rem_uid24_fpCbrtTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--fracXAddr_uid27_fpCbrtTest(BITSELECT,26)@0
fracXAddr_uid27_fpCbrtTest_in <= a(22 downto 0);
fracXAddr_uid27_fpCbrtTest_b <= fracXAddr_uid27_fpCbrtTest_in(22 downto 16);
--ld_fracXAddr_uid27_fpCbrtTest_b_to_reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_a(DELAY,140)@0
ld_fracXAddr_uid27_fpCbrtTest_b_to_reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => fracXAddr_uid27_fpCbrtTest_b, xout => ld_fracXAddr_uid27_fpCbrtTest_b_to_reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0(REG,72)@3
reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_q <= ld_fracXAddr_uid27_fpCbrtTest_b_to_reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_a_q;
END IF;
END IF;
END PROCESS;
--addrTable_uid28_fpCbrtTest(BITJOIN,27)@4
addrTable_uid28_fpCbrtTest_q <= reg_divBy3Rem_uid24_fpCbrtTest_lutmem_0_to_addrTable_uid28_fpCbrtTest_1_q & reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_q;
--reg_addrTable_uid28_fpCbrtTest_0_to_memoryC2_uid46_cbrtTableGenerator_lutmem_0(REG,74)@4
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC2_uid46_cbrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC2_uid46_cbrtTableGenerator_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC2_uid46_cbrtTableGenerator_lutmem_0_q <= addrTable_uid28_fpCbrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid46_cbrtTableGenerator_lutmem(DUALMEM,69)@5
memoryC2_uid46_cbrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid46_cbrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid46_cbrtTableGenerator_lutmem_ab <= reg_addrTable_uid28_fpCbrtTest_0_to_memoryC2_uid46_cbrtTableGenerator_lutmem_0_q;
memoryC2_uid46_cbrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 384,
width_b => 12,
widthad_b => 9,
numwords_b => 384,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cbrt_s5_memoryC2_uid46_cbrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid46_cbrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid46_cbrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid46_cbrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid46_cbrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid46_cbrtTableGenerator_lutmem_ia
);
memoryC2_uid46_cbrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid46_cbrtTableGenerator_lutmem_q <= memoryC2_uid46_cbrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid46_cbrtTableGenerator_lutmem_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_1(REG,76)@7
reg_memoryC2_uid46_cbrtTableGenerator_lutmem_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid46_cbrtTableGenerator_lutmem_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid46_cbrtTableGenerator_lutmem_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_1_q <= memoryC2_uid46_cbrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor(LOGICAL,190)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_b <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_q <= not (ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_a or ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_b);
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_mem_top(CONSTANT,186)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_mem_top_q <= "0100";
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp(LOGICAL,187)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_a <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_mem_top_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q);
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_q <= "1" when ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_a = ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_b else "0";
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg(REG,188)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena(REG,191)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_q = "1") THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd(LOGICAL,192)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_a <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_b <= en;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_a and ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_b;
--X15dto0_uid29_fpCbrtTest(BITSELECT,28)@0
X15dto0_uid29_fpCbrtTest_in <= a(15 downto 0);
X15dto0_uid29_fpCbrtTest_b <= X15dto0_uid29_fpCbrtTest_in(15 downto 0);
--yT1_uid47_cbrtPolyEval(BITSELECT,46)@0
yT1_uid47_cbrtPolyEval_in <= X15dto0_uid29_fpCbrtTest_b;
yT1_uid47_cbrtPolyEval_b <= yT1_uid47_cbrtPolyEval_in(15 downto 4);
--reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0(REG,75)@0
reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q <= yT1_uid47_cbrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_inputreg(DELAY,180)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q, xout => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt(COUNTER,182)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg(REG,183)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux(MUX,184)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_s <= en;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux: PROCESS (ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_s, ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q, ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem(DUALMEM,181)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_ia <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_inputreg_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_aa <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_ab <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 3,
numwords_a => 5,
width_b => 12,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_iq,
address_a => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_aa,
data_a => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_ia
);
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_iq(11 downto 0);
--prodXY_uid60_pT1_uid48_cbrtPolyEval(MULT,59)@8
prodXY_uid60_pT1_uid48_cbrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid60_pT1_uid48_cbrtPolyEval_a),13)) * SIGNED(prodXY_uid60_pT1_uid48_cbrtPolyEval_b);
prodXY_uid60_pT1_uid48_cbrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid60_pT1_uid48_cbrtPolyEval_a <= (others => '0');
prodXY_uid60_pT1_uid48_cbrtPolyEval_b <= (others => '0');
prodXY_uid60_pT1_uid48_cbrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid60_pT1_uid48_cbrtPolyEval_a <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_q;
prodXY_uid60_pT1_uid48_cbrtPolyEval_b <= reg_memoryC2_uid46_cbrtTableGenerator_lutmem_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_1_q;
prodXY_uid60_pT1_uid48_cbrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid60_pT1_uid48_cbrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid60_pT1_uid48_cbrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid60_pT1_uid48_cbrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid60_pT1_uid48_cbrtPolyEval_q <= prodXY_uid60_pT1_uid48_cbrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval(BITSELECT,60)@11
prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_in <= prodXY_uid60_pT1_uid48_cbrtPolyEval_q;
prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_b <= prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_in(23 downto 11);
--highBBits_uid50_cbrtPolyEval(BITSELECT,49)@11
highBBits_uid50_cbrtPolyEval_in <= prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_b;
highBBits_uid50_cbrtPolyEval_b <= highBBits_uid50_cbrtPolyEval_in(12 downto 1);
--ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_a(DELAY,145)@4
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => addrTable_uid28_fpCbrtTest_q, xout => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0(REG,77)@7
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_q <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid45_cbrtTableGenerator_lutmem(DUALMEM,68)@8
memoryC1_uid45_cbrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid45_cbrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid45_cbrtTableGenerator_lutmem_ab <= reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_q;
memoryC1_uid45_cbrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 384,
width_b => 21,
widthad_b => 9,
numwords_b => 384,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cbrt_s5_memoryC1_uid45_cbrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid45_cbrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid45_cbrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid45_cbrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid45_cbrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid45_cbrtTableGenerator_lutmem_ia
);
memoryC1_uid45_cbrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid45_cbrtTableGenerator_lutmem_q <= memoryC1_uid45_cbrtTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0(REG,78)@10
reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0_q <= memoryC1_uid45_cbrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid51_cbrtPolyEval(ADD,50)@11
sumAHighB_uid51_cbrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0_q(20)) & reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0_q);
sumAHighB_uid51_cbrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid50_cbrtPolyEval_b(11)) & highBBits_uid50_cbrtPolyEval_b);
sumAHighB_uid51_cbrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid51_cbrtPolyEval_a) + SIGNED(sumAHighB_uid51_cbrtPolyEval_b));
sumAHighB_uid51_cbrtPolyEval_q <= sumAHighB_uid51_cbrtPolyEval_o(21 downto 0);
--lowRangeB_uid49_cbrtPolyEval(BITSELECT,48)@11
lowRangeB_uid49_cbrtPolyEval_in <= prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_b(0 downto 0);
lowRangeB_uid49_cbrtPolyEval_b <= lowRangeB_uid49_cbrtPolyEval_in(0 downto 0);
--s1_uid49_uid52_cbrtPolyEval(BITJOIN,51)@11
s1_uid49_uid52_cbrtPolyEval_q <= sumAHighB_uid51_cbrtPolyEval_q & lowRangeB_uid49_cbrtPolyEval_b;
--reg_s1_uid49_uid52_cbrtPolyEval_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_1(REG,80)@11
reg_s1_uid49_uid52_cbrtPolyEval_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid49_uid52_cbrtPolyEval_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid49_uid52_cbrtPolyEval_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_1_q <= s1_uid49_uid52_cbrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor(LOGICAL,203)
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_b <= ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena_q;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_q <= not (ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_a or ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_b);
--ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena(REG,204)
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_q = "1") THEN
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd(LOGICAL,205)
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_a <= ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena_q;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_b <= en;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_q <= ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_a and ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_b;
--reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0(REG,79)@0
reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q <= X15dto0_uid29_fpCbrtTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_inputreg(DELAY,193)
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q, xout => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem(DUALMEM,194)
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_ia <= ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_inputreg_q;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_aa <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_ab <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 9,
width_b => 16,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_iq,
address_a => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_aa,
data_a => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_ia
);
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_q <= ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid63_pT2_uid54_cbrtPolyEval(MULT,62)@12
prodXY_uid63_pT2_uid54_cbrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid63_pT2_uid54_cbrtPolyEval_a),17)) * SIGNED(prodXY_uid63_pT2_uid54_cbrtPolyEval_b);
prodXY_uid63_pT2_uid54_cbrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid63_pT2_uid54_cbrtPolyEval_a <= (others => '0');
prodXY_uid63_pT2_uid54_cbrtPolyEval_b <= (others => '0');
prodXY_uid63_pT2_uid54_cbrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid63_pT2_uid54_cbrtPolyEval_a <= ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_q;
prodXY_uid63_pT2_uid54_cbrtPolyEval_b <= reg_s1_uid49_uid52_cbrtPolyEval_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_1_q;
prodXY_uid63_pT2_uid54_cbrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid63_pT2_uid54_cbrtPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid63_pT2_uid54_cbrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid63_pT2_uid54_cbrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid63_pT2_uid54_cbrtPolyEval_q <= prodXY_uid63_pT2_uid54_cbrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval(BITSELECT,63)@15
prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_in <= prodXY_uid63_pT2_uid54_cbrtPolyEval_q;
prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_b <= prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_in(38 downto 15);
--highBBits_uid56_cbrtPolyEval(BITSELECT,55)@15
highBBits_uid56_cbrtPolyEval_in <= prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_b;
highBBits_uid56_cbrtPolyEval_b <= highBBits_uid56_cbrtPolyEval_in(23 downto 2);
--ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor(LOGICAL,216)
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena(REG,217)
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,218)
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_inputreg(DELAY,206)
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => addrTable_uid28_fpCbrtTest_q, xout => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,207)
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_iq(8 downto 0);
--reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0(REG,81)@11
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_q <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid44_cbrtTableGenerator_lutmem(DUALMEM,67)@12
memoryC0_uid44_cbrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid44_cbrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid44_cbrtTableGenerator_lutmem_ab <= reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_q;
memoryC0_uid44_cbrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 9,
numwords_a => 384,
width_b => 29,
widthad_b => 9,
numwords_b => 384,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cbrt_s5_memoryC0_uid44_cbrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid44_cbrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid44_cbrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid44_cbrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid44_cbrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid44_cbrtTableGenerator_lutmem_ia
);
memoryC0_uid44_cbrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid44_cbrtTableGenerator_lutmem_q <= memoryC0_uid44_cbrtTableGenerator_lutmem_iq(28 downto 0);
--reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0(REG,82)@14
reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0_q <= memoryC0_uid44_cbrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid57_cbrtPolyEval(ADD,56)@15
sumAHighB_uid57_cbrtPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0_q(28)) & reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0_q);
sumAHighB_uid57_cbrtPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid56_cbrtPolyEval_b(21)) & highBBits_uid56_cbrtPolyEval_b);
sumAHighB_uid57_cbrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid57_cbrtPolyEval_a) + SIGNED(sumAHighB_uid57_cbrtPolyEval_b));
sumAHighB_uid57_cbrtPolyEval_q <= sumAHighB_uid57_cbrtPolyEval_o(29 downto 0);
--lowRangeB_uid55_cbrtPolyEval(BITSELECT,54)@15
lowRangeB_uid55_cbrtPolyEval_in <= prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_b(1 downto 0);
lowRangeB_uid55_cbrtPolyEval_b <= lowRangeB_uid55_cbrtPolyEval_in(1 downto 0);
--s2_uid55_uid58_cbrtPolyEval(BITJOIN,57)@15
s2_uid55_uid58_cbrtPolyEval_q <= sumAHighB_uid57_cbrtPolyEval_q & lowRangeB_uid55_cbrtPolyEval_b;
--fracR_uid31_fpCbrtTest(BITSELECT,30)@15
fracR_uid31_fpCbrtTest_in <= s2_uid55_uid58_cbrtPolyEval_q(28 downto 0);
fracR_uid31_fpCbrtTest_b <= fracR_uid31_fpCbrtTest_in(28 downto 6);
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor(LOGICAL,164)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_b <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_q <= not (ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_a or ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_b);
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_mem_top(CONSTANT,160)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_mem_top_q <= "01001";
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp(LOGICAL,161)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_mem_top_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_q);
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_q <= "1" when ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_a = ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_b else "0";
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmpReg(REG,162)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmpReg_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena(REG,165)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_q = "1") THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd(LOGICAL,166)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_b <= en;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_a and ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_b;
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_inputreg(DELAY,154)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => excREnc_uid33_fpCbrtTest_q, xout => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt(COUNTER,156)
-- every=1, low=0, high=9, step=1, init=1
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i = 8 THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_eq = '1') THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i - 9;
ELSE
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i,4));
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg(REG,157)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux(MUX,158)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_s <= en;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux: PROCESS (ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_s, ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg_q, ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg_q;
WHEN "1" => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem(DUALMEM,155)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_ia <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_inputreg_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_aa <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_ab <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 10,
width_b => 2,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_iq,
address_a => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_aa,
data_a => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_ia
);
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_reset0 <= areset;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid37_fpCbrtTest(MUX,36)@15
fracRPostExc_uid37_fpCbrtTest_s <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_q;
fracRPostExc_uid37_fpCbrtTest: PROCESS (fracRPostExc_uid37_fpCbrtTest_s, en, cstAllZWF_uid9_fpCbrtTest_q, fracR_uid31_fpCbrtTest_b, cstAllZWF_uid9_fpCbrtTest_q, oneFracRPostExc2_uid34_fpCbrtTest_q)
BEGIN
CASE fracRPostExc_uid37_fpCbrtTest_s IS
WHEN "00" => fracRPostExc_uid37_fpCbrtTest_q <= cstAllZWF_uid9_fpCbrtTest_q;
WHEN "01" => fracRPostExc_uid37_fpCbrtTest_q <= fracR_uid31_fpCbrtTest_b;
WHEN "10" => fracRPostExc_uid37_fpCbrtTest_q <= cstAllZWF_uid9_fpCbrtTest_q;
WHEN "11" => fracRPostExc_uid37_fpCbrtTest_q <= oneFracRPostExc2_uid34_fpCbrtTest_q;
WHEN OTHERS => fracRPostExc_uid37_fpCbrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--RCbrt_uid42_fpCbrtTest(BITJOIN,41)@15
RCbrt_uid42_fpCbrtTest_q <= ld_signX_uid7_fpCbrtTest_b_to_RCbrt_uid42_fpCbrtTest_c_q & ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_q & fracRPostExc_uid37_fpCbrtTest_q;
--xOut(GPOUT,4)@15
q <= RCbrt_uid42_fpCbrtTest_q;
end normal;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_cbrt_s5.vhd | 10 | 110806 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cbrt_s5
-- VHDL created on Thu Mar 7 15:10:45 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cbrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cbrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCbrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCbrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid10_fpCbrtTest_q : std_logic_vector (7 downto 0);
signal oneFracRPostExc2_uid34_fpCbrtTest_q : std_logic_vector (22 downto 0);
signal prodXY_uid60_pT1_uid48_cbrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid60_pT1_uid48_cbrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid60_pT1_uid48_cbrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid60_pT1_uid48_cbrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid60_pT1_uid48_cbrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid63_pT2_uid54_cbrtPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid63_pT2_uid54_cbrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid63_pT2_uid54_cbrtPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid63_pT2_uid54_cbrtPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid63_pT2_uid54_cbrtPolyEval_q : std_logic_vector (38 downto 0);
signal divBy3Rem_uid24_fpCbrtTest_lutmem_reset0 : std_logic;
signal divBy3Rem_uid24_fpCbrtTest_lutmem_ia : std_logic_vector (1 downto 0);
signal divBy3Rem_uid24_fpCbrtTest_lutmem_aa : std_logic_vector (7 downto 0);
signal divBy3Rem_uid24_fpCbrtTest_lutmem_ab : std_logic_vector (7 downto 0);
signal divBy3Rem_uid24_fpCbrtTest_lutmem_iq : std_logic_vector (1 downto 0);
signal divBy3Rem_uid24_fpCbrtTest_lutmem_q : std_logic_vector (1 downto 0);
signal divBy3DivRes_uid25_fpCbrtTest_lutmem_reset0 : std_logic;
signal divBy3DivRes_uid25_fpCbrtTest_lutmem_ia : std_logic_vector (7 downto 0);
signal divBy3DivRes_uid25_fpCbrtTest_lutmem_aa : std_logic_vector (7 downto 0);
signal divBy3DivRes_uid25_fpCbrtTest_lutmem_ab : std_logic_vector (7 downto 0);
signal divBy3DivRes_uid25_fpCbrtTest_lutmem_iq : std_logic_vector (7 downto 0);
signal divBy3DivRes_uid25_fpCbrtTest_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC0_uid44_cbrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid44_cbrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid44_cbrtTableGenerator_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid44_cbrtTableGenerator_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid44_cbrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid44_cbrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid45_cbrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid45_cbrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid45_cbrtTableGenerator_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid45_cbrtTableGenerator_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid45_cbrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid45_cbrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid46_cbrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid46_cbrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid46_cbrtTableGenerator_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid46_cbrtTableGenerator_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid46_cbrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid46_cbrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_q : std_logic_vector (6 downto 0);
signal reg_divBy3Rem_uid24_fpCbrtTest_lutmem_0_to_addrTable_uid28_fpCbrtTest_1_q : std_logic_vector (1 downto 0);
signal reg_addrTable_uid28_fpCbrtTest_0_to_memoryC2_uid46_cbrtTableGenerator_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid46_cbrtTableGenerator_lutmem_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid49_uid52_cbrtPolyEval_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_excREnc_uid33_fpCbrtTest_0_to_expRPostExc_uid41_fpCbrtTest_1_q : std_logic_vector (1 downto 0);
signal reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3_q : std_logic_vector (7 downto 0);
signal ld_reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q_to_excREnc_uid33_fpCbrtTest_a_q : std_logic_vector (2 downto 0);
signal ld_signX_uid7_fpCbrtTest_b_to_RCbrt_uid42_fpCbrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracXAddr_uid27_fpCbrtTest_b_to_reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_a_q : std_logic_vector (6 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_a_q : std_logic_vector (8 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_reset0 : std_logic;
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_eq : std_logic;
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpCbrtTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCbrtTest_b : std_logic_vector (7 downto 0);
signal signX_uid7_fpCbrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid7_fpCbrtTest_b : std_logic_vector (0 downto 0);
signal frac_uid15_fpCbrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid15_fpCbrtTest_b : std_logic_vector (22 downto 0);
signal fracXAddr_uid27_fpCbrtTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid27_fpCbrtTest_b : std_logic_vector (6 downto 0);
signal X15dto0_uid29_fpCbrtTest_in : std_logic_vector (15 downto 0);
signal X15dto0_uid29_fpCbrtTest_b : std_logic_vector (15 downto 0);
signal expXIsZero_uid12_fpCbrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid12_fpCbrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid12_fpCbrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid14_fpCbrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid14_fpCbrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid14_fpCbrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid16_fpCbrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid16_fpCbrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid16_fpCbrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid17_fpCbrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid17_fpCbrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid17_fpCbrtTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid33_fpCbrtTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid41_fpCbrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid41_fpCbrtTest_q : std_logic_vector (7 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_b : std_logic_vector (23 downto 0);
signal addrTable_uid28_fpCbrtTest_q : std_logic_vector (8 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal yT1_uid47_cbrtPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid47_cbrtPolyEval_b : std_logic_vector (11 downto 0);
signal InvFracXIsZero_uid18_fpCbrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid18_fpCbrtTest_q : std_logic_vector(0 downto 0);
signal lowRangeB_uid49_cbrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid49_cbrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid50_cbrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid50_cbrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid55_cbrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid55_cbrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid56_cbrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid56_cbrtPolyEval_b : std_logic_vector (21 downto 0);
signal exc_N_uid19_fpCbrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid19_fpCbrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid19_fpCbrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid51_cbrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid51_cbrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid51_cbrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid51_cbrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid57_cbrtPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid57_cbrtPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid57_cbrtPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid57_cbrtPolyEval_q : std_logic_vector (29 downto 0);
signal concExc_uid32_fpCbrtTest_q : std_logic_vector (2 downto 0);
signal s1_uid49_uid52_cbrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid55_uid58_cbrtPolyEval_q : std_logic_vector (31 downto 0);
signal fracR_uid31_fpCbrtTest_in : std_logic_vector (28 downto 0);
signal fracR_uid31_fpCbrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid37_fpCbrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid37_fpCbrtTest_q : std_logic_vector (22 downto 0);
signal RCbrt_uid42_fpCbrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid7_fpCbrtTest(BITSELECT,6)@0
signX_uid7_fpCbrtTest_in <= a;
signX_uid7_fpCbrtTest_b <= signX_uid7_fpCbrtTest_in(31 downto 31);
--ld_signX_uid7_fpCbrtTest_b_to_RCbrt_uid42_fpCbrtTest_c(DELAY,113)@0
ld_signX_uid7_fpCbrtTest_b_to_RCbrt_uid42_fpCbrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signX_uid7_fpCbrtTest_b, xout => ld_signX_uid7_fpCbrtTest_b_to_RCbrt_uid42_fpCbrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable(LOGICAL,163)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_a <= en;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q <= not ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_a;
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor(LOGICAL,177)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_b <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_q <= not (ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_a or ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_b);
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_mem_top(CONSTANT,173)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_mem_top_q <= "01000";
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp(LOGICAL,174)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_a <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_mem_top_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_a = ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg(REG,175)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena(REG,178)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd(LOGICAL,179)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_a <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_sticky_ena_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_a and ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_b;
--cstAllOWE_uid8_fpCbrtTest(CONSTANT,7)
cstAllOWE_uid8_fpCbrtTest_q <= "11111111";
--expX_uid6_fpCbrtTest(BITSELECT,5)@0
expX_uid6_fpCbrtTest_in <= a(30 downto 0);
expX_uid6_fpCbrtTest_b <= expX_uid6_fpCbrtTest_in(30 downto 23);
--reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0(REG,71)@0
reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0_q <= expX_uid6_fpCbrtTest_b;
END IF;
END IF;
END PROCESS;
--divBy3DivRes_uid25_fpCbrtTest_lutmem(DUALMEM,66)@1
divBy3DivRes_uid25_fpCbrtTest_lutmem_ia <= (others => '0');
divBy3DivRes_uid25_fpCbrtTest_lutmem_aa <= (others => '0');
divBy3DivRes_uid25_fpCbrtTest_lutmem_ab <= reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0_q;
divBy3DivRes_uid25_fpCbrtTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 8,
numwords_a => 255,
width_b => 8,
widthad_b => 8,
numwords_b => 255,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cbrt_s5_divBy3DivRes_uid25_fpCbrtTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => divBy3DivRes_uid25_fpCbrtTest_lutmem_reset0,
clock0 => clk,
address_b => divBy3DivRes_uid25_fpCbrtTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => divBy3DivRes_uid25_fpCbrtTest_lutmem_iq,
address_a => divBy3DivRes_uid25_fpCbrtTest_lutmem_aa,
data_a => divBy3DivRes_uid25_fpCbrtTest_lutmem_ia
);
divBy3DivRes_uid25_fpCbrtTest_lutmem_reset0 <= areset;
divBy3DivRes_uid25_fpCbrtTest_lutmem_q <= divBy3DivRes_uid25_fpCbrtTest_lutmem_iq(7 downto 0);
--reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3(REG,85)@3
reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3_q <= divBy3DivRes_uid25_fpCbrtTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--cstAllZWE_uid10_fpCbrtTest(CONSTANT,9)
cstAllZWE_uid10_fpCbrtTest_q <= "00000000";
--cstAllZWF_uid9_fpCbrtTest(CONSTANT,8)
cstAllZWF_uid9_fpCbrtTest_q <= "00000000000000000000000";
--frac_uid15_fpCbrtTest(BITSELECT,14)@0
frac_uid15_fpCbrtTest_in <= a(22 downto 0);
frac_uid15_fpCbrtTest_b <= frac_uid15_fpCbrtTest_in(22 downto 0);
--fracXIsZero_uid16_fpCbrtTest(LOGICAL,15)@0
fracXIsZero_uid16_fpCbrtTest_a <= frac_uid15_fpCbrtTest_b;
fracXIsZero_uid16_fpCbrtTest_b <= cstAllZWF_uid9_fpCbrtTest_q;
fracXIsZero_uid16_fpCbrtTest_q <= "1" when fracXIsZero_uid16_fpCbrtTest_a = fracXIsZero_uid16_fpCbrtTest_b else "0";
--InvFracXIsZero_uid18_fpCbrtTest(LOGICAL,17)@0
InvFracXIsZero_uid18_fpCbrtTest_a <= fracXIsZero_uid16_fpCbrtTest_q;
InvFracXIsZero_uid18_fpCbrtTest_q <= not InvFracXIsZero_uid18_fpCbrtTest_a;
--expXIsMax_uid14_fpCbrtTest(LOGICAL,13)@0
expXIsMax_uid14_fpCbrtTest_a <= expX_uid6_fpCbrtTest_b;
expXIsMax_uid14_fpCbrtTest_b <= cstAllOWE_uid8_fpCbrtTest_q;
expXIsMax_uid14_fpCbrtTest_q <= "1" when expXIsMax_uid14_fpCbrtTest_a = expXIsMax_uid14_fpCbrtTest_b else "0";
--exc_N_uid19_fpCbrtTest(LOGICAL,18)@0
exc_N_uid19_fpCbrtTest_a <= expXIsMax_uid14_fpCbrtTest_q;
exc_N_uid19_fpCbrtTest_b <= InvFracXIsZero_uid18_fpCbrtTest_q;
exc_N_uid19_fpCbrtTest_q <= exc_N_uid19_fpCbrtTest_a and exc_N_uid19_fpCbrtTest_b;
--exc_I_uid17_fpCbrtTest(LOGICAL,16)@0
exc_I_uid17_fpCbrtTest_a <= expXIsMax_uid14_fpCbrtTest_q;
exc_I_uid17_fpCbrtTest_b <= fracXIsZero_uid16_fpCbrtTest_q;
exc_I_uid17_fpCbrtTest_q <= exc_I_uid17_fpCbrtTest_a and exc_I_uid17_fpCbrtTest_b;
--expXIsZero_uid12_fpCbrtTest(LOGICAL,11)@0
expXIsZero_uid12_fpCbrtTest_a <= expX_uid6_fpCbrtTest_b;
expXIsZero_uid12_fpCbrtTest_b <= cstAllZWE_uid10_fpCbrtTest_q;
expXIsZero_uid12_fpCbrtTest_q <= "1" when expXIsZero_uid12_fpCbrtTest_a = expXIsZero_uid12_fpCbrtTest_b else "0";
--concExc_uid32_fpCbrtTest(BITJOIN,31)@0
concExc_uid32_fpCbrtTest_q <= exc_N_uid19_fpCbrtTest_q & exc_I_uid17_fpCbrtTest_q & expXIsZero_uid12_fpCbrtTest_q;
--reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0(REG,70)@0
reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q <= concExc_uid32_fpCbrtTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q_to_excREnc_uid33_fpCbrtTest_a(DELAY,106)@1
ld_reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q_to_excREnc_uid33_fpCbrtTest_a : dspba_delay
GENERIC MAP ( width => 3, depth => 2 )
PORT MAP ( xin => reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q, xout => ld_reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q_to_excREnc_uid33_fpCbrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excREnc_uid33_fpCbrtTest(LOOKUP,32)@3
excREnc_uid33_fpCbrtTest: PROCESS (ld_reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q_to_excREnc_uid33_fpCbrtTest_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_concExc_uid32_fpCbrtTest_0_to_excREnc_uid33_fpCbrtTest_0_q_to_excREnc_uid33_fpCbrtTest_a_q) IS
WHEN "000" => excREnc_uid33_fpCbrtTest_q <= "01";
WHEN "001" => excREnc_uid33_fpCbrtTest_q <= "00";
WHEN "010" => excREnc_uid33_fpCbrtTest_q <= "10";
WHEN "011" => excREnc_uid33_fpCbrtTest_q <= "00";
WHEN "100" => excREnc_uid33_fpCbrtTest_q <= "11";
WHEN "101" => excREnc_uid33_fpCbrtTest_q <= "00";
WHEN "110" => excREnc_uid33_fpCbrtTest_q <= "00";
WHEN "111" => excREnc_uid33_fpCbrtTest_q <= "00";
WHEN OTHERS =>
excREnc_uid33_fpCbrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_excREnc_uid33_fpCbrtTest_0_to_expRPostExc_uid41_fpCbrtTest_1(REG,84)@3
reg_excREnc_uid33_fpCbrtTest_0_to_expRPostExc_uid41_fpCbrtTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid33_fpCbrtTest_0_to_expRPostExc_uid41_fpCbrtTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid33_fpCbrtTest_0_to_expRPostExc_uid41_fpCbrtTest_1_q <= excREnc_uid33_fpCbrtTest_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid41_fpCbrtTest(MUX,40)@4
expRPostExc_uid41_fpCbrtTest_s <= reg_excREnc_uid33_fpCbrtTest_0_to_expRPostExc_uid41_fpCbrtTest_1_q;
expRPostExc_uid41_fpCbrtTest: PROCESS (expRPostExc_uid41_fpCbrtTest_s, en, cstAllZWE_uid10_fpCbrtTest_q, reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3_q, cstAllOWE_uid8_fpCbrtTest_q, cstAllOWE_uid8_fpCbrtTest_q)
BEGIN
CASE expRPostExc_uid41_fpCbrtTest_s IS
WHEN "00" => expRPostExc_uid41_fpCbrtTest_q <= cstAllZWE_uid10_fpCbrtTest_q;
WHEN "01" => expRPostExc_uid41_fpCbrtTest_q <= reg_divBy3DivRes_uid25_fpCbrtTest_lutmem_0_to_expRPostExc_uid41_fpCbrtTest_3_q;
WHEN "10" => expRPostExc_uid41_fpCbrtTest_q <= cstAllOWE_uid8_fpCbrtTest_q;
WHEN "11" => expRPostExc_uid41_fpCbrtTest_q <= cstAllOWE_uid8_fpCbrtTest_q;
WHEN OTHERS => expRPostExc_uid41_fpCbrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_inputreg(DELAY,167)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid41_fpCbrtTest_q, xout => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt(COUNTER,169)
-- every=1, low=0, high=8, step=1, init=1
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i = 7 THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i - 8;
ELSE
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_i,4));
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg(REG,170)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux(MUX,171)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_s, ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q, ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem(DUALMEM,168)
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_ia <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_inputreg_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_aa <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_ab <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_iq(7 downto 0);
--oneFracRPostExc2_uid34_fpCbrtTest(CONSTANT,33)
oneFracRPostExc2_uid34_fpCbrtTest_q <= "00000000000000000000001";
--divBy3Rem_uid24_fpCbrtTest_lutmem(DUALMEM,65)@1
divBy3Rem_uid24_fpCbrtTest_lutmem_ia <= (others => '0');
divBy3Rem_uid24_fpCbrtTest_lutmem_aa <= (others => '0');
divBy3Rem_uid24_fpCbrtTest_lutmem_ab <= reg_expX_uid6_fpCbrtTest_0_to_divBy3Rem_uid24_fpCbrtTest_lutmem_0_q;
divBy3Rem_uid24_fpCbrtTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 8,
numwords_a => 255,
width_b => 2,
widthad_b => 8,
numwords_b => 255,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cbrt_s5_divBy3Rem_uid24_fpCbrtTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => divBy3Rem_uid24_fpCbrtTest_lutmem_reset0,
clock0 => clk,
address_b => divBy3Rem_uid24_fpCbrtTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => divBy3Rem_uid24_fpCbrtTest_lutmem_iq,
address_a => divBy3Rem_uid24_fpCbrtTest_lutmem_aa,
data_a => divBy3Rem_uid24_fpCbrtTest_lutmem_ia
);
divBy3Rem_uid24_fpCbrtTest_lutmem_reset0 <= areset;
divBy3Rem_uid24_fpCbrtTest_lutmem_q <= divBy3Rem_uid24_fpCbrtTest_lutmem_iq(1 downto 0);
--reg_divBy3Rem_uid24_fpCbrtTest_lutmem_0_to_addrTable_uid28_fpCbrtTest_1(REG,73)@3
reg_divBy3Rem_uid24_fpCbrtTest_lutmem_0_to_addrTable_uid28_fpCbrtTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_divBy3Rem_uid24_fpCbrtTest_lutmem_0_to_addrTable_uid28_fpCbrtTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_divBy3Rem_uid24_fpCbrtTest_lutmem_0_to_addrTable_uid28_fpCbrtTest_1_q <= divBy3Rem_uid24_fpCbrtTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--fracXAddr_uid27_fpCbrtTest(BITSELECT,26)@0
fracXAddr_uid27_fpCbrtTest_in <= a(22 downto 0);
fracXAddr_uid27_fpCbrtTest_b <= fracXAddr_uid27_fpCbrtTest_in(22 downto 16);
--ld_fracXAddr_uid27_fpCbrtTest_b_to_reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_a(DELAY,140)@0
ld_fracXAddr_uid27_fpCbrtTest_b_to_reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => fracXAddr_uid27_fpCbrtTest_b, xout => ld_fracXAddr_uid27_fpCbrtTest_b_to_reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0(REG,72)@3
reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_q <= ld_fracXAddr_uid27_fpCbrtTest_b_to_reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_a_q;
END IF;
END IF;
END PROCESS;
--addrTable_uid28_fpCbrtTest(BITJOIN,27)@4
addrTable_uid28_fpCbrtTest_q <= reg_divBy3Rem_uid24_fpCbrtTest_lutmem_0_to_addrTable_uid28_fpCbrtTest_1_q & reg_fracXAddr_uid27_fpCbrtTest_0_to_addrTable_uid28_fpCbrtTest_0_q;
--reg_addrTable_uid28_fpCbrtTest_0_to_memoryC2_uid46_cbrtTableGenerator_lutmem_0(REG,74)@4
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC2_uid46_cbrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC2_uid46_cbrtTableGenerator_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC2_uid46_cbrtTableGenerator_lutmem_0_q <= addrTable_uid28_fpCbrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid46_cbrtTableGenerator_lutmem(DUALMEM,69)@5
memoryC2_uid46_cbrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid46_cbrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid46_cbrtTableGenerator_lutmem_ab <= reg_addrTable_uid28_fpCbrtTest_0_to_memoryC2_uid46_cbrtTableGenerator_lutmem_0_q;
memoryC2_uid46_cbrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 384,
width_b => 12,
widthad_b => 9,
numwords_b => 384,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cbrt_s5_memoryC2_uid46_cbrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid46_cbrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid46_cbrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid46_cbrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid46_cbrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid46_cbrtTableGenerator_lutmem_ia
);
memoryC2_uid46_cbrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid46_cbrtTableGenerator_lutmem_q <= memoryC2_uid46_cbrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid46_cbrtTableGenerator_lutmem_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_1(REG,76)@7
reg_memoryC2_uid46_cbrtTableGenerator_lutmem_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid46_cbrtTableGenerator_lutmem_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid46_cbrtTableGenerator_lutmem_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_1_q <= memoryC2_uid46_cbrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor(LOGICAL,190)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_b <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_q <= not (ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_a or ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_b);
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_mem_top(CONSTANT,186)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_mem_top_q <= "0100";
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp(LOGICAL,187)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_a <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_mem_top_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q);
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_q <= "1" when ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_a = ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_b else "0";
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg(REG,188)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena(REG,191)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_nor_q = "1") THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd(LOGICAL,192)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_a <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_sticky_ena_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_b <= en;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_a and ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_b;
--X15dto0_uid29_fpCbrtTest(BITSELECT,28)@0
X15dto0_uid29_fpCbrtTest_in <= a(15 downto 0);
X15dto0_uid29_fpCbrtTest_b <= X15dto0_uid29_fpCbrtTest_in(15 downto 0);
--yT1_uid47_cbrtPolyEval(BITSELECT,46)@0
yT1_uid47_cbrtPolyEval_in <= X15dto0_uid29_fpCbrtTest_b;
yT1_uid47_cbrtPolyEval_b <= yT1_uid47_cbrtPolyEval_in(15 downto 4);
--reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0(REG,75)@0
reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q <= yT1_uid47_cbrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_inputreg(DELAY,180)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q, xout => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt(COUNTER,182)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg(REG,183)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux(MUX,184)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_s <= en;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux: PROCESS (ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_s, ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q, ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem(DUALMEM,181)
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_ia <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_inputreg_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_aa <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_ab <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 3,
numwords_a => 5,
width_b => 12,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_iq,
address_a => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_aa,
data_a => ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_ia
);
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_iq(11 downto 0);
--prodXY_uid60_pT1_uid48_cbrtPolyEval(MULT,59)@8
prodXY_uid60_pT1_uid48_cbrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid60_pT1_uid48_cbrtPolyEval_a),13)) * SIGNED(prodXY_uid60_pT1_uid48_cbrtPolyEval_b);
prodXY_uid60_pT1_uid48_cbrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid60_pT1_uid48_cbrtPolyEval_a <= (others => '0');
prodXY_uid60_pT1_uid48_cbrtPolyEval_b <= (others => '0');
prodXY_uid60_pT1_uid48_cbrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid60_pT1_uid48_cbrtPolyEval_a <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_mem_q;
prodXY_uid60_pT1_uid48_cbrtPolyEval_b <= reg_memoryC2_uid46_cbrtTableGenerator_lutmem_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_1_q;
prodXY_uid60_pT1_uid48_cbrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid60_pT1_uid48_cbrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid60_pT1_uid48_cbrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid60_pT1_uid48_cbrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid60_pT1_uid48_cbrtPolyEval_q <= prodXY_uid60_pT1_uid48_cbrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval(BITSELECT,60)@11
prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_in <= prodXY_uid60_pT1_uid48_cbrtPolyEval_q;
prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_b <= prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_in(23 downto 11);
--highBBits_uid50_cbrtPolyEval(BITSELECT,49)@11
highBBits_uid50_cbrtPolyEval_in <= prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_b;
highBBits_uid50_cbrtPolyEval_b <= highBBits_uid50_cbrtPolyEval_in(12 downto 1);
--ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_a(DELAY,145)@4
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => addrTable_uid28_fpCbrtTest_q, xout => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0(REG,77)@7
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_q <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid45_cbrtTableGenerator_lutmem(DUALMEM,68)@8
memoryC1_uid45_cbrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid45_cbrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid45_cbrtTableGenerator_lutmem_ab <= reg_addrTable_uid28_fpCbrtTest_0_to_memoryC1_uid45_cbrtTableGenerator_lutmem_0_q;
memoryC1_uid45_cbrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 384,
width_b => 21,
widthad_b => 9,
numwords_b => 384,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cbrt_s5_memoryC1_uid45_cbrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid45_cbrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid45_cbrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid45_cbrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid45_cbrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid45_cbrtTableGenerator_lutmem_ia
);
memoryC1_uid45_cbrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid45_cbrtTableGenerator_lutmem_q <= memoryC1_uid45_cbrtTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0(REG,78)@10
reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0_q <= memoryC1_uid45_cbrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid51_cbrtPolyEval(ADD,50)@11
sumAHighB_uid51_cbrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0_q(20)) & reg_memoryC1_uid45_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid51_cbrtPolyEval_0_q);
sumAHighB_uid51_cbrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid50_cbrtPolyEval_b(11)) & highBBits_uid50_cbrtPolyEval_b);
sumAHighB_uid51_cbrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid51_cbrtPolyEval_a) + SIGNED(sumAHighB_uid51_cbrtPolyEval_b));
sumAHighB_uid51_cbrtPolyEval_q <= sumAHighB_uid51_cbrtPolyEval_o(21 downto 0);
--lowRangeB_uid49_cbrtPolyEval(BITSELECT,48)@11
lowRangeB_uid49_cbrtPolyEval_in <= prodXYTruncFR_uid61_pT1_uid48_cbrtPolyEval_b(0 downto 0);
lowRangeB_uid49_cbrtPolyEval_b <= lowRangeB_uid49_cbrtPolyEval_in(0 downto 0);
--s1_uid49_uid52_cbrtPolyEval(BITJOIN,51)@11
s1_uid49_uid52_cbrtPolyEval_q <= sumAHighB_uid51_cbrtPolyEval_q & lowRangeB_uid49_cbrtPolyEval_b;
--reg_s1_uid49_uid52_cbrtPolyEval_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_1(REG,80)@11
reg_s1_uid49_uid52_cbrtPolyEval_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid49_uid52_cbrtPolyEval_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid49_uid52_cbrtPolyEval_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_1_q <= s1_uid49_uid52_cbrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor(LOGICAL,203)
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_b <= ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena_q;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_q <= not (ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_a or ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_b);
--ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena(REG,204)
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_nor_q = "1") THEN
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena_q <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd(LOGICAL,205)
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_a <= ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_sticky_ena_q;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_b <= en;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_q <= ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_a and ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_b;
--reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0(REG,79)@0
reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q <= X15dto0_uid29_fpCbrtTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_inputreg(DELAY,193)
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q, xout => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem(DUALMEM,194)
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_ia <= ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_inputreg_q;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_aa <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdreg_q;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_ab <= ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_rdmux_q;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 9,
width_b => 16,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_iq,
address_a => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_aa,
data_a => ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_ia
);
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_q <= ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid63_pT2_uid54_cbrtPolyEval(MULT,62)@12
prodXY_uid63_pT2_uid54_cbrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid63_pT2_uid54_cbrtPolyEval_a),17)) * SIGNED(prodXY_uid63_pT2_uid54_cbrtPolyEval_b);
prodXY_uid63_pT2_uid54_cbrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid63_pT2_uid54_cbrtPolyEval_a <= (others => '0');
prodXY_uid63_pT2_uid54_cbrtPolyEval_b <= (others => '0');
prodXY_uid63_pT2_uid54_cbrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid63_pT2_uid54_cbrtPolyEval_a <= ld_reg_X15dto0_uid29_fpCbrtTest_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_0_q_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_a_replace_mem_q;
prodXY_uid63_pT2_uid54_cbrtPolyEval_b <= reg_s1_uid49_uid52_cbrtPolyEval_0_to_prodXY_uid63_pT2_uid54_cbrtPolyEval_1_q;
prodXY_uid63_pT2_uid54_cbrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid63_pT2_uid54_cbrtPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid63_pT2_uid54_cbrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid63_pT2_uid54_cbrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid63_pT2_uid54_cbrtPolyEval_q <= prodXY_uid63_pT2_uid54_cbrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval(BITSELECT,63)@15
prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_in <= prodXY_uid63_pT2_uid54_cbrtPolyEval_q;
prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_b <= prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_in(38 downto 15);
--highBBits_uid56_cbrtPolyEval(BITSELECT,55)@15
highBBits_uid56_cbrtPolyEval_in <= prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_b;
highBBits_uid56_cbrtPolyEval_b <= highBBits_uid56_cbrtPolyEval_in(23 downto 2);
--ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor(LOGICAL,216)
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena(REG,217)
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,218)
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_inputreg(DELAY,206)
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => addrTable_uid28_fpCbrtTest_q, xout => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,207)
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdreg_q;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_yT1_uid47_cbrtPolyEval_0_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_0_q_to_prodXY_uid60_pT1_uid48_cbrtPolyEval_a_replace_rdmux_q;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_iq(8 downto 0);
--reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0(REG,81)@11
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_q <= ld_addrTable_uid28_fpCbrtTest_q_to_reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid44_cbrtTableGenerator_lutmem(DUALMEM,67)@12
memoryC0_uid44_cbrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid44_cbrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid44_cbrtTableGenerator_lutmem_ab <= reg_addrTable_uid28_fpCbrtTest_0_to_memoryC0_uid44_cbrtTableGenerator_lutmem_0_q;
memoryC0_uid44_cbrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 9,
numwords_a => 384,
width_b => 29,
widthad_b => 9,
numwords_b => 384,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cbrt_s5_memoryC0_uid44_cbrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid44_cbrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid44_cbrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid44_cbrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid44_cbrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid44_cbrtTableGenerator_lutmem_ia
);
memoryC0_uid44_cbrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid44_cbrtTableGenerator_lutmem_q <= memoryC0_uid44_cbrtTableGenerator_lutmem_iq(28 downto 0);
--reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0(REG,82)@14
reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0_q <= memoryC0_uid44_cbrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid57_cbrtPolyEval(ADD,56)@15
sumAHighB_uid57_cbrtPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0_q(28)) & reg_memoryC0_uid44_cbrtTableGenerator_lutmem_0_to_sumAHighB_uid57_cbrtPolyEval_0_q);
sumAHighB_uid57_cbrtPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid56_cbrtPolyEval_b(21)) & highBBits_uid56_cbrtPolyEval_b);
sumAHighB_uid57_cbrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid57_cbrtPolyEval_a) + SIGNED(sumAHighB_uid57_cbrtPolyEval_b));
sumAHighB_uid57_cbrtPolyEval_q <= sumAHighB_uid57_cbrtPolyEval_o(29 downto 0);
--lowRangeB_uid55_cbrtPolyEval(BITSELECT,54)@15
lowRangeB_uid55_cbrtPolyEval_in <= prodXYTruncFR_uid64_pT2_uid54_cbrtPolyEval_b(1 downto 0);
lowRangeB_uid55_cbrtPolyEval_b <= lowRangeB_uid55_cbrtPolyEval_in(1 downto 0);
--s2_uid55_uid58_cbrtPolyEval(BITJOIN,57)@15
s2_uid55_uid58_cbrtPolyEval_q <= sumAHighB_uid57_cbrtPolyEval_q & lowRangeB_uid55_cbrtPolyEval_b;
--fracR_uid31_fpCbrtTest(BITSELECT,30)@15
fracR_uid31_fpCbrtTest_in <= s2_uid55_uid58_cbrtPolyEval_q(28 downto 0);
fracR_uid31_fpCbrtTest_b <= fracR_uid31_fpCbrtTest_in(28 downto 6);
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor(LOGICAL,164)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_notEnable_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_b <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_q <= not (ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_a or ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_b);
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_mem_top(CONSTANT,160)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_mem_top_q <= "01001";
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp(LOGICAL,161)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_mem_top_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_q);
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_q <= "1" when ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_a = ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_b else "0";
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmpReg(REG,162)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmpReg_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena(REG,165)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_nor_q = "1") THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd(LOGICAL,166)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_a <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_sticky_ena_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_b <= en;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_a and ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_b;
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_inputreg(DELAY,154)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => excREnc_uid33_fpCbrtTest_q, xout => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt(COUNTER,156)
-- every=1, low=0, high=9, step=1, init=1
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i = 8 THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_eq = '1') THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i - 9;
ELSE
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_i,4));
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg(REG,157)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux(MUX,158)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_s <= en;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux: PROCESS (ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_s, ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg_q, ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg_q;
WHEN "1" => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem(DUALMEM,155)
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_ia <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_inputreg_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_aa <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdreg_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_ab <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_rdmux_q;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 10,
width_b => 2,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_iq,
address_a => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_aa,
data_a => ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_ia
);
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_reset0 <= areset;
ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_q <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid37_fpCbrtTest(MUX,36)@15
fracRPostExc_uid37_fpCbrtTest_s <= ld_excREnc_uid33_fpCbrtTest_q_to_fracRPostExc_uid37_fpCbrtTest_b_replace_mem_q;
fracRPostExc_uid37_fpCbrtTest: PROCESS (fracRPostExc_uid37_fpCbrtTest_s, en, cstAllZWF_uid9_fpCbrtTest_q, fracR_uid31_fpCbrtTest_b, cstAllZWF_uid9_fpCbrtTest_q, oneFracRPostExc2_uid34_fpCbrtTest_q)
BEGIN
CASE fracRPostExc_uid37_fpCbrtTest_s IS
WHEN "00" => fracRPostExc_uid37_fpCbrtTest_q <= cstAllZWF_uid9_fpCbrtTest_q;
WHEN "01" => fracRPostExc_uid37_fpCbrtTest_q <= fracR_uid31_fpCbrtTest_b;
WHEN "10" => fracRPostExc_uid37_fpCbrtTest_q <= cstAllZWF_uid9_fpCbrtTest_q;
WHEN "11" => fracRPostExc_uid37_fpCbrtTest_q <= oneFracRPostExc2_uid34_fpCbrtTest_q;
WHEN OTHERS => fracRPostExc_uid37_fpCbrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--RCbrt_uid42_fpCbrtTest(BITJOIN,41)@15
RCbrt_uid42_fpCbrtTest_q <= ld_signX_uid7_fpCbrtTest_b_to_RCbrt_uid42_fpCbrtTest_c_q & ld_expRPostExc_uid41_fpCbrtTest_q_to_RCbrt_uid42_fpCbrtTest_b_replace_mem_q & fracRPostExc_uid37_fpCbrtTest_q;
--xOut(GPOUT,4)@15
q <= RCbrt_uid42_fpCbrtTest_q;
end normal;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_cntusgn36.vhd | 10 | 4376 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN36.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn36;
ARCHITECTURE rtl OF hcc_cntusgn36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(35) OR frac(34) OR frac(33) OR frac(32) OR frac(31) OR frac(30);
sec(2) <= frac(29) OR frac(28) OR frac(27) OR frac(26) OR frac(25) OR frac(24);
sec(3) <= frac(23) OR frac(22) OR frac(21) OR frac(20) OR frac(19) OR frac(18);
sec(4) <= frac(17) OR frac(16) OR frac(15) OR frac(14) OR frac(13) OR frac(12);
sec(5) <= frac(11) OR frac(10) OR frac(9) OR frac(8) OR frac(7) OR frac(6);
sec(6) <= frac(5) OR frac(4) OR frac(3) OR frac(2) OR frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(35 DOWNTO 30),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(29 DOWNTO 24),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(23 DOWNTO 18),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(17 DOWNTO 12),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(11 DOWNTO 6),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(5 DOWNTO 1) & '0';
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/SinPiDPStratixVf400_safe_path.vhd | 10 | 437 | -- safe_path for SinPiDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinPiDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinPiDPStratixVf400_safe_path;
PACKAGE body SinPiDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END SinPiDPStratixVf400_safe_path;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/dp_div_core.vhd | 10 | 10866 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION DIVIDER - CORE ***
--*** ***
--*** DP_DIV_CORE.VHD ***
--*** ***
--*** Function: Fixed Point 54 Bit Divider ***
--*** ***
--*** Multiplier Convergence Algorithm ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 19 + 4*doublespeed ***
--*** SIII/IV Latency = 18 + 2*doublespeed ***
--***************************************************
ENTITY dp_div_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dividend : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
divisor : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (55 DOWNTO 1)
);
END dp_div_core;
ARCHITECTURE rtl OF dp_div_core IS
--SII mullatency = doublespeed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
--SII addlatency = 2*doublespeed+1, SIII/IV addlatency = doublespeed+1
constant addlatency : positive := 2*doublespeed+1 - device*doublespeed;
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
-- estimate
signal invdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal dividenddel, divisordel : STD_LOGIC_VECTOR (54 DOWNTO 1);
-- scale
signal scaleden, scalenum : STD_LOGIC_VECTOR (54 DOWNTO 1);
-- iteration
signal twonode, subscaleden : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal guessone : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal absoluteval : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal absolutevalff, absoluteff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal abscarryff : STD_LOGIC;
signal delscalenum : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal iteratenumnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal iteratenum : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal absoluteerror : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal mulabsguesslower : STD_LOGIC_VECTOR (19 DOWNTO 1);
signal mulabsguessnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal mulabsguess : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal quotientnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
component fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component dp_fxadd
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
invcore: fp_div_est
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>divisor(54 DOWNTO 36),invdivisor=>invdivisor);
delinone: fp_del
GENERIC MAP (width=>54,pipes=>5)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dividend,cc=>dividenddel);
delintwo: fp_del
GENERIC MAP (width=>54,pipes=>5)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>divisor,cc=>divisordel);
--**********************************
--*** ITERATION 0 - SCALE INPUTS ***
--**********************************
-- in level 5, out level 8+doublespeed
mulscaleone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>54,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>divisordel,databb=>invdivisor,
result=>scaleden);
mulscaletwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>54,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dividenddel,databb=>invdivisor,
result=>scalenum);
--********************
--*** ITERATION 1 ***
--********************
twonode <= '1' & zerovec(54 DOWNTO 1);
gta: FOR k IN 1 TO 54 GENERATE
subscaleden(k) <= NOT(scaleden(k));
END GENERATE;
subscaleden(55) <= '1';
-- in level 8+speed, outlevel 9+2*speed
addtwoone: dp_fxadd
GENERIC MAP (width=>55,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>twonode,bb=>subscaleden,carryin=>'1',
cc=>guessone);
guessonevec <= guessone(54 DOWNTO 1);
-- absolute value of guess lower 36 bits
-- this is still correct, because (for positive), value will be 1.(17 zeros)error
-- can also be calculated from guessonevec (code below)
-- gabs: FOR k IN 1 TO 36 GENERATE
-- absoluteval(k) <= guessonevec(k) XOR NOT(guessonevec(54));
-- END GENERATE;
gabs: FOR k IN 1 TO 36 GENERATE
absoluteval(k) <= scaleden(k) XOR NOT(scaleden(54));
END GENERATE;
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
absolutevalff(k) <= '0';
absoluteff(k) <= '0';
END LOOP;
abscarryff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absolutevalff <= absoluteval; -- out level 9+speed
abscarryff <= NOT(scaleden(54));
absoluteff <= absolutevalff +
(zerovec(35 DOWNTO 1) & abscarryff); -- out level 10+speed
END IF;
END IF;
END PROCESS;
deloneone: fp_del
GENERIC MAP (width=>54,pipes=>doublespeed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>scalenum,
cc=>delscalenum);
-- in level 9+2*doublespeed
-- SII out level 14+3*doublespeed
-- SIII/IV out level 13+2*doublespeed
muloneone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>delscalenum,databb=>guessonevec,
result=>iteratenumnode);
gia: IF (device = 0) GENERATE
iteratenum <= iteratenumnode(71 DOWNTO 18);
END GENERATE;
gib: IF (device = 1) GENERATE
-- SIII/IV out level 14+2*doublespeed
delit: fp_del
GENERIC MAP (width=>54,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>iteratenumnode(71 DOWNTO 18),
cc=>iteratenum);
END GENERATE;
-- in level 10+doublespeed, out level 13+doublespeed
mulonetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>absoluteff,databb=>absoluteff,
result=>absoluteerror);
-- if speed = 0, delay absoluteerror 1 clock, else 2
-- this guess always positive (check??)
-- change here, error can be [19:1], not [18:1] - this is because (1.[17 zeros].error)^2
-- gives 1.[34 zeros].error
-- in level 13+speed
-- SII out level 14+3*speed
-- SIII/IV out level 14+2*speed
addtwotwo: dp_fxadd
GENERIC MAP (width=>19,pipes=>addlatency,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absoluteerror(72 DOWNTO 54),
bb=>zerovec(19 DOWNTO 1),
carryin=>absoluteerror(53),
cc=>mulabsguesslower);
mulabsguessnode(19 DOWNTO 1) <= mulabsguesslower;
gmga: FOR k IN 20 TO 53 GENERATE
mulabsguessnode(k) <= '0';
END GENERATE;
mulabsguessnode(54) <= '1';
mulabsguess <= mulabsguessnode;
--*********************
--*** OUTPUT SCALE ***
--*********************
-- SII: in level 14+3*doublespeed, out level 19+4*doublespeed
-- SIII/IV: in level 14+2*doublespeed, out level 18+2*doublespeed
mulout: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>iteratenum,databb=>mulabsguess,
result=>quotientnode);
quotient <= quotientnode(71 DOWNTO 17);
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/hcc_lsftpipe32_sv.vhd | 20 | 4030 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_inv.vhd | 10 | 8297 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** FP_INV.VHD ***
--*** ***
--*** Function: IEEE754 SP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 14 ***
--***************************************************
ENTITY fp_inv IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_inv;
ARCHITECTURE div OF fp_inv IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 12;
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (expwidth DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (manwidth DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- inverse always less than 1, decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(34 DOWNTO 11),
nanin=>nanff(coredepth-3),dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END div;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_mulfp2x.vhd | 10 | 24298 |
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP2X.VHD ***
--*** ***
--*** Function: Double precision multiplier ***
--*** (unsigned mantissa) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 28/01/08 - see below ***
--*** ***
--*** ***
--***************************************************
-- 28/01/08 - correct manoverflow for ieee output, effects of mantissa shift
-- for both ieee and mult output, test output widths, also reversed exp and man
-- order in ieee output
-- 31/08/08 - behavioral and synth mults both now return "001X" (> 2) OR "0001X" (<2)
-- change xoutput to 1 bit less right shift (behavioral mult changed)
ENTITY hcc_mulfp2x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_mulfp2x;
ARCHITECTURE rtl OF hcc_mulfp2x IS
type ccxexpdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type cceexpdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- multiplier core interface
signal mulinaaman, mulinbbman : STD_LOGIC_VECTOR(54 DOWNTO 1);
signal mulinaaexp, mulinbbexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal mulinaasat, mulinaazip : STD_LOGIC;
signal mulinbbsat, mulinbbzip : STD_LOGIC;
signal mulinaasign, mulinbbsign : STD_LOGIC;
signal mulinaasignff, mulinbbsignff : STD_LOGIC;
signal mulsignff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal ccmannode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccexpnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccsatnode, cczipnode : STD_LOGIC;
-- output section (x out)
signal ccmanshiftnode, signedccxmannode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccxroundnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccxroundff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccxexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccxsatff, ccxzipff : STD_LOGIC;
signal ccxexpdelff : ccxexpdelfftype;
signal ccxsatdelff, ccxzipdelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
-- output section (ieeeout)
signal shiftroundbit : STD_LOGIC;
signal cceroundnode : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal cceroundcarry : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal ccemannode : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal ccemanoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal cceexpoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal ccesignbitff : STD_LOGIC;
signal cceroundff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal cceexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccesatff, ccezipff : STD_LOGIC;
signal ccesignff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal cceexpdelff : cceexpdelfftype;
signal ccesatdelff, ccezipdelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal ccesigndelff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal cceexpbase, cceexpplus : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccesatbase, ccezipbase : STD_LOGIC;
signal cceexpmax, cceexpzero : STD_LOGIC;
signal manoutzero, expoutzero, expoutmax : STD_LOGIC;
signal manoverflow : STD_LOGIC;
-- output section (multout)
signal shiftmanbit : STD_LOGIC;
signal manshiftnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal manshiftff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal ccexpdelff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccsatdelff, cczipdelff : STD_LOGIC;
signal muloutsignff : STD_LOGIC;
-- debug
signal aaexp, bbexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (11 + 2*multoutput + 2*xoutput DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (54+10*xoutput DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_mulufp54
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bbman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (13 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--**************************************************
--*** ***
--*** Input Section - Normalization, if required ***
--*** ***
--**************************************************
--********************************************************
--*** NOTE THAT IN ALL CASES SIGN BIT IS PACKED IN MSB ***
--*** OF UNSIGNED MULTIPLIER ***
--********************************************************
--*** ieee754 input when multiplier input is from cast ***
--*** cast now creates different ***
--*** formats for multiplier, divider, and alu ***
--*** multiplier format [S][1][mantissa....] ***
--********************************************************
--********************************************************
--*** if input from another double multiplier (special ***
--*** output mode normalizes to 54 bit mantissa and ***
--*** 13 bit exponent ***
--*** multiplier format [S][1][mantissa....] ***
--********************************************************
--********************************************************
--*** if input from internal format, must be normed ***
--*** by normfp2x first, creates [S][1][mantissa...] ***
--********************************************************
mulinaaman <= '0' & aa(66 DOWNTO 14);
mulinaaexp <= aa(13 DOWNTO 1);
mulinbbman <= '0' & bb(66 DOWNTO 14);
mulinbbexp <= bb(13 DOWNTO 1);
mulinaasat <= aasat;
mulinaazip <= aazip;
mulinbbsat <= bbsat;
mulinbbzip <= bbzip;
-- signbits packed in MSB of mantissas
mulinaasign <= aa(67);
mulinbbsign <= bb(67);
--**************************************************
--*** ***
--*** Multiplier Section ***
--*** ***
--**************************************************
mult: hcc_mulufp54
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mulinaaman,aaexp=>mulinaaexp,aasat=>mulinaasat,aazip=>mulinaazip,
bbman=>mulinbbman,bbexp=>mulinbbexp,bbsat=>mulinbbsat,bbzip=>mulinbbzip,
ccman=>ccmannode,ccexp=>ccexpnode,ccsat=>ccsatnode,cczip=>cczipnode);
psd: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
mulinaasignff <= '0';
mulinbbsignff <= '0';
FOR k IN 1 TO 5 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mulinaasignff <= mulinaasign;
mulinbbsignff <= mulinbbsign;
mulsignff(1) <= mulinaasignff XOR mulinbbsignff;
FOR k IN 2 TO 5 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************************************************
--*** ***
--*** Output Section ***
--*** ***
--**************************************************
--********************************************************
--*** internal format output, convert back to signed ***
--*** no need for fine normalization ***
--********************************************************
goxa: IF (xoutput = 1) GENERATE
-- result will be "001X" (>2) or "0001X" (<2)
-- Y is SSSSS1 (<2) - therefore right shift 2 bits
-- 31/08/08 - behavioral mult changed to be same as synth one
ccmanshiftnode <= "00" & ccmannode(64 DOWNTO 3);
goxb: FOR k IN 1 TO 64 GENERATE
signedccxmannode(k) <= ccmanshiftnode(k) XOR mulsignff(5);
END GENERATE;
goxc: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
--*** OUTPUTS ***
cc(77 DOWNTO 14) <= signedccxmannode;
cc(13 DOWNTO 1) <= ccexpnode;
ccsat <= ccsatnode;
cczip <= cczipnode;
END GENERATE;
goxd: IF ((roundconvert = 0 AND outputpipe = 1) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
goxe: IF (roundconvert = 0) GENERATE
ccxroundnode <= signedccxmannode;
END GENERATE;
goxf: IF (roundconvert = 1) GENERATE
ccxroundnode <= signedccxmannode + (zerovec(63 DOWNTO 1) & mulsignff(5));
END GENERATE;
poxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
ccxroundff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
ccxexpff(k) <= '0';
END LOOP;
ccxsatff <= '0';
ccxzipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccxroundff <= ccxroundnode;
ccxexpff <= ccexpnode;
ccxsatff <= ccsatnode;
ccxzipff <= cczipnode;
END IF;
END IF;
END PROCESS;
--*** OUTPUTS ***
cc(77 DOWNTO 14) <= ccxroundff;
cc(13 DOWNTO 1) <= ccxexpff(13 DOWNTO 1);
ccsat <= ccxsatff;
cczip <= ccxzipff;
END GENERATE;
goxg: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
poxb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
ccxexpdelff(1)(k) <= '0';
ccxexpdelff(2)(k) <= '0';
END LOOP;
ccxsatdelff <= "00";
ccxzipdelff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccxexpdelff(1)(13 DOWNTO 1) <= ccexpnode;
ccxexpdelff(2)(13 DOWNTO 1) <= ccxexpdelff(1)(13 DOWNTO 1);
ccxsatdelff(1) <= ccsatnode;
ccxsatdelff(2) <= ccxsatdelff(1);
ccxzipdelff(1) <= cczipnode;
ccxzipdelff(2) <= ccxzipdelff(1);
END IF;
END IF;
END PROCESS;
goxh: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signedccxmannode,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(5),
cc=>ccxroundnode);
END GENERATE;
goxi: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signedccxmannode,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(5),
cc=>ccxroundnode);
END GENERATE;
--*** OUTPUTS ***
cc(77 DOWNTO 14) <= ccxroundnode;
cc(13 DOWNTO 1) <= ccxexpdelff(2)(13 DOWNTO 1);
ccsat <= ccxsatdelff(2);
cczip <= ccxzipdelff(2);
END GENERATE;
END GENERATE;
--********************************************************
--*** if output directly out of datapath, convert here ***
--*** input to multiplier always "01XXX" format, so ***
--*** just 1 bit normalization required ***
--********************************************************
goea: IF (ieeeoutput = 1) GENERATE -- ieee754 out of datapath, do conversion
-- output either "0001XXXX.." (<2) or "001XXXX.." (>=2), need to make output
-- 01XXXX
shiftroundbit <= NOT(ccmannode(62));
goeb: FOR k IN 1 TO 55 GENERATE -- format "01"[52..1]R
cceroundnode(k) <= (ccmannode(k+7) AND shiftroundbit) OR
(ccmannode(k+8) AND NOT(shiftroundbit));
END GENERATE;
goec: IF (roundconvert = 0) GENERATE
ccemannode <= cceroundnode(53 DOWNTO 2);
poia: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= '0';
END LOOP;
ccesignbitff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= ccemannode(k) AND NOT(manoutzero);
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= (cceexpplus(k) OR expoutmax) AND NOT(expoutzero);
END LOOP;
ccesignbitff <= mulsignff(5);
END IF;
END IF;
END PROCESS;
cceexpplus <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftroundbit)); -- change 28/01/08
ccesatbase <= ccsatnode;
ccezipbase <= cczipnode;
manoverflow <= '0'; -- change 28/01/08
--*** OUTPUTS ***
cc(64) <= ccesignbitff;
-- change 28/01/08
cc(63 DOWNTO 53) <= cceexpoutff;
cc(52 DOWNTO 1) <= ccemanoutff;
END GENERATE;
goed: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
cceroundcarry <= zerovec(53 DOWNTO 1) & cceroundnode(1);
poeb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
cceroundff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
cceexpff(k) <= '0';
END LOOP;
ccesatff <= '0';
ccezipff <= '0';
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= '0';
END LOOP;
ccesignff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
cceroundff <= cceroundnode(55 DOWNTO 2) + cceroundcarry;
-- change 28/01/08
cceexpff(13 DOWNTO 1) <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftroundbit));
ccesatff <= ccsatnode;
ccezipff <= cczipnode;
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= cceroundff(k) AND NOT(manoutzero);
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= (cceexpplus(k) OR expoutmax) AND NOT(expoutzero);
END LOOP;
ccesignff(1) <= mulsignff(5);
ccesignff(2) <= ccesignff(1);
END IF;
END IF;
END PROCESS;
manoverflow <= cceroundff(54);
cceexpbase <= cceexpff(13 DOWNTO 1);
ccesatbase <= ccesatff;
ccezipbase <= ccezipff;
cceexpplus <= cceexpbase + ("000000000000" & cceroundff(54));
--*** OUTPUTS ***
cc(64) <= ccesignff(2);
-- change 28/01/08
cc(63 DOWNTO 53) <= cceexpoutff;
cc(52 DOWNTO 1) <= ccemanoutff;
END GENERATE;
goef: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
cceroundcarry <= zerovec(53 DOWNTO 1) & cceroundnode(1);
goeg: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cceroundnode(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),
carryin=>cceroundnode(1),
cc=>cceroundnode);
END GENERATE;
goeh: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cceroundnode(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),
carryin=>cceroundnode(1),
cc=>cceroundnode);
END GENERATE;
poea: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
cceexpdelff(1)(k) <= '0';
cceexpdelff(2)(k) <= '0';
END LOOP;
ccesatdelff <= "00";
ccezipdelff <= "00";
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= '0';
END LOOP;
ccesigndelff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- change 28/01/08
cceexpdelff(1)(13 DOWNTO 1) <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftroundbit));
cceexpdelff(2)(13 DOWNTO 1) <= cceexpdelff(1)(13 DOWNTO 1);
ccesatdelff(1) <= ccsatnode;
ccesatdelff(2) <= ccesatdelff(1);
ccezipdelff(1) <= cczipnode;
ccezipdelff(2) <= ccezipdelff(1);
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= cceroundnode(k) AND NOT(manoutzero);
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= (cceexpplus(k) OR expoutmax) AND NOT(expoutzero);
END LOOP;
ccesigndelff(1) <= mulsignff(5);
ccesigndelff(2) <= ccesigndelff(1);
ccesigndelff(3) <= ccesigndelff(2);
END IF;
END IF;
END PROCESS;
manoverflow <= cceroundnode(54);
cceexpbase <= cceexpdelff(2)(13 DOWNTO 1);
ccesatbase <= ccesatdelff(2);
ccezipbase <= ccezipdelff(2);
cceexpplus <= cceexpbase + ("000000000000" & cceroundnode(54));
--*** OUTPUTS ***
cc(64) <= ccesigndelff(3);
-- change 28/01/08
cc(63 DOWNTO 53) <= cceexpoutff;
cc(52 DOWNTO 1) <= ccemanoutff;
END GENERATE;
cceexpmax <= cceexpplus(11) AND cceexpplus(10) AND cceexpplus(9) AND cceexpplus(8) AND
cceexpplus(7) AND cceexpplus(6) AND cceexpplus(5) AND cceexpplus(4) AND
cceexpplus(3) AND cceexpplus(2) AND cceexpplus(1);
cceexpzero <= NOT(cceexpplus(11) OR cceexpplus(10) OR cceexpplus(9) OR cceexpplus(8) OR
cceexpplus(7) OR cceexpplus(6) OR cceexpplus(5) OR cceexpplus(4) OR
cceexpplus(3) OR cceexpplus(2) OR cceexpplus(1));
-- any special condition turns mantissa zero
manoutzero <= ccesatbase OR ccezipbase OR
cceexpmax OR cceexpzero OR
cceexpplus(13) OR cceexpplus(12) OR
manoverflow;
expoutzero <= ccezipbase OR cceexpzero OR cceexpplus(13);
expoutmax <= cceexpmax OR cceexpplus(12);
-- dummy only
ccsat <= '0';
cczip <= '0';
END GENERATE;
--********************************************************
--*** if output directly into DP mult, convert here ***
--*** input to multiplier always "01XXX" format, so ***
--*** just 1 bit normalization required, no round ***
--********************************************************
goma: IF (multoutput = 1) GENERATE -- to another multiplier
-- output either "0001XXXX.." (<2) or "001XXXX.." (>=2), need to make output
-- 01XXXX
shiftmanbit <= NOT(ccmannode(62));
gomb: FOR k IN 1 TO 54 GENERATE -- format "01"[52..1]
manshiftnode(k) <= (ccmannode(k+8) AND shiftmanbit) OR
(ccmannode(k+9) AND NOT(shiftmanbit));
END GENERATE;
poma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
manshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
ccexpdelff(k) <= '0';
END LOOP;
ccsatdelff <= '0';
cczipdelff <= '0';
muloutsignff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
manshiftff <= manshiftnode;
-- change 28/01/08
ccexpdelff(13 DOWNTO 1) <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftmanbit));
ccsatdelff <= ccsatnode;
cczipdelff <= cczipnode;
muloutsignff <= mulsignff(5);
END IF;
END IF;
END PROCESS;
cc(67) <= muloutsignff;
cc(66 DOWNTO 14) <= manshiftff(53 DOWNTO 1);
cc(13 DOWNTO 1) <= ccexpdelff(13 DOWNTO 1);
ccsat <= ccsatdelff;
cczip <= cczipdelff;
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
aaman <= aa(67 DOWNTO 14);
bbman <= bb(67 DOWNTO 14);
gdba: IF (xoutput = 1) GENERATE
gdbb: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
ccman <= signedccxmannode;
ccexp <= ccexpnode;
END GENERATE;
gdbc: IF ((roundconvert = 0 AND outputpipe = 1) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
ccman <= ccxroundff;
ccexp <= ccxexpff(13 DOWNTO 1);
END GENERATE;
gdbd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
ccman <= ccxroundnode;
ccexp <= ccxexpdelff(2)(13 DOWNTO 1);
END GENERATE;
END GENERATE;
-- change 28/01/08
gdbe: IF (ieeeoutput = 1) GENERATE
ccexp <= cceexpoutff;
ccman <= "01" & ccemanoutff;
END GENERATE;
-- change 28/01/08
gdbf: IF (multoutput = 1) GENERATE
ccexp <= ccexpdelff(13 DOWNTO 1);
ccman <= '0' & manshiftff(53 DOWNTO 1);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/fp_neg.vhd | 10 | 3070 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_NEG.VHD ***
--*** ***
--*** Function: Single Precision Negative Value ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_neg IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_neg;
ARCHITECTURE rtl OF fp_neg IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 8 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= NOT(signin);
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(8));
expmax <= expmaxchk(8);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(23));
mannonzero <= manzerochk(23);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
| mit |
QuantumRipple/VHDL | basic/sha256.vhd | 1 | 5363 | --status: somewhat pipelined but yet to be timing optimized. Could also use DSPs for faster math.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.general_pkg.all;
entity sha256 is
port(
clk : in std_logic;
chunk : in std_logic_vector(511 downto 0); --requires preprocessing for arbitrary datastreams
state : in std_logic_vector(255 downto 0);
hash : out std_logic_vector(255 downto 0) --65 cycle delay, likewise processing data streams beyond one chunk should be done with 65 streams in parallel (or 64 with a dead cycle to make the muxing cheaper)
);
end sha256;
architecture rtl of sha256 is
constant c_k : t_unsigned_vec(0 to 63)(31 downto 0) := (
x"428a2f98", x"71374491", x"b5c0fbcf", x"e9b5dba5", x"3956c25b", x"59f111f1", x"923f82a4", x"ab1c5ed5",
x"d807aa98", x"12835b01", x"243185be", x"550c7dc3", x"72be5d74", x"80deb1fe", x"9bdc06a7", x"c19bf174",
x"e49b69c1", x"efbe4786", x"0fc19dc6", x"240ca1cc", x"2de92c6f", x"4a7484aa", x"5cb0a9dc", x"76f988da",
x"983e5152", x"a831c66d", x"b00327c8", x"bf597fc7", x"c6e00bf3", x"d5a79147", x"06ca6351", x"14292967",
x"27b70a85", x"2e1b2138", x"4d2c6dfc", x"53380d13", x"650a7354", x"766a0abb", x"81c2c92e", x"92722c85",
x"a2bfe8a1", x"a81a664b", x"c24b8b70", x"c76c51a3", x"d192e819", x"d6990624", x"f40e3585", x"106aa070",
x"19a4c116", x"1e376c08", x"2748774c", x"34b0bcb5", x"391c0cb3", x"4ed8aa4a", x"5b9cca4f", x"682e6ff3",
x"748f82ee", x"78a5636f", x"84c87814", x"8cc70208", x"90befffa", x"a4506ceb", x"bef9a3f7", x"c67178f2");
signal e_set : t_unsigned_vec(0 to 64)(511 downto 0); --expansion set, only 16 words are maintained at a time, the last 16 indices should be progressively optimized away (#63 only uses word 0 and #64 is completely unused)
signal d_set : t_unsigned_vec(0 to 64)(255 downto 0); --digest set, used to pipeline compression
signal state_d : t_unsigned_vec(1 to 64)(255 downto 0); --delay line
begin
--0 = h
--1 = g
--2 = f
--3 = e
--4 = d
--5 = c
--6 = b
--7 = a
process(clk, state, chunk)
variable v_sum0 : unsigned(31 downto 0);
variable v_sum1 : unsigned(31 downto 0);
variable v_Sigma1 : unsigned(31 downto 0);
variable v_ch : unsigned(31 downto 0);
variable v_temp1 : unsigned(31 downto 0);
variable v_Sigma0 : unsigned(31 downto 0);
variable v_maj : unsigned(31 downto 0);
variable v_temp2 : unsigned(31 downto 0);
begin
d_set(0) <= unsigned(state); --to avoid riviera's bug thinking this process assigns d_set(0)
e_set(0) <= unsigned(chunk);
if rising_edge(clk) then
for i in 0 to 63 loop
e_set(i+1)(479 downto 0) <= e_set(i)(511 downto 32); --shift the bottom 32 bits out
v_sum0 := rotate_right(e_set(i)(63 downto 32), 7) xor --32 bits
rotate_right(e_set(i)(63 downto 32),18) xor
shift_right(e_set(i)(63 downto 32), 3);
v_sum1 := rotate_right(e_set(i)(32*14+31 downto 32*14),17) xor
rotate_right(e_set(i)(32*14+31 downto 32*14),19) xor
shift_right(e_set(i)(32*14+31 downto 32*14),10);
e_set(i+1)(511 downto 480) <= v_sum1 + v_sum0 + e_set(i)(31 downto 0) + e_set(i)(32*9+31 downto 32*9); --word[i+16] = sum1 + sum0 + word[i] word[i+9], although we always put it in slot 15 due to the downshift
v_Sigma1 := rotate_right(d_set(i)(32*3+31 downto 32*3),6) xor rotate_right(d_set(i)(32*3+31 downto 32*3),11) xor rotate_right(d_set(i)(32*3+31 downto 32*3),25);
v_ch := (d_set(i)(32*3+31 downto 32*3) and d_set(i)(32*2+31 downto 32*2)) xor (not(d_set(i)(32*3+31 downto 32*3)) and d_set(i)(32*1+31 downto 32*1));
v_temp1 := d_set(i)(32*0+31 downto 32*0) + v_Sigma1 + v_ch + c_k(i) + e_set(i)(31 downto 0);
v_Sigma0 := rotate_right(d_set(i)(32*7+31 downto 32*7),2) xor rotate_right(d_set(i)(32*7+31 downto 32*7),13) xor rotate_right(d_set(i)(32*7+31 downto 32*7),22);
v_maj := (d_set(i)(32*7+31 downto 32*7) and d_set(i)(32*6+31 downto 32*6)) xor (d_set(i)(32*7+31 downto 32*7) and d_set(i)(32*5+31 downto 32*5)) xor (d_set(i)(32*6+31 downto 32*6) and d_set(i)(32*5+31 downto 32*5));
v_temp2 := v_Sigma0 + v_maj;
d_set(i+1)(32*2+31 downto 32*0) <= d_set(i)(32*3+31 downto 32*1); --h := g, g := f, f := e
d_set(i+1)(32*3+31 downto 32*3) <= d_set(i)(32*4+31 downto 32*4) + v_temp1; --e := d+temp1
d_set(i+1)(32*6+31 downto 32*4) <= d_set(i)(32*7+31 downto 32*5); --d := c, c := b, b := a
d_set(i+1)(32*7+31 downto 32*7) <= v_temp1 + v_temp2; --a := temp1+temp2
end loop;
state_d(1) <= unsigned(state);
state_d(2 to 64) <= state_d(1 to 63);
for i in 0 to 7 loop
hash(32*i+31 downto 32*i) <= std_logic_vector(d_set(64)(32*i+31 downto 32*i) + state_d(64)(32*i+31 downto 32*i));
end loop;
end if;
end process;
end architecture rtl; | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/dp_sqr.vhd | 10 | 8540 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** DP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 DP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 57 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY dp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END dp_sqr;
ARCHITECTURE rtl OF dp_sqr IS
constant manwidth : positive := 52;
constant expwidth : positive := 11;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 54
-- top latency = core + 1 (input) + 2 (output) = 57
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_rsft32x5.vhd | 10 | 4329 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT32X5.VHD ***
--*** ***
--*** Function: Single Precision Right Shift ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft32x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END fp_rsft32x5;
ARCHITECTURE rtl OF fp_rsft32x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 29 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(30) <= (inbus(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(31) AND NOT(shift(2)) AND shift(1)) OR
(inbus(32) AND shift(2) AND NOT(shift(1)));
rightone(31) <= (inbus(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(32) AND NOT(shift(2)) AND shift(1));
rightone(32) <= inbus(32) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 20 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 21 TO 24 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 25 TO 28 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 29 TO 32 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 16 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 17 TO 32 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/hcc_castdtox.vhd | 10 | 4863 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_normus64.vhd | 10 | 4503 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/dp_lnrnd.vhd | 10 | 5431 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/dp_lnrnd.vhd | 10 | 5431 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
| mit |
ReneHerthel/MP3Player | FPGA/TESTBENCH.vhd | 1 | 6117 | -------------------------------------------------------------------------------
-- file: TESTBENCH.vhd
-- author: Hauke Sondermann <[email protected]>
-- author: Rene Herthel <[email protected]>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TESTBENCH is
generic (
HCLK : time := 6 ns; -- Clockzyklus des Microcontrollers
HOLD : positive := 1; -- Haltezyklus beim Schreibzugriff
PAUSE : positive := 2; -- Pausenzyklen mit deaktivierten Steuersignalen
ADDSET_W : positive := 1;
DATAST_W : positive := 2;
ADDSET_R : positive := 1;
DATAST_R : positive := 2
);
end TESTBENCH;
architecture BEHAVIORAL_TESTBENCH of TESTBENCH is
component TOP_EQ is
port(
CLK : in std_logic;
ANODES : out std_logic_vector(3 downto 0);
CATHODES : out std_logic_vector(7 downto 0);
NWE : in std_logic;
NE : in std_logic;
NOE : in std_logic;
DATA : inout std_logic_vector(15 downto 0);
RDY : out std_logic;
------------------- OSCILLOPCOPE --------------------
NWE_OUT : out std_logic;
NE_OUT : out std_logic;
NOE_OUT : out std_logic;
RDY_OUT : out std_logic
---------------------- TIMSIM -----------------------
;LOCKED_O : out std_logic
------------------------ SIM ------------------------
;CLK_SYN : in std_logic;
CLK_PE : in std_logic;
CLK_ORIG : in std_logic;
LOCKED : in std_logic
);
end component;
for all : TOP_EQ use entity work.TOP_EQ(TOP_EQ_ARCH);
--for all : TOP_EQ use entity work.TOP_EQ(Structure);
-------------------------------------------------------------------------------
-- signal initialization
-------------------------------------------------------------------------------
signal NWE : std_logic := '1';
signal NE : std_logic := '1';
signal NOE : std_logic := '1';
signal RESET_N : std_logic := '0';
signal DATA : std_logic_vector(15 downto 0) := (others => 'Z');
signal RDY : std_logic;
signal COUNTER : std_logic_vector(15 downto 0) := "1000000000000000";
signal CLK_FPGA : std_logic := '0';
signal FPGA_IN : std_logic_vector(15 downto 0);
signal FPGA_OUT : std_logic_vector(15 downto 0);
signal FPGA_IN_EN : std_logic := '0';
signal FPGA_OUT_EN : std_logic := '0';
signal CLK : std_logic := '0';
signal EN_N : std_logic := '0';
signal ANODES : std_logic_vector(3 downto 0) := (others => '0');
signal CATHODES : std_logic_vector(7 downto 0) := (others => '0');
------------------- OSCILLOPCOPE --------------------
signal NWE_OUT : std_logic;
signal NE_OUT : std_logic;
signal NOE_OUT : std_logic;
signal RDY_OUT : std_logic;
-----------------------------------------------------
------------------------ SIM ------------------------
signal CLK_PE : std_logic := '0';
signal CLK_SYN : std_logic := '0';
signal CLK_ORIG : std_logic := '0';
signal LOCKED : std_logic := '0';
-----------------------------------------------------
---------------------- TIMSIM -----------------------
signal LOCKED_O : std_logic;
-----------------------------------------------------
begin
-------------------------------------------------------------------------------
-- signals stimuli
-------------------------------------------------------------------------------
READ_WRITE_P: process
begin
wait until LOCKED_O'event and LOCKED_O = '1';
WHILE (LOCKED_O = '1') LOOP
--WRITE
NE <= '0';
wait for (HCLK * ADDSET_W);
NWE <= '0';
DATA <= COUNTER;
wait for (HCLK * DATAST_W);
FPGA_IN_EN <= '1';
NWE <= '1';
wait for (HCLK * HOLD);
FPGA_IN_EN <= '0';
--PAUSE
DATA <= (others => 'Z');
NE <= '1';
wait for (HCLK * PAUSE);
--WAIT
wait until RDY = '1';
--READ
NE <= '0';
wait for (HCLK * ADDSET_R);
NOE <= '0';
wait for (HCLK * DATAST_R);
--PAUSE
FPGA_OUT_EN <= '1';
NOE <= '1';
NE <= '1';
wait for (HCLK * PAUSE/2);
FPGA_OUT_EN <= '0';
wait for (HCLK * PAUSE/2);
COUNTER <= COUNTER + 1;
END LOOP;
end process;
CLK_P: process
begin
CLK <= '0';
wait for 20 ns;
CLK <= '1';
wait for 20 ns;
end process;
RESET_N_P: process
begin
wait for 20 ns;
RESET_N <= '1';
end process;
CLK_FPGA_P: process
begin
CLK_FPGA <= '0';
wait for 3 ns;
CLK_FPGA <= '1';
wait for 3 ns;
end process;
FPGA_IN_P: process(CLK_FPGA, RESET_N)
begin
if (RESET_N = '0') then
FPGA_IN <= (others => '0');
elsif (CLK_FPGA = '1' and CLK_FPGA'event) then
if (FPGA_IN_EN = '1') then
FPGA_IN <= DATA;
end if;
end if;
end process;
FPGA_OUT_P: process(CLK_FPGA, RESET_N)
begin
if (RESET_N = '0') then
FPGA_OUT <= (others => '0');
elsif (CLK_FPGA = '1' and CLK_FPGA'event) then
if (FPGA_OUT_EN = '1') then
FPGA_OUT <= DATA;
end if;
end if;
end process;
------------------------ SIM ------------------------
CLK_SYN_P: process
begin
CLK_SYN <= '0';
wait for 1500 ps;
CLK_SYN <= '1';
wait for 1500 ps;
end process;
CLK_PE_P: process
begin
CLK_PE <= '0';
wait for 3 ns;
CLK_PE <= '1';
wait for 3 ns;
end process;
CLK_ORIG_P: process
begin
CLK_ORIG <= '0';
wait for 20 ns;
CLK_ORIG <= '1';
wait for 20 ns;
end process;
LOCKED_P: process
begin
wait for 100 ns;
LOCKED <= '1';
end process;
-----------------------------------------------------
DUT : TOP_EQ
port map (
CLK => CLK,
ANODES => ANODES,
CATHODES => CATHODES,
NWE => NWE,
NE => NE,
NOE => NOE,
DATA => DATA,
RDY => RDY,
------------------- OSCILLOPCOPE --------------------
NWE_OUT => NWE_OUT,
NE_OUT => NE_OUT,
NOE_OUT => NOE_OUT,
RDY_OUT => RDY_OUT
---------------------- TIMSIM -----------------------
,LOCKED_O => LOCKED_O
------------------------ SIM ------------------------
,CLK_SYN => CLK_SYN,
CLK_PE => CLK_PE,
CLK_ORIG => CLK_ORIG,
LOCKED => LOCKED
);
end BEHAVIORAL_TESTBENCH;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_addpipes.vhd | 10 | 2515 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ADDPIPES.VHD ***
--*** ***
--*** Function: Synthesizable Pipelined Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_addpipes IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_addpipes;
ARCHITECTURE syn of hcc_addpipes IS
component lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
cin : IN STD_LOGIC ;
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0)
);
end component;
BEGIN
addtwo: lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
lpm_pipeline => pipes,
lpm_type => "LPM_ADD_SUB",
lpm_width => width
)
PORT MAP (
dataa => aa,
datab => bb,
cin => carryin,
clken => enable,
aclr => reset,
clock => sysclk,
result => cc
);
END syn;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_sincos_fused.vhd | 10 | 17997 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_SIN.VHD ***
--*** ***
--*** Function: Single Precision SIN Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take cos(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 7 ***
--*** (1 more than cos) ***
--***************************************************
ENTITY fp_sincos_fused IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout_sin : OUT STD_LOGIC;
exponentout_sin : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout_sin : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
signout_cos : OUT STD_LOGIC;
exponentout_cos : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout_cos : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_sincos_fused;
ARCHITECTURE rtl of fp_sincos_fused IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal input_number : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal input_number_delay : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (9 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign_sin, quadrantsign_cos, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff_sin,signcalcff_cos : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4+cordic_depth DOWNTO 1);
signal fixed_sin : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sinnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sinff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_cos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_cosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_cosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode_sin : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff_sin : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode_sin : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff_sin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode_sin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff_sin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode_sin : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal mantissaoutff_sin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff_sin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff_sin : STD_LOGIC;
signal countnode_cos : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff_cos : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode_cos : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff_cos : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode_cos : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff_cos : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode_cos : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal mantissaoutff_cos : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff_cos : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff_cos : STD_LOGIC;
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1_fused
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** SIN(X) = X when exponent < 115 ***
input_number <= signin & exponentin & mantissain;
-- level 1 in, level range_depth+cordic_depth+7 out
cdin: fp_del
GENERIC MAP (width=>32,pipes=>range_depth+cordic_depth+6)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>input_number,
cc=>input_number_delay);
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign_sin <= circle(36); -- sin negative in quadrants 3&4
quadrantsign_cos <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- sin (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take cos rather than sin
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff_sin(k) <= '0';
signcalcff_cos(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO range_depth+cordic_depth+5 LOOP
selectoutputff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4+cordic_depth LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff_sin(1) <= quadrantsign_sin XOR signinff(range_depth);
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff_sin(k) <= signcalcff_sin(k-1);
END LOOP;
signcalcff_cos(1) <= quadrantsign_cos;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff_cos(k) <= signcalcff_cos(k-1);
END LOOP;
exponentinff <= exponentin; -- level 1
selectoutputff(1) <= exponentcheck(9); -- level 2 to range_depth+cordic_depth+6
FOR k IN 2 TO range_depth+cordic_depth+5 LOOP
selectoutputff(k) <= selectoutputff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + NOT(quadrant(34)); -- level range_depth+1
-- level range depth+1 to range_depth+4
-- Here is an interesting thing - depending on the quadrant the input is in, computation
-- or a sin or cosine can use sin or cosine result. What this means is that we may have to swap
-- results when they come out of the cordic block.
select_sincosff(1) <= quadrant(34);
FOR k IN 2 TO 4+cordic_depth LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- if exponent < 115, sin = input
exponentcheck <= ('0' & exponentinff) - ('0' & x"73");
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1_fused
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sin_out=>fixed_sin,
cos_out=>fixed_cos);
gfxa: IF (width < 36) GENERATE
fixed_sinnode <= (fixed_sin & zerovec(36-width DOWNTO 1)) when (select_sincosff(4+cordic_depth) = '1') else (fixed_cos & zerovec(36-width DOWNTO 1));
fixed_cosnode <= (fixed_cos & zerovec(36-width DOWNTO 1)) when (select_sincosff(4+cordic_depth) = '1') else (fixed_sin & zerovec(36-width DOWNTO 1));
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sinnode <= fixed_sin when (select_sincosff(4+cordic_depth) = '1') else fixed_cos;
fixed_cosnode <= fixed_cos when (select_sincosff(4+cordic_depth) = '1') else fixed_sin;
END GENERATE;
clz1: fp_clz36
PORT MAP (mantissa=>fixed_sinnode,leading=>countnode_sin);
clz2: fp_clz36
PORT MAP (mantissa=>fixed_cosnode,leading=>countnode_cos);
sft1: fp_lsft36
PORT MAP (inbus=>fixed_sinff,shift=>countff_sin,
outbus=>mantissanormnode_sin);
sft2: fp_lsft36
PORT MAP (inbus=>fixed_cosff,shift=>countff_cos,
outbus=>mantissanormnode_cos);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode_sin <= "10000000" - ("00" & countff_sin);
exponentnormnode_cos <= "10000000" - ("00" & countff_cos);
overflownode_sin(1) <= mantissanormnode_sin(12);
gova1: FOR k IN 2 TO 24 GENERATE
overflownode_sin(k) <= mantissanormnode_sin(k+11) AND overflownode_sin(k-1);
END GENERATE;
overflownode_cos(1) <= mantissanormnode_cos(12);
gova2: FOR k IN 2 TO 24 GENERATE
overflownode_cos(k) <= mantissanormnode_cos(k+11) AND overflownode_cos(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sinff(k) <= '0';
fixed_cosff(k) <= '0';
END LOOP;
countff_sin <= "000000";
countff_cos <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff_sin(k) <= '0';
mantissaoutff_sin(k) <= '0';
mantissanormff_cos(k) <= '0';
mantissaoutff_cos(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff_sin(k) <= '0';
exponentoutff_sin(k) <= '0';
exponentnormff_cos(k) <= '0';
exponentoutff_cos(k) <= '0';
END LOOP;
signoutff_sin <= '0';
signoutff_cos <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sinff <= fixed_sinnode; -- level range_depth+cordic_depth+5
fixed_cosff <= fixed_cosnode; -- level range_depth+cordic_depth+5
countff_sin <= countnode_sin; -- level range_depth+4+cordic_depth+5
countff_cos <= countnode_cos; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff_cos <= mantissanormnode_cos(35 DOWNTO 13) + mantissanormnode_cos(12);
exponentnormff_cos <= exponentnormnode_cos(8 DOWNTO 1) + overflownode_cos(24);
mantissanormff_sin <= mantissanormnode_sin(35 DOWNTO 13) + mantissanormnode_sin(12);
exponentnormff_sin <= exponentnormnode_sin(8 DOWNTO 1) + overflownode_sin(24);
-- level range_depth+cordic_depth+7
FOR k IN 1 TO 23 LOOP
mantissaoutff_sin(k) <= (mantissanormff_sin(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(k) AND selectoutputff(range_depth+cordic_depth+5));
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff_sin(k) <= (exponentnormff_sin(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(k+23) AND selectoutputff(range_depth+cordic_depth+5));
END LOOP;
signoutff_sin <= (signcalcff_sin(cordic_depth+6) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(32) AND selectoutputff(range_depth+cordic_depth+5));
mantissaoutff_cos <= mantissanormff_cos;
exponentoutff_cos <= exponentnormff_cos;
signoutff_cos <= signcalcff_cos(cordic_depth+6);
END IF;
END IF;
END PROCESS;
mantissaout_sin <= mantissaoutff_sin;
exponentout_sin <= exponentoutff_sin;
signout_sin <= signoutff_sin;
mantissaout_cos <= mantissaoutff_cos;
exponentout_cos <= exponentoutff_cos;
signout_cos <= signoutff_cos;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/dp_subb.vhd | 10 | 3154 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_SUBB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Subtract ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_subb;
ARCHITECTURE rtl OF dp_subb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal bbinv : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
gia: FOR k IN 1 TO width GENERATE
bbinv(k) <= NOT(bb(k));
END GENERATE;
-- lpm_add_sub subs 1's complement of bb
ccnode <= aa + bbinv + (zerovec & borrowin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_atanlut.vhd | 10 | 165265 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_ATANLUT.VHD ***
--*** ***
--*** Function: ArcTangent Look Up Table ***
--*** (Generated by MATLAB Utility) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_atanlut IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_atanlut;
ARCHITECTURE rtl OF fp_atanlut IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
WHEN "0000000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(255,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(262058,18);
WHEN "0000000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(511,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(261461,18);
WHEN "0000000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(767,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(259840,18);
WHEN "0000000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(1023,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(256682,18);
WHEN "0000000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(1279,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251477,18);
WHEN "0000000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(1535,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(243713,18);
WHEN "0000000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(1791,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232877,18);
WHEN "0000001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(2047,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218459,18);
WHEN "0000001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(2303,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199947,18);
WHEN "0000001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(2559,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176830,18);
WHEN "0000001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(2815,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148596,18);
WHEN "0000001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(3071,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(114736,18);
WHEN "0000001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(3327,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74739,18);
WHEN "0000001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(3583,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(28094,18);
WHEN "0000001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(3838,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(236436,18);
WHEN "0000010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(4094,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174967,18);
WHEN "0000010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(4350,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105322,18);
WHEN "0000010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(4606,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(26992,18);
WHEN "0000010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(4861,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201613,18);
WHEN "0000010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(5117,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104389,18);
WHEN "0000010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(5372,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(259100,18);
WHEN "0000010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(5628,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140951,18);
WHEN "0000010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(5884,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11580,18);
WHEN "0000011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(6139,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(132624,18);
WHEN "0000011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(6394,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241434,18);
WHEN "0000011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(6650,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(75361,18);
WHEN "0000011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(6905,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158188,18);
WHEN "0000011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(7160,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(227268,18);
WHEN "0000011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(7416,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19954,18);
WHEN "0000011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(7671,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(60030,18);
WHEN "0000011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(7926,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84851,18);
WHEN "0000100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(8181,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(93916,18);
WHEN "0000100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(8436,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(86725,18);
WHEN "0000100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(8691,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62776,18);
WHEN "0000100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(8946,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21573,18);
WHEN "0000100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(9200,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224760,18);
WHEN "0000100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(9455,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(147552,18);
WHEN "0000100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(9710,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51596,18);
WHEN "0000100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(9964,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(198541,18);
WHEN "0000101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(10219,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(63603,18);
WHEN "0000101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(10473,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170578,18);
WHEN "0000101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(10727,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(256827,18);
WHEN "0000101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(10982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59715,18);
WHEN "0000101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(11236,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(103038,18);
WHEN "0000101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(11490,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(124162,18);
WHEN "0000101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(11744,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122599,18);
WHEN "0000101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(11998,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97859,18);
WHEN "0000110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(12252,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49456,18);
WHEN "0000110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(12505,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239047,18);
WHEN "0000110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(12759,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(141859,18);
WHEN "0000110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(13013,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19553,18);
WHEN "0000110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(13266,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133790,18);
WHEN "0000110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(13519,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(221944,18);
WHEN "0000110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(13773,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21390,18);
WHEN "0000110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(14026,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(55937,18);
WHEN "0000111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(14279,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62963,18);
WHEN "0000111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(14532,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41991,18);
WHEN "0000111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(14784,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(254689,18);
WHEN "0000111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(15037,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176296,18);
WHEN "0000111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(15290,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68480,18);
WHEN "0000111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(15542,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192916,18);
WHEN "0000111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(15795,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24844,18);
WHEN "0000111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(16047,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88083,18);
WHEN "0001000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(16299,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(120021,18);
WHEN "0001000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(16551,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(120191,18);
WHEN "0001000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(16803,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88130,18);
WHEN "0001000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(17055,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23371,18);
WHEN "0001000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(17306,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(187599,18);
WHEN "0001000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(17558,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(56063,18);
WHEN "0001000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(17809,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152592,18);
WHEN "0001000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(18060,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214584,18);
WHEN "0001001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(18311,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241584,18);
WHEN "0001001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(18562,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233135,18);
WHEN "0001001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(18813,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(188785,18);
WHEN "0001001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(19064,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108082,18);
WHEN "0001001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(19314,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(252719,18);
WHEN "0001001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(19565,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97960,18);
WHEN "0001001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(19815,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167646,18);
WHEN "0001001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(20065,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199187,18);
WHEN "0001010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(20315,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192140,18);
WHEN "0001010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(20565,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(146062,18);
WHEN "0001010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(20815,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(60512,18);
WHEN "0001010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(21064,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197196,18);
WHEN "0001010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(21314,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(31389,18);
WHEN "0001010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(21563,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(86943,18);
WHEN "0001010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(21812,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(101281,18);
WHEN "0001010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(22061,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(73969,18);
WHEN "0001011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(22310,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(4579,18);
WHEN "0001011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(22558,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154826,18);
WHEN "0001011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(22806,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(262139,18);
WHEN "0001011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(23055,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(63948,18);
WHEN "0001011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(23303,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84120,18);
WHEN "0001011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(23551,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(60088,18);
WHEN "0001011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(23798,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(253578,18);
WHEN "0001011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(24046,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(139883,18);
WHEN "0001100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(24293,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(242876,18);
WHEN "0001100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(24541,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(37856,18);
WHEN "0001100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(24788,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48697,18);
WHEN "0001100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(25035,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(12847,18);
WHEN "0001100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(25281,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192040,18);
WHEN "0001100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(25528,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61583,18);
WHEN "0001100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(25774,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(145360,18);
WHEN "0001100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(26020,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(180824,18);
WHEN "0001101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(26266,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167574,18);
WHEN "0001101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(26512,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105213,18);
WHEN "0001101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(26757,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(255489,18);
WHEN "0001101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27003,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(93717,18);
WHEN "0001101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27248,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143796,18);
WHEN "0001101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27493,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143189,18);
WHEN "0001101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27738,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(91508,18);
WHEN "0001101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250512,18);
WHEN "0001110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(28227,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95529,18);
WHEN "0001110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(28471,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150463,18);
WHEN "0001110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(28715,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152791,18);
WHEN "0001110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(28959,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(102135,18);
WHEN "0001110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(29202,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(260263,18);
WHEN "0001110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(29446,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(102513,18);
WHEN "0001110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(29689,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152801,18);
WHEN "0001110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(29932,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148615,18);
WHEN "0001111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(30175,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89586,18);
WHEN "0001111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(30417,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(237492,18);
WHEN "0001111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(30660,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67684,18);
WHEN "0001111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(30902,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104088,18);
WHEN "0001111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(31144,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84201,18);
WHEN "0001111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(31386,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7666,18);
WHEN "0001111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(31627,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(136273,18);
WHEN "0001111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(31868,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(207526,18);
WHEN "0010000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(32109,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(221074,18);
WHEN "0010000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(32350,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176570,18);
WHEN "0010000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(32591,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(73668,18);
WHEN "0010000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(32831,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174167,18);
WHEN "0010000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(33071,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215584,18);
WHEN "0010000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(33311,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197579,18);
WHEN "0010000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(33551,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(119815,18);
WHEN "0010000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(33790,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244102,18);
WHEN "0010001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34030,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45819,18);
WHEN "0010001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34269,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48923,18);
WHEN "0010001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34507,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(253089,18);
WHEN "0010001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34746,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133701,18);
WHEN "0010001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34984,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214724,18);
WHEN "0010001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(35222,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233694,18);
WHEN "0010001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(35460,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(190291,18);
WHEN "0010001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(35698,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84200,18);
WHEN "0010010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(35935,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(177249,18);
WHEN "0010010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(36172,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206983,18);
WHEN "0010010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(36409,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173093,18);
WHEN "0010010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(36646,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(75271,18);
WHEN "0010010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(36882,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(175356,18);
WHEN "0010010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(37118,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(210901,18);
WHEN "0010010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(37354,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(181607,18);
WHEN "0010010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(37590,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(87173,18);
WHEN "0010011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(37825,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(189450,18);
WHEN "0010011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38060,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(226000,18);
WHEN "0010011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38295,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196531,18);
WHEN "0010011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38530,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(100754,18);
WHEN "0010011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38764,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200528,18);
WHEN "0010011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38998,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233423,18);
WHEN "0010011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(39232,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199158,18);
WHEN "0010011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(39466,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97454,18);
WHEN "0010100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(39699,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(190176,18);
WHEN "0010100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(39932,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214908,18);
WHEN "0010100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(40165,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171374,18);
WHEN "0010100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(40398,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59307,18);
WHEN "0010100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(40630,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140580,18);
WHEN "0010100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(40862,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152786,18);
WHEN "0010100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(41094,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95661,18);
WHEN "0010100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(41325,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(231088,18);
WHEN "0010101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(41557,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34520,18);
WHEN "0010101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(41788,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29989,18);
WHEN "0010101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42018,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217242,18);
WHEN "0010101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42249,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(71738,18);
WHEN "0010101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42479,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(117517,18);
WHEN "0010101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42709,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92187,18);
WHEN "0010101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42938,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257648,18);
WHEN "0010101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(43168,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89371,18);
WHEN "0010110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(43397,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111402,18);
WHEN "0010110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(43626,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61360,18);
WHEN "0010110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(43854,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201155,18);
WHEN "0010110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44083,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(6265,18);
WHEN "0010110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44311,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(747,18);
WHEN "0010110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44538,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184374,18);
WHEN "0010110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44766,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(32631,18);
WHEN "0010110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44993,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(69583,18);
WHEN "0010111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(45220,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(32865,18);
WHEN "0010111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(45446,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184401,18);
WHEN "0010111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(45672,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(261830,18);
WHEN "0010111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(45899,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2795,18);
WHEN "0010111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(46124,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(193515,18);
WHEN "0010111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(46350,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47349,18);
WHEN "0010111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(46575,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88377,18);
WHEN "0010111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(46800,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54250,18);
WHEN "0011000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47024,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206908,18);
WHEN "0011000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47249,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21864,18);
WHEN "0011000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47473,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23207,18);
WHEN "0011000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47696,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(210741,18);
WHEN "0011000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47920,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59984,18);
WHEN "0011000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(48143,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95032,18);
WHEN "0011000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(48366,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(53554,18);
WHEN "0011000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(48588,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197504,18);
WHEN "0011001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(48811,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2412,18);
WHEN "0011001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49032,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(254526,18);
WHEN "0011001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49254,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167234,18);
WHEN "0011001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49476,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2502,18);
WHEN "0011001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49697,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(22299,18);
WHEN "0011001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49917,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(226451,18);
WHEN "0011001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(50138,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(90499,18);
WHEN "0011001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(50358,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(138562,18);
WHEN "0011010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(50578,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108329,18);
WHEN "0011010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(50797,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(261779,18);
WHEN "0011010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51017,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74462,18);
WHEN "0011010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51236,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70506,18);
WHEN "0011010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51454,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249754,18);
WHEN "0011010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51673,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(87760,18);
WHEN "0011010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51891,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108660,18);
WHEN "0011010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52109,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(50158,18);
WHEN "0011011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52326,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174249,18);
WHEN "0011011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52543,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218642,18);
WHEN "0011011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52760,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(183192,18);
WHEN "0011011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52977,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67756,18);
WHEN "0011011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(53193,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(134338,18);
WHEN "0011011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(53409,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(120655,18);
WHEN "0011011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(53625,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(26571,18);
WHEN "0011011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(53840,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(114096,18);
WHEN "0011100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54055,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(120953,18);
WHEN "0011100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54270,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47013,18);
WHEN "0011100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54484,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154291,18);
WHEN "0011100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54698,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(180519,18);
WHEN "0011100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54912,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(125572,18);
WHEN "0011100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55125,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251472,18);
WHEN "0011100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55339,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33813,18);
WHEN "0011100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55551,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258909,18);
WHEN "0011101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55764,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140212,18);
WHEN "0011101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55976,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201898,18);
WHEN "0011101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(56188,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(181710,18);
WHEN "0011101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(56400,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(79540,18);
WHEN "0011101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(56611,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157424,18);
WHEN "0011101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(56822,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153114,18);
WHEN "0011101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57033,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(66506,18);
WHEN "0011101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57243,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(159643,18);
WHEN "0011110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57453,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170281,18);
WHEN "0011110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57663,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98325,18);
WHEN "0011110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57872,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205822,18);
WHEN "0011110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58081,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230535,18);
WHEN "0011110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58290,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172373,18);
WHEN "0011110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58499,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(31247,18);
WHEN "0011110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58707,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(69214,18);
WHEN "0011110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58915,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24044,18);
WHEN "0011111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59122,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157797,18);
WHEN "0011111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59329,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(208248,18);
WHEN "0011111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59536,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(175318,18);
WHEN "0011111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59743,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58929,18);
WHEN "0011111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59949,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(121149,18);
WHEN "0011111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60155,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(99760,18);
WHEN "0011111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60360,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(256834,18);
WHEN "0011111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60566,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68012,18);
WHEN "0100000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60771,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(57516,18);
WHEN "0100000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60975,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(225277,18);
WHEN "0100000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61180,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46944,18);
WHEN "0100000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61384,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46741,18);
WHEN "0100000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61587,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224608,18);
WHEN "0100000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61791,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(56198,18);
WHEN "0100000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61994,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(65741,18);
WHEN "0100000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(62196,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(253182,18);
WHEN "0100001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(62399,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(94178,18);
WHEN "0100001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(62601,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(112967,18);
WHEN "0100001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(62803,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47353,18);
WHEN "0100001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63004,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(159433,18);
WHEN "0100001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63205,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(187015,18);
WHEN "0100001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63406,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(130055,18);
WHEN "0100001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63606,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250654,18);
WHEN "0100001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63807,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24481,18);
WHEN "0100010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64006,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(237930,18);
WHEN "0100010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64206,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104530,18);
WHEN "0100010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64405,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148532,18);
WHEN "0100010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64604,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(107758,18);
WHEN "0100010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64802,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244320,18);
WHEN "0100010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65001,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33897,18);
WHEN "0100010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65199,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(747,18);
WHEN "0100010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65396,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144844,18);
WHEN "0100011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65593,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(204016,18);
WHEN "0100011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65790,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178238,18);
WHEN "0100011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65987,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67488,18);
WHEN "0100011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66183,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133888,18);
WHEN "0100011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66379,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(115273,18);
WHEN "0100011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66575,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11625,18);
WHEN "0100011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66770,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(85072,18);
WHEN "0100011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66965,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(73455,18);
WHEN "0100100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67159,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(238902,18);
WHEN "0100100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67354,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(57115,18);
WHEN "0100100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67548,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(52371,18);
WHEN "0100100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67741,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224661,18);
WHEN "0100100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67935,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49688,18);
WHEN "0100100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68128,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51735,18);
WHEN "0100100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68320,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230798,18);
WHEN "0100100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68513,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62585,18);
WHEN "0100101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68705,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(71382,18);
WHEN "0100101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68896,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257190,18);
WHEN "0100101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69088,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95722,18);
WHEN "0100101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69279,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111268,18);
WHEN "0100101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69470,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41689,18);
WHEN "0100101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69660,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(149135,18);
WHEN "0100101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69850,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171468,18);
WHEN "0100101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70040,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108696,18);
WHEN "0100110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70229,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(222974,18);
WHEN "0100110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70418,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(252170,18);
WHEN "0100110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70607,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196294,18);
WHEN "0100110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70796,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(55362,18);
WHEN "0100110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70984,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(91533,18);
WHEN "0100110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71172,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(42680,18);
WHEN "0100110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71359,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170964,18);
WHEN "0100110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71546,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214261,18);
WHEN "0100111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71733,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172591,18);
WHEN "0100111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71920,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45977,18);
WHEN "0100111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72106,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(96586,18);
WHEN "0100111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72292,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62298,18);
WHEN "0100111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72477,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205284,18);
WHEN "0100111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72663,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1281,18);
WHEN "0100111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72847,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(236752,18);
WHEN "0100111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73032,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(125293,18);
WHEN "0101000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73216,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191223,18);
WHEN "0101000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73400,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172431,18);
WHEN "0101000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73584,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68949,18);
WHEN "0101000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73767,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(142957,18);
WHEN "0101000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73950,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(132346,18);
WHEN "0101000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74133,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(37152,18);
WHEN "0101000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74315,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(119559,18);
WHEN "0101000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74497,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(117461,18);
WHEN "0101001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74679,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30899,18);
WHEN "0101001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74860,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122058,18);
WHEN "0101001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75041,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(128837,18);
WHEN "0101001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75222,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51281,18);
WHEN "0101001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75402,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(151578,18);
WHEN "0101001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75582,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167630,18);
WHEN "0101001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75762,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(99484,18);
WHEN "0101001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75941,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(209334,18);
WHEN "0101010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76120,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235084,18);
WHEN "0101010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76299,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176784,18);
WHEN "0101010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76478,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34487,18);
WHEN "0101010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76656,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70389,18);
WHEN "0101010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76834,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(22400,18);
WHEN "0101010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77011,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152718,18);
WHEN "0101010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77188,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199256,18);
WHEN "0101010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77365,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(162070,18);
WHEN "0101011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77542,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41217,18);
WHEN "0101011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77718,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98901,18);
WHEN "0101011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77894,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(73038,18);
WHEN "0101011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78069,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(225832,18);
WHEN "0101011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78245,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33058,18);
WHEN "0101011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78420,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19065,18);
WHEN "0101011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78594,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(183917,18);
WHEN "0101011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78769,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3392,18);
WHEN "0101100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78943,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1843,18);
WHEN "0101100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79116,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179336,18);
WHEN "0101100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79290,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11651,18);
WHEN "0101100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79463,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23144,18);
WHEN "0101100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79635,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(213885,18);
WHEN "0101100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79808,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59656,18);
WHEN "0101100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79980,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84815,18);
WHEN "0101100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80152,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(27291,18);
WHEN "0101101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80323,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(149301,18);
WHEN "0101101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80494,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(188773,18);
WHEN "0101101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80665,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(145784,18);
WHEN "0101101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80836,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20408,18);
WHEN "0101101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81006,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74865,18);
WHEN "0101101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81176,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47089,18);
WHEN "0101101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81345,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199302,18);
WHEN "0101101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81515,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7293,18);
WHEN "0101110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81683,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257575,18);
WHEN "0101110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81852,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(163796,18);
WHEN "0101110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82020,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250325,18);
WHEN "0101110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82188,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(255100,18);
WHEN "0101110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82356,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178203,18);
WHEN "0101110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82524,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19719,18);
WHEN "0101110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82691,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41874,18);
WHEN "0101110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82857,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244755,18);
WHEN "0101111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83024,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104158,18);
WHEN "0101111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83190,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144458,18);
WHEN "0101111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83356,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(103598,18);
WHEN "0101111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83521,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(243810,18);
WHEN "0101111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83687,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(40895,18);
WHEN "0101111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83852,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19229,18);
WHEN "0101111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84016,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178903,18);
WHEN "0101111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84180,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257864,18);
WHEN "0110000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84344,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(256201,18);
WHEN "0110000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84508,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174008,18);
WHEN "0110000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84672,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11377,18);
WHEN "0110000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84835,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30546,18);
WHEN "0110000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84997,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(231607,18);
WHEN "0110000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85160,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(90368,18);
WHEN "0110000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85322,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(131213,18);
WHEN "0110000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85484,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92091,18);
WHEN "0110001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85645,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235245,18);
WHEN "0110001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85807,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(36483,18);
WHEN "0110001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85968,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20191,18);
WHEN "0110001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86128,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(186467,18);
WHEN "0110001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86289,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11121,18);
WHEN "0110001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86449,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(18541,18);
WHEN "0110001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86608,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(208828,18);
WHEN "0110001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86768,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(57793,18);
WHEN "0110010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86927,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89826,18);
WHEN "0110010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87086,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(42884,18);
WHEN "0110010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87244,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179213,18);
WHEN "0110010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87402,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(236772,18);
WHEN "0110010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87560,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215665,18);
WHEN "0110010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87718,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(115995,18);
WHEN "0110010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87875,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200010,18);
WHEN "0110010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88032,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205672,18);
WHEN "0110011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88189,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133084,18);
WHEN "0110011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88345,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244498,18);
WHEN "0110011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88502,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15731,18);
WHEN "0110011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88657,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233323,18);
WHEN "0110011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88813,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(110948,18);
WHEN "0110011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88968,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173002,18);
WHEN "0110011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89123,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157449,18);
WHEN "0110011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89278,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(64397,18);
WHEN "0110100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89432,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156101,18);
WHEN "0110100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89586,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170525,18);
WHEN "0110100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89740,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(107780,18);
WHEN "0110100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89893,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230119,18);
WHEN "0110100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90047,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(13365,18);
WHEN "0110100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90199,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244062,18);
WHEN "0110100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90352,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(135889,18);
WHEN "0110100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90504,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(213247,18);
WHEN "0110101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90656,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214103,18);
WHEN "0110101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90808,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(138570,18);
WHEN "0110101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90959,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(248907,18);
WHEN "0110101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91111,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20937,18);
WHEN "0110101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91261,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241208,18);
WHEN "0110101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91412,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123401,18);
WHEN "0110101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91562,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191920,18);
WHEN "0110101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91712,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184734,18);
WHEN "0110110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91862,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(101960,18);
WHEN "0110110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92011,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205858,18);
WHEN "0110110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92160,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(234399,18);
WHEN "0110110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92309,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(187700,18);
WHEN "0110110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92458,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(65877,18);
WHEN "0110110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92606,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(131192,18);
WHEN "0110110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92754,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(121618,18);
WHEN "0110110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92902,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(37273,18);
WHEN "0110111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93049,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140418,18);
WHEN "0110111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93196,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(169029,18);
WHEN "0110111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93343,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123223,18);
WHEN "0110111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93490,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3119,18);
WHEN "0110111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93636,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70981,18);
WHEN "0110111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93782,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(64784,18);
WHEN "0110111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93927,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(246792,18);
WHEN "0110111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94073,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92836,18);
WHEN "0111000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94218,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(127326,18);
WHEN "0111000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94363,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88237,18);
WHEN "0111000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94507,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(237834,18);
WHEN "0111000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94652,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51950,18);
WHEN "0111000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94796,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54995,18);
WHEN "0111000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94939,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(247090,18);
WHEN "0111000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95083,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104069,18);
WHEN "0111000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95226,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150342,18);
WHEN "0111001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95369,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123886,18);
WHEN "0111001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95512,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24825,18);
WHEN "0111001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95654,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(115424,18);
WHEN "0111001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95796,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133663,18);
WHEN "0111001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95938,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(79665,18);
WHEN "0111001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96079,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215697,18);
WHEN "0111001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96221,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(17594,18);
WHEN "0111001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96362,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9768,18);
WHEN "0111010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96502,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192343,18);
WHEN "0111010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96643,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41154,18);
WHEN "0111010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96783,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(80615,18);
WHEN "0111010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96923,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48704,18);
WHEN "0111010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97062,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(207691,18);
WHEN "0111010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97202,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33412,18);
WHEN "0111010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97341,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(50281,18);
WHEN "0111010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97479,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258422,18);
WHEN "0111011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97618,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133671,18);
WHEN "0111011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97756,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200444,18);
WHEN "0111011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97894,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196720,18);
WHEN "0111011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98032,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122625,18);
WHEN "0111011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98169,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(240430,18);
WHEN "0111011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98307,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(25971,18);
WHEN "0111011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98444,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3664,18);
WHEN "0111011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98580,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173633,18);
WHEN "0111100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98717,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11717,18);
WHEN "0111100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98853,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(42330,18);
WHEN "0111100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98989,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3456,18);
WHEN "0111100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99124,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157363,18);
WHEN "0111100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99259,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(242035,18);
WHEN "0111100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99394,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257599,18);
WHEN "0111100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99529,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(204180,18);
WHEN "0111100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99664,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(81908,18);
WHEN "0111101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99798,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153051,18);
WHEN "0111101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99932,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(155593,18);
WHEN "0111101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100066,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89662,18);
WHEN "0111101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100199,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217528,18);
WHEN "0111101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100333,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15031,18);
WHEN "0111101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100466,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(6586,18);
WHEN "0111101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100598,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192320,18);
WHEN "0111101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100731,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48074,18);
WHEN "0111110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100863,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98261,18);
WHEN "0111110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100995,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(80868,18);
WHEN "0111110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101126,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258163,18);
WHEN "0111110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101258,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105988,18);
WHEN "0111110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101389,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148759,18);
WHEN "0111110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101520,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(124458,18);
WHEN "0111110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101651,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33214,18);
WHEN "0111110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101781,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(137298,18);
WHEN "0111111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101911,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174695,18);
WHEN "0111111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102041,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(145532,18);
WHEN "0111111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102171,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49937,18);
WHEN "0111111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102300,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150182,18);
WHEN "0111111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102429,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184251,18);
WHEN "0111111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102558,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152273,18);
WHEN "0111111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102687,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54374,18);
WHEN "0111111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102815,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152827,18);
WHEN "1000000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102943,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(185617,18);
WHEN "1000000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103071,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152870,18);
WHEN "1000000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103199,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54715,18);
WHEN "1000000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103326,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153425,18);
WHEN "1000000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103453,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(186982,18);
WHEN "1000000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103580,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(155515,18);
WHEN "1000000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103707,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59152,18);
WHEN "1000000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103833,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(160165,18);
WHEN "1000001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103959,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196538,18);
WHEN "1000001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104085,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(168399,18);
WHEN "1000001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104211,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(75875,18);
WHEN "1000001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104336,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(181239,18);
WHEN "1000001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104461,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(222475,18);
WHEN "1000001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104586,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199709,18);
WHEN "1000001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104711,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(113070,18);
WHEN "1000001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104835,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224830,18);
WHEN "1000010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104960,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(10829,18);
WHEN "1000010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105083,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257625,18);
WHEN "1000010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105207,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178916,18);
WHEN "1000010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105331,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(36971,18);
WHEN "1000010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105454,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(94064,18);
WHEN "1000010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105577,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88176,18);
WHEN "1000010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105700,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19436,18);
WHEN "1000010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105822,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150116,18);
WHEN "1000011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105944,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218198,18);
WHEN "1000011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106066,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(223809,18);
WHEN "1000011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106188,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167077,18);
WHEN "1000011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106310,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48129,18);
WHEN "1000011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106431,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(129236,18);
WHEN "1000011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106552,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148382,18);
WHEN "1000011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106673,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105692,18);
WHEN "1000011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106794,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1293,18);
WHEN "1000100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106914,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97458,18);
WHEN "1000100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107034,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(132167,18);
WHEN "1000100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107154,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105548,18);
WHEN "1000100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107274,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(17728,18);
WHEN "1000100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107393,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(130976,18);
WHEN "1000100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107512,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(183276,18);
WHEN "1000100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107631,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174753,18);
WHEN "1000100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107750,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105533,18);
WHEN "1000101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107868,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(237887,18);
WHEN "1000101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107987,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47653,18);
WHEN "1000101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108105,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59244,18);
WHEN "1000101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108223,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(10643,18);
WHEN "1000101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108340,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(164119,18);
WHEN "1000101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108457,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257653,18);
WHEN "1000101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108575,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29228,18);
WHEN "1000101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108692,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3255,18);
WHEN "1000110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108808,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179862,18);
WHEN "1000110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108925,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34885,18);
WHEN "1000110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109041,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92737,18);
WHEN "1000110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109157,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(91399,18);
WHEN "1000110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109273,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30995,18);
WHEN "1000110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109388,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173795,18);
WHEN "1000110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109503,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257779,18);
WHEN "1000110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109619,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20928,18);
WHEN "1000111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109733,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249798,18);
WHEN "1000111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109848,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158081,18);
WHEN "1000111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109963,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(8045,18);
WHEN "1000111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110077,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61959,18);
WHEN "1000111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110191,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(57801,18);
WHEN "1000111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110304,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257841,18);
WHEN "1000111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110418,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(137913,18);
WHEN "1000111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110531,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(222429,18);
WHEN "1001000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110644,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249369,18);
WHEN "1001000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110757,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218855,18);
WHEN "1001000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110870,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(131010,18);
WHEN "1001000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(248102,18);
WHEN "1001000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111095,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45965,18);
WHEN "1001000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111207,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49010,18);
WHEN "1001000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111318,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257360,18);
WHEN "1001000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111430,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(146848,18);
WHEN "1001001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111541,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241886,18);
WHEN "1001001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111653,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(18306,18);
WHEN "1001001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111764,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(520,18);
WHEN "1001001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111874,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(188648,18);
WHEN "1001001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111985,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58525,18);
WHEN "1001001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112095,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(134560,18);
WHEN "1001001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112205,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154730,18);
WHEN "1001001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112315,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(119156,18);
WHEN "1001010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112425,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(27960,18);
WHEN "1001010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112534,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143406,18);
WHEN "1001010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112643,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(203471,18);
WHEN "1001010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112752,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(208276,18);
WHEN "1001010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112861,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157941,18);
WHEN "1001010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112970,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(52586,18);
WHEN "1001010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113078,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154475,18);
WHEN "1001010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113186,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201584,18);
WHEN "1001011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113294,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(194033,18);
WHEN "1001011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113402,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(131941,18);
WHEN "1001011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113510,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15429,18);
WHEN "1001011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113617,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(106759,18);
WHEN "1001011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113724,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143905,18);
WHEN "1001011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113831,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(126988,18);
WHEN "1001011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113938,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(56126,18);
WHEN "1001011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114044,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(193581,18);
WHEN "1001100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114151,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15184,18);
WHEN "1001100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114257,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45342,18);
WHEN "1001100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114363,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(22027,18);
WHEN "1001100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114468,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(207502,18);
WHEN "1001100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114574,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(77597,18);
WHEN "1001100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114679,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156717,18);
WHEN "1001100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114784,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(182836,18);
WHEN "1001100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114889,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156070,18);
WHEN "1001101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114994,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(76538,18);
WHEN "1001101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115098,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206498,18);
WHEN "1001101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115203,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21782,18);
WHEN "1001101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115307,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46791,18);
WHEN "1001101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115411,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19500,18);
WHEN "1001101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115514,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202167,18);
WHEN "1001101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115618,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70622,18);
WHEN "1001101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115721,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(149267,18);
WHEN "1001110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115824,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176075,18);
WHEN "1001110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115927,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(151160,18);
WHEN "1001110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116030,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74638,18);
WHEN "1001110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116132,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(208767,18);
WHEN "1001110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116235,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29375,18);
WHEN "1001110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116337,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(60864,18);
WHEN "1001110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116439,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41205,18);
WHEN "1001110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116540,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232655,18);
WHEN "1001111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116642,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111041,18);
WHEN "1001111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116743,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200765,18);
WHEN "1001111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116844,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239796,18);
WHEN "1001111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116945,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(228248,18);
WHEN "1001111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117046,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(166234,18);
WHEN "1001111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117147,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(53867,18);
WHEN "1001111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117247,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153404,18);
WHEN "1001111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117347,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202814,18);
WHEN "1010000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117447,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202209,18);
WHEN "1010000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117547,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(151701,18);
WHEN "1010000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117647,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51403,18);
WHEN "1010000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117746,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(163571,18);
WHEN "1010000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117845,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(226171,18);
WHEN "1010000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117944,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239317,18);
WHEN "1010000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118043,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(203118,18);
WHEN "1010000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118142,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(117687,18);
WHEN "1010001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118240,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(245278,18);
WHEN "1010001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118339,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61714,18);
WHEN "1010001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118437,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(91393,18);
WHEN "1010001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118535,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(72282,18);
WHEN "1010001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118633,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(4490,18);
WHEN "1010001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118730,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150272,18);
WHEN "1010001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118827,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(247594,18);
WHEN "1010001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118925,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34421,18);
WHEN "1010010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119022,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(35150,18);
WHEN "1010010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119118,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249890,18);
WHEN "1010010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119215,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154463,18);
WHEN "1010010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119312,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11120,18);
WHEN "1010010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119408,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(82116,18);
WHEN "1010010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119504,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105413,18);
WHEN "1010010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119600,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(81120,18);
WHEN "1010010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119696,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9344,18);
WHEN "1010011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119791,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152339,18);
WHEN "1010011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119886,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(248066,18);
WHEN "1010011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34490,18);
WHEN "1010011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120077,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(36005,18);
WHEN "1010011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120171,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(252718,18);
WHEN "1010011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120266,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(160448,18);
WHEN "1010011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120361,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21445,18);
WHEN "1010011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120455,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97961,18);
WHEN "1010100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120549,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(127955,18);
WHEN "1010100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120643,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111535,18);
WHEN "1010100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120737,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48807,18);
WHEN "1010100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120830,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202019,18);
WHEN "1010100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120924,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46988,18);
WHEN "1010100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121017,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108109,18);
WHEN "1010100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121110,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123341,18);
WHEN "1010100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121203,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92789,18);
WHEN "1010101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121296,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(16558,18);
WHEN "1010101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121388,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156895,18);
WHEN "1010101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121480,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251761,18);
WHEN "1010101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121573,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(39116,18);
WHEN "1010101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121665,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(43350,18);
WHEN "1010101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121757,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2424,18);
WHEN "1010101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121848,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178584,18);
WHEN "1010101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121940,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47646,18);
WHEN "1010110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122031,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(134000,18);
WHEN "1010110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122122,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(175604,18);
WHEN "1010110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122213,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172562,18);
WHEN "1010110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122304,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(124974,18);
WHEN "1010110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122395,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(32943,18);
WHEN "1010110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122485,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158715,18);
WHEN "1010110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122575,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(240246,18);
WHEN "1010110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122666,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15495,18);
WHEN "1010111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122756,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(8850,18);
WHEN "1010111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122845,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(220412,18);
WHEN "1010111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122935,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(125994,18);
WHEN "1010111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123024,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249984,18);
WHEN "1010111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123114,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68194,18);
WHEN "1010111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123203,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105012,18);
WHEN "1010111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123292,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98395,18);
WHEN "1010111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123381,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48441,18);
WHEN "1011000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123469,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217394,18);
WHEN "1011000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123558,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(81065,18);
WHEN "1011000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123646,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(163841,18);
WHEN "1011000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123734,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(203676,18);
WHEN "1011000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123822,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200670,18);
WHEN "1011000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123910,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154921,18);
WHEN "1011000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123998,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(66526,18);
WHEN "1011000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124085,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197727,18);
WHEN "1011001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124173,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24335,18);
WHEN "1011001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124260,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70734,18);
WHEN "1011001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124347,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74878,18);
WHEN "1011001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124434,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(36865,18);
WHEN "1011001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124520,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218933,18);
WHEN "1011001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124607,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(96893,18);
WHEN "1011001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124693,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(195129,18);
WHEN "1011001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124779,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251593,18);
WHEN "1011010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124866,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(4237,18);
WHEN "1011010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124951,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239588,18);
WHEN "1011010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125037,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171311,18);
WHEN "1011010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125123,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61644,18);
WHEN "1011010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125208,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172827,18);
WHEN "1011010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125293,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(242811,18);
WHEN "1011010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125379,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9546,18);
WHEN "1011010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125463,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(259559,18);
WHEN "1011011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125548,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206512,18);
WHEN "1011011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125633,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(112644,18);
WHEN "1011011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125717,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(240192,18);
WHEN "1011011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125802,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(64962,18);
WHEN "1011011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125886,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111335,18);
WHEN "1011011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125970,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(117261,18);
WHEN "1011011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126054,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(82832,18);
WHEN "1011011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126138,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(8142,18);
WHEN "1011100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126221,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(155428,18);
WHEN "1011100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126305,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(492,18);
WHEN "1011100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126388,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67717,18);
WHEN "1011100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126471,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95050,18);
WHEN "1011100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126554,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(82582,18);
WHEN "1011100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126637,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30405,18);
WHEN "1011100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126719,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200755,18);
WHEN "1011100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126802,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(69435,18);
WHEN "1011101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126884,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(160824,18);
WHEN "1011101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126966,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(212868,18);
WHEN "1011101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127048,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(225659,18);
WHEN "1011101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127130,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199286,18);
WHEN "1011101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127212,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133839,18);
WHEN "1011101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127294,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29409,18);
WHEN "1011101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127375,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148230,18);
WHEN "1011101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127456,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(228246,18);
WHEN "1011110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127538,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7403,18);
WHEN "1011110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127619,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(10079,18);
WHEN "1011110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127699,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(236362,18);
WHEN "1011110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127780,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(162053,18);
WHEN "1011110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127861,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49384,18);
WHEN "1011110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127941,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(160588,18);
WHEN "1011110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128021,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233609,18);
WHEN "1011110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128102,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(6390,18);
WHEN "1011111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128182,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3308,18);
WHEN "1011111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128261,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224450,18);
WHEN "1011111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128341,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(145614,18);
WHEN "1011111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128421,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29034,18);
WHEN "1011111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128500,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(136938,18);
WHEN "1011111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128579,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(207270,18);
WHEN "1011111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128658,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(240116,18);
WHEN "1011111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128737,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235563,18);
WHEN "1100000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128816,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(193696,18);
WHEN "1100000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128895,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(114602,18);
WHEN "1100000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128973,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(260510,18);
WHEN "1100000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129052,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(107217,18);
WHEN "1100000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129130,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179097,18);
WHEN "1100000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129208,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214091,18);
WHEN "1100000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129286,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(212284,18);
WHEN "1100000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129364,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173760,18);
WHEN "1100001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129442,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98604,18);
WHEN "1100001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129519,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249044,18);
WHEN "1100001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129597,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(100876,18);
WHEN "1100001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129674,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178473,18);
WHEN "1100001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129751,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(219772,18);
WHEN "1100001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129828,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224859,18);
WHEN "1100001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129905,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(193817,18);
WHEN "1100001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(126728,18);
WHEN "1100010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130059,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23675,18);
WHEN "1100010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130135,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(146885,18);
WHEN "1100010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130211,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(234296,18);
WHEN "1100010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130288,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23847,18);
WHEN "1100010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130364,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(39908,18);
WHEN "1100010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130440,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20417,18);
WHEN "1100010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130515,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(227599,18);
WHEN "1100010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130591,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(137248,18);
WHEN "1100011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130667,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11588,18);
WHEN "1100011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130742,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(112847,18);
WHEN "1100011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130817,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178959,18);
WHEN "1100011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130892,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(210006,18);
WHEN "1100011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130967,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206068,18);
WHEN "1100011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131042,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167226,18);
WHEN "1100011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131117,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(93560,18);
WHEN "1100011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131191,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(247293,18);
WHEN "1100100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131266,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104218,18);
WHEN "1100100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131340,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(188702,18);
WHEN "1100100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131414,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(238680,18);
WHEN "1100100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131488,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(254231,18);
WHEN "1100100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131562,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235435,18);
WHEN "1100100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131636,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(182370,18);
WHEN "1100100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131710,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95115,18);
WHEN "1100100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131783,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235893,18);
WHEN "1100101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131857,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(80492,18);
WHEN "1100101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131930,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153280,18);
WHEN "1100101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132003,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192190,18);
WHEN "1100101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132076,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197300,18);
WHEN "1100101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132149,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(168687,18);
WHEN "1100101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132222,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(106429,18);
WHEN "1100101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132295,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(10602,18);
WHEN "1100101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132367,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143428,18);
WHEN "1100110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132439,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(242839,18);
WHEN "1100110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132512,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46768,18);
WHEN "1100110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132584,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(79578,18);
WHEN "1100110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132656,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(79203,18);
WHEN "1100110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132728,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45718,18);
WHEN "1100110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132799,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241342,18);
WHEN "1100110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132871,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(141864,18);
WHEN "1100110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132943,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9502,18);
WHEN "1100111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133014,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(106476,18);
WHEN "1100111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133085,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170717,18);
WHEN "1100111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133156,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202300,18);
WHEN "1100111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133227,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201300,18);
WHEN "1100111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133298,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167790,18);
WHEN "1100111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133369,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(101845,18);
WHEN "1100111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133440,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3539,18);
WHEN "1100111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133510,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(135090,18);
WHEN "1101000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133580,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(234429,18);
WHEN "1101000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133651,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(39483,18);
WHEN "1101000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133721,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74615,18);
WHEN "1101000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133791,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(77754,18);
WHEN "1101000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133861,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48973,18);
WHEN "1101000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133930,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250488,18);
WHEN "1101000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134000,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158085,18);
WHEN "1101000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134070,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33979,18);
WHEN "1101001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134139,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140388,18);
WHEN "1101001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134208,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215238,18);
WHEN "1101001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134277,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258603,18);
WHEN "1101001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134347,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(8409,18);
WHEN "1101001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134415,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251160,18);
WHEN "1101001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134484,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200497,18);
WHEN "1101001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134553,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(118633,18);
WHEN "1101001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134622,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(5640,18);
WHEN "1101010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134690,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123732,18);
WHEN "1101010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134758,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(210837,18);
WHEN "1101010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134827,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(4881,18);
WHEN "1101010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134895,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30222,18);
WHEN "1101010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134963,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24786,18);
WHEN "1101010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135030,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250788,18);
WHEN "1101010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135098,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184008,18);
WHEN "1101010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135166,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(86662,18);
WHEN "1101011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135233,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(220961,18);
WHEN "1101011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135301,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62688,18);
WHEN "1101011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135368,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(136199,18);
WHEN "1101011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135435,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179420,18);
WHEN "1101011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135502,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192419,18);
WHEN "1101011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135569,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(175264,18);
WHEN "1101011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135636,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(128025,18);
WHEN "1101011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135703,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(50768,18);
WHEN "1101100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135769,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205708,18);
WHEN "1101100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135836,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68622,18);
WHEN "1101100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135902,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(163868,18);
WHEN "1101100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135968,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(229368,18);
WHEN "1101100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136035,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3045,18);
WHEN "1101100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136101,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9256,18);
WHEN "1101100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136166,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(248067,18);
WHEN "1101100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136232,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(195258,18);
WHEN "1101101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136298,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(113037,18);
WHEN "1101101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136364,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1473,18);
WHEN "1101101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136429,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122776,18);
WHEN "1101101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136494,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214867,18);
WHEN "1101101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136560,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15669,18);
WHEN "1101101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136625,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49536,18);
WHEN "1101101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136690,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54389,18);
WHEN "1101101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136755,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30294,18);
WHEN "1101110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136819,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239461,18);
WHEN "1101110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136884,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157665,18);
WHEN "1101110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136949,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47117,18);
WHEN "1101110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137013,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170026,18);
WHEN "1101110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137078,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2168,18);
WHEN "1101110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137142,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67895,18);
WHEN "1101110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137206,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105128,18);
WHEN "1101110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137270,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(113931,18);
WHEN "1101111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137334,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(94369,18);
WHEN "1101111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137398,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46504,18);
WHEN "1101111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137461,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232546,18);
WHEN "1101111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137525,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(128269,18);
WHEN "1101111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137588,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258024,18);
WHEN "1101111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137652,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97588,18);
WHEN "1101111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137715,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171311,18);
WHEN "1101111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137778,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217112,18);
WHEN "1110000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137841,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235053,18);
WHEN "1110000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137904,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(225198,18);
WHEN "1110000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137967,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(187609,18);
WHEN "1110000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138030,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122349,18);
WHEN "1110000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138093,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29478,18);
WHEN "1110000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138155,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171204,18);
WHEN "1110000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138218,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23299,18);
WHEN "1110000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138280,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(110115,18);
WHEN "1110001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138342,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(169567,18);
WHEN "1110001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138404,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201718,18);
WHEN "1110001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138466,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206629,18);
WHEN "1110001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138528,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184361,18);
WHEN "1110001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138590,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(134974,18);
WHEN "1110001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138652,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58530,18);
WHEN "1110001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138713,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217232,18);
WHEN "1110001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138775,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(86854,18);
WHEN "1110010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138836,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191743,18);
WHEN "1110010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138898,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7673,18);
WHEN "1110010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138959,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58989,18);
WHEN "1110010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139020,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(83609,18);
WHEN "1110010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139081,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(81593,18);
WHEN "1110010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139142,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(52999,18);
WHEN "1110010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139202,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(260030,18);
WHEN "1110010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139263,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178459,18);
WHEN "1110011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139324,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70488,18);
WHEN "1110011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139384,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(198320,18);
WHEN "1110011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139445,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(37726,18);
WHEN "1110011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139505,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(113052,18);
WHEN "1110011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139565,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(162212,18);
WHEN "1110011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139625,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(185266,18);
WHEN "1110011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139685,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(182271,18);
WHEN "1110011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139745,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153286,18);
WHEN "1110100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139805,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98367,18);
WHEN "1110100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139865,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(17573,18);
WHEN "1110100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139924,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173106,18);
WHEN "1110100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139984,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(40734,18);
WHEN "1110100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140043,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144803,18);
WHEN "1110100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140102,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(223226,18);
WHEN "1110100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140162,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(13916,18);
WHEN "1110100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140221,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41217,18);
WHEN "1110101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140280,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(43044,18);
WHEN "1110101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140339,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19451,18);
WHEN "1110101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140397,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232640,18);
WHEN "1110101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140456,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158378,18);
WHEN "1110101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140515,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58866,18);
WHEN "1110101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140573,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196304,18);
WHEN "1110101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140632,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46459,18);
WHEN "1110101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140690,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133676,18);
WHEN "1110110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140748,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(195865,18);
WHEN "1110110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140806,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233082,18);
WHEN "1110110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140864,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(245382,18);
WHEN "1110110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140922,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232821,18);
WHEN "1110110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140980,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(195453,18);
WHEN "1110110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141038,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133334,18);
WHEN "1110110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141096,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46517,18);
WHEN "1110110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141153,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197201,18);
WHEN "1110111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141211,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61153,18);
WHEN "1110111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141268,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(162716,18);
WHEN "1110111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141325,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239798,18);
WHEN "1110111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141383,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30311,18);
WHEN "1110111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141440,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58595,18);
WHEN "1110111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141497,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62561,18);
WHEN "1110111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141554,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(42262,18);
WHEN "1110111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141610,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(259896,18);
WHEN "1111000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141667,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191228,18);
WHEN "1111000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141724,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98455,18);
WHEN "1111000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141780,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(243774,18);
WHEN "1111000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141837,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(102950,18);
WHEN "1111000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141893,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200324,18);
WHEN "1111000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141950,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11660,18);
WHEN "1111000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142006,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61299,18);
WHEN "1111000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142062,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(87149,18);
WHEN "1111001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142118,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89262,18);
WHEN "1111001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142174,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67691,18);
WHEN "1111001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142230,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(22487,18);
WHEN "1111001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142285,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215847,18);
WHEN "1111001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142341,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123533,18);
WHEN "1111001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142397,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7742,18);
WHEN "1111001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142452,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(130668,18);
WHEN "1111001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142507,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230220,18);
WHEN "1111010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142563,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(44304,18);
WHEN "1111010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142618,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97259,18);
WHEN "1111010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142673,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(126992,18);
WHEN "1111010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142728,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133554,18);
WHEN "1111010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142783,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(116996,18);
WHEN "1111010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142838,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(77368,18);
WHEN "1111010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142893,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(14720,18);
WHEN "1111010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142947,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191247,18);
WHEN "1111011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143002,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(82710,18);
WHEN "1111011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143056,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(213448,18);
WHEN "1111011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143111,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59223,18);
WHEN "1111011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143165,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144372,18);
WHEN "1111011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143219,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206801,18);
WHEN "1111011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143273,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(246559,18);
WHEN "1111011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143328,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1553,18);
WHEN "1111011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143381,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258262,18);
WHEN "1111100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143435,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230304,18);
WHEN "1111100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143489,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179872,18);
WHEN "1111100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143543,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(107014,18);
WHEN "1111100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143597,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11781,18);
WHEN "1111100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143650,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156363,18);
WHEN "1111100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143704,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(16522,18);
WHEN "1111100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143757,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(116595,18);
WHEN "1111100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143810,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(194484,18);
WHEN "1111101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143863,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250238,18);
WHEN "1111101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143917,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21762,18);
WHEN "1111101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143970,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33391,18);
WHEN "1111101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144023,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23028,18);
WHEN "1111101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144075,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(252866,18);
WHEN "1111101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144128,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(198664,18);
WHEN "1111101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144181,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122614,18);
WHEN "1111101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144234,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24761,18);
WHEN "1111110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144286,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167299,18);
WHEN "1111110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144339,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(25984,18);
WHEN "1111110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144391,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(125154,18);
WHEN "1111110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144443,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202709,18);
WHEN "1111110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144495,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258698,18);
WHEN "1111110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144548,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(31022,18);
WHEN "1111110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144600,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(44016,18);
WHEN "1111110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144652,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(35582,18);
WHEN "1111111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144704,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(5766,18);
WHEN "1111111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144755,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(216758,18);
WHEN "1111111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144807,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144317,18);
WHEN "1111111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144859,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(50632,18);
WHEN "1111111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144910,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197892,18);
WHEN "1111111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144962,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61856,18);
WHEN "1111111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(145013,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(166857,18);
WHEN "1111111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(145064,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250795,18);
WHEN others =>
data(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_exp2_s5.vhd | 10 | 180176 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_s5
-- VHDL created on Fri Apr 5 13:35:21 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (7 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (7 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (7 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (5 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (22 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(32 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(32 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(32 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(32 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (11 downto 0);
signal rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(11 downto 0);
signal rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (2 downto 0);
signal rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(2 downto 0);
signal memoryC0_uid123_exp2TabGen_q : std_logic_vector(27 downto 0);
signal memoryC1_uid125_exp2TabGen_q : std_logic_vector(20 downto 0);
signal memoryC2_uid127_exp2TabGen_q : std_logic_vector(11 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (32 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (32 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (32 downto 0);
signal reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (32 downto 0);
signal reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (32 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (9 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (10 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_q : std_logic_vector (6 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (22 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (5 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (22 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (7 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (28 downto 0);
signal ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (24 downto 0);
signal ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (20 downto 0);
signal ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (30 downto 0);
signal ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (29 downto 0);
signal ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d_q : std_logic_vector (32 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a_q : std_logic_vector (6 downto 0);
signal ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a_q : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_mem_top_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(13 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(13 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (13 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(13 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(13 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (13 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (23 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (7 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (31 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (22 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(8 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(8 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (8 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (8 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (5 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(11 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(11 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (11 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (10 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_b : std_logic_vector (23 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(32 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(32 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(32 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(34 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(34 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (34 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (33 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (15 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (15 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_a : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_b : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (8 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (5 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (7 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (7 downto 0);
signal RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (28 downto 0);
signal RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (24 downto 0);
signal RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (20 downto 0);
signal lowRangeB_uid131_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid131_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid132_exp2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid132_exp2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid137_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid137_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid138_exp2PolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid138_exp2PolyEval_b : std_logic_vector (21 downto 0);
signal RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (31 downto 0);
signal RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (30 downto 0);
signal RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (29 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (32 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (9 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (22 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (22 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (32 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (32 downto 0);
signal yT1_uid129_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid129_exp2PolyEval_b : std_logic_vector (11 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid133_exp2PolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid133_exp2PolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid133_exp2PolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid133_exp2PolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid139_exp2PolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid139_exp2PolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid139_exp2PolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid139_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (22 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (6 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (16 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal s1_uid131_uid134_exp2PolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid137_uid140_exp2PolyEval_q : std_logic_vector (30 downto 0);
signal rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (28 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (23 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (22 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (22 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable(LOGICAL,342)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_a <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q <= not ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,343)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_mem_top(CONSTANT,339)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_mem_top_q <= "011";
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp(LOGICAL,340)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_mem_top_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_q <= "1" when ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_a = ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_b else "0";
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg(REG,341)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,344)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,345)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(31 downto 31);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,187)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(22 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(22 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,184)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((32 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((34 downto 33 => onesCmpFxpIn_uid35_fpExp2Test_q(32)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(33 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(32 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(32 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 32);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,278)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000";
--rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((2 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 3, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,256)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000";
--rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((11 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 12, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((32 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 33, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,151)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 16);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,150)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,149)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "100001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(30 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(30 downto 23);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000111";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(8 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(5 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(5 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,196)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,147)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((10 downto 9 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(8)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(11);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,148)@1
reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 12);
--ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,266)@2
ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= cstZeroWE_uid13_fpExp2Test_q;
rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 8);
--ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,262)@2
ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 4);
--ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,258)@2
ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,153)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(3 downto 0);
rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a(DELAY,319)@1
ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,152)@2
reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 3);
--ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,284)@3
ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 2);
--ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,280)@3
ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@1
rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,277)@2
ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xout => ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 1);
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@3
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b_q & RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_b;
--ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d(DELAY,289)@3
ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, xout => ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,155)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(1 downto 0);
rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_in(1 downto 0);
--ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a(DELAY,321)@1
ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,154)@3
reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(32 downto 23);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,156)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((11 downto 10 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(9)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(10 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(7 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(7 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,238)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "00000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,233)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@0
InvSignX_uid62_fpExp2Test_a <= signX_uid7_fpExp2Test_b;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(8 downto 8);
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@0
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_b;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,230)@0
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,212)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,157)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(10)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(13);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,213)@0
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--posInf_uid67_fpExp2Test(LOGICAL,66)@0
posInf_uid67_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,228)@0
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,218)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@0
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_b;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= signX_uid7_fpExp2Test_b;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,217)@0
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(10)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(13);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,159)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (expRPostExc_uid78_fpExp2Test_s, en, cstZeroWE_uid13_fpExp2Test_q, ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, cstAllOWE_uid16_fpExp2Test_q, cstAllOWE_uid16_fpExp2Test_q)
BEGIN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,333)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt(COUNTER,335)
-- every=1, low=0, high=3, step=1, init=1
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i,2));
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg(REG,336)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux(MUX,337)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_s <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux: PROCESS (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_s, ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q, ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,334)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 2,
numwords_a => 4,
width_b => 8,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(7 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "00000000000000000000001";
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q(22 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(22 downto 0);
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(22 downto 16);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0(REG,160)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid127_exp2TabGen(LOOKUP,126)@5
memoryC2_uid127_exp2TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid127_exp2TabGen_q <= "001111011001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q) IS
WHEN "0000000" => memoryC2_uid127_exp2TabGen_q <= "001111011001";
WHEN "0000001" => memoryC2_uid127_exp2TabGen_q <= "001111100010";
WHEN "0000010" => memoryC2_uid127_exp2TabGen_q <= "001111100110";
WHEN "0000011" => memoryC2_uid127_exp2TabGen_q <= "001111101011";
WHEN "0000100" => memoryC2_uid127_exp2TabGen_q <= "001111110000";
WHEN "0000101" => memoryC2_uid127_exp2TabGen_q <= "001111110111";
WHEN "0000110" => memoryC2_uid127_exp2TabGen_q <= "001111111100";
WHEN "0000111" => memoryC2_uid127_exp2TabGen_q <= "010000000001";
WHEN "0001000" => memoryC2_uid127_exp2TabGen_q <= "010000000110";
WHEN "0001001" => memoryC2_uid127_exp2TabGen_q <= "010000001101";
WHEN "0001010" => memoryC2_uid127_exp2TabGen_q <= "010000010010";
WHEN "0001011" => memoryC2_uid127_exp2TabGen_q <= "010000010111";
WHEN "0001100" => memoryC2_uid127_exp2TabGen_q <= "010000011101";
WHEN "0001101" => memoryC2_uid127_exp2TabGen_q <= "010000100011";
WHEN "0001110" => memoryC2_uid127_exp2TabGen_q <= "010000101001";
WHEN "0001111" => memoryC2_uid127_exp2TabGen_q <= "010000101101";
WHEN "0010000" => memoryC2_uid127_exp2TabGen_q <= "010000110011";
WHEN "0010001" => memoryC2_uid127_exp2TabGen_q <= "010000111010";
WHEN "0010010" => memoryC2_uid127_exp2TabGen_q <= "010001000000";
WHEN "0010011" => memoryC2_uid127_exp2TabGen_q <= "010001000101";
WHEN "0010100" => memoryC2_uid127_exp2TabGen_q <= "010001001011";
WHEN "0010101" => memoryC2_uid127_exp2TabGen_q <= "010001010010";
WHEN "0010110" => memoryC2_uid127_exp2TabGen_q <= "010001010110";
WHEN "0010111" => memoryC2_uid127_exp2TabGen_q <= "010001011011";
WHEN "0011000" => memoryC2_uid127_exp2TabGen_q <= "010001100101";
WHEN "0011001" => memoryC2_uid127_exp2TabGen_q <= "010001101001";
WHEN "0011010" => memoryC2_uid127_exp2TabGen_q <= "010001110011";
WHEN "0011011" => memoryC2_uid127_exp2TabGen_q <= "010001110111";
WHEN "0011100" => memoryC2_uid127_exp2TabGen_q <= "010001111011";
WHEN "0011101" => memoryC2_uid127_exp2TabGen_q <= "010010000011";
WHEN "0011110" => memoryC2_uid127_exp2TabGen_q <= "010010001001";
WHEN "0011111" => memoryC2_uid127_exp2TabGen_q <= "010010001101";
WHEN "0100000" => memoryC2_uid127_exp2TabGen_q <= "010010010110";
WHEN "0100001" => memoryC2_uid127_exp2TabGen_q <= "010010011101";
WHEN "0100010" => memoryC2_uid127_exp2TabGen_q <= "010010100011";
WHEN "0100011" => memoryC2_uid127_exp2TabGen_q <= "010010101001";
WHEN "0100100" => memoryC2_uid127_exp2TabGen_q <= "010010101111";
WHEN "0100101" => memoryC2_uid127_exp2TabGen_q <= "010010110100";
WHEN "0100110" => memoryC2_uid127_exp2TabGen_q <= "010010111100";
WHEN "0100111" => memoryC2_uid127_exp2TabGen_q <= "010011000011";
WHEN "0101000" => memoryC2_uid127_exp2TabGen_q <= "010011001001";
WHEN "0101001" => memoryC2_uid127_exp2TabGen_q <= "010011001110";
WHEN "0101010" => memoryC2_uid127_exp2TabGen_q <= "010011010111";
WHEN "0101011" => memoryC2_uid127_exp2TabGen_q <= "010011011100";
WHEN "0101100" => memoryC2_uid127_exp2TabGen_q <= "010011100011";
WHEN "0101101" => memoryC2_uid127_exp2TabGen_q <= "010011101001";
WHEN "0101110" => memoryC2_uid127_exp2TabGen_q <= "010011110011";
WHEN "0101111" => memoryC2_uid127_exp2TabGen_q <= "010011110111";
WHEN "0110000" => memoryC2_uid127_exp2TabGen_q <= "010011111101";
WHEN "0110001" => memoryC2_uid127_exp2TabGen_q <= "010100001001";
WHEN "0110010" => memoryC2_uid127_exp2TabGen_q <= "010100001111";
WHEN "0110011" => memoryC2_uid127_exp2TabGen_q <= "010100010110";
WHEN "0110100" => memoryC2_uid127_exp2TabGen_q <= "010100011110";
WHEN "0110101" => memoryC2_uid127_exp2TabGen_q <= "010100100101";
WHEN "0110110" => memoryC2_uid127_exp2TabGen_q <= "010100101010";
WHEN "0110111" => memoryC2_uid127_exp2TabGen_q <= "010100110000";
WHEN "0111000" => memoryC2_uid127_exp2TabGen_q <= "010100110110";
WHEN "0111001" => memoryC2_uid127_exp2TabGen_q <= "010100111111";
WHEN "0111010" => memoryC2_uid127_exp2TabGen_q <= "010101000101";
WHEN "0111011" => memoryC2_uid127_exp2TabGen_q <= "010101001101";
WHEN "0111100" => memoryC2_uid127_exp2TabGen_q <= "010101010101";
WHEN "0111101" => memoryC2_uid127_exp2TabGen_q <= "010101011011";
WHEN "0111110" => memoryC2_uid127_exp2TabGen_q <= "010101100101";
WHEN "0111111" => memoryC2_uid127_exp2TabGen_q <= "010101101101";
WHEN "1000000" => memoryC2_uid127_exp2TabGen_q <= "010101110100";
WHEN "1000001" => memoryC2_uid127_exp2TabGen_q <= "010101111010";
WHEN "1000010" => memoryC2_uid127_exp2TabGen_q <= "010110000001";
WHEN "1000011" => memoryC2_uid127_exp2TabGen_q <= "010110001001";
WHEN "1000100" => memoryC2_uid127_exp2TabGen_q <= "010110010001";
WHEN "1000101" => memoryC2_uid127_exp2TabGen_q <= "010110011000";
WHEN "1000110" => memoryC2_uid127_exp2TabGen_q <= "010110100011";
WHEN "1000111" => memoryC2_uid127_exp2TabGen_q <= "010110101001";
WHEN "1001000" => memoryC2_uid127_exp2TabGen_q <= "010110110000";
WHEN "1001001" => memoryC2_uid127_exp2TabGen_q <= "010110111001";
WHEN "1001010" => memoryC2_uid127_exp2TabGen_q <= "010111000010";
WHEN "1001011" => memoryC2_uid127_exp2TabGen_q <= "010111001000";
WHEN "1001100" => memoryC2_uid127_exp2TabGen_q <= "010111001111";
WHEN "1001101" => memoryC2_uid127_exp2TabGen_q <= "010111011011";
WHEN "1001110" => memoryC2_uid127_exp2TabGen_q <= "010111100001";
WHEN "1001111" => memoryC2_uid127_exp2TabGen_q <= "010111100111";
WHEN "1010000" => memoryC2_uid127_exp2TabGen_q <= "010111110100";
WHEN "1010001" => memoryC2_uid127_exp2TabGen_q <= "010111111010";
WHEN "1010010" => memoryC2_uid127_exp2TabGen_q <= "011000000010";
WHEN "1010011" => memoryC2_uid127_exp2TabGen_q <= "011000001010";
WHEN "1010100" => memoryC2_uid127_exp2TabGen_q <= "011000010011";
WHEN "1010101" => memoryC2_uid127_exp2TabGen_q <= "011000011100";
WHEN "1010110" => memoryC2_uid127_exp2TabGen_q <= "011000100011";
WHEN "1010111" => memoryC2_uid127_exp2TabGen_q <= "011000101101";
WHEN "1011000" => memoryC2_uid127_exp2TabGen_q <= "011000110101";
WHEN "1011001" => memoryC2_uid127_exp2TabGen_q <= "011000111111";
WHEN "1011010" => memoryC2_uid127_exp2TabGen_q <= "011001000110";
WHEN "1011011" => memoryC2_uid127_exp2TabGen_q <= "011001001101";
WHEN "1011100" => memoryC2_uid127_exp2TabGen_q <= "011001011001";
WHEN "1011101" => memoryC2_uid127_exp2TabGen_q <= "011001100000";
WHEN "1011110" => memoryC2_uid127_exp2TabGen_q <= "011001101001";
WHEN "1011111" => memoryC2_uid127_exp2TabGen_q <= "011001110010";
WHEN "1100000" => memoryC2_uid127_exp2TabGen_q <= "011001111001";
WHEN "1100001" => memoryC2_uid127_exp2TabGen_q <= "011010000011";
WHEN "1100010" => memoryC2_uid127_exp2TabGen_q <= "011010001100";
WHEN "1100011" => memoryC2_uid127_exp2TabGen_q <= "011010011001";
WHEN "1100100" => memoryC2_uid127_exp2TabGen_q <= "011010100000";
WHEN "1100101" => memoryC2_uid127_exp2TabGen_q <= "011010101000";
WHEN "1100110" => memoryC2_uid127_exp2TabGen_q <= "011010110010";
WHEN "1100111" => memoryC2_uid127_exp2TabGen_q <= "011010111011";
WHEN "1101000" => memoryC2_uid127_exp2TabGen_q <= "011011000100";
WHEN "1101001" => memoryC2_uid127_exp2TabGen_q <= "011011001101";
WHEN "1101010" => memoryC2_uid127_exp2TabGen_q <= "011011011001";
WHEN "1101011" => memoryC2_uid127_exp2TabGen_q <= "011011100001";
WHEN "1101100" => memoryC2_uid127_exp2TabGen_q <= "011011101001";
WHEN "1101101" => memoryC2_uid127_exp2TabGen_q <= "011011110010";
WHEN "1101110" => memoryC2_uid127_exp2TabGen_q <= "011011111111";
WHEN "1101111" => memoryC2_uid127_exp2TabGen_q <= "011100000111";
WHEN "1110000" => memoryC2_uid127_exp2TabGen_q <= "011100010010";
WHEN "1110001" => memoryC2_uid127_exp2TabGen_q <= "011100011100";
WHEN "1110010" => memoryC2_uid127_exp2TabGen_q <= "011100100110";
WHEN "1110011" => memoryC2_uid127_exp2TabGen_q <= "011100110000";
WHEN "1110100" => memoryC2_uid127_exp2TabGen_q <= "011100111001";
WHEN "1110101" => memoryC2_uid127_exp2TabGen_q <= "011101000011";
WHEN "1110110" => memoryC2_uid127_exp2TabGen_q <= "011101001110";
WHEN "1110111" => memoryC2_uid127_exp2TabGen_q <= "011101011000";
WHEN "1111000" => memoryC2_uid127_exp2TabGen_q <= "011101100001";
WHEN "1111001" => memoryC2_uid127_exp2TabGen_q <= "011101101001";
WHEN "1111010" => memoryC2_uid127_exp2TabGen_q <= "011101111000";
WHEN "1111011" => memoryC2_uid127_exp2TabGen_q <= "011110000001";
WHEN "1111100" => memoryC2_uid127_exp2TabGen_q <= "011110001010";
WHEN "1111101" => memoryC2_uid127_exp2TabGen_q <= "011110010110";
WHEN "1111110" => memoryC2_uid127_exp2TabGen_q <= "011110100010";
WHEN "1111111" => memoryC2_uid127_exp2TabGen_q <= "011110101011";
WHEN OTHERS =>
memoryC2_uid127_exp2TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,200)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(15 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(15 downto 0);
--yT1_uid129_exp2PolyEval(BITSELECT,128)@5
yT1_uid129_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid129_exp2PolyEval_b <= yT1_uid129_exp2PolyEval_in(15 downto 4);
--reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0(REG,161)@5
reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0_q <= yT1_uid129_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid142_pT1_uid130_exp2PolyEval(MULT,141)@6
prodXY_uid142_pT1_uid130_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid142_pT1_uid130_exp2PolyEval_a),13)) * SIGNED(prodXY_uid142_pT1_uid130_exp2PolyEval_b);
prodXY_uid142_pT1_uid130_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid142_pT1_uid130_exp2PolyEval_a <= (others => '0');
prodXY_uid142_pT1_uid130_exp2PolyEval_b <= (others => '0');
prodXY_uid142_pT1_uid130_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid142_pT1_uid130_exp2PolyEval_a <= reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0_q;
prodXY_uid142_pT1_uid130_exp2PolyEval_b <= memoryC2_uid127_exp2TabGen_q;
prodXY_uid142_pT1_uid130_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid142_pT1_uid130_exp2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid142_pT1_uid130_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid142_pT1_uid130_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid142_pT1_uid130_exp2PolyEval_q <= prodXY_uid142_pT1_uid130_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval(BITSELECT,142)@9
prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_in <= prodXY_uid142_pT1_uid130_exp2PolyEval_q;
prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_b <= prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_in(23 downto 11);
--highBBits_uid132_exp2PolyEval(BITSELECT,131)@9
highBBits_uid132_exp2PolyEval_in <= prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_b;
highBBits_uid132_exp2PolyEval_b <= highBBits_uid132_exp2PolyEval_in(12 downto 1);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a(DELAY,293)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid125_exp2TabGen(LOOKUP,124)@8
memoryC1_uid125_exp2TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid125_exp2TabGen_q <= "001011000101110010001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a_q) IS
WHEN "0000000" => memoryC1_uid125_exp2TabGen_q <= "001011000101110010001";
WHEN "0000001" => memoryC1_uid125_exp2TabGen_q <= "001011001001101000011";
WHEN "0000010" => memoryC1_uid125_exp2TabGen_q <= "001011001101100000100";
WHEN "0000011" => memoryC1_uid125_exp2TabGen_q <= "001011010001011010000";
WHEN "0000100" => memoryC1_uid125_exp2TabGen_q <= "001011010101010100101";
WHEN "0000101" => memoryC1_uid125_exp2TabGen_q <= "001011011001010000100";
WHEN "0000110" => memoryC1_uid125_exp2TabGen_q <= "001011011101001110001";
WHEN "0000111" => memoryC1_uid125_exp2TabGen_q <= "001011100001001100111";
WHEN "0001000" => memoryC1_uid125_exp2TabGen_q <= "001011100101001101010";
WHEN "0001001" => memoryC1_uid125_exp2TabGen_q <= "001011101001001110101";
WHEN "0001010" => memoryC1_uid125_exp2TabGen_q <= "001011101101010001101";
WHEN "0001011" => memoryC1_uid125_exp2TabGen_q <= "001011110001010110001";
WHEN "0001100" => memoryC1_uid125_exp2TabGen_q <= "001011110101011011111";
WHEN "0001101" => memoryC1_uid125_exp2TabGen_q <= "001011111001100011001";
WHEN "0001110" => memoryC1_uid125_exp2TabGen_q <= "001011111101101011101";
WHEN "0001111" => memoryC1_uid125_exp2TabGen_q <= "001100000001110110000";
WHEN "0010000" => memoryC1_uid125_exp2TabGen_q <= "001100000110000001100";
WHEN "0010001" => memoryC1_uid125_exp2TabGen_q <= "001100001010001110011";
WHEN "0010010" => memoryC1_uid125_exp2TabGen_q <= "001100001110011100110";
WHEN "0010011" => memoryC1_uid125_exp2TabGen_q <= "001100010010101100110";
WHEN "0010100" => memoryC1_uid125_exp2TabGen_q <= "001100010110111110010";
WHEN "0010101" => memoryC1_uid125_exp2TabGen_q <= "001100011011010000111";
WHEN "0010110" => memoryC1_uid125_exp2TabGen_q <= "001100011111100101100";
WHEN "0010111" => memoryC1_uid125_exp2TabGen_q <= "001100100011111011100";
WHEN "0011000" => memoryC1_uid125_exp2TabGen_q <= "001100101000010010011";
WHEN "0011001" => memoryC1_uid125_exp2TabGen_q <= "001100101100101011100";
WHEN "0011010" => memoryC1_uid125_exp2TabGen_q <= "001100110001000101100";
WHEN "0011011" => memoryC1_uid125_exp2TabGen_q <= "001100110101100001101";
WHEN "0011100" => memoryC1_uid125_exp2TabGen_q <= "001100111001111111100";
WHEN "0011101" => memoryC1_uid125_exp2TabGen_q <= "001100111110011110011";
WHEN "0011110" => memoryC1_uid125_exp2TabGen_q <= "001101000010111110111";
WHEN "0011111" => memoryC1_uid125_exp2TabGen_q <= "001101000111100001011";
WHEN "0100000" => memoryC1_uid125_exp2TabGen_q <= "001101001100000100110";
WHEN "0100001" => memoryC1_uid125_exp2TabGen_q <= "001101010000101010001";
WHEN "0100010" => memoryC1_uid125_exp2TabGen_q <= "001101010101010001000";
WHEN "0100011" => memoryC1_uid125_exp2TabGen_q <= "001101011001111001101";
WHEN "0100100" => memoryC1_uid125_exp2TabGen_q <= "001101011110100011110";
WHEN "0100101" => memoryC1_uid125_exp2TabGen_q <= "001101100011001111110";
WHEN "0100110" => memoryC1_uid125_exp2TabGen_q <= "001101100111111101000";
WHEN "0100111" => memoryC1_uid125_exp2TabGen_q <= "001101101100101011111";
WHEN "0101000" => memoryC1_uid125_exp2TabGen_q <= "001101110001011100101";
WHEN "0101001" => memoryC1_uid125_exp2TabGen_q <= "001101110110001111001";
WHEN "0101010" => memoryC1_uid125_exp2TabGen_q <= "001101111011000010110";
WHEN "0101011" => memoryC1_uid125_exp2TabGen_q <= "001101111111111000110";
WHEN "0101100" => memoryC1_uid125_exp2TabGen_q <= "001110000100110000000";
WHEN "0101101" => memoryC1_uid125_exp2TabGen_q <= "001110001001101001001";
WHEN "0101110" => memoryC1_uid125_exp2TabGen_q <= "001110001110100011011";
WHEN "0101111" => memoryC1_uid125_exp2TabGen_q <= "001110010011100000010";
WHEN "0110000" => memoryC1_uid125_exp2TabGen_q <= "001110011000011110100";
WHEN "0110001" => memoryC1_uid125_exp2TabGen_q <= "001110011101011101110";
WHEN "0110010" => memoryC1_uid125_exp2TabGen_q <= "001110100010011111100";
WHEN "0110011" => memoryC1_uid125_exp2TabGen_q <= "001110100111100010111";
WHEN "0110100" => memoryC1_uid125_exp2TabGen_q <= "001110101100100111111";
WHEN "0110101" => memoryC1_uid125_exp2TabGen_q <= "001110110001101110110";
WHEN "0110110" => memoryC1_uid125_exp2TabGen_q <= "001110110110110111101";
WHEN "0110111" => memoryC1_uid125_exp2TabGen_q <= "001110111100000010010";
WHEN "0111000" => memoryC1_uid125_exp2TabGen_q <= "001111000001001110101";
WHEN "0111001" => memoryC1_uid125_exp2TabGen_q <= "001111000110011100011";
WHEN "0111010" => memoryC1_uid125_exp2TabGen_q <= "001111001011101100100";
WHEN "0111011" => memoryC1_uid125_exp2TabGen_q <= "001111010000111110001";
WHEN "0111100" => memoryC1_uid125_exp2TabGen_q <= "001111010110010001100";
WHEN "0111101" => memoryC1_uid125_exp2TabGen_q <= "001111011011100111000";
WHEN "0111110" => memoryC1_uid125_exp2TabGen_q <= "001111100000111101111";
WHEN "0111111" => memoryC1_uid125_exp2TabGen_q <= "001111100110010111000";
WHEN "1000000" => memoryC1_uid125_exp2TabGen_q <= "001111101011110001111";
WHEN "1000001" => memoryC1_uid125_exp2TabGen_q <= "001111110001001111000";
WHEN "1000010" => memoryC1_uid125_exp2TabGen_q <= "001111110110101101110";
WHEN "1000011" => memoryC1_uid125_exp2TabGen_q <= "001111111100001110011";
WHEN "1000100" => memoryC1_uid125_exp2TabGen_q <= "010000000001110000111";
WHEN "1000101" => memoryC1_uid125_exp2TabGen_q <= "010000000111010101011";
WHEN "1000110" => memoryC1_uid125_exp2TabGen_q <= "010000001100111011011";
WHEN "1000111" => memoryC1_uid125_exp2TabGen_q <= "010000010010100100000";
WHEN "1001000" => memoryC1_uid125_exp2TabGen_q <= "010000011000001110011";
WHEN "1001001" => memoryC1_uid125_exp2TabGen_q <= "010000011101111010101";
WHEN "1001010" => memoryC1_uid125_exp2TabGen_q <= "010000100011101000101";
WHEN "1001011" => memoryC1_uid125_exp2TabGen_q <= "010000101001011001001";
WHEN "1001100" => memoryC1_uid125_exp2TabGen_q <= "010000101111001011100";
WHEN "1001101" => memoryC1_uid125_exp2TabGen_q <= "010000110100111111010";
WHEN "1001110" => memoryC1_uid125_exp2TabGen_q <= "010000111010110101110";
WHEN "1001111" => memoryC1_uid125_exp2TabGen_q <= "010001000000101110011";
WHEN "1010000" => memoryC1_uid125_exp2TabGen_q <= "010001000110101000001";
WHEN "1010001" => memoryC1_uid125_exp2TabGen_q <= "010001001100100100110";
WHEN "1010010" => memoryC1_uid125_exp2TabGen_q <= "010001010010100011011";
WHEN "1010011" => memoryC1_uid125_exp2TabGen_q <= "010001011000100011111";
WHEN "1010100" => memoryC1_uid125_exp2TabGen_q <= "010001011110100110100";
WHEN "1010101" => memoryC1_uid125_exp2TabGen_q <= "010001100100101011001";
WHEN "1010110" => memoryC1_uid125_exp2TabGen_q <= "010001101010110010001";
WHEN "1010111" => memoryC1_uid125_exp2TabGen_q <= "010001110000111011000";
WHEN "1011000" => memoryC1_uid125_exp2TabGen_q <= "010001110111000110000";
WHEN "1011001" => memoryC1_uid125_exp2TabGen_q <= "010001111101010011001";
WHEN "1011010" => memoryC1_uid125_exp2TabGen_q <= "010010000011100010110";
WHEN "1011011" => memoryC1_uid125_exp2TabGen_q <= "010010001001110100100";
WHEN "1011100" => memoryC1_uid125_exp2TabGen_q <= "010010010000000111111";
WHEN "1011101" => memoryC1_uid125_exp2TabGen_q <= "010010010110011110000";
WHEN "1011110" => memoryC1_uid125_exp2TabGen_q <= "010010011100110110010";
WHEN "1011111" => memoryC1_uid125_exp2TabGen_q <= "010010100011010000100";
WHEN "1100000" => memoryC1_uid125_exp2TabGen_q <= "010010101001101101011";
WHEN "1100001" => memoryC1_uid125_exp2TabGen_q <= "010010110000001100001";
WHEN "1100010" => memoryC1_uid125_exp2TabGen_q <= "010010110110101101001";
WHEN "1100011" => memoryC1_uid125_exp2TabGen_q <= "010010111101010000000";
WHEN "1100100" => memoryC1_uid125_exp2TabGen_q <= "010011000011110101111";
WHEN "1100101" => memoryC1_uid125_exp2TabGen_q <= "010011001010011110000";
WHEN "1100110" => memoryC1_uid125_exp2TabGen_q <= "010011010001001000001";
WHEN "1100111" => memoryC1_uid125_exp2TabGen_q <= "010011010111110100101";
WHEN "1101000" => memoryC1_uid125_exp2TabGen_q <= "010011011110100011101";
WHEN "1101001" => memoryC1_uid125_exp2TabGen_q <= "010011100101010100110";
WHEN "1101010" => memoryC1_uid125_exp2TabGen_q <= "010011101100001000000";
WHEN "1101011" => memoryC1_uid125_exp2TabGen_q <= "010011110010111110001";
WHEN "1101100" => memoryC1_uid125_exp2TabGen_q <= "010011111001110110101";
WHEN "1101101" => memoryC1_uid125_exp2TabGen_q <= "010100000000110001011";
WHEN "1101110" => memoryC1_uid125_exp2TabGen_q <= "010100000111101110000";
WHEN "1101111" => memoryC1_uid125_exp2TabGen_q <= "010100001110101101110";
WHEN "1110000" => memoryC1_uid125_exp2TabGen_q <= "010100010101101111101";
WHEN "1110001" => memoryC1_uid125_exp2TabGen_q <= "010100011100110011111";
WHEN "1110010" => memoryC1_uid125_exp2TabGen_q <= "010100100011111010110";
WHEN "1110011" => memoryC1_uid125_exp2TabGen_q <= "010100101011000100000";
WHEN "1110100" => memoryC1_uid125_exp2TabGen_q <= "010100110010001111111";
WHEN "1110101" => memoryC1_uid125_exp2TabGen_q <= "010100111001011110010";
WHEN "1110110" => memoryC1_uid125_exp2TabGen_q <= "010101000000101110111";
WHEN "1110111" => memoryC1_uid125_exp2TabGen_q <= "010101001000000010010";
WHEN "1111000" => memoryC1_uid125_exp2TabGen_q <= "010101001111011000001";
WHEN "1111001" => memoryC1_uid125_exp2TabGen_q <= "010101010110110000111";
WHEN "1111010" => memoryC1_uid125_exp2TabGen_q <= "010101011110001011010";
WHEN "1111011" => memoryC1_uid125_exp2TabGen_q <= "010101100101101001000";
WHEN "1111100" => memoryC1_uid125_exp2TabGen_q <= "010101101101001001010";
WHEN "1111101" => memoryC1_uid125_exp2TabGen_q <= "010101110100101011110";
WHEN "1111110" => memoryC1_uid125_exp2TabGen_q <= "010101111100010001000";
WHEN "1111111" => memoryC1_uid125_exp2TabGen_q <= "010110000011111001010";
WHEN OTHERS =>
memoryC1_uid125_exp2TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid133_exp2PolyEval(ADD,132)@9
sumAHighB_uid133_exp2PolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid125_exp2TabGen_q(20)) & memoryC1_uid125_exp2TabGen_q);
sumAHighB_uid133_exp2PolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid132_exp2PolyEval_b(11)) & highBBits_uid132_exp2PolyEval_b);
sumAHighB_uid133_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid133_exp2PolyEval_a) + SIGNED(sumAHighB_uid133_exp2PolyEval_b));
sumAHighB_uid133_exp2PolyEval_q <= sumAHighB_uid133_exp2PolyEval_o(21 downto 0);
--lowRangeB_uid131_exp2PolyEval(BITSELECT,130)@9
lowRangeB_uid131_exp2PolyEval_in <= prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_b(0 downto 0);
lowRangeB_uid131_exp2PolyEval_b <= lowRangeB_uid131_exp2PolyEval_in(0 downto 0);
--s1_uid131_uid134_exp2PolyEval(BITJOIN,133)@9
s1_uid131_uid134_exp2PolyEval_q <= sumAHighB_uid133_exp2PolyEval_q & lowRangeB_uid131_exp2PolyEval_b;
--reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1(REG,164)@9
reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1_q <= s1_uid131_uid134_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor(LOGICAL,354)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_b <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_a or ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg(REG,352)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena(REG,355)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd(LOGICAL,356)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0(REG,163)@5
reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q <= yPPolyEval_uid48_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg(DELAY,346)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q, xout => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt(COUNTER,348)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg(REG,349)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux(MUX,350)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem(DUALMEM,347)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 1,
numwords_a => 2,
width_b => 16,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid145_pT2_uid136_exp2PolyEval(MULT,144)@10
prodXY_uid145_pT2_uid136_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid145_pT2_uid136_exp2PolyEval_a),17)) * SIGNED(prodXY_uid145_pT2_uid136_exp2PolyEval_b);
prodXY_uid145_pT2_uid136_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid145_pT2_uid136_exp2PolyEval_a <= (others => '0');
prodXY_uid145_pT2_uid136_exp2PolyEval_b <= (others => '0');
prodXY_uid145_pT2_uid136_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid145_pT2_uid136_exp2PolyEval_a <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_q;
prodXY_uid145_pT2_uid136_exp2PolyEval_b <= reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1_q;
prodXY_uid145_pT2_uid136_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid145_pT2_uid136_exp2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid145_pT2_uid136_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid145_pT2_uid136_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid145_pT2_uid136_exp2PolyEval_q <= prodXY_uid145_pT2_uid136_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval(BITSELECT,145)@13
prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_in <= prodXY_uid145_pT2_uid136_exp2PolyEval_q;
prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_b <= prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_in(38 downto 15);
--highBBits_uid138_exp2PolyEval(BITSELECT,137)@13
highBBits_uid138_exp2PolyEval_in <= prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_b;
highBBits_uid138_exp2PolyEval_b <= highBBits_uid138_exp2PolyEval_in(23 downto 2);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor(LOGICAL,367)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_mem_top(CONSTANT,363)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_mem_top_q <= "0100";
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp(LOGICAL,364)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_mem_top_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_q <= "1" when ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_a = ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_b else "0";
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg(REG,365)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena(REG,368)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd(LOGICAL,369)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg(DELAY,357)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt(COUNTER,359)
-- every=1, low=0, high=4, step=1, init=1
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i = 3 THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i - 4;
ELSE
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i,3));
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg(REG,360)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux(MUX,361)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_s <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux: PROCESS (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_s, ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q, ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_s IS
WHEN "0" => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q;
WHEN "1" => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem(DUALMEM,358)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_aa <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ab <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_iq(6 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0(REG,165)@11
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid123_exp2TabGen(LOOKUP,122)@12
memoryC0_uid123_exp2TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid123_exp2TabGen_q <= "0100000000000000000000000100";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_q) IS
WHEN "0000000" => memoryC0_uid123_exp2TabGen_q <= "0100000000000000000000000100";
WHEN "0000001" => memoryC0_uid123_exp2TabGen_q <= "0100000001011000111101101111";
WHEN "0000010" => memoryC0_uid123_exp2TabGen_q <= "0100000010110010011010010100";
WHEN "0000011" => memoryC0_uid123_exp2TabGen_q <= "0100000100001100010101111110";
WHEN "0000100" => memoryC0_uid123_exp2TabGen_q <= "0100000101100110110000111001";
WHEN "0000101" => memoryC0_uid123_exp2TabGen_q <= "0100000111000001101011001111";
WHEN "0000110" => memoryC0_uid123_exp2TabGen_q <= "0100001000011101000101001010";
WHEN "0000111" => memoryC0_uid123_exp2TabGen_q <= "0100001001111000111110110111";
WHEN "0001000" => memoryC0_uid123_exp2TabGen_q <= "0100001011010101011000011111";
WHEN "0001001" => memoryC0_uid123_exp2TabGen_q <= "0100001100110010010010001111";
WHEN "0001010" => memoryC0_uid123_exp2TabGen_q <= "0100001110001111101100010001";
WHEN "0001011" => memoryC0_uid123_exp2TabGen_q <= "0100001111101101100110110000";
WHEN "0001100" => memoryC0_uid123_exp2TabGen_q <= "0100010001001100000001111000";
WHEN "0001101" => memoryC0_uid123_exp2TabGen_q <= "0100010010101010111101110100";
WHEN "0001110" => memoryC0_uid123_exp2TabGen_q <= "0100010100001010011010110000";
WHEN "0001111" => memoryC0_uid123_exp2TabGen_q <= "0100010101101010011000110110";
WHEN "0010000" => memoryC0_uid123_exp2TabGen_q <= "0100010111001010111000010011";
WHEN "0010001" => memoryC0_uid123_exp2TabGen_q <= "0100011000101011111001010010";
WHEN "0010010" => memoryC0_uid123_exp2TabGen_q <= "0100011010001101011011111111";
WHEN "0010011" => memoryC0_uid123_exp2TabGen_q <= "0100011011101111100000100101";
WHEN "0010100" => memoryC0_uid123_exp2TabGen_q <= "0100011101010010000111010000";
WHEN "0010101" => memoryC0_uid123_exp2TabGen_q <= "0100011110110101010000001101";
WHEN "0010110" => memoryC0_uid123_exp2TabGen_q <= "0100100000011000111011100110";
WHEN "0010111" => memoryC0_uid123_exp2TabGen_q <= "0100100001111101001001101000";
WHEN "0011000" => memoryC0_uid123_exp2TabGen_q <= "0100100011100001111010100000";
WHEN "0011001" => memoryC0_uid123_exp2TabGen_q <= "0100100101000111001110011000";
WHEN "0011010" => memoryC0_uid123_exp2TabGen_q <= "0100100110101101000101011110";
WHEN "0011011" => memoryC0_uid123_exp2TabGen_q <= "0100101000010011011111111101";
WHEN "0011100" => memoryC0_uid123_exp2TabGen_q <= "0100101001111010011110000001";
WHEN "0011101" => memoryC0_uid123_exp2TabGen_q <= "0100101011100001111111111000";
WHEN "0011110" => memoryC0_uid123_exp2TabGen_q <= "0100101101001010000101101110";
WHEN "0011111" => memoryC0_uid123_exp2TabGen_q <= "0100101110110010101111101110";
WHEN "0100000" => memoryC0_uid123_exp2TabGen_q <= "0100110000011011111110000111";
WHEN "0100001" => memoryC0_uid123_exp2TabGen_q <= "0100110010000101110001000011";
WHEN "0100010" => memoryC0_uid123_exp2TabGen_q <= "0100110011110000001000110001";
WHEN "0100011" => memoryC0_uid123_exp2TabGen_q <= "0100110101011011000101011100";
WHEN "0100100" => memoryC0_uid123_exp2TabGen_q <= "0100110111000110100111010010";
WHEN "0100101" => memoryC0_uid123_exp2TabGen_q <= "0100111000110010101110011111";
WHEN "0100110" => memoryC0_uid123_exp2TabGen_q <= "0100111010011111011011010001";
WHEN "0100111" => memoryC0_uid123_exp2TabGen_q <= "0100111100001100101101110101";
WHEN "0101000" => memoryC0_uid123_exp2TabGen_q <= "0100111101111010100110010111";
WHEN "0101001" => memoryC0_uid123_exp2TabGen_q <= "0100111111101001000101000101";
WHEN "0101010" => memoryC0_uid123_exp2TabGen_q <= "0101000001011000001010001101";
WHEN "0101011" => memoryC0_uid123_exp2TabGen_q <= "0101000011000111110101111010";
WHEN "0101100" => memoryC0_uid123_exp2TabGen_q <= "0101000100111000001000011100";
WHEN "0101101" => memoryC0_uid123_exp2TabGen_q <= "0101000110101001000001111111";
WHEN "0101110" => memoryC0_uid123_exp2TabGen_q <= "0101001000011010100010110010";
WHEN "0101111" => memoryC0_uid123_exp2TabGen_q <= "0101001010001100101011000000";
WHEN "0110000" => memoryC0_uid123_exp2TabGen_q <= "0101001011111111011010111001";
WHEN "0110001" => memoryC0_uid123_exp2TabGen_q <= "0101001101110010110010101011";
WHEN "0110010" => memoryC0_uid123_exp2TabGen_q <= "0101001111100110110010100010";
WHEN "0110011" => memoryC0_uid123_exp2TabGen_q <= "0101010001011011011010101101";
WHEN "0110100" => memoryC0_uid123_exp2TabGen_q <= "0101010011010000101011011010";
WHEN "0110101" => memoryC0_uid123_exp2TabGen_q <= "0101010101000110100100110111";
WHEN "0110110" => memoryC0_uid123_exp2TabGen_q <= "0101010110111101000111010010";
WHEN "0110111" => memoryC0_uid123_exp2TabGen_q <= "0101011000110100010010111001";
WHEN "0111000" => memoryC0_uid123_exp2TabGen_q <= "0101011010101100000111111011";
WHEN "0111001" => memoryC0_uid123_exp2TabGen_q <= "0101011100100100100110100111";
WHEN "0111010" => memoryC0_uid123_exp2TabGen_q <= "0101011110011101101111001001";
WHEN "0111011" => memoryC0_uid123_exp2TabGen_q <= "0101100000010111100001110010";
WHEN "0111100" => memoryC0_uid123_exp2TabGen_q <= "0101100010010001111110110000";
WHEN "0111101" => memoryC0_uid123_exp2TabGen_q <= "0101100100001101000110010001";
WHEN "0111110" => memoryC0_uid123_exp2TabGen_q <= "0101100110001000111000100101";
WHEN "0111111" => memoryC0_uid123_exp2TabGen_q <= "0101101000000101010101111001";
WHEN "1000000" => memoryC0_uid123_exp2TabGen_q <= "0101101010000010011110011110";
WHEN "1000001" => memoryC0_uid123_exp2TabGen_q <= "0101101100000000010010100001";
WHEN "1000010" => memoryC0_uid123_exp2TabGen_q <= "0101101101111110110010010011";
WHEN "1000011" => memoryC0_uid123_exp2TabGen_q <= "0101101111111101111110000010";
WHEN "1000100" => memoryC0_uid123_exp2TabGen_q <= "0101110001111101110101111110";
WHEN "1000101" => memoryC0_uid123_exp2TabGen_q <= "0101110011111110011010010110";
WHEN "1000110" => memoryC0_uid123_exp2TabGen_q <= "0101110101111111101011011010";
WHEN "1000111" => memoryC0_uid123_exp2TabGen_q <= "0101111000000001101001011000";
WHEN "1001000" => memoryC0_uid123_exp2TabGen_q <= "0101111010000100010100100001";
WHEN "1001001" => memoryC0_uid123_exp2TabGen_q <= "0101111100000111101101000100";
WHEN "1001010" => memoryC0_uid123_exp2TabGen_q <= "0101111110001011110011010010";
WHEN "1001011" => memoryC0_uid123_exp2TabGen_q <= "0110000000010000100111011001";
WHEN "1001100" => memoryC0_uid123_exp2TabGen_q <= "0110000010010110001001101010";
WHEN "1001101" => memoryC0_uid123_exp2TabGen_q <= "0110000100011100011010010110";
WHEN "1001110" => memoryC0_uid123_exp2TabGen_q <= "0110000110100011011001101011";
WHEN "1001111" => memoryC0_uid123_exp2TabGen_q <= "0110001000101011000111111010";
WHEN "1010000" => memoryC0_uid123_exp2TabGen_q <= "0110001010110011100101010101";
WHEN "1010001" => memoryC0_uid123_exp2TabGen_q <= "0110001100111100110010001010";
WHEN "1010010" => memoryC0_uid123_exp2TabGen_q <= "0110001111000110101110101010";
WHEN "1010011" => memoryC0_uid123_exp2TabGen_q <= "0110010001010001011011000111";
WHEN "1010100" => memoryC0_uid123_exp2TabGen_q <= "0110010011011100110111110000";
WHEN "1010101" => memoryC0_uid123_exp2TabGen_q <= "0110010101101001000100110111";
WHEN "1010110" => memoryC0_uid123_exp2TabGen_q <= "0110010111110110000010101100";
WHEN "1010111" => memoryC0_uid123_exp2TabGen_q <= "0110011010000011110001100000";
WHEN "1011000" => memoryC0_uid123_exp2TabGen_q <= "0110011100010010010001100101";
WHEN "1011001" => memoryC0_uid123_exp2TabGen_q <= "0110011110100001100011001011";
WHEN "1011010" => memoryC0_uid123_exp2TabGen_q <= "0110100000110001100110100011";
WHEN "1011011" => memoryC0_uid123_exp2TabGen_q <= "0110100011000010011011111111";
WHEN "1011100" => memoryC0_uid123_exp2TabGen_q <= "0110100101010100000011110001";
WHEN "1011101" => memoryC0_uid123_exp2TabGen_q <= "0110100111100110011110001001";
WHEN "1011110" => memoryC0_uid123_exp2TabGen_q <= "0110101001111001101011011001";
WHEN "1011111" => memoryC0_uid123_exp2TabGen_q <= "0110101100001101101011110100";
WHEN "1100000" => memoryC0_uid123_exp2TabGen_q <= "0110101110100010011111101010";
WHEN "1100001" => memoryC0_uid123_exp2TabGen_q <= "0110110000111000000111001110";
WHEN "1100010" => memoryC0_uid123_exp2TabGen_q <= "0110110011001110100010110010";
WHEN "1100011" => memoryC0_uid123_exp2TabGen_q <= "0110110101100101110010101000";
WHEN "1100100" => memoryC0_uid123_exp2TabGen_q <= "0110110111111101110111000001";
WHEN "1100101" => memoryC0_uid123_exp2TabGen_q <= "0110111010010110110000010000";
WHEN "1100110" => memoryC0_uid123_exp2TabGen_q <= "0110111100110000011110101000";
WHEN "1100111" => memoryC0_uid123_exp2TabGen_q <= "0110111111001011000010011011";
WHEN "1101000" => memoryC0_uid123_exp2TabGen_q <= "0111000001100110011011111011";
WHEN "1101001" => memoryC0_uid123_exp2TabGen_q <= "0111000100000010101011011100";
WHEN "1101010" => memoryC0_uid123_exp2TabGen_q <= "0111000110011111110001010000";
WHEN "1101011" => memoryC0_uid123_exp2TabGen_q <= "0111001000111101101101101001";
WHEN "1101100" => memoryC0_uid123_exp2TabGen_q <= "0111001011011100100000111011";
WHEN "1101101" => memoryC0_uid123_exp2TabGen_q <= "0111001101111100001011011001";
WHEN "1101110" => memoryC0_uid123_exp2TabGen_q <= "0111010000011100101101010111";
WHEN "1101111" => memoryC0_uid123_exp2TabGen_q <= "0111010010111110000111000110";
WHEN "1110000" => memoryC0_uid123_exp2TabGen_q <= "0111010101100000011000111011";
WHEN "1110001" => memoryC0_uid123_exp2TabGen_q <= "0111011000000011100011001010";
WHEN "1110010" => memoryC0_uid123_exp2TabGen_q <= "0111011010100111100110000101";
WHEN "1110011" => memoryC0_uid123_exp2TabGen_q <= "0111011101001100100010000001";
WHEN "1110100" => memoryC0_uid123_exp2TabGen_q <= "0111011111110010010111010001";
WHEN "1110101" => memoryC0_uid123_exp2TabGen_q <= "0111100010011001000110001001";
WHEN "1110110" => memoryC0_uid123_exp2TabGen_q <= "0111100101000000101110111110";
WHEN "1110111" => memoryC0_uid123_exp2TabGen_q <= "0111100111101001010010000011";
WHEN "1111000" => memoryC0_uid123_exp2TabGen_q <= "0111101010010010101111101101";
WHEN "1111001" => memoryC0_uid123_exp2TabGen_q <= "0111101100111101001000001111";
WHEN "1111010" => memoryC0_uid123_exp2TabGen_q <= "0111101111101000011100000000";
WHEN "1111011" => memoryC0_uid123_exp2TabGen_q <= "0111110010010100101011010010";
WHEN "1111100" => memoryC0_uid123_exp2TabGen_q <= "0111110101000001110110011011";
WHEN "1111101" => memoryC0_uid123_exp2TabGen_q <= "0111110111101111111101110000";
WHEN "1111110" => memoryC0_uid123_exp2TabGen_q <= "0111111010011111000001100101";
WHEN "1111111" => memoryC0_uid123_exp2TabGen_q <= "0111111101001111000010001111";
WHEN OTHERS =>
memoryC0_uid123_exp2TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid139_exp2PolyEval(ADD,138)@13
sumAHighB_uid139_exp2PolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => memoryC0_uid123_exp2TabGen_q(27)) & memoryC0_uid123_exp2TabGen_q);
sumAHighB_uid139_exp2PolyEval_b <= STD_LOGIC_VECTOR((28 downto 22 => highBBits_uid138_exp2PolyEval_b(21)) & highBBits_uid138_exp2PolyEval_b);
sumAHighB_uid139_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid139_exp2PolyEval_a) + SIGNED(sumAHighB_uid139_exp2PolyEval_b));
sumAHighB_uid139_exp2PolyEval_q <= sumAHighB_uid139_exp2PolyEval_o(28 downto 0);
--lowRangeB_uid137_exp2PolyEval(BITSELECT,136)@13
lowRangeB_uid137_exp2PolyEval_in <= prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_b(1 downto 0);
lowRangeB_uid137_exp2PolyEval_b <= lowRangeB_uid137_exp2PolyEval_in(1 downto 0);
--s2_uid137_uid140_exp2PolyEval(BITJOIN,139)@13
s2_uid137_uid140_exp2PolyEval_q <= sumAHighB_uid139_exp2PolyEval_q & lowRangeB_uid137_exp2PolyEval_b;
--peOR_uid50_fpExp2Test(BITSELECT,49)@13
peOR_uid50_fpExp2Test_in <= s2_uid137_uid140_exp2PolyEval_q(28 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(28 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@13
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(22 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(22 downto 0);
--ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b(DELAY,235)@7
ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 6 )
PORT MAP ( xin => excREnc_uid70_fpExp2Test_q, xout => ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid74_fpExp2Test(MUX,73)@13
fracRPostExc_uid74_fpExp2Test_s <= ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, fracR_uid52_fpExp2Test_b, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= fracR_uid52_fpExp2Test_b;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@13
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@13
q <= RExp2_uid79_fpExp2Test_q;
end normal;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/hcc_divrnd.vhd | 10 | 5592 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVRND.VHD ***
--*** ***
--*** Function: Output Stage, Rounding ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 2 ***
--***************************************************
ENTITY hcc_divrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divrnd;
ARCHITECTURE rtl OF hcc_divrnd IS
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal satinff, zipinff, naninff : STD_LOGIC;
signal overflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= "00";
satinff <= '0';
zipinff <= '0';
naninff <= '0';
overflowbitff <= '0';
FOR k IN 1 TO 52 LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff(1) <= signin;
signff(2) <= signff(1);
satinff <= satin;
zipinff <= zipin;
naninff <= nanin;
overflowbitff <= manoverflow(53);
roundmantissaff <= mantissain(53 DOWNTO 2) + (zerovec & mantissain(1));
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(13 DOWNTO 1) <= exponentin(13 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(13 DOWNTO 1) +
(zerovec(12 DOWNTO 1) & overflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissain(1);
gmoa: FOR k IN 2 TO 53 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissain(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentnode(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentnode(k);
END GENERATE;
-- 12/05/09 - make sure exponentnode = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentnode(12)) AND NOT(exponentnode(13))) OR
satinff OR (exponentnode(12) AND NOT(exponentnode(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentnode(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentnode(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipinff OR exponentnode(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= naninff;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR naninff;
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/SinPiDPStratixVf400.vhd | 10 | 665970 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Debug Version 12.0
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from SinPiDPStratixVf400
-- VHDL created on Wed Sep 05 17:55:57 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
USE work.SinPiDPStratixVf400_safe_path.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240
entity SinPiDPStratixVf400 is
port (
xIn_v : in std_logic_vector(0 downto 0);
xIn_c : in std_logic_vector(7 downto 0);
xIn_0 : in std_logic_vector(63 downto 0);
xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic;
bus_clk : in std_logic;
h_areset : in std_logic
);
end;
architecture normal of SinPiDPStratixVf400 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (51 downto 0);
signal cstAllZWE_uid11_fpSinPiTest_q : std_logic_vector (10 downto 0);
signal cstBias_uid12_fpSinPiTest_q : std_logic_vector (10 downto 0);
signal cstBiasPwF_uid13_fpSinPiTest_q : std_logic_vector (10 downto 0);
signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal biasM1_uid27_fpSinPiTest_q : std_logic_vector (10 downto 0);
signal biasMwShift_uid29_fpSinPiTest_q : std_logic_vector (10 downto 0);
signal shiftBias_uid32_fpSinPiTest_q : std_logic_vector (10 downto 0);
signal cst01pWShift_uid34_fpSinPiTest_q : std_logic_vector (27 downto 0);
signal ozz_uid41_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal cOne_uid44_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal oneMinusY_uid45_fpSinPiTest_a : std_logic_vector(81 downto 0);
signal oneMinusY_uid45_fpSinPiTest_b : std_logic_vector(81 downto 0);
signal oneMinusY_uid45_fpSinPiTest_o : std_logic_vector (81 downto 0);
signal oneMinusY_uid45_fpSinPiTest_q : std_logic_vector (81 downto 0);
signal cmpYToOneMinusY_uid46_fpSinPiTest_a : std_logic_vector(84 downto 0);
signal cmpYToOneMinusY_uid46_fpSinPiTest_b : std_logic_vector(84 downto 0);
signal cmpYToOneMinusY_uid46_fpSinPiTest_o : std_logic_vector (84 downto 0);
signal cmpYToOneMinusY_uid46_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid46_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal piwFP2_uid67_fpSinPiTest_q : std_logic_vector (53 downto 0);
signal or_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal or_uid88_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal or_uid88_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal or_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid89_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid89_fpSinPiTest_q : std_logic_vector (51 downto 0);
signal oneFracRPostExc2_uid90_fpSinPiTest_q : std_logic_vector (51 downto 0);
signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (10 downto 0);
signal InvXIsInt_uid100_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid100_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal mO_uid148_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal memoryC3_uid229_sinPiZTableGenerator_q : std_logic_vector(34 downto 0);
signal memoryC4_uid230_sinPiZTableGenerator_q : std_logic_vector(25 downto 0);
signal memoryC5_uid231_sinPiZTableGenerator_q : std_logic_vector(16 downto 0);
signal rndBit_uid246_sinPiZPolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid258_sinPiZPolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_q : std_logic_vector (33 downto 0);
signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_a : std_logic_vector (25 downto 0);
signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (27 downto 0);
signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid271_pT3_uid245_sinPiZPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid271_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid271_pT3_uid245_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid271_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid288_pT4_uid251_sinPiZPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid288_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid288_pT4_uid251_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid288_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid303_pT5_uid257_sinPiZPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid303_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid303_pT5_uid257_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid303_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_zero_36_q : std_logic_vector (26 downto 0);
type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type;
type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type;
type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type;
type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type;
type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type;
type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type;
type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type;
signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type;
type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type;
type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type;
type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type;
type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type;
type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type;
type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type;
signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type;
type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type;
type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type;
type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type;
type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type;
type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type;
type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type;
signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0);
signal reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q : std_logic_vector (80 downto 0);
signal reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q : std_logic_vector (80 downto 0);
signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q : std_logic_vector (79 downto 0);
signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q : std_logic_vector (79 downto 0);
signal reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q : std_logic_vector (0 downto 0);
signal reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q : std_logic_vector (79 downto 0);
signal reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q : std_logic_vector (79 downto 0);
signal reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q : std_logic_vector (78 downto 0);
signal reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q : std_logic_vector (78 downto 0);
signal reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q : std_logic_vector (78 downto 0);
signal reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q : std_logic_vector (78 downto 0);
signal reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0);
signal reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q : std_logic_vector (25 downto 0);
signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0);
signal reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0);
signal reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0);
signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0);
signal reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0);
signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q : std_logic_vector (26 downto 0);
signal reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q : std_logic_vector (6 downto 0);
signal reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q : std_logic_vector (78 downto 0);
signal ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q : std_logic_vector (78 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q : std_logic_vector (78 downto 0);
signal ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q : std_logic_vector (14 downto 0);
signal ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (31 downto 0);
signal ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (15 downto 0);
signal ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (15 downto 0);
signal ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q : std_logic_vector (0 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0);
signal ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0);
signal ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0);
signal ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0);
signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0);
signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0);
signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0);
signal ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q : std_logic_vector (79 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0);
signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic;
signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic;
signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0);
signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic;
signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q : std_logic_vector (52 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ir : std_logic_vector (52 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ir : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q : std_logic_vector (10 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ir : std_logic_vector (10 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q : std_logic_vector (2 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0);
signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q : std_logic_vector (78 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q : std_logic_vector (2 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 : std_logic;
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ir : std_logic_vector (52 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq : std_logic;
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q : std_logic_vector (25 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ir : std_logic_vector (25 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0);
signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal yIsZero_uid40_fpSinPiTest_a : std_logic_vector(79 downto 0);
signal yIsZero_uid40_fpSinPiTest_b : std_logic_vector(79 downto 0);
signal yIsZero_uid40_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (26 downto 0);
signal z_uid49_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid49_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal expHardCase_uid57_fpSinPiTest_a : std_logic_vector(11 downto 0);
signal expHardCase_uid57_fpSinPiTest_b : std_logic_vector(11 downto 0);
signal expHardCase_uid57_fpSinPiTest_o : std_logic_vector (11 downto 0);
signal expHardCase_uid57_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal expXP1_uid58_fpSinPiTest_a : std_logic_vector(11 downto 0);
signal expXP1_uid58_fpSinPiTest_b : std_logic_vector(11 downto 0);
signal expXP1_uid58_fpSinPiTest_o : std_logic_vector (11 downto 0);
signal expXP1_uid58_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal rndExpUpdate_uid75_uid76_fpSinPiTest_q : std_logic_vector (53 downto 0);
signal expFracComp_uid77_fpSinPiTest_a : std_logic_vector(64 downto 0);
signal expFracComp_uid77_fpSinPiTest_b : std_logic_vector(64 downto 0);
signal expFracComp_uid77_fpSinPiTest_o : std_logic_vector (64 downto 0);
signal expFracComp_uid77_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal fracRPostExc_uid91_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid91_fpSinPiTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid98_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid98_fpSinPiTest_q : std_logic_vector (10 downto 0);
signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal memoryC0_uid226_sinPiZTableGenerator_q : std_logic_vector(57 downto 0);
signal memoryC1_uid227_sinPiZTableGenerator_q : std_logic_vector(49 downto 0);
signal memoryC2_uid228_sinPiZTableGenerator_q : std_logic_vector(42 downto 0);
signal sumAHighB_uid242_sinPiZPolyEval_a : std_logic_vector(35 downto 0);
signal sumAHighB_uid242_sinPiZPolyEval_b : std_logic_vector(35 downto 0);
signal sumAHighB_uid242_sinPiZPolyEval_o : std_logic_vector (35 downto 0);
signal sumAHighB_uid242_sinPiZPolyEval_q : std_logic_vector (35 downto 0);
signal ts3_uid248_sinPiZPolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid248_sinPiZPolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid248_sinPiZPolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid248_sinPiZPolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid254_sinPiZPolyEval_a : std_logic_vector(52 downto 0);
signal ts4_uid254_sinPiZPolyEval_b : std_logic_vector(52 downto 0);
signal ts4_uid254_sinPiZPolyEval_o : std_logic_vector (52 downto 0);
signal ts4_uid254_sinPiZPolyEval_q : std_logic_vector (52 downto 0);
signal ts5_uid260_sinPiZPolyEval_a : std_logic_vector(61 downto 0);
signal ts5_uid260_sinPiZPolyEval_b : std_logic_vector(61 downto 0);
signal ts5_uid260_sinPiZPolyEval_o : std_logic_vector (61 downto 0);
signal ts5_uid260_sinPiZPolyEval_q : std_logic_vector (61 downto 0);
signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (54 downto 0);
signal join_uid42_fpSinPiTest_q : std_logic_vector (79 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (10 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (51 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (51 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (63 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsMax_uid16_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid16_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid17_fpSinPiTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid17_fpSinPiTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid15_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid15_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid26_fpSinPiTest_a : std_logic_vector(13 downto 0);
signal xIntExp_uid26_fpSinPiTest_b : std_logic_vector(13 downto 0);
signal xIntExp_uid26_fpSinPiTest_o : std_logic_vector (13 downto 0);
signal xIntExp_uid26_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid26_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid28_fpSinPiTest_a : std_logic_vector(13 downto 0);
signal xFrac_uid28_fpSinPiTest_b : std_logic_vector(13 downto 0);
signal xFrac_uid28_fpSinPiTest_o : std_logic_vector (13 downto 0);
signal xFrac_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid30_fpSinPiTest_a : std_logic_vector(13 downto 0);
signal sinXIsX_uid30_fpSinPiTest_b : std_logic_vector(13 downto 0);
signal sinXIsX_uid30_fpSinPiTest_o : std_logic_vector (13 downto 0);
signal sinXIsX_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid33_fpSinPiTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid33_fpSinPiTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid33_fpSinPiTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid33_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal oMyBottom_uid47_fpSinPiTest_in : std_logic_vector (78 downto 0);
signal oMyBottom_uid47_fpSinPiTest_b : std_logic_vector (78 downto 0);
signal vCount_uid155_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid155_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid155_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal vCount_uid147_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(63 downto 0);
signal vCount_uid147_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(63 downto 0);
signal vCount_uid147_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal vCount_uid167_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid167_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid167_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid161_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid161_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid161_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal cStage_uid150_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0);
signal cIncludingRoundingBit_uid247_sinPiZPolyEval_q : std_logic_vector (44 downto 0);
signal cIncludingRoundingBit_uid253_sinPiZPolyEval_q : std_logic_vector (51 downto 0);
signal cIncludingRoundingBit_uid259_sinPiZPolyEval_q : std_logic_vector (60 downto 0);
signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in : std_logic_vector (53 downto 0);
signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0);
signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (29 downto 0);
signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0);
signal yIsZero_uid43_fpSinPiTest_a : std_logic_vector(79 downto 0);
signal yIsZero_uid43_fpSinPiTest_b : std_logic_vector(79 downto 0);
signal yIsZero_uid43_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid87_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal InvFracXIsZero_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid64_fpSinPiTest_in : std_logic_vector (71 downto 0);
signal zPPolyEval_uid64_fpSinPiTest_b : std_logic_vector (44 downto 0);
signal InvSinXIsX_uid80_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid80_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid99_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid99_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid101_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid101_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid101_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid101_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0);
signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal s2_uid240_uid243_sinPiZPolyEval_q : std_logic_vector (36 downto 0);
signal add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (55 downto 0);
signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (79 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a : std_logic_vector(3 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b : std_logic_vector(3 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal R_uid105_fpSinPiTest_q : std_logic_vector (63 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a : std_logic_vector(2 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b : std_logic_vector(2 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a : std_logic_vector(2 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b : std_logic_vector(2 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid244_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT3_uid244_sinPiZPolyEval_b : std_logic_vector (34 downto 0);
signal yT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT4_uid250_sinPiZPolyEval_b : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0);
signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal zAddr_uid63_fpSinPiTest_in : std_logic_vector (78 downto 0);
signal zAddr_uid63_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (78 downto 0);
signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0);
signal vStage_uid149_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (14 downto 0);
signal vStage_uid149_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (14 downto 0);
signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (46 downto 0);
signal expHardCaseR_uid60_fpSinPiTest_in : std_logic_vector (10 downto 0);
signal expHardCaseR_uid60_fpSinPiTest_b : std_logic_vector (10 downto 0);
signal expXP1R_uid59_fpSinPiTest_in : std_logic_vector (10 downto 0);
signal expXP1R_uid59_fpSinPiTest_b : std_logic_vector (10 downto 0);
signal fracRComp_uid78_fpSinPiTest_in : std_logic_vector (52 downto 0);
signal fracRComp_uid78_fpSinPiTest_b : std_logic_vector (51 downto 0);
signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (63 downto 0);
signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (10 downto 0);
signal intXParity_uid38_fpSinPiTest_in : std_logic_vector (80 downto 0);
signal intXParity_uid38_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid39_fpSinPiTest_in : std_logic_vector (79 downto 0);
signal y_uid39_fpSinPiTest_b : std_logic_vector (79 downto 0);
signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (77 downto 0);
signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (77 downto 0);
signal s3_uid249_sinPiZPolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid249_sinPiZPolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid255_sinPiZPolyEval_in : std_logic_vector (52 downto 0);
signal s4_uid255_sinPiZPolyEval_b : std_logic_vector (51 downto 0);
signal s5_uid261_sinPiZPolyEval_in : std_logic_vector (61 downto 0);
signal s5_uid261_sinPiZPolyEval_b : std_logic_vector (60 downto 0);
signal oFracX_uid31_uid31_fpSinPiTest_q : std_logic_vector (52 downto 0);
signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid36_fpSinPiTest_in : std_logic_vector (6 downto 0);
signal fxpShifterBits_uid36_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal lowRangeB_uid234_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid234_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid235_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal highBBits_uid235_sinPiZPolyEval_b : std_logic_vector (16 downto 0);
signal lowRangeB_uid240_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid240_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid241_sinPiZPolyEval_in : std_logic_vector (28 downto 0);
signal highBBits_uid241_sinPiZPolyEval_b : std_logic_vector (27 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0);
signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (29 downto 0);
signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0);
signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0);
signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal normBit_uid70_fpSinPiTest_in : std_logic_vector (106 downto 0);
signal normBit_uid70_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid71_fpSinPiTest_in : std_logic_vector (105 downto 0);
signal highRes_uid71_fpSinPiTest_b : std_logic_vector (52 downto 0);
signal lowRes_uid72_fpSinPiTest_in : std_logic_vector (104 downto 0);
signal lowRes_uid72_fpSinPiTest_b : std_logic_vector (52 downto 0);
signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid174_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid174_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (70 downto 0);
signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (70 downto 0);
signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (54 downto 0);
signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (54 downto 0);
signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid232_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid238_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT2_uid238_sinPiZPolyEval_b : std_logic_vector (25 downto 0);
signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid156_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal vStage_uid156_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid162_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid162_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid168_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid168_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0);
signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (9 downto 0);
signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (9 downto 0);
signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0);
signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal R_uid285_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (54 downto 0);
signal R_uid285_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (36 downto 0);
signal R_uid300_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (71 downto 0);
signal R_uid300_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (45 downto 0);
signal R_uid315_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (78 downto 0);
signal R_uid315_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0);
signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0);
signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0);
signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (7 downto 0);
signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (7 downto 0);
signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (15 downto 0);
signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expP_uid61_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid61_fpSinPiTest_q : std_logic_vector (10 downto 0);
signal yBottom_uid48_fpSinPiTest_in : std_logic_vector (78 downto 0);
signal yBottom_uid48_fpSinPiTest_b : std_logic_vector (78 downto 0);
signal leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (51 downto 0);
signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0);
signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid66_fpSinPiTest_in : std_logic_vector (58 downto 0);
signal fxpSinRes_uid66_fpSinPiTest_b : std_logic_vector (53 downto 0);
signal extendedFracX_uid35_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal sumAHighB_uid236_sinPiZPolyEval_a : std_logic_vector(26 downto 0);
signal sumAHighB_uid236_sinPiZPolyEval_b : std_logic_vector(26 downto 0);
signal sumAHighB_uid236_sinPiZPolyEval_o : std_logic_vector (26 downto 0);
signal sumAHighB_uid236_sinPiZPolyEval_q : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0);
signal fracRCompPreRnd_uid73_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid73_fpSinPiTest_q : std_logic_vector (52 downto 0);
signal join_uid97_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid173_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid173_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid173_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal signR_uid104_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid104_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid104_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (10 downto 0);
signal pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal xIsInt_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal multRightOp_uid68_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid68_fpSinPiTest_q : std_logic_vector (53 downto 0);
signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (48 downto 0);
signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (16 downto 0);
signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (16 downto 0);
signal s1_uid234_uid237_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0);
signal expFracPreRnd_uid74_uid74_fpSinPiTest_q : std_logic_vector (63 downto 0);
signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid180_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid180_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (17 downto 0);
signal alignedZLow_uid53_fpSinPiTest_in : std_logic_vector (78 downto 0);
signal alignedZLow_uid53_fpSinPiTest_b : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_b_1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_b_1_b : std_logic_vector (26 downto 0);
signal leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0);
signal vCount_uid179_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid179_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid179_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (74 downto 0);
signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (72 downto 0);
signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (72 downto 0);
signal pHardCase_uid54_fpSinPiTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0);
signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0);
signal p_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid55_fpSinPiTest_q : std_logic_vector (52 downto 0);
signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (72 downto 0);
signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (72 downto 0);
signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (64 downto 0);
signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (56 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0);
signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0);
signal vCount_uid185_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid185_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid185_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal r_uid186_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (6 downto 0);
signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (78 downto 0);
signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (78 downto 0);
signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (74 downto 0);
signal leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (79 downto 0);
signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (79 downto 0);
signal leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0);
begin
--ld_xIn_v_to_xOut_v_notEnable(LOGICAL,909)
ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q;
ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a;
--ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor(LOGICAL,1028)
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q;
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q <= not (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a or ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b);
--ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top(CONSTANT,1024)
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q <= "0100100";
--ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp(LOGICAL,1025)
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q;
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q);
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q <= "1" when ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a = ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b else "0";
--ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg(REG,1026)
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q;
END IF;
END PROCESS;
--ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena(REG,1029)
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q = "1") THEN
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd(LOGICAL,1030)
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q;
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b <= VCC_q;
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a and ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b;
--LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest(BITSELECT,134)@0
LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in(74 downto 0);
--leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest(CONSTANT,133)
leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q <= "000000";
--leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest(BITJOIN,135)@0
leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q;
--LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest(BITSELECT,131)@0
LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(76 downto 0);
LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in(76 downto 0);
--leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest(CONSTANT,130)
leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q <= "0000";
--leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest(BITJOIN,132)@0
leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q;
--LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest(BITSELECT,128)@0
LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(78 downto 0);
LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in(78 downto 0);
--leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest(CONSTANT,127)
leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q <= "00";
--leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest(BITJOIN,129)@0
leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q;
--LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest(BITSELECT,123)@0
LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(56 downto 0);
LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in(56 downto 0);
--leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest(BITJOIN,124)@0
leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q;
--LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest(BITSELECT,120)@0
LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(64 downto 0);
LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in(64 downto 0);
--leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest(CONSTANT,119)
leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest(BITJOIN,121)@0
leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q;
--LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest(BITSELECT,117)@0
LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(72 downto 0);
LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in(72 downto 0);
--leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest(CONSTANT,116)
leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest(BITJOIN,118)@0
leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q;
--leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--X16dto0_uid112_fixedPointX_uid37_fpSinPiTest(BITSELECT,111)@0
X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(16 downto 0);
X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in(16 downto 0);
--leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest(CONSTANT,110)
leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest(BITJOIN,112)@0
leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q;
--X48dto0_uid109_fixedPointX_uid37_fpSinPiTest(BITSELECT,108)@0
X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(48 downto 0);
X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in(48 downto 0);
--leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest(CONSTANT,107)
leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest(BITJOIN,109)@0
leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q;
--cst01pWShift_uid34_fpSinPiTest(CONSTANT,33)
cst01pWShift_uid34_fpSinPiTest_q <= "0000000000000000000000000000";
--xIn(PORTIN,3)@0
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= xIn_0(51 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(51 downto 0);
--oFracX_uid31_uid31_fpSinPiTest(BITJOIN,30)@0
oFracX_uid31_uid31_fpSinPiTest_q <= VCC_q & fracX_uid7_fpSinPiTest_b;
--extendedFracX_uid35_fpSinPiTest(BITJOIN,34)@0
extendedFracX_uid35_fpSinPiTest_q <= cst01pWShift_uid34_fpSinPiTest_q & oFracX_uid31_uid31_fpSinPiTest_q;
--shiftBias_uid32_fpSinPiTest(CONSTANT,31)
shiftBias_uid32_fpSinPiTest_q <= "01111100011";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= xIn_0(62 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(62 downto 52);
--shiftValue_uid33_fpSinPiTest(SUB,32)@0
shiftValue_uid33_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid33_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid32_fpSinPiTest_q);
shiftValue_uid33_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid33_fpSinPiTest_a) - UNSIGNED(shiftValue_uid33_fpSinPiTest_b));
shiftValue_uid33_fpSinPiTest_q <= shiftValue_uid33_fpSinPiTest_o(11 downto 0);
--fxpShifterBits_uid36_fpSinPiTest(BITSELECT,35)@0
fxpShifterBits_uid36_fpSinPiTest_in <= shiftValue_uid33_fpSinPiTest_q(6 downto 0);
fxpShifterBits_uid36_fpSinPiTest_b <= fxpShifterBits_uid36_fpSinPiTest_in(6 downto 0);
--leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest(BITSELECT,114)@0
leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b;
leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in(6 downto 5);
--leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest(MUX,115)@0
leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b;
leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s, extendedFracX_uid35_fpSinPiTest_q, leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= extendedFracX_uid35_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest(BITSELECT,125)@0
leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(4 downto 0);
leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in(4 downto 3);
--leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest(MUX,126)@0
leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b;
leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q;
WHEN "01" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest(BITSELECT,136)@0
leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(2 downto 0);
leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in(2 downto 1);
--leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest(MUX,137)@0
leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b;
leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q;
WHEN "01" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest(BITSELECT,139)@0
LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q(79 downto 0);
LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in(79 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest(BITJOIN,140)@0
leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b & GND_q;
--reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3(REG,357)@0
reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q;
END IF;
END PROCESS;
--reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2(REG,358)@0
reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q;
END IF;
END PROCESS;
--leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest(BITSELECT,141)@0
leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(0 downto 0);
leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b(DELAY,581)@0
ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q, clk => clk, aclr => areset );
--leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest(MUX,142)@1
leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q;
leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s, reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q, reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q)
BEGIN
CASE leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s IS
WHEN "0" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q;
WHEN "1" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q;
WHEN OTHERS => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid38_fpSinPiTest(BITSELECT,37)@1
intXParity_uid38_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q;
intXParity_uid38_fpSinPiTest_b <= intXParity_uid38_fpSinPiTest_in(80 downto 80);
--ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c(DELAY,536)@1
ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid38_fpSinPiTest_b, xout => ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q, clk => clk, aclr => areset );
--biasM1_uid27_fpSinPiTest(CONSTANT,26)
biasM1_uid27_fpSinPiTest_q <= "01111111110";
--xFrac_uid28_fpSinPiTest(COMPARE,27)@0
xFrac_uid28_fpSinPiTest_cin <= GND_q;
xFrac_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid27_fpSinPiTest_q) & '0';
xFrac_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid28_fpSinPiTest_cin(0);
xFrac_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid28_fpSinPiTest_a) - UNSIGNED(xFrac_uid28_fpSinPiTest_b));
xFrac_uid28_fpSinPiTest_n(0) <= not xFrac_uid28_fpSinPiTest_o(13);
--ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a(DELAY,532)@0
ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => xFrac_uid28_fpSinPiTest_n, xout => ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q, clk => clk, aclr => areset );
--InvXFrac_uid99_fpSinPiTest(LOGICAL,98)@3
InvXFrac_uid99_fpSinPiTest_a <= ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q;
InvXFrac_uid99_fpSinPiTest_q <= not InvXFrac_uid99_fpSinPiTest_a;
--biasMwShift_uid29_fpSinPiTest(CONSTANT,28)
biasMwShift_uid29_fpSinPiTest_q <= "01111100100";
--sinXIsX_uid30_fpSinPiTest(COMPARE,29)@0
sinXIsX_uid30_fpSinPiTest_cin <= GND_q;
sinXIsX_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid29_fpSinPiTest_q) & sinXIsX_uid30_fpSinPiTest_cin(0);
sinXIsX_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid30_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid30_fpSinPiTest_b));
sinXIsX_uid30_fpSinPiTest_c(0) <= sinXIsX_uid30_fpSinPiTest_o(13);
--ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a(DELAY,502)@0
ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q, clk => clk, aclr => areset );
--InvSinXIsX_uid80_fpSinPiTest(LOGICAL,79)@2
InvSinXIsX_uid80_fpSinPiTest_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q;
InvSinXIsX_uid80_fpSinPiTest_q <= not InvSinXIsX_uid80_fpSinPiTest_a;
--y_uid39_fpSinPiTest(BITSELECT,38)@1
y_uid39_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q(79 downto 0);
y_uid39_fpSinPiTest_b <= y_uid39_fpSinPiTest_in(79 downto 0);
--reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0(REG,360)@1
reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b;
END IF;
END PROCESS;
--yIsZero_uid40_fpSinPiTest(LOGICAL,39)@2
yIsZero_uid40_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q;
yIsZero_uid40_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid40_fpSinPiTest_q <= "1" when yIsZero_uid40_fpSinPiTest_a = yIsZero_uid40_fpSinPiTest_b else "0";
--And2YIsZeroInvSinXIsX_uid81_fpSinPiTest(LOGICAL,80)@2
And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a <= yIsZero_uid40_fpSinPiTest_q;
And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b <= InvSinXIsX_uid80_fpSinPiTest_q;
And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a and And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b;
--cstBiasPwF_uid13_fpSinPiTest(CONSTANT,12)
cstBiasPwF_uid13_fpSinPiTest_q <= "10000110011";
--xIntExp_uid26_fpSinPiTest(COMPARE,25)@0
xIntExp_uid26_fpSinPiTest_cin <= GND_q;
xIntExp_uid26_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid13_fpSinPiTest_q) & '0';
xIntExp_uid26_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid26_fpSinPiTest_cin(0);
xIntExp_uid26_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid26_fpSinPiTest_a) - UNSIGNED(xIntExp_uid26_fpSinPiTest_b));
xIntExp_uid26_fpSinPiTest_c(0) <= xIntExp_uid26_fpSinPiTest_o(13);
--ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a(DELAY,505)@0
ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xIntExp_uid26_fpSinPiTest_c, xout => ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q, clk => clk, aclr => areset );
--Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest(LOGICAL,81)@2
Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q;
Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q;
Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a or Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid17_fpSinPiTest(LOGICAL,16)@0
fracXIsZero_uid17_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid17_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid17_fpSinPiTest_q <= "1" when fracXIsZero_uid17_fpSinPiTest_a = fracXIsZero_uid17_fpSinPiTest_b else "0";
--ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a(DELAY,442)@0
ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid17_fpSinPiTest_q, xout => ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q, clk => clk, aclr => areset );
--InvFracXIsZero_uid19_fpSinPiTest(LOGICAL,18)@1
InvFracXIsZero_uid19_fpSinPiTest_a <= ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q;
InvFracXIsZero_uid19_fpSinPiTest_q <= not InvFracXIsZero_uid19_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111111";
--expXIsMax_uid16_fpSinPiTest(LOGICAL,15)@0
expXIsMax_uid16_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid16_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid16_fpSinPiTest_q <= "1" when expXIsMax_uid16_fpSinPiTest_a = expXIsMax_uid16_fpSinPiTest_b else "0";
--ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a(DELAY,443)@0
ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid16_fpSinPiTest_q, xout => ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q, clk => clk, aclr => areset );
--And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest(LOGICAL,19)@1
And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a <= ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q;
And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b <= InvFracXIsZero_uid19_fpSinPiTest_q;
And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b;
--InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest(LOGICAL,20)@1
InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q;
InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a;
--And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a <= expXIsMax_uid16_fpSinPiTest_q;
And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b <= fracXIsZero_uid17_fpSinPiTest_q;
And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a and And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b;
--InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q;
InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a;
--cstAllZWE_uid11_fpSinPiTest(CONSTANT,10)
cstAllZWE_uid11_fpSinPiTest_q <= "00000000000";
--expXIsZero_uid15_fpSinPiTest(LOGICAL,14)@0
expXIsZero_uid15_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid15_fpSinPiTest_b <= cstAllZWE_uid11_fpSinPiTest_q;
expXIsZero_uid15_fpSinPiTest_q <= "1" when expXIsZero_uid15_fpSinPiTest_a = expXIsZero_uid15_fpSinPiTest_b else "0";
--InvExpXIsZero_uid23_fpSinPiTest(LOGICAL,22)@0
InvExpXIsZero_uid23_fpSinPiTest_a <= expXIsZero_uid15_fpSinPiTest_q;
InvExpXIsZero_uid23_fpSinPiTest_q <= not InvExpXIsZero_uid23_fpSinPiTest_a;
--And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a <= InvExpXIsZero_uid23_fpSinPiTest_q;
And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q;
And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b;
--ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a(DELAY,450)@0
ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q, xout => ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q, clk => clk, aclr => areset );
--And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest(LOGICAL,24)@1
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a <= ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q;
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q;
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b;
END IF;
END PROCESS;
--xIsInt_uid83_fpSinPiTest(LOGICAL,82)@2
xIsInt_uid83_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q;
xIsInt_uid83_fpSinPiTest_b <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q;
xIsInt_uid83_fpSinPiTest_q <= xIsInt_uid83_fpSinPiTest_a and xIsInt_uid83_fpSinPiTest_b;
--InvXIsInt_uid100_fpSinPiTest(LOGICAL,99)@2
InvXIsInt_uid100_fpSinPiTest_a <= xIsInt_uid83_fpSinPiTest_q;
InvXIsInt_uid100_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvXIsInt_uid100_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
InvXIsInt_uid100_fpSinPiTest_q <= not InvXIsInt_uid100_fpSinPiTest_a;
END IF;
END PROCESS;
--signComp_uid101_fpSinPiTest(LOGICAL,100)@3
signComp_uid101_fpSinPiTest_a <= InvXIsInt_uid100_fpSinPiTest_q;
signComp_uid101_fpSinPiTest_b <= InvXFrac_uid99_fpSinPiTest_q;
signComp_uid101_fpSinPiTest_c <= ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q;
signComp_uid101_fpSinPiTest_q <= signComp_uid101_fpSinPiTest_a and signComp_uid101_fpSinPiTest_b and signComp_uid101_fpSinPiTest_c;
--ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a(DELAY,537)@2
ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid40_fpSinPiTest_q, xout => ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q, clk => clk, aclr => areset );
--InvYIsZero_uid102_fpSinPiTest(LOGICAL,101)@3
InvYIsZero_uid102_fpSinPiTest_a <= ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q;
InvYIsZero_uid102_fpSinPiTest_q <= not InvYIsZero_uid102_fpSinPiTest_a;
--And2InvYIsZeroSignComp_uid103_fpSinPiTest(LOGICAL,102)@3
And2InvYIsZeroSignComp_uid103_fpSinPiTest_a <= InvYIsZero_uid102_fpSinPiTest_q;
And2InvYIsZeroSignComp_uid103_fpSinPiTest_b <= signComp_uid101_fpSinPiTest_q;
And2InvYIsZeroSignComp_uid103_fpSinPiTest_q <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_a and And2InvYIsZeroSignComp_uid103_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= xIn_0;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(63 downto 63);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a(DELAY,540)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q, clk => clk, aclr => areset );
--signR_uid104_fpSinPiTest(LOGICAL,103)@3
signR_uid104_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q;
signR_uid104_fpSinPiTest_b <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_q;
signR_uid104_fpSinPiTest_q <= signR_uid104_fpSinPiTest_a xor signR_uid104_fpSinPiTest_b;
--ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt(COUNTER,1020)
-- every=1, low=0, high=36, step=1, init=1
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i = 35 THEN
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i - 36;
ELSE
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg(REG,1021)
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q;
END IF;
END PROCESS;
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux(MUX,1022)
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s <= VCC_q;
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux: PROCESS (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem(DUALMEM,1019)
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia <= signR_uid104_fpSinPiTest_q;
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q;
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q;
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 37,
width_b => 1,
widthad_b => 6,
numwords_b => 37,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq,
address_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa,
data_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia
);
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq(0 downto 0);
--ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg(DELAY,1018)
ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q, xout => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset );
--cstBias_uid12_fpSinPiTest(CONSTANT,11)
cstBias_uid12_fpSinPiTest_q <= "01111111111";
--piwFP2_uid67_fpSinPiTest(CONSTANT,66)
piwFP2_uid67_fpSinPiTest_q <= "110010010000111111011010101000100010000101101000110001";
--reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1(REG,363)@1
reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= y_uid39_fpSinPiTest_b;
END IF;
END PROCESS;
--cOne_uid44_fpSinPiTest(CONSTANT,43)
cOne_uid44_fpSinPiTest_q <= "100000000000000000000000000000000000000000000000000000000000000000000000000000000";
--oneMinusY_uid45_fpSinPiTest(SUB,44)@2
oneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid44_fpSinPiTest_q);
oneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q);
oneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oneMinusY_uid45_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
oneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid45_fpSinPiTest_b));
END IF;
END PROCESS;
oneMinusY_uid45_fpSinPiTest_q <= oneMinusY_uid45_fpSinPiTest_o(81 downto 0);
--oMyBottom_uid47_fpSinPiTest(BITSELECT,46)@3
oMyBottom_uid47_fpSinPiTest_in <= oneMinusY_uid45_fpSinPiTest_q(78 downto 0);
oMyBottom_uid47_fpSinPiTest_b <= oMyBottom_uid47_fpSinPiTest_in(78 downto 0);
--ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d(DELAY,471)@3
ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => oMyBottom_uid47_fpSinPiTest_b, xout => ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q, clk => clk, aclr => areset );
--yBottom_uid48_fpSinPiTest(BITSELECT,47)@1
yBottom_uid48_fpSinPiTest_in <= y_uid39_fpSinPiTest_b(78 downto 0);
yBottom_uid48_fpSinPiTest_b <= yBottom_uid48_fpSinPiTest_in(78 downto 0);
--ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c(DELAY,470)@1
ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 79, depth => 2 )
PORT MAP ( xin => yBottom_uid48_fpSinPiTest_b, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, clk => clk, aclr => areset );
--ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg(DELAY,926)
ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset );
--ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a(DELAY,833)@1
ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 80, depth => 1 )
PORT MAP ( xin => y_uid39_fpSinPiTest_b, xout => ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q, clk => clk, aclr => areset );
--reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1(REG,364)@2
reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid46_fpSinPiTest(COMPARE,45)@3
cmpYToOneMinusY_uid46_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid46_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & oneMinusY_uid45_fpSinPiTest_q) & '0';
cmpYToOneMinusY_uid46_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q) & cmpYToOneMinusY_uid46_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid46_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid46_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
cmpYToOneMinusY_uid46_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_b));
END IF;
END PROCESS;
cmpYToOneMinusY_uid46_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid46_fpSinPiTest_o(84);
--z_uid49_fpSinPiTest(MUX,48)@4
z_uid49_fpSinPiTest_s <= cmpYToOneMinusY_uid46_fpSinPiTest_c;
z_uid49_fpSinPiTest: PROCESS (z_uid49_fpSinPiTest_s, ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q)
BEGIN
CASE z_uid49_fpSinPiTest_s IS
WHEN "0" => z_uid49_fpSinPiTest_q <= ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q;
WHEN "1" => z_uid49_fpSinPiTest_q <= ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q;
WHEN OTHERS => z_uid49_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid63_fpSinPiTest(BITSELECT,62)@4
zAddr_uid63_fpSinPiTest_in <= z_uid49_fpSinPiTest_q;
zAddr_uid63_fpSinPiTest_b <= zAddr_uid63_fpSinPiTest_in(78 downto 72);
--reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0(REG,382)@4
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= "0000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= zAddr_uid63_fpSinPiTest_b;
END IF;
END PROCESS;
--memoryC5_uid231_sinPiZTableGenerator(LOOKUP,230)@5
memoryC5_uid231_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001";
WHEN "0000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111110101101000";
WHEN "0000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111101101011101";
WHEN "0000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100110001110";
WHEN "0000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100000000010";
WHEN "0000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111011000000000";
WHEN "0000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111010001101101";
WHEN "0000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111001010010111";
WHEN "0001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111000010110010";
WHEN "0001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110111100010100";
WHEN "0001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110110100011111";
WHEN "0001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110101100101101";
WHEN "0001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110100101101011";
WHEN "0001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110011111011101";
WHEN "0001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010111001010";
WHEN "0001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010001011011";
WHEN "0010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110001010101011";
WHEN "0010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110000011011001";
WHEN "0010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101111011000001";
WHEN "0010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101110101001010";
WHEN "0010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101101110100110";
WHEN "0010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101100111100011";
WHEN "0010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011111111111";
WHEN "0010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011001001010";
WHEN "0011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101010010100110";
WHEN "0011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101001010011011";
WHEN "0011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101000100011100";
WHEN "0011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100111101010110";
WHEN "0011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100110110111000";
WHEN "0011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100101111110010";
WHEN "0011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100111110010";
WHEN "0011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100001010101";
WHEN "0100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100011011011111";
WHEN "0100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100010011110111";
WHEN "0100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100001110001010";
WHEN "0100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100000111000100";
WHEN "0100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111111110101";
WHEN "0100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111001010110";
WHEN "0100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011110011000111";
WHEN "0100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011101101000000";
WHEN "0101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011100110000011";
WHEN "0101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011111111001";
WHEN "0101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011000100110";
WHEN "0101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011010010101100";
WHEN "0101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011001100010010";
WHEN "0101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011000101010111";
WHEN "0101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111111101010";
WHEN "0101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111001010000";
WHEN "0110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010110011010011";
WHEN "0110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010101100101011";
WHEN "0110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010100110111110";
WHEN "0110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011111111000";
WHEN "0110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011010110010";
WHEN "0110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010010101001110";
WHEN "0110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001110010011";
WHEN "0110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001000111011";
WHEN "0111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010000001111011";
WHEN "0111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001111011111110";
WHEN "0111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110111001010";
WHEN "0111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110001110111";
WHEN "0111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001101011000100";
WHEN "0111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100101010010";
WHEN "0111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100000011111";
WHEN "0111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001011010001010";
WHEN "1000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001010100111110";
WHEN "1000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001110110010";
WHEN "1000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001010111000";
WHEN "1000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001000100111111";
WHEN "1000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111111001100";
WHEN "1000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111010001001";
WHEN "1000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110101010110";
WHEN "1000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110000011101";
WHEN "1001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000101001110100";
WHEN "1001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000100101111001";
WHEN "1001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011111111010";
WHEN "1001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011011110110";
WHEN "1001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010110001100";
WHEN "1001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010001001000";
WHEN "1001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001101111001";
WHEN "1001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001000000111";
WHEN "1010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000000010111001";
WHEN "1010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111110110110";
WHEN "1010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111001111111";
WHEN "1010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110110010100";
WHEN "1010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110001011000";
WHEN "1010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101100010111";
WHEN "1010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101000010010";
WHEN "1010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100100010000";
WHEN "1011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100000111100";
WHEN "1011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111011011111111";
WHEN "1011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010111100000";
WHEN "1011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010011110100";
WHEN "1011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010000011100";
WHEN "1011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111001011011110";
WHEN "1011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000111111101";
WHEN "1011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000100101011";
WHEN "1100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000001100100";
WHEN "1100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111101101110";
WHEN "1100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111010011000";
WHEN "1100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110110110000";
WHEN "1100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110010011010";
WHEN "1100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110000011110";
WHEN "1100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101100101100";
WHEN "1100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101000101110";
WHEN "1101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100110100000";
WHEN "1101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100100010001";
WHEN "1101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100001000000";
WHEN "1101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011101101110";
WHEN "1101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011011011111";
WHEN "1101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010111000100";
WHEN "1101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010101110011";
WHEN "1101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010001111100";
WHEN "1110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010000001111";
WHEN "1110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001110011001";
WHEN "1110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001010100010";
WHEN "1110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000111111000";
WHEN "1110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101110110";
WHEN "1110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101000100";
WHEN "1110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000010100010";
WHEN "1110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111111110011";
WHEN "1111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111110010000";
WHEN "1111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111100110111";
WHEN "1111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111010111000";
WHEN "1111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111000101000";
WHEN "1111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110110110100";
WHEN "1111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110101011010";
WHEN "1111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110100000011";
WHEN "1111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110010001011";
WHEN OTHERS =>
memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001";
END CASE;
END IF;
END PROCESS;
--ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a(DELAY,485)@4
ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => z_uid49_fpSinPiTest_q, xout => ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q, clk => clk, aclr => areset );
--zPPolyEval_uid64_fpSinPiTest(BITSELECT,63)@5
zPPolyEval_uid64_fpSinPiTest_in <= ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q(71 downto 0);
zPPolyEval_uid64_fpSinPiTest_b <= zPPolyEval_uid64_fpSinPiTest_in(71 downto 27);
--yT1_uid232_sinPiZPolyEval(BITSELECT,231)@5
yT1_uid232_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b;
yT1_uid232_sinPiZPolyEval_b <= yT1_uid232_sinPiZPolyEval_in(44 downto 28);
--reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0(REG,383)@5
reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= "00000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= yT1_uid232_sinPiZPolyEval_b;
END IF;
END PROCESS;
--prodXY_uid263_pT1_uid233_sinPiZPolyEval(MULT,262)@6
prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_b);
prodXY_uid263_pT1_uid233_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= (others => '0');
prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= (others => '0');
prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q;
prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= memoryC5_uid231_sinPiZTableGenerator_q;
prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr,34));
END IF;
END PROCESS;
prodXY_uid263_pT1_uid233_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval(BITSELECT,263)@9
prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_q;
prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in(33 downto 16);
--highBBits_uid235_sinPiZPolyEval(BITSELECT,234)@9
highBBits_uid235_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b;
highBBits_uid235_sinPiZPolyEval_b <= highBBits_uid235_sinPiZPolyEval_in(17 downto 1);
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a(DELAY,853)@4
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => zAddr_uid63_fpSinPiTest_b, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q, clk => clk, aclr => areset );
--reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0(REG,384)@7
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= "0000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q;
END IF;
END PROCESS;
--memoryC4_uid230_sinPiZTableGenerator(LOOKUP,229)@8
memoryC4_uid230_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110";
WHEN "0000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110011111111100";
WHEN "0000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100101101100110011";
WHEN "0000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100100010011000101";
WHEN "0000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100010010010010110";
WHEN "0000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011111110011000100";
WHEN "0000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011100101011001100";
WHEN "0000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011001000001111000";
WHEN "0001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010100110101100100";
WHEN "0001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010000000010110001";
WHEN "0001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001001010101111100100";
WHEN "0001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001000100111000100010";
WHEN "0001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000111110011011110101";
WHEN "0001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000110111011001010101";
WHEN "0001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000101111111000110001";
WHEN "0001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000100111101101111110";
WHEN "0010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000011111000010010110";
WHEN "0010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000010101110100101111";
WHEN "0010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000001100000110110101";
WHEN "0010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000000001101111000000";
WHEN "0010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111110110110101110011";
WHEN "0010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111101011011010111001";
WHEN "0010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111011111011110000110";
WHEN "0010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111010010111100110100";
WHEN "0011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111000101110111111001";
WHEN "0011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110111000010100011101";
WHEN "0011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110101010001000110011";
WHEN "0011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110011011011101100111";
WHEN "0011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110001100001110001111";
WHEN "0011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101111100011110001010";
WHEN "0011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101101100001110100101";
WHEN "0011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101011011011000110110";
WHEN "0100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101001001111111101110";
WHEN "0100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100111000001001001111";
WHEN "0100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100100101101100011001";
WHEN "0100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100010010110001110000";
WHEN "0100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011111111010101110110";
WHEN "0100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011101011010111000111";
WHEN "0100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011010110110110011110";
WHEN "0100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011000001110100011110";
WHEN "0101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010101100010100010011";
WHEN "0101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010010110010001000111";
WHEN "0101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001111111110001000100";
WHEN "0101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001101000101100110110";
WHEN "0101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001010001001001111011";
WHEN "0101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000111001001000001110";
WHEN "0101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000100000100011110110";
WHEN "0101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000000111100001111001";
WHEN "0110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111101101111111011111";
WHEN "0110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111010011111111100110";
WHEN "0110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110111001011110100100";
WHEN "0110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110011110100010000111";
WHEN "0110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110000011000010001001";
WHEN "0110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101100111000101000011";
WHEN "0110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101001010101101011111";
WHEN "0110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100101101110011101110";
WHEN "0111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100010000100000111110";
WHEN "0111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011110010101101110100";
WHEN "0111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011010100011010011110";
WHEN "0111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010110101101011010111";
WHEN "0111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010010110100011011101";
WHEN "0111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001110110111100001001";
WHEN "0111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001010110110110010000";
WHEN "0111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000110110011000001101";
WHEN "1000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000010101011011011001";
WHEN "1000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111110100000101110010";
WHEN "1000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111010010001110101001";
WHEN "1000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110110000000001101011";
WHEN "1000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110001101011001110011";
WHEN "1000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101101010010101011101";
WHEN "1000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101000110110101111111";
WHEN "1000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111100100010111100111100";
WHEN "1001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011111110101110100100";
WHEN "1001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011011001111111110100";
WHEN "1001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010110100111101000111";
WHEN "1001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010001111011100101001";
WHEN "1001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001101001100111100001";
WHEN "1001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001000011011000101011";
WHEN "1001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111000011100101100110010";
WHEN "1001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111110101110000000011";
WHEN "1010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111001110011001111101";
WHEN "1010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110110100110101001110001";
WHEN "1010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101111110100101001011";
WHEN "1010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101010110000110010110";
WHEN "1010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100101101010100111010";
WHEN "1010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100000100001101101101";
WHEN "1010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110011011010101110011000";
WHEN "1010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010110000111001010011";
WHEN "1011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010000110101101010010";
WHEN "1011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110001011100010001000010";
WHEN "1011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000110001011111001110";
WHEN "1011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000000110010110110100";
WHEN "1011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101111011010111010001000";
WHEN "1011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110101111001110001011";
WHEN "1011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110000011001011001100";
WHEN "1011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101101010110110100111111";
WHEN "1100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101100101010001011011001";
WHEN "1100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011111101010010000000";
WHEN "1100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011010000000101001000";
WHEN "1100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101010100010100111110111";
WHEN "1100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001110100111011010110";
WHEN "1100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001000110110111101100";
WHEN "1100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101000011000101000001000";
WHEN "1100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100111101010001001010101";
WHEN "1101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110111011010110000011";
WHEN "1101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110001100010011011010";
WHEN "1101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100101011101000100011001";
WHEN "1101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100100101101100110100111";
WHEN "1101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011111101110111111010";
WHEN "1101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011001110000000101100";
WHEN "1101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100010011101110011110101";
WHEN "1101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100001101101100000010000";
WHEN "1110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000111100111010001011";
WHEN "1110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000001100000111111010";
WHEN "1110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011111011011001110101000";
WHEN "1110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011110101010000110010111";
WHEN "1110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101111000110001000001";
WHEN "1110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101000111001101001001";
WHEN "1110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011100010101100011001010";
WHEN "1110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011011100011101111010110";
WHEN "1111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011010110001101110011110";
WHEN "1111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001111111100011010111";
WHEN "1111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001001101010000100101";
WHEN "1111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011000011010110101101110";
WHEN "1111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010111101000010001000000";
WHEN "1111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110110101100011000101";
WHEN "1111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110000010101101010111";
WHEN "1111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010101001111110001011010";
WHEN OTHERS =>
memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid236_sinPiZPolyEval(ADD,235)@9
sumAHighB_uid236_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid230_sinPiZTableGenerator_q(25)) & memoryC4_uid230_sinPiZTableGenerator_q);
sumAHighB_uid236_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid235_sinPiZPolyEval_b(16)) & highBBits_uid235_sinPiZPolyEval_b);
sumAHighB_uid236_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid236_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid236_sinPiZPolyEval_b));
sumAHighB_uid236_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_o(26 downto 0);
--lowRangeB_uid234_sinPiZPolyEval(BITSELECT,233)@9
lowRangeB_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid234_sinPiZPolyEval_b <= lowRangeB_uid234_sinPiZPolyEval_in(0 downto 0);
--s1_uid234_uid237_sinPiZPolyEval(BITJOIN,236)@9
s1_uid234_uid237_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_q & lowRangeB_uid234_sinPiZPolyEval_b;
--reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1(REG,385)@9
reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= "0000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= s1_uid234_uid237_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor(LOGICAL,1179)
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q;
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q <= not (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a or ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b);
--ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg(REG,1177)
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END PROCESS;
--ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena(REG,1180)
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd(LOGICAL,1181)
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q;
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b <= VCC_q;
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a and ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b;
--yT2_uid238_sinPiZPolyEval(BITSELECT,237)@5
yT2_uid238_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b;
yT2_uid238_sinPiZPolyEval_b <= yT2_uid238_sinPiZPolyEval_in(44 downto 19);
--ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt(COUNTER,1173)
-- every=1, low=0, high=1, step=1, init=1
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END PROCESS;
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i,1));
--ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg(REG,1174)
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux(MUX,1175)
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s <= VCC_q;
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem(DUALMEM,1172)
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia <= yT2_uid238_sinPiZPolyEval_b;
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q;
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q;
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq(25 downto 0);
--ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg(DELAY,1171)
ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q, xout => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q, clk => clk, aclr => areset );
--reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0(REG,386)@9
reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= "00000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q;
END IF;
END PROCESS;
--prodXY_uid266_pT2_uid239_sinPiZPolyEval(MULT,265)@10
prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_b);
prodXY_uid266_pT2_uid239_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= (others => '0');
prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= (others => '0');
prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q;
prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q;
prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
prodXY_uid266_pT2_uid239_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval(BITSELECT,266)@13
prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_q;
prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in(53 downto 25);
--highBBits_uid241_sinPiZPolyEval(BITSELECT,240)@13
highBBits_uid241_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b;
highBBits_uid241_sinPiZPolyEval_b <= highBBits_uid241_sinPiZPolyEval_in(28 downto 1);
--reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1(REG,388)@13
reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= "0000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= highBBits_uid241_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor(LOGICAL,1192)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b);
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1188)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q <= "0101";
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp(LOGICAL,1189)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q);
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b else "0";
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg(REG,1190)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena(REG,1193)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q = "1") THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1194)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1184)
-- every=1, low=0, high=5, step=1, init=1
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i = 4 THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i - 5;
ELSE
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i,3));
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg(REG,1185)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1186)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1183)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 6,
width_b => 7,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq,
address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa,
data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia
);
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg(DELAY,1182)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset );
--reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0(REG,387)@12
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= "0000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q;
END IF;
END PROCESS;
--memoryC3_uid229_sinPiZTableGenerator(LOOKUP,228)@13
memoryC3_uid229_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011";
WHEN "0000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000001010001100110101000111010101";
WHEN "0000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000010100011001100101101010110011";
WHEN "0000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000011110100110001101010100011011";
WHEN "0000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000101000110010100111100101110011";
WHEN "0000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000110010111110101111101101101000";
WHEN "0000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000111101001010100001100001001101";
WHEN "0000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001000111010101111000010100001000";
WHEN "0001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001010001100000101111101001011010";
WHEN "0001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001011011101011000011001000111110";
WHEN "0001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001100101110100101110001001110101";
WHEN "0001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001101111111101101100010100000001";
WHEN "0001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001111010000101111001001101010110";
WHEN "0001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010000100001101010000011000110101";
WHEN "0001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010001110010011101101001010101000";
WHEN "0001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010011000011001001011011101011111";
WHEN "0010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010100010011101100110100011101011";
WHEN "0010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010101100100000111010000011110001";
WHEN "0010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010110110100011000001011111010110";
WHEN "0010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011000000100011111000101110110101";
WHEN "0010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011001010100011011011001000001011";
WHEN "0010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011010100100001100100010010100101";
WHEN "0010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011011110011110001111110110101010";
WHEN "0010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011101000011001011001100000011011";
WHEN "0011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011110010010010111100111000010100";
WHEN "0011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011111100001010110101011110000110";
WHEN "0011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100000110000000111111001110100010";
WHEN "0011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100001111110101010101100100101101";
WHEN "0011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100011001100111110100010110001111";
WHEN "0011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100100011011000010111001001011111";
WHEN "0011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100101101000110111001101001101001";
WHEN "0011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100110110110011010111110011001100";
WHEN "0100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101000000011101101101010000100110";
WHEN "0100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101001010000101110101101000010110";
WHEN "0100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101010011101011101100111100100100";
WHEN "0100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101011101001111001110110000110010";
WHEN "0100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101100110110000010111000000110011";
WHEN "0100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101110000001111000001100011110100";
WHEN "0100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101111001101011001010010000000001";
WHEN "0100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110000011000100101100111100001110";
WHEN "0101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110001100011011100101011010100101";
WHEN "0101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110010101101111101111110000010101";
WHEN "0101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110011111000001000111101011101100";
WHEN "0101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110101000001111101001011001100010";
WHEN "0101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110110001011011010000101101010010";
WHEN "0101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110111010100011111001100111101100";
WHEN "0101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111000011101001100000010000100010";
WHEN "0101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111001100101100000000100001010000";
WHEN "0110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111010101101011010110100011101100";
WHEN "0110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111011110100111011110011000011110";
WHEN "0110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111100111100000010100001101010000";
WHEN "0110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111110000010101110100000001010000";
WHEN "0110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111111001000111111010001101010001";
WHEN "0110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000000001110110100010110001111010";
WHEN "0110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000001010100001101001110111110101";
WHEN "0110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000010011001001001011111110000001";
WHEN "0111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000011011101101000101000010101111";
WHEN "0111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000100100001101010001101000100100";
WHEN "0111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000101100101001101110000011010101";
WHEN "0111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000110101000010010110100001011010";
WHEN "0111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000111101010111000111010101011110";
WHEN "0111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001000101100111111101000110111000";
WHEN "0111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001001101110100110100001111001100";
WHEN "0111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001010101111101101001000001001010";
WHEN "1000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001011110000010011000001001000011";
WHEN "1000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001100110000010111101111101010011";
WHEN "1000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001101101111111010111010011001111";
WHEN "1000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001110101110111100000011010000110";
WHEN "1000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001111101101011010110000011010010";
WHEN "1000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010000101011010110100111100000101";
WHEN "1000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010001101000101111001101110100011";
WHEN "1000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010010100101100100001000101010010";
WHEN "1001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010011100001110100111101001010100";
WHEN "1001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010100011101100001010100001011100";
WHEN "1001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010101011000101000110001011100100";
WHEN "1001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010110010011001010111110000100100";
WHEN "1001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010111001101000111011111001000111";
WHEN "1001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000000110011101111101001011111";
WHEN "1001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000111111001110000000110011110";
WHEN "1001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011001110111010111001110111111110";
WHEN "1010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011010101110111001010010001110110";
WHEN "1010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011011100101110011110011000111101";
WHEN "1010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011100011100000110011001001001001";
WHEN "1010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011101010001110000101111000101100";
WHEN "1010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110000110110010011100011000111";
WHEN "1010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110111011001011001011101010011";
WHEN "1010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011111101110111010100111100011100";
WHEN "1010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100000100010000000011001111101101";
WHEN "1011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100001010100011100001101110011100";
WHEN "1011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010000110001101101100011100011";
WHEN "1011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010110111010100100010100000100";
WHEN "1011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100011100111110000011100000001010";
WHEN "1011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100100010111100001000100001101001";
WHEN "1011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101000110100110000110001111011";
WHEN "1011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101110100111111010000100111001";
WHEN "1011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100110100010101100001111010001101";
WHEN "1100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111001111101100101111101110000";
WHEN "1100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111111100000000011110011100101";
WHEN "1100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101000100111100111001010011110100";
WHEN "1100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001010010100000100001001001101";
WHEN "1100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001111100101100010000111001000";
WHEN "1100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101010100110001010001010100001101";
WHEN "1100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011001110111001111010101110101";
WHEN "1100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011110110111011010001101111010";
WHEN "1101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101100011110001110000000111001111";
WHEN "1101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101000100110001110111010010001";
WHEN "1101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101101010100110100100110101101";
WHEN "1101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110001111101011111011001010101";
WHEN "1101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110110100000001101100000100000";
WHEN "1101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111010111100111100111010111000";
WHEN "1101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111111010011101100010000110110";
WHEN "1101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000011100100011001011010100000";
WHEN "1110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000111101111000011000011110011";
WHEN "1110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001011110011100111011010000000";
WHEN "1110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001111110010000100101111100001";
WHEN "1110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010011101010011001110010000111";
WHEN "1110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010111011100100100111111111001";
WHEN "1110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011011001000100101000000101011";
WHEN "1110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011110101110011000001011101010";
WHEN "1110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100010001101111101010010100010";
WHEN "1111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100101100111010011001000110011";
WHEN "1111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101000111010011000011010000011";
WHEN "1111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101100000111001011110100010010";
WHEN "1111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101111001101101100001110011100";
WHEN "1111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110010001101111000100101110110";
WHEN "1111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110101000111101111110101001010";
WHEN "1111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110111111011010000111000110000";
WHEN "1111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110111010101000011010110000100000";
WHEN OTHERS =>
memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid242_sinPiZPolyEval(ADD,241)@14
sumAHighB_uid242_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid229_sinPiZTableGenerator_q(34)) & memoryC3_uid229_sinPiZTableGenerator_q);
sumAHighB_uid242_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q);
sumAHighB_uid242_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid242_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid242_sinPiZPolyEval_b));
sumAHighB_uid242_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_o(35 downto 0);
--lowRangeB_uid240_sinPiZPolyEval(BITSELECT,239)@13
lowRangeB_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid240_sinPiZPolyEval_b <= lowRangeB_uid240_sinPiZPolyEval_in(0 downto 0);
--ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a(DELAY,686)@13
ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid240_sinPiZPolyEval_b, xout => ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--s2_uid240_uid243_sinPiZPolyEval(BITJOIN,242)@14
s2_uid240_uid243_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_q & ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q;
--yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval(BITSELECT,274)@14
yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q;
yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in(36 downto 19);
--reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9(REG,389)@14
reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor(LOGICAL,950)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top(CONSTANT,946)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q <= "0110";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp(LOGICAL,947)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg(REG,948)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena(REG,951)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd(LOGICAL,952)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b <= VCC_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt(COUNTER,942)
-- every=1, low=0, high=6, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i = 5 THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i - 6;
ELSE
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg(REG,943)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux(MUX,944)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s <= VCC_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem(DUALMEM,1069)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 3,
numwords_a => 7,
width_b => 45,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq(44 downto 0);
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg(DELAY,1068)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--yT3_uid244_sinPiZPolyEval(BITSELECT,243)@14
yT3_uid244_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q;
yT3_uid244_sinPiZPolyEval_b <= yT3_uid244_sinPiZPolyEval_in(44 downto 10);
--xBottomBits_uid274_pT3_uid245_sinPiZPolyEval(BITSELECT,273)@14
xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b(7 downto 0);
xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in(7 downto 0);
--pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval(BITJOIN,276)@14
pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7(REG,391)@14
reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= "00000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q;
END IF;
END PROCESS;
--yBottomBits_uid273_pT3_uid245_sinPiZPolyEval(BITSELECT,272)@14
yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q(9 downto 0);
yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b <= yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in(9 downto 0);
--spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval(BITJOIN,275)@14
spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q <= GND_q & yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b;
--pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval(BITJOIN,277)@14
pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q <= spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6(REG,390)@14
reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q;
END IF;
END PROCESS;
--xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval(BITSELECT,271)@14
xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b;
xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in(34 downto 17);
--reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4(REG,392)@14
reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b;
END IF;
END PROCESS;
--multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma(CHAINMULTADD,345)@15
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0);
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1);
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1),38);
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0);
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0);
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q),19));
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q),19));
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q),18));
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q),18));
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0);
END IF;
END PROCESS;
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0),37));
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval(BITSELECT,279)@18
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q;
multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in(36 downto 7);
--highBBits_uid282_pT3_uid245_sinPiZPolyEval(BITSELECT,281)@18
highBBits_uid282_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b;
highBBits_uid282_pT3_uid245_sinPiZPolyEval_b <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_in(29 downto 1);
--reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1(REG,395)@18
reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_b;
END IF;
END PROCESS;
--yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval(BITSELECT,269)@14
yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q;
yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in(36 downto 10);
--reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1(REG,393)@14
reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b;
END IF;
END PROCESS;
--xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval(BITSELECT,268)@14
xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b;
xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in(34 downto 8);
--reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0(REG,394)@14
reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b;
END IF;
END PROCESS;
--topProd_uid271_pT3_uid245_sinPiZPolyEval(MULT,270)@15
topProd_uid271_pT3_uid245_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_b);
topProd_uid271_pT3_uid245_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= (others => '0');
topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= (others => '0');
topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q;
topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q;
topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid271_pT3_uid245_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
topProd_uid271_pT3_uid245_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0(REG,396)@18
reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_q;
END IF;
END PROCESS;
--sumAHighB_uid283_pT3_uid245_sinPiZPolyEval(ADD,282)@19
sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q(53)) & reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q);
sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q);
sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b));
sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o(54 downto 0);
--lowRangeB_uid281_pT3_uid245_sinPiZPolyEval(BITSELECT,280)@18
lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b <= lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in(0 downto 0);
--ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a(DELAY,724)@18
ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b, xout => ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--add0_uid281_uid284_pT3_uid245_sinPiZPolyEval(BITJOIN,283)@19
add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q & ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q;
--R_uid285_pT3_uid245_sinPiZPolyEval(BITSELECT,284)@19
R_uid285_pT3_uid245_sinPiZPolyEval_in <= add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q(54 downto 0);
R_uid285_pT3_uid245_sinPiZPolyEval_b <= R_uid285_pT3_uid245_sinPiZPolyEval_in(54 downto 18);
--reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1(REG,397)@19
reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= R_uid285_pT3_uid245_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor(LOGICAL,1168)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b);
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1164)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q <= "01011";
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp(LOGICAL,1165)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q);
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b else "0";
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg(REG,1166)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena(REG,1169)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q = "1") THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1170)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1160)
-- every=1, low=0, high=11, step=1, init=1
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i = 10 THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i - 11;
ELSE
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i,4));
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg(REG,1161)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1162)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1159)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 4,
numwords_a => 12,
width_b => 7,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq,
address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa,
data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia
);
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg(DELAY,1158)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset );
--reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0(REG,381)@18
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= "0000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q;
END IF;
END PROCESS;
--memoryC2_uid228_sinPiZTableGenerator(LOOKUP,227)@19
memoryC2_uid228_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000";
WHEN "0000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000";
WHEN "0000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101";
WHEN "0000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011";
WHEN "0000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110";
WHEN "0000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100";
WHEN "0000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001";
WHEN "0000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000";
WHEN "0001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001";
WHEN "0001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011";
WHEN "0001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010";
WHEN "0001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110";
WHEN "0001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000";
WHEN "0001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101";
WHEN "0001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110";
WHEN "0001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001";
WHEN "0010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111";
WHEN "0010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110";
WHEN "0010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110";
WHEN "0010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000";
WHEN "0010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100";
WHEN "0010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000";
WHEN "0010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011";
WHEN "0010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001";
WHEN "0011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101";
WHEN "0011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001";
WHEN "0011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000";
WHEN "0011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111";
WHEN "0011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010";
WHEN "0011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100";
WHEN "0011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100";
WHEN "0011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101";
WHEN "0100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010";
WHEN "0100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100";
WHEN "0100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010";
WHEN "0100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111";
WHEN "0100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111";
WHEN "0100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011";
WHEN "0100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000";
WHEN "0100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001";
WHEN "0101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011";
WHEN "0101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010";
WHEN "0101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010";
WHEN "0101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110";
WHEN "0101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111";
WHEN "0101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010";
WHEN "0101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010";
WHEN "0101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011";
WHEN "0110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110";
WHEN "0110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001";
WHEN "0110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101";
WHEN "0110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100";
WHEN "0110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000";
WHEN "0110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101";
WHEN "0110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001";
WHEN "0110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100";
WHEN "0111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100";
WHEN "0111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110";
WHEN "0111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100";
WHEN "0111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111";
WHEN "0111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101";
WHEN "0111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100";
WHEN "0111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100";
WHEN "0111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110";
WHEN "1000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110";
WHEN "1000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101";
WHEN "1000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000";
WHEN "1000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001";
WHEN "1000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111";
WHEN "1000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001";
WHEN "1000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110";
WHEN "1000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111";
WHEN "1001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011";
WHEN "1001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100";
WHEN "1001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000";
WHEN "1001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101";
WHEN "1001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111";
WHEN "1001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010";
WHEN "1001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000";
WHEN "1001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100";
WHEN "1010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100";
WHEN "1010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010";
WHEN "1010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101";
WHEN "1010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100";
WHEN "1010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110";
WHEN "1010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011";
WHEN "1010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001";
WHEN "1010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110";
WHEN "1011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111";
WHEN "1011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001";
WHEN "1011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110";
WHEN "1011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101";
WHEN "1011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001";
WHEN "1011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101";
WHEN "1011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011";
WHEN "1011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001";
WHEN "1100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010";
WHEN "1100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111";
WHEN "1100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010";
WHEN "1100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111";
WHEN "1100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010";
WHEN "1100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000";
WHEN "1100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011";
WHEN "1100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001";
WHEN "1101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101";
WHEN "1101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100";
WHEN "1101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111";
WHEN "1101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000";
WHEN "1101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101";
WHEN "1101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101";
WHEN "1101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101";
WHEN "1101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011";
WHEN "1110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100";
WHEN "1110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011";
WHEN "1110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111";
WHEN "1110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011";
WHEN "1110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001";
WHEN "1110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111";
WHEN "1110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101";
WHEN "1110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111";
WHEN "1111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001";
WHEN "1111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100";
WHEN "1111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011";
WHEN "1111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011";
WHEN "1111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011";
WHEN "1111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011";
WHEN "1111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001";
WHEN "1111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101";
WHEN OTHERS =>
memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000";
END CASE;
-- End reserved scope level
END PROCESS;
--rndBit_uid246_sinPiZPolyEval(CONSTANT,245)
rndBit_uid246_sinPiZPolyEval_q <= "01";
--cIncludingRoundingBit_uid247_sinPiZPolyEval(BITJOIN,246)@19
cIncludingRoundingBit_uid247_sinPiZPolyEval_q <= memoryC2_uid228_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q;
--reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0(REG,398)@19
reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid247_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ts3_uid248_sinPiZPolyEval(ADD,247)@20
ts3_uid248_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q);
ts3_uid248_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q(36)) & reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q);
ts3_uid248_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid248_sinPiZPolyEval_a) + SIGNED(ts3_uid248_sinPiZPolyEval_b));
ts3_uid248_sinPiZPolyEval_q <= ts3_uid248_sinPiZPolyEval_o(45 downto 0);
--s3_uid249_sinPiZPolyEval(BITSELECT,248)@20
s3_uid249_sinPiZPolyEval_in <= ts3_uid248_sinPiZPolyEval_q;
s3_uid249_sinPiZPolyEval_b <= s3_uid249_sinPiZPolyEval_in(45 downto 1);
--yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval(BITSELECT,286)@20
yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b;
yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in(44 downto 18);
--reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9(REG,399)@20
reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor(LOGICAL,1091)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b);
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top(CONSTANT,1087)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp(LOGICAL,1088)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg(REG,1089)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena(REG,1092)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd(LOGICAL,1093)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b <= VCC_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1083)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg(REG,1084)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux(MUX,1085)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem(DUALMEM,1082)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 4,
numwords_a => 13,
width_b => 45,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq(44 downto 0);
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg(DELAY,1081)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--yT4_uid250_sinPiZPolyEval(BITSELECT,249)@20
yT4_uid250_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q;
yT4_uid250_sinPiZPolyEval_b <= yT4_uid250_sinPiZPolyEval_in(44 downto 2);
--xBottomBits_uid290_pT4_uid251_sinPiZPolyEval(BITSELECT,289)@20
xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in <= yT4_uid250_sinPiZPolyEval_b(15 downto 0);
xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in(15 downto 0);
--pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval(BITJOIN,291)@20
pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7(REG,401)@20
reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q;
END IF;
END PROCESS;
--yBottomBits_uid289_pT4_uid251_sinPiZPolyEval(BITSELECT,288)@20
yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b(17 downto 0);
yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b <= yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in(17 downto 0);
--ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a(DELAY,733)@20
ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b, xout => ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval(BITJOIN,290)@21
spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q;
--pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval(BITJOIN,292)@21
pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q <= spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6(REG,400)@21
reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a(DELAY,727)@20
ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid250_sinPiZPolyEval_b, xout => ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval(BITSELECT,285)@21
xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in <= ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q;
xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4(REG,402)@21
reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b;
END IF;
END PROCESS;
--multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma(CHAINMULTADD,346)@22
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0);
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1);
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0),56);
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1),56);
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0);
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1);
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0);
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1);
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q),28));
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q),28));
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q),27));
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q),27));
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0);
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1);
END IF;
END PROCESS;
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0),55));
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval(BITSELECT,294)@25
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q;
multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in(54 downto 8);
--highBBits_uid297_pT4_uid251_sinPiZPolyEval(BITSELECT,296)@25
highBBits_uid297_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b;
highBBits_uid297_pT4_uid251_sinPiZPolyEval_b <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_in(46 downto 18);
--reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1(REG,405)@25
reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_b;
END IF;
END PROCESS;
--reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1(REG,403)@20
reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b(DELAY,730)@21
ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q, clk => clk, aclr => areset );
--reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0(REG,404)@21
reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b;
END IF;
END PROCESS;
--topProd_uid288_pT4_uid251_sinPiZPolyEval(MULT,287)@22
topProd_uid288_pT4_uid251_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_b);
topProd_uid288_pT4_uid251_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= (others => '0');
topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= (others => '0');
topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q;
topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q;
topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT4_uid251_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
topProd_uid288_pT4_uid251_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0(REG,406)@25
reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_q;
END IF;
END PROCESS;
--sumAHighB_uid298_pT4_uid251_sinPiZPolyEval(ADD,297)@26
sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q(53)) & reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q);
sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q);
sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b));
sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o(54 downto 0);
--lowRangeB_uid296_pT4_uid251_sinPiZPolyEval(BITSELECT,295)@25
lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b(17 downto 0);
lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b <= lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in(17 downto 0);
--ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a(DELAY,741)@25
ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b, xout => ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--add0_uid296_uid299_pT4_uid251_sinPiZPolyEval(BITJOIN,298)@26
add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q & ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q;
--R_uid300_pT4_uid251_sinPiZPolyEval(BITSELECT,299)@26
R_uid300_pT4_uid251_sinPiZPolyEval_in <= add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q(71 downto 0);
R_uid300_pT4_uid251_sinPiZPolyEval_b <= R_uid300_pT4_uid251_sinPiZPolyEval_in(71 downto 26);
--reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1(REG,407)@26
reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= R_uid300_pT4_uid251_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor(LOGICAL,1155)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b);
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1151)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q <= "010010";
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp(LOGICAL,1152)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q);
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b else "0";
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg(REG,1153)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena(REG,1156)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q = "1") THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1157)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1147)
-- every=1, low=0, high=18, step=1, init=1
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i = 17 THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i - 18;
ELSE
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i,5));
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg(REG,1148)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1149)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1146)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 19,
width_b => 7,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq,
address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa,
data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia
);
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg(DELAY,1145)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset );
--reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0(REG,380)@25
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= "0000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q;
END IF;
END PROCESS;
--memoryC1_uid227_sinPiZTableGenerator(LOOKUP,226)@26
memoryC1_uid227_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110";
WHEN "0000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011";
WHEN "0000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110";
WHEN "0000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110";
WHEN "0000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011";
WHEN "0000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100";
WHEN "0000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000";
WHEN "0000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010";
WHEN "0001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111";
WHEN "0001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110";
WHEN "0001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101";
WHEN "0001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101";
WHEN "0001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001";
WHEN "0001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110";
WHEN "0001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100";
WHEN "0001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111";
WHEN "0010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000";
WHEN "0010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100";
WHEN "0010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010";
WHEN "0010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010";
WHEN "0010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100";
WHEN "0010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100";
WHEN "0010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000";
WHEN "0010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000";
WHEN "0011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110";
WHEN "0011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010";
WHEN "0011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100";
WHEN "0011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000";
WHEN "0011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010";
WHEN "0011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110";
WHEN "0011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010";
WHEN "0011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010";
WHEN "0100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001";
WHEN "0100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101";
WHEN "0100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011";
WHEN "0100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000";
WHEN "0100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111";
WHEN "0100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001";
WHEN "0100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110";
WHEN "0100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001";
WHEN "0101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000";
WHEN "0101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001";
WHEN "0101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001";
WHEN "0101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110";
WHEN "0101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110";
WHEN "0101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000";
WHEN "0101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100";
WHEN "0101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011";
WHEN "0110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100";
WHEN "0110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101";
WHEN "0110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001";
WHEN "0110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010";
WHEN "0110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100";
WHEN "0110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111";
WHEN "0110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111";
WHEN "0110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000";
WHEN "0111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100";
WHEN "0111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111";
WHEN "0111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111";
WHEN "0111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111";
WHEN "0111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011";
WHEN "0111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011";
WHEN "0111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010";
WHEN "0111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101";
WHEN "1000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101";
WHEN "1000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010";
WHEN "1000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001";
WHEN "1000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111";
WHEN "1000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011";
WHEN "1000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001";
WHEN "1000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100";
WHEN "1000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001";
WHEN "1001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011";
WHEN "1001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010";
WHEN "1001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101";
WHEN "1001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100";
WHEN "1001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010";
WHEN "1001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001";
WHEN "1001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000";
WHEN "1001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100";
WHEN "1010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100";
WHEN "1010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010";
WHEN "1010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101";
WHEN "1010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111";
WHEN "1010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010";
WHEN "1010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101";
WHEN "1010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101";
WHEN "1010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011";
WHEN "1011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101";
WHEN "1011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010";
WHEN "1011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001";
WHEN "1011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001";
WHEN "1011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100";
WHEN "1011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011";
WHEN "1011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100";
WHEN "1011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101";
WHEN "1100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000";
WHEN "1100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011";
WHEN "1100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011";
WHEN "1100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001";
WHEN "1100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101";
WHEN "1100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000";
WHEN "1100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111";
WHEN "1100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010";
WHEN "1101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010";
WHEN "1101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110";
WHEN "1101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011";
WHEN "1101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110";
WHEN "1101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101";
WHEN "1101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010";
WHEN "1101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110";
WHEN "1101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110";
WHEN "1110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100";
WHEN "1110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100";
WHEN "1110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000";
WHEN "1110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001";
WHEN "1110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001";
WHEN "1110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101";
WHEN "1110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011";
WHEN "1110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001";
WHEN "1111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011";
WHEN "1111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111";
WHEN "1111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101";
WHEN "1111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110";
WHEN "1111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010";
WHEN "1111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110";
WHEN "1111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001";
WHEN "1111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111";
WHEN OTHERS =>
memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110";
END CASE;
-- End reserved scope level
END PROCESS;
--cIncludingRoundingBit_uid253_sinPiZPolyEval(BITJOIN,252)@26
cIncludingRoundingBit_uid253_sinPiZPolyEval_q <= memoryC1_uid227_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q;
--reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0(REG,408)@26
reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid253_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ts4_uid254_sinPiZPolyEval(ADD,253)@27
ts4_uid254_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q);
ts4_uid254_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q(45)) & reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q);
ts4_uid254_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid254_sinPiZPolyEval_a) + SIGNED(ts4_uid254_sinPiZPolyEval_b));
ts4_uid254_sinPiZPolyEval_q <= ts4_uid254_sinPiZPolyEval_o(52 downto 0);
--s4_uid255_sinPiZPolyEval(BITSELECT,254)@27
s4_uid255_sinPiZPolyEval_in <= ts4_uid254_sinPiZPolyEval_q;
s4_uid255_sinPiZPolyEval_b <= s4_uid255_sinPiZPolyEval_in(52 downto 1);
--yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval(BITSELECT,301)@27
yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b;
yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in(51 downto 25);
--reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9(REG,409)@27
reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor(LOGICAL,1117)
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b);
--ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top(CONSTANT,1113)
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q <= "010011";
--ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp(LOGICAL,1114)
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q;
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg(REG,1115)
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q;
END IF;
END PROCESS;
--ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena(REG,1118)
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd(LOGICAL,1119)
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b <= VCC_q;
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b;
--xBottomBits_uid305_pT5_uid257_sinPiZPolyEval(BITSELECT,304)@5
xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b(17 downto 0);
xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in(17 downto 0);
--ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1109)
-- every=1, low=0, high=19, step=1, init=1
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i - 19;
ELSE
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg(REG,1110)
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux(MUX,1111)
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q;
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem(DUALMEM,1108)
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b;
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 5,
numwords_a => 20,
width_b => 18,
widthad_b => 5,
numwords_b => 20,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq(17 downto 0);
--ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg(DELAY,1107)
ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset );
--pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval(BITJOIN,306)@27
pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7(REG,411)@27
reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q;
END IF;
END PROCESS;
--yBottomBits_uid304_pT5_uid257_sinPiZPolyEval(BITSELECT,303)@27
yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b(24 downto 0);
yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b <= yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in(24 downto 0);
--ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a(DELAY,750)@27
ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b, xout => ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval(BITJOIN,305)@28
spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q;
--pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval(BITJOIN,307)@28
pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q <= spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q & GND_q;
--reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6(REG,410)@28
reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor(LOGICAL,1104)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b);
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top(CONSTANT,1100)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q <= "010100";
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp(LOGICAL,1101)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg(REG,1102)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena(REG,1105)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd(LOGICAL,1106)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b <= VCC_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1096)
-- every=1, low=0, high=20, step=1, init=1
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i - 20;
ELSE
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i,5));
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg(REG,1097)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux(MUX,1098)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem(DUALMEM,1095)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 5,
numwords_a => 21,
width_b => 45,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq(44 downto 0);
--ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg(DELAY,1094)
ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval(BITSELECT,300)@28
xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q;
xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in(44 downto 18);
--reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4(REG,412)@28
reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b;
END IF;
END PROCESS;
--multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma(CHAINMULTADD,347)@29
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0);
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1);
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0),56);
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1),56);
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0);
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1);
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0);
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1);
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q),28));
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q),28));
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q),27));
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q),27));
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0);
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1);
END IF;
END PROCESS;
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0),55));
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval(BITSELECT,309)@32
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q;
multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in(54 downto 1);
--highBBits_uid312_pT5_uid257_sinPiZPolyEval(BITSELECT,311)@32
highBBits_uid312_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b;
highBBits_uid312_pT5_uid257_sinPiZPolyEval_b <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_in(53 downto 25);
--reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1(REG,415)@32
reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_b;
END IF;
END PROCESS;
--reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1(REG,413)@27
reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b(DELAY,747)@28
ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q, clk => clk, aclr => areset );
--reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0(REG,414)@28
reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b;
END IF;
END PROCESS;
--topProd_uid303_pT5_uid257_sinPiZPolyEval(MULT,302)@29
topProd_uid303_pT5_uid257_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_b);
topProd_uid303_pT5_uid257_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= (others => '0');
topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= (others => '0');
topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q;
topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q;
topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid303_pT5_uid257_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
topProd_uid303_pT5_uid257_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0(REG,416)@32
reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_q;
END IF;
END PROCESS;
--sumAHighB_uid313_pT5_uid257_sinPiZPolyEval(ADD,312)@33
sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q(53)) & reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q);
sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q);
sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b));
sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o(54 downto 0);
--lowRangeB_uid311_pT5_uid257_sinPiZPolyEval(BITSELECT,310)@32
lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b(24 downto 0);
lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b <= lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in(24 downto 0);
--ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a(DELAY,758)@32
ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b, xout => ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--add0_uid311_uid314_pT5_uid257_sinPiZPolyEval(BITJOIN,313)@33
add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q & ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q;
--R_uid315_pT5_uid257_sinPiZPolyEval(BITSELECT,314)@33
R_uid315_pT5_uid257_sinPiZPolyEval_in <= add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q(78 downto 0);
R_uid315_pT5_uid257_sinPiZPolyEval_b <= R_uid315_pT5_uid257_sinPiZPolyEval_in(78 downto 25);
--reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1(REG,417)@33
reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= R_uid315_pT5_uid257_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor(LOGICAL,1142)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b);
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1138)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q <= "011001";
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp(LOGICAL,1139)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q);
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b else "0";
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg(REG,1140)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena(REG,1143)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q = "1") THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1144)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1134)
-- every=1, low=0, high=25, step=1, init=1
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i = 24 THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i - 25;
ELSE
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i,5));
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg(REG,1135)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1136)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1133)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q;
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 26,
width_b => 7,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq,
address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa,
data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia
);
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg(DELAY,1132)
ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset );
--reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0(REG,379)@32
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= "0000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q;
END IF;
END PROCESS;
--memoryC0_uid226_sinPiZTableGenerator(LOOKUP,225)@33
memoryC0_uid226_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000";
WHEN "0000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010";
WHEN "0000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100";
WHEN "0000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001";
WHEN "0000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010";
WHEN "0000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101";
WHEN "0000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101";
WHEN "0000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101";
WHEN "0001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010";
WHEN "0001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101";
WHEN "0001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010";
WHEN "0001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111";
WHEN "0001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010";
WHEN "0001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110";
WHEN "0001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110";
WHEN "0001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111";
WHEN "0010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111";
WHEN "0010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100";
WHEN "0010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111";
WHEN "0010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000";
WHEN "0010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110";
WHEN "0010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100";
WHEN "0010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110";
WHEN "0010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011";
WHEN "0011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111";
WHEN "0011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011";
WHEN "0011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001";
WHEN "0011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101";
WHEN "0011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111";
WHEN "0011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001";
WHEN "0011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111";
WHEN "0011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001";
WHEN "0100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001";
WHEN "0100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100";
WHEN "0100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110";
WHEN "0100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000";
WHEN "0100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100";
WHEN "0100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111";
WHEN "0100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010";
WHEN "0100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101";
WHEN "0101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100";
WHEN "0101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111";
WHEN "0101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101";
WHEN "0101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000";
WHEN "0101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111";
WHEN "0101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010";
WHEN "0101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111";
WHEN "0101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110";
WHEN "0110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101";
WHEN "0110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111";
WHEN "0110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101";
WHEN "0110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101";
WHEN "0110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010";
WHEN "0110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001";
WHEN "0110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011";
WHEN "0110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111";
WHEN "0111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101";
WHEN "0111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110";
WHEN "0111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111";
WHEN "0111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100";
WHEN "0111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101";
WHEN "0111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101";
WHEN "0111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011";
WHEN "0111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110";
WHEN "1000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101";
WHEN "1000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001";
WHEN "1000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101";
WHEN "1000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110";
WHEN "1000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011";
WHEN "1000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101";
WHEN "1000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111";
WHEN "1000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111";
WHEN "1001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001";
WHEN "1001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001";
WHEN "1001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010";
WHEN "1001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010";
WHEN "1001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100";
WHEN "1001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110";
WHEN "1001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011";
WHEN "1001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101";
WHEN "1010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110";
WHEN "1010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111";
WHEN "1010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001";
WHEN "1010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001";
WHEN "1010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100";
WHEN "1010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010";
WHEN "1010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000";
WHEN "1010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110";
WHEN "1011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000";
WHEN "1011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000";
WHEN "1011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110";
WHEN "1011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101";
WHEN "1011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000";
WHEN "1011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110";
WHEN "1011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101";
WHEN "1011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010";
WHEN "1100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000";
WHEN "1100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111";
WHEN "1100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001";
WHEN "1100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000";
WHEN "1100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110";
WHEN "1100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001";
WHEN "1100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001";
WHEN "1100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010";
WHEN "1101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101";
WHEN "1101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110";
WHEN "1101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011";
WHEN "1101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100";
WHEN "1101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001";
WHEN "1101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100";
WHEN "1101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111";
WHEN "1101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101";
WHEN "1110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010";
WHEN "1110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101";
WHEN "1110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111";
WHEN "1110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001";
WHEN "1110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000";
WHEN "1110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101";
WHEN "1110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011";
WHEN "1110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100";
WHEN "1111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110";
WHEN "1111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001";
WHEN "1111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011";
WHEN "1111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001";
WHEN "1111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110";
WHEN "1111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010";
WHEN "1111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111";
WHEN "1111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011";
WHEN OTHERS =>
memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000";
END CASE;
-- End reserved scope level
END PROCESS;
--rndBit_uid258_sinPiZPolyEval(CONSTANT,257)
rndBit_uid258_sinPiZPolyEval_q <= "001";
--cIncludingRoundingBit_uid259_sinPiZPolyEval(BITJOIN,258)@33
cIncludingRoundingBit_uid259_sinPiZPolyEval_q <= memoryC0_uid226_sinPiZTableGenerator_q & rndBit_uid258_sinPiZPolyEval_q;
--reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0(REG,418)@33
reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid259_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ts5_uid260_sinPiZPolyEval(ADD,259)@34
ts5_uid260_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q);
ts5_uid260_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q(53)) & reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q);
ts5_uid260_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid260_sinPiZPolyEval_a) + SIGNED(ts5_uid260_sinPiZPolyEval_b));
ts5_uid260_sinPiZPolyEval_q <= ts5_uid260_sinPiZPolyEval_o(61 downto 0);
--s5_uid261_sinPiZPolyEval(BITSELECT,260)@34
s5_uid261_sinPiZPolyEval_in <= ts5_uid260_sinPiZPolyEval_q;
s5_uid261_sinPiZPolyEval_b <= s5_uid261_sinPiZPolyEval_in(61 downto 1);
--fxpSinRes_uid66_fpSinPiTest(BITSELECT,65)@34
fxpSinRes_uid66_fpSinPiTest_in <= s5_uid261_sinPiZPolyEval_b(58 downto 0);
fxpSinRes_uid66_fpSinPiTest_b <= fxpSinRes_uid66_fpSinPiTest_in(58 downto 5);
--ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor(LOGICAL,963)
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q;
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q <= not (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a or ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b);
--ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top(CONSTANT,959)
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q <= "011111";
--ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp(LOGICAL,960)
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q;
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q);
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q <= "1" when ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a = ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b else "0";
--ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg(REG,961)
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena(REG,964)
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q = "1") THEN
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd(LOGICAL,965)
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q;
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b <= VCC_q;
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a and ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b;
--ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt(COUNTER,955)
-- every=1, low=0, high=31, step=1, init=1
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END PROCESS;
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i,5));
--ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg(REG,956)
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux(MUX,957)
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s <= VCC_q;
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux: PROCESS (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem(DUALMEM,954)
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia <= sinXIsX_uid30_fpSinPiTest_c;
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q;
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q;
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq,
address_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa,
data_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia
);
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq(0 downto 0);
--ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg(DELAY,953)
ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset );
--multRightOp_uid68_fpSinPiTest(MUX,67)@34
multRightOp_uid68_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q;
multRightOp_uid68_fpSinPiTest: PROCESS (multRightOp_uid68_fpSinPiTest_s, fxpSinRes_uid66_fpSinPiTest_b)
BEGIN
CASE multRightOp_uid68_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid68_fpSinPiTest_q <= fxpSinRes_uid66_fpSinPiTest_b;
WHEN "1" => multRightOp_uid68_fpSinPiTest_q <= piwFP2_uid67_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid68_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--mul2xSinRes_uid69_fpSinPiTest_b_1(BITSELECT,318)@34
mul2xSinRes_uid69_fpSinPiTest_b_1_in <= multRightOp_uid68_fpSinPiTest_q;
mul2xSinRes_uid69_fpSinPiTest_b_1_b <= mul2xSinRes_uid69_fpSinPiTest_b_1_in(53 downto 27);
--reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1(REG,423)@34
reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b;
END IF;
END PROCESS;
--ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor(LOGICAL,1129)
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q;
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q <= not (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a or ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b);
--ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top(CONSTANT,1125)
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q <= "010110";
--ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp(LOGICAL,1126)
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q;
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q);
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q <= "1" when ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a = ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b else "0";
--ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg(REG,1127)
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q;
END IF;
END PROCESS;
--ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena(REG,1130)
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q = "1") THEN
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd(LOGICAL,1131)
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q;
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b <= VCC_q;
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a and ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b;
--ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor(LOGICAL,937)
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a or ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b);
--ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top(CONSTANT,933)
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q <= "0111";
--ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp(LOGICAL,934)
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a = ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg(REG,935)
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q;
END IF;
END PROCESS;
--ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena(REG,938)
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd(LOGICAL,939)
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b <= VCC_q;
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt(COUNTER,929)
-- every=1, low=0, high=7, step=1, init=1
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END PROCESS;
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i,3));
--ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg(REG,930)
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux(MUX,931)
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s <= VCC_q;
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem(DUALMEM,928)
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia <= oFracX_uid31_uid31_fpSinPiTest_q;
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 8,
width_b => 53,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq(52 downto 0);
--ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg(DELAY,927)
ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q, xout => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q, clk => clk, aclr => areset );
--LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest(BITSELECT,220)@10
LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q(77 downto 0);
LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in(77 downto 0);
--leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest(BITJOIN,221)@10
leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b & GND_q;
--LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest(BITSELECT,204)@9
LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(54 downto 0);
LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in(54 downto 0);
--leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest(BITJOIN,205)@9
leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q;
--LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest(BITSELECT,201)@9
LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in(62 downto 0);
--leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest(BITJOIN,202)@9
leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q;
--LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest(BITSELECT,198)@9
LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(70 downto 0);
LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in(70 downto 0);
--leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest(BITJOIN,199)@9
leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q;
--ozz_uid41_fpSinPiTest(CONSTANT,40)
ozz_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000";
--ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor(LOGICAL,1040)
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q;
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q <= not (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a or ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b);
--ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top(CONSTANT,1036)
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q <= "011";
--ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp(LOGICAL,1037)
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q;
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q);
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q <= "1" when ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a = ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b else "0";
--ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg(REG,1038)
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena(REG,1041)
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q = "1") THEN
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd(LOGICAL,1042)
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q;
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b <= VCC_q;
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a and ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b;
--vStage_uid149_lzcZ_uid51_fpSinPiTest(BITSELECT,148)@4
vStage_uid149_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(14 downto 0);
vStage_uid149_lzcZ_uid51_fpSinPiTest_b <= vStage_uid149_lzcZ_uid51_fpSinPiTest_in(14 downto 0);
--ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt(COUNTER,1032)
-- every=1, low=0, high=3, step=1, init=1
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ELSIF (clk'EVENT AND clk = '1') THEN
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END PROCESS;
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i,2));
--ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg(REG,1033)
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux(MUX,1034)
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s <= VCC_q;
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1043)
ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= vStage_uid149_lzcZ_uid51_fpSinPiTest_b;
ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q;
ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q;
ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 2,
numwords_a => 4,
width_b => 15,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia
);
ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(14 downto 0);
--leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest(BITJOIN,193)@9
leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q;
--X46dto0_uid190_alignedZ_uid52_fpSinPiTest(BITSELECT,189)@4
X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(46 downto 0);
X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in(46 downto 0);
--ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1031)
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b;
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q;
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q;
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 47,
widthad_a => 2,
numwords_a => 4,
width_b => 47,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia
);
ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(46 downto 0);
--leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest(BITJOIN,190)@9
leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q;
--ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor(LOGICAL,1065)
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q;
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q <= not (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a or ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b);
--ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top(CONSTANT,1061)
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q <= "010";
--ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp(LOGICAL,1062)
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q;
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q);
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q <= "1" when ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a = ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b else "0";
--ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg(REG,1063)
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q;
END IF;
END PROCESS;
--ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena(REG,1066)
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd(LOGICAL,1067)
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q;
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b <= VCC_q;
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a and ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b;
--ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt(COUNTER,1057)
-- every=1, low=0, high=2, step=1, init=1
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i = 1 THEN
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i - 2;
ELSE
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i,2));
--ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg(REG,1058)
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux(MUX,1059)
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s <= VCC_q;
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux: PROCESS (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q;
WHEN "1" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem(DUALMEM,1056)
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia <= z_uid49_fpSinPiTest_q;
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q;
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q;
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 79,
widthad_a => 2,
numwords_a => 3,
width_b => 79,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq(78 downto 0);
--ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg(DELAY,1055)
ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q, xout => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset );
--rVStage_uid146_lzcZ_uid51_fpSinPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q;
rVStage_uid146_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_in(78 downto 15);
--reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0(REG,365)@4
reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_b;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid51_fpSinPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q;
vCount_uid147_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q;
vCount_uid147_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid147_lzcZ_uid51_fpSinPiTest_a = vCount_uid147_lzcZ_uid51_fpSinPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g(DELAY,629)@5
ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q, clk => clk, aclr => areset );
--ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b(DELAY,587)@4
ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => vStage_uid149_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q, clk => clk, aclr => areset );
--mO_uid148_lzcZ_uid51_fpSinPiTest(CONSTANT,147)
mO_uid148_lzcZ_uid51_fpSinPiTest_q <= "1111111111111111111111111111111111111111111111111";
--cStage_uid150_lzcZ_uid51_fpSinPiTest(BITJOIN,149)@5
cStage_uid150_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q & mO_uid148_lzcZ_uid51_fpSinPiTest_q;
--ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c(DELAY,589)@4
ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid146_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset );
--vStagei_uid152_lzcZ_uid51_fpSinPiTest(MUX,151)@5
vStagei_uid152_lzcZ_uid51_fpSinPiTest_s <= vCount_uid147_lzcZ_uid51_fpSinPiTest_q;
vStagei_uid152_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid152_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, cStage_uid150_lzcZ_uid51_fpSinPiTest_q)
BEGIN
CASE vStagei_uid152_lzcZ_uid51_fpSinPiTest_s IS
WHEN "0" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= cStage_uid150_lzcZ_uid51_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid154_lzcZ_uid51_fpSinPiTest(BITSELECT,153)@5
rVStage_uid154_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q;
rVStage_uid154_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_in(63 downto 32);
--reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0(REG,366)@5
reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= "00000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_b;
END IF;
END PROCESS;
--vCount_uid155_lzcZ_uid51_fpSinPiTest(LOGICAL,154)@6
vCount_uid155_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q;
vCount_uid155_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q;
vCount_uid155_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid155_lzcZ_uid51_fpSinPiTest_a = vCount_uid155_lzcZ_uid51_fpSinPiTest_b else "0";
--ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f(DELAY,628)@6
ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid155_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q, clk => clk, aclr => areset );
--vStage_uid156_lzcZ_uid51_fpSinPiTest(BITSELECT,155)@5
vStage_uid156_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q(31 downto 0);
vStage_uid156_lzcZ_uid51_fpSinPiTest_b <= vStage_uid156_lzcZ_uid51_fpSinPiTest_in(31 downto 0);
--ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d(DELAY,596)@5
ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid156_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset );
--ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c(DELAY,595)@5
ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid154_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset );
--vStagei_uid158_lzcZ_uid51_fpSinPiTest(MUX,157)@6
vStagei_uid158_lzcZ_uid51_fpSinPiTest_s <= vCount_uid155_lzcZ_uid51_fpSinPiTest_q;
vStagei_uid158_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid158_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q)
BEGIN
CASE vStagei_uid158_lzcZ_uid51_fpSinPiTest_s IS
WHEN "0" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q;
WHEN OTHERS => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid160_lzcZ_uid51_fpSinPiTest(BITSELECT,159)@6
rVStage_uid160_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q;
rVStage_uid160_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_in(31 downto 16);
--reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0(REG,367)@6
reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_b;
END IF;
END PROCESS;
--vCount_uid161_lzcZ_uid51_fpSinPiTest(LOGICAL,160)@7
vCount_uid161_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q;
vCount_uid161_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q;
vCount_uid161_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid161_lzcZ_uid51_fpSinPiTest_a = vCount_uid161_lzcZ_uid51_fpSinPiTest_b else "0";
--ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e(DELAY,627)@7
ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid161_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q, clk => clk, aclr => areset );
--vStage_uid162_lzcZ_uid51_fpSinPiTest(BITSELECT,161)@6
vStage_uid162_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q(15 downto 0);
vStage_uid162_lzcZ_uid51_fpSinPiTest_b <= vStage_uid162_lzcZ_uid51_fpSinPiTest_in(15 downto 0);
--ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d(DELAY,602)@6
ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => vStage_uid162_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset );
--ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c(DELAY,601)@6
ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => rVStage_uid160_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset );
--vStagei_uid164_lzcZ_uid51_fpSinPiTest(MUX,163)@7
vStagei_uid164_lzcZ_uid51_fpSinPiTest_s <= vCount_uid161_lzcZ_uid51_fpSinPiTest_q;
vStagei_uid164_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid164_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q)
BEGIN
CASE vStagei_uid164_lzcZ_uid51_fpSinPiTest_s IS
WHEN "0" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q;
WHEN OTHERS => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid166_lzcZ_uid51_fpSinPiTest(BITSELECT,165)@7
rVStage_uid166_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q;
rVStage_uid166_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0(REG,368)@7
reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= "00000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b;
END IF;
END PROCESS;
--vCount_uid167_lzcZ_uid51_fpSinPiTest(LOGICAL,166)@8
vCount_uid167_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q;
vCount_uid167_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q;
vCount_uid167_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid167_lzcZ_uid51_fpSinPiTest_a = vCount_uid167_lzcZ_uid51_fpSinPiTest_b else "0";
--vStage_uid168_lzcZ_uid51_fpSinPiTest(BITSELECT,167)@7
vStage_uid168_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q(7 downto 0);
vStage_uid168_lzcZ_uid51_fpSinPiTest_b <= vStage_uid168_lzcZ_uid51_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3(REG,369)@7
reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= "00000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= vStage_uid168_lzcZ_uid51_fpSinPiTest_b;
END IF;
END PROCESS;
--reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2(REG,370)@7
reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= "00000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b;
END IF;
END PROCESS;
--vStagei_uid170_lzcZ_uid51_fpSinPiTest(MUX,169)@8
vStagei_uid170_lzcZ_uid51_fpSinPiTest_s <= vCount_uid167_lzcZ_uid51_fpSinPiTest_q;
vStagei_uid170_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid170_lzcZ_uid51_fpSinPiTest_s, reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q, reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid170_lzcZ_uid51_fpSinPiTest_s IS
WHEN "0" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid172_lzcZ_uid51_fpSinPiTest(BITSELECT,171)@8
rVStage_uid172_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q;
rVStage_uid172_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_in(7 downto 4);
--vCount_uid173_lzcZ_uid51_fpSinPiTest(LOGICAL,172)@8
vCount_uid173_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b;
vCount_uid173_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q;
vCount_uid173_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid173_lzcZ_uid51_fpSinPiTest_a = vCount_uid173_lzcZ_uid51_fpSinPiTest_b else "0";
--vStage_uid174_lzcZ_uid51_fpSinPiTest(BITSELECT,173)@8
vStage_uid174_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q(3 downto 0);
vStage_uid174_lzcZ_uid51_fpSinPiTest_b <= vStage_uid174_lzcZ_uid51_fpSinPiTest_in(3 downto 0);
--vStagei_uid176_lzcZ_uid51_fpSinPiTest(MUX,175)@8
vStagei_uid176_lzcZ_uid51_fpSinPiTest_s <= vCount_uid173_lzcZ_uid51_fpSinPiTest_q;
vStagei_uid176_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid51_fpSinPiTest_s, rVStage_uid172_lzcZ_uid51_fpSinPiTest_b, vStage_uid174_lzcZ_uid51_fpSinPiTest_b)
BEGIN
CASE vStagei_uid176_lzcZ_uid51_fpSinPiTest_s IS
WHEN "0" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b;
WHEN "1" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= vStage_uid174_lzcZ_uid51_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid178_lzcZ_uid51_fpSinPiTest(BITSELECT,177)@8
rVStage_uid178_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q;
rVStage_uid178_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_in(3 downto 2);
--vCount_uid179_lzcZ_uid51_fpSinPiTest(LOGICAL,178)@8
vCount_uid179_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b;
vCount_uid179_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q;
vCount_uid179_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid179_lzcZ_uid51_fpSinPiTest_a = vCount_uid179_lzcZ_uid51_fpSinPiTest_b else "0";
--vStage_uid180_lzcZ_uid51_fpSinPiTest(BITSELECT,179)@8
vStage_uid180_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q(1 downto 0);
vStage_uid180_lzcZ_uid51_fpSinPiTest_b <= vStage_uid180_lzcZ_uid51_fpSinPiTest_in(1 downto 0);
--vStagei_uid182_lzcZ_uid51_fpSinPiTest(MUX,181)@8
vStagei_uid182_lzcZ_uid51_fpSinPiTest_s <= vCount_uid179_lzcZ_uid51_fpSinPiTest_q;
vStagei_uid182_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid51_fpSinPiTest_s, rVStage_uid178_lzcZ_uid51_fpSinPiTest_b, vStage_uid180_lzcZ_uid51_fpSinPiTest_b)
BEGIN
CASE vStagei_uid182_lzcZ_uid51_fpSinPiTest_s IS
WHEN "0" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b;
WHEN "1" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= vStage_uid180_lzcZ_uid51_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid184_lzcZ_uid51_fpSinPiTest(BITSELECT,183)@8
rVStage_uid184_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid51_fpSinPiTest_q;
rVStage_uid184_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_in(1 downto 1);
--vCount_uid185_lzcZ_uid51_fpSinPiTest(LOGICAL,184)@8
vCount_uid185_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_b;
vCount_uid185_lzcZ_uid51_fpSinPiTest_b <= GND_q;
vCount_uid185_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid51_fpSinPiTest_a = vCount_uid185_lzcZ_uid51_fpSinPiTest_b else "0";
--r_uid186_lzcZ_uid51_fpSinPiTest(BITJOIN,185)@8
r_uid186_lzcZ_uid51_fpSinPiTest_q <= ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q & ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q & ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q & vCount_uid167_lzcZ_uid51_fpSinPiTest_q & vCount_uid173_lzcZ_uid51_fpSinPiTest_q & vCount_uid179_lzcZ_uid51_fpSinPiTest_q & vCount_uid185_lzcZ_uid51_fpSinPiTest_q;
--leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest(BITSELECT,195)@8
leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q;
leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in(6 downto 5);
--reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1(REG,371)@8
reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b;
END IF;
END PROCESS;
--leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest(MUX,196)@9
leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q;
leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q, leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q;
WHEN "01" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ozz_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest(BITSELECT,206)@8
leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1(REG,372)@8
reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b;
END IF;
END PROCESS;
--leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest(MUX,207)@9
leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q;
leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s, leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q;
WHEN "01" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest(BITSELECT,215)@9
LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(72 downto 0);
LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in(72 downto 0);
--leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest(BITJOIN,216)@9
leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q;
--reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5(REG,374)@9
reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q;
END IF;
END PROCESS;
--LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest(BITSELECT,212)@9
LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in(74 downto 0);
--leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest(BITJOIN,213)@9
leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q;
--reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4(REG,375)@9
reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q;
END IF;
END PROCESS;
--LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest(BITSELECT,209)@9
LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(76 downto 0);
LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in(76 downto 0);
--leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest(BITJOIN,210)@9
leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q;
--reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3(REG,376)@9
reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q;
END IF;
END PROCESS;
--reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2(REG,377)@9
reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest(BITSELECT,217)@8
leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1(REG,373)@8
reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b(DELAY,657)@9
ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset );
--leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest(MUX,218)@10
leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q;
leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s, reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q, reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q, reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q, reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q)
BEGIN
CASE leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q;
WHEN "10" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q;
WHEN "11" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q;
WHEN OTHERS => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest(BITSELECT,222)@8
leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in(0 downto 0);
--reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1(REG,378)@8
reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b(DELAY,665)@9
ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset );
--leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest(MUX,223)@10
leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q;
leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s, leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q, leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q)
BEGIN
CASE leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s IS
WHEN "0" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q;
WHEN "1" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid53_fpSinPiTest(BITSELECT,52)@10
alignedZLow_uid53_fpSinPiTest_in <= leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q;
alignedZLow_uid53_fpSinPiTest_b <= alignedZLow_uid53_fpSinPiTest_in(78 downto 27);
--pHardCase_uid54_fpSinPiTest(BITJOIN,53)@10
pHardCase_uid54_fpSinPiTest_q <= alignedZLow_uid53_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b(DELAY,474)@0
ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q, clk => clk, aclr => areset );
--p_uid55_fpSinPiTest(MUX,54)@10
p_uid55_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q;
p_uid55_fpSinPiTest: PROCESS (p_uid55_fpSinPiTest_s, pHardCase_uid54_fpSinPiTest_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q)
BEGIN
CASE p_uid55_fpSinPiTest_s IS
WHEN "0" => p_uid55_fpSinPiTest_q <= pHardCase_uid54_fpSinPiTest_q;
WHEN "1" => p_uid55_fpSinPiTest_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q;
WHEN OTHERS => p_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt(COUNTER,1121)
-- every=1, low=0, high=22, step=1, init=1
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i = 21 THEN
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq = '1') THEN
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i - 22;
ELSE
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i,5));
--ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg(REG,1122)
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux(MUX,1123)
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s <= VCC_q;
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux: PROCESS (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q;
WHEN "1" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem(DUALMEM,1120)
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 <= areset;
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia <= p_uid55_fpSinPiTest_q;
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q;
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q;
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 5,
numwords_a => 23,
width_b => 53,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq,
address_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa,
data_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia
);
ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq(52 downto 0);
--mul2xSinRes_uid69_fpSinPiTest_a_1(BITSELECT,316)@34
mul2xSinRes_uid69_fpSinPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q);
mul2xSinRes_uid69_fpSinPiTest_a_1_b <= mul2xSinRes_uid69_fpSinPiTest_a_1_in(53 downto 27);
--reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0(REG,424)@34
reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b;
END IF;
END PROCESS;
--mul2xSinRes_uid69_fpSinPiTest_a1_b1(MULT,322)@35
mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_b);
mul2xSinRes_uid69_fpSinPiTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= (others => '0');
mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= (others => '0');
mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q;
mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q;
mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr);
END IF;
END PROCESS;
mul2xSinRes_uid69_fpSinPiTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1(BITSELECT,329)@38
mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q(26 downto 0);
mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in(26 downto 0);
--reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1(REG,425)@34
reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b;
END IF;
END PROCESS;
--mul2xSinRes_uid69_fpSinPiTest_a_0(BITSELECT,315)@34
mul2xSinRes_uid69_fpSinPiTest_a_0_in <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q(26 downto 0);
mul2xSinRes_uid69_fpSinPiTest_a_0_b <= mul2xSinRes_uid69_fpSinPiTest_a_0_in(26 downto 0);
--reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0(REG,426)@34
reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b;
END IF;
END PROCESS;
--mul2xSinRes_uid69_fpSinPiTest_a0_b1(MULT,321)@35
mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_b);
mul2xSinRes_uid69_fpSinPiTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= (others => '0');
mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= (others => '0');
mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q;
mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q;
mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr);
END IF;
END PROCESS;
mul2xSinRes_uid69_fpSinPiTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1(BITSELECT,327)@38
mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q(26 downto 0);
mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in(26 downto 0);
--mul2xSinRes_uid69_fpSinPiTest_zero_36(CONSTANT,332)
mul2xSinRes_uid69_fpSinPiTest_zero_36_q <= "000000000000000000000000000";
--mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2(BITJOIN,336)@38
mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q;
--mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1(BITSELECT,328)@38
mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q;
mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in(53 downto 27);
--mul2xSinRes_uid69_fpSinPiTest_b_0(BITSELECT,317)@34
mul2xSinRes_uid69_fpSinPiTest_b_0_in <= multRightOp_uid68_fpSinPiTest_q(26 downto 0);
mul2xSinRes_uid69_fpSinPiTest_b_0_b <= mul2xSinRes_uid69_fpSinPiTest_b_0_in(26 downto 0);
--reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1(REG,421)@34
reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b;
END IF;
END PROCESS;
--reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0(REG,422)@34
reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b;
END IF;
END PROCESS;
--mul2xSinRes_uid69_fpSinPiTest_a1_b0(MULT,320)@35
mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_b);
mul2xSinRes_uid69_fpSinPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= (others => '0');
mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= (others => '0');
mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q;
mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q;
mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr);
END IF;
END PROCESS;
mul2xSinRes_uid69_fpSinPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0(BITSELECT,325)@38
mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q(26 downto 0);
mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in(26 downto 0);
--mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1(BITJOIN,335)@38
mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q;
--mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC(LOGICAL,340)@38
mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q;
mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q;
mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b;
--mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1(BITSELECT,330)@38
mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q;
mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in(53 downto 27);
--mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0(BITSELECT,326)@38
mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q;
mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in(53 downto 27);
--reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1(REG,419)@34
reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b;
END IF;
END PROCESS;
--reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0(REG,420)@34
reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b;
END IF;
END PROCESS;
--mul2xSinRes_uid69_fpSinPiTest_a0_b0(MULT,319)@35
mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_b);
mul2xSinRes_uid69_fpSinPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= (others => '0');
mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= (others => '0');
mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q;
mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q;
mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr);
END IF;
END PROCESS;
mul2xSinRes_uid69_fpSinPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0(BITSELECT,324)@38
mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q;
mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in(53 downto 27);
--mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0(BITSELECT,323)@38
mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q(26 downto 0);
mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in(26 downto 0);
--mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0(BITJOIN,334)@38
mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b;
--mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC(LOGICAL,339)@38
mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q;
mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q;
mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b;
--mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB(LOGICAL,338)@38
mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q;
mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q;
mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b;
--mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne(LOGICAL,341)@38
mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q;
mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q;
mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q;
mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c;
--mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS(BITSELECT,342)@38
mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q(106 downto 0);
mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in(106 downto 0);
--mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ(BITJOIN,343)@38
mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b & GND_q;
--mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b(BITJOIN,350)@38
mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q;
--mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b(BITSELECT,353)@38
mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q;
mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(88 downto 0);
mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(108 downto 89);
--mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne(LOGICAL,337)@38
mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q;
mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q;
mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q;
mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c;
--mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a(BITJOIN,348)@38
mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q;
--mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a(BITSELECT,352)@38
mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q;
mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(88 downto 0);
mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(108 downto 89);
--mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2(ADD,354)@38
mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin <= GND_q;
mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b) & '1';
mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin(0);
mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b));
END IF;
END PROCESS;
mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(90);
mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(89 downto 1);
--ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b(DELAY,822)@38
ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : dspba_delay
GENERIC MAP ( width => 20, depth => 1 )
PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset );
--ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a(DELAY,821)@38
ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : dspba_delay
GENERIC MAP ( width => 20, depth => 1 )
PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset );
--mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2(ADD,355)@39
mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c;
mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q) & '1';
mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin(0);
mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b));
END IF;
END PROCESS;
mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o(20 downto 1);
--ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a(DELAY,824)@39
ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a : dspba_delay
GENERIC MAP ( width => 89, depth => 1 )
PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset );
--mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q(BITJOIN,356)@40
mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q;
--normBit_uid70_fpSinPiTest(BITSELECT,69)@40
normBit_uid70_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(106 downto 0);
normBit_uid70_fpSinPiTest_b <= normBit_uid70_fpSinPiTest_in(106 downto 106);
--ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c(DELAY,497)@40
ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => normBit_uid70_fpSinPiTest_b, xout => ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q, clk => clk, aclr => areset );
--rndExpUpdate_uid75_uid76_fpSinPiTest(BITJOIN,75)@41
rndExpUpdate_uid75_uid76_fpSinPiTest_q <= ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor(LOGICAL,976)
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q <= not (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a or ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b);
--ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top(CONSTANT,972)
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q <= "011100";
--ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp(LOGICAL,973)
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q;
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a = ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg(REG,974)
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena(REG,977)
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd(LOGICAL,978)
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b <= VCC_q;
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a and ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem(DUALMEM,941)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia <= expX_uid6_fpSinPiTest_b;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 7,
width_b => 11,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq(10 downto 0);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg(DELAY,940)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q, clk => clk, aclr => areset );
--expXP1_uid58_fpSinPiTest(ADD,57)@9
expXP1_uid58_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q);
expXP1_uid58_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & VCC_q);
expXP1_uid58_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid58_fpSinPiTest_a) + UNSIGNED(expXP1_uid58_fpSinPiTest_b));
expXP1_uid58_fpSinPiTest_q <= expXP1_uid58_fpSinPiTest_o(11 downto 0);
--expXP1R_uid59_fpSinPiTest(BITSELECT,58)@9
expXP1R_uid59_fpSinPiTest_in <= expXP1_uid58_fpSinPiTest_q(10 downto 0);
expXP1R_uid59_fpSinPiTest_b <= expXP1R_uid59_fpSinPiTest_in(10 downto 0);
--reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1(REG,427)@8
reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= "0000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= r_uid186_lzcZ_uid51_fpSinPiTest_q;
END IF;
END PROCESS;
--expHardCase_uid57_fpSinPiTest(SUB,56)@9
expHardCase_uid57_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid27_fpSinPiTest_q);
expHardCase_uid57_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000" & reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q);
expHardCase_uid57_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid57_fpSinPiTest_a) - UNSIGNED(expHardCase_uid57_fpSinPiTest_b));
expHardCase_uid57_fpSinPiTest_q <= expHardCase_uid57_fpSinPiTest_o(11 downto 0);
--expHardCaseR_uid60_fpSinPiTest(BITSELECT,59)@9
expHardCaseR_uid60_fpSinPiTest_in <= expHardCase_uid57_fpSinPiTest_q(10 downto 0);
expHardCaseR_uid60_fpSinPiTest_b <= expHardCaseR_uid60_fpSinPiTest_in(10 downto 0);
--ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b(DELAY,481)@0
ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 9 )
PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q, clk => clk, aclr => areset );
--expP_uid61_fpSinPiTest(MUX,60)@9
expP_uid61_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q;
expP_uid61_fpSinPiTest: PROCESS (expP_uid61_fpSinPiTest_s, expHardCaseR_uid60_fpSinPiTest_b, expXP1R_uid59_fpSinPiTest_b)
BEGIN
CASE expP_uid61_fpSinPiTest_s IS
WHEN "0" => expP_uid61_fpSinPiTest_q <= expHardCaseR_uid60_fpSinPiTest_b;
WHEN "1" => expP_uid61_fpSinPiTest_q <= expXP1R_uid59_fpSinPiTest_b;
WHEN OTHERS => expP_uid61_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt(COUNTER,968)
-- every=1, low=0, high=28, step=1, init=1
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i = 27 THEN
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i - 28;
ELSE
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i,5));
--ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg(REG,969)
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux(MUX,970)
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s <= VCC_q;
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem(DUALMEM,967)
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia <= expP_uid61_fpSinPiTest_q;
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 29,
width_b => 11,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq(10 downto 0);
--ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg(DELAY,966)
ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q, xout => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset );
--highRes_uid71_fpSinPiTest(BITSELECT,70)@40
highRes_uid71_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(105 downto 0);
highRes_uid71_fpSinPiTest_b <= highRes_uid71_fpSinPiTest_in(105 downto 53);
--lowRes_uid72_fpSinPiTest(BITSELECT,71)@40
lowRes_uid72_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(104 downto 0);
lowRes_uid72_fpSinPiTest_b <= lowRes_uid72_fpSinPiTest_in(104 downto 52);
--fracRCompPreRnd_uid73_fpSinPiTest(MUX,72)@40
fracRCompPreRnd_uid73_fpSinPiTest_s <= normBit_uid70_fpSinPiTest_b;
fracRCompPreRnd_uid73_fpSinPiTest: PROCESS (fracRCompPreRnd_uid73_fpSinPiTest_s, lowRes_uid72_fpSinPiTest_b, highRes_uid71_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid73_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid73_fpSinPiTest_q <= lowRes_uid72_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid73_fpSinPiTest_q <= highRes_uid71_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid73_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid74_uid74_fpSinPiTest(BITJOIN,73)@40
expFracPreRnd_uid74_uid74_fpSinPiTest_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q & fracRCompPreRnd_uid73_fpSinPiTest_q;
--reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0(REG,428)@40
reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= expFracPreRnd_uid74_uid74_fpSinPiTest_q;
END IF;
END PROCESS;
--expFracComp_uid77_fpSinPiTest(ADD,76)@41
expFracComp_uid77_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q);
expFracComp_uid77_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid75_uid76_fpSinPiTest_q);
expFracComp_uid77_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid77_fpSinPiTest_a) + UNSIGNED(expFracComp_uid77_fpSinPiTest_b));
expFracComp_uid77_fpSinPiTest_q <= expFracComp_uid77_fpSinPiTest_o(64 downto 0);
--expRComp_uid79_fpSinPiTest(BITSELECT,78)@41
expRComp_uid79_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(63 downto 0);
expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(63 downto 53);
--ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor(LOGICAL,1015)
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q;
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q <= not (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a or ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b);
--ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top(CONSTANT,1011)
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q <= "0100010";
--ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp(LOGICAL,1012)
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q;
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q);
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q <= "1" when ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a = ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b else "0";
--ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg(REG,1013)
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena(REG,1016)
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q = "1") THEN
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd(LOGICAL,1017)
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q;
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b <= VCC_q;
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a and ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b;
--reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1(REG,429)@2
reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= xIsInt_uid83_fpSinPiTest_q;
END IF;
END PROCESS;
--ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c(DELAY,516)@0
ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q, xout => ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q, clk => clk, aclr => areset );
--ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b(DELAY,515)@0
ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => expXIsZero_uid15_fpSinPiTest_q, xout => ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q, clk => clk, aclr => areset );
--reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0(REG,361)@2
reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= xIsInt_uid83_fpSinPiTest_q;
END IF;
END PROCESS;
--excRZero_uid87_fpSinPiTest(LOGICAL,86)@3
excRZero_uid87_fpSinPiTest_a <= reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q;
excRZero_uid87_fpSinPiTest_b <= ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q;
excRZero_uid87_fpSinPiTest_c <= ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q;
excRZero_uid87_fpSinPiTest_q <= excRZero_uid87_fpSinPiTest_a or excRZero_uid87_fpSinPiTest_b or excRZero_uid87_fpSinPiTest_c;
--Or2ExcRZeroXIsInt_uid92_fpSinPiTest(LOGICAL,91)@3
Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a <= excRZero_uid87_fpSinPiTest_q;
Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b <= reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q;
Or2ExcRZeroXIsInt_uid92_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a or Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b;
END IF;
END PROCESS;
--ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt(COUNTER,1007)
-- every=1, low=0, high=34, step=1, init=1
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i = 33 THEN
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i - 34;
ELSE
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i,6));
--ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg(REG,1008)
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux(MUX,1009)
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s <= VCC_q;
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux: PROCESS (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem(DUALMEM,1006)
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q;
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q;
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q;
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 35,
width_b => 1,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq,
address_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa,
data_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia
);
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq(0 downto 0);
--ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg(DELAY,1005)
ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q, xout => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset );
--expRPostExc1_uid95_fpSinPiTest(MUX,94)@41
expRPostExc1_uid95_fpSinPiTest_s <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q;
expRPostExc1_uid95_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
CASE expRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid95_fpSinPiTest_q <= expRComp_uid79_fpSinPiTest_b;
WHEN "1" => expRPostExc1_uid95_fpSinPiTest_q <= cstAllZWE_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END PROCESS;
--InvXIntExp_uid84_fpSinPiTest(LOGICAL,83)@2
InvXIntExp_uid84_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q;
InvXIntExp_uid84_fpSinPiTest_q <= not InvXIntExp_uid84_fpSinPiTest_a;
--join_uid42_fpSinPiTest(BITJOIN,41)@2
join_uid42_fpSinPiTest_q <= VCC_q & ozz_uid41_fpSinPiTest_q;
--reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0(REG,359)@1
reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b;
END IF;
END PROCESS;
--yIsZero_uid43_fpSinPiTest(LOGICAL,42)@2
yIsZero_uid43_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q;
yIsZero_uid43_fpSinPiTest_b <= join_uid42_fpSinPiTest_q;
yIsZero_uid43_fpSinPiTest_q <= "1" when yIsZero_uid43_fpSinPiTest_a = yIsZero_uid43_fpSinPiTest_b else "0";
--And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest(LOGICAL,85)@2
And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q;
And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b <= yIsZero_uid43_fpSinPiTest_q;
And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c <= InvSinXIsX_uid80_fpSinPiTest_q;
And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d <= InvXIntExp_uid84_fpSinPiTest_q;
And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d;
--Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest(LOGICAL,95)@1
Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a <= GND_q;
Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q;
Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q <= Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a or Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b;
--ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a(DELAY,528)@1
ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q, xout => ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q, clk => clk, aclr => areset );
--join_uid97_fpSinPiTest(BITJOIN,96)@2
join_uid97_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q & ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q;
--ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg(DELAY,1195)
ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid97_fpSinPiTest_q, xout => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q, clk => clk, aclr => areset );
--ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem(DUALMEM,1196)
ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q;
ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q;
ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q;
ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 6,
numwords_a => 37,
width_b => 2,
widthad_b => 6,
numwords_b => 37,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1(REG,430)@41
reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q;
END IF;
END PROCESS;
--expRPostExc_uid98_fpSinPiTest(MUX,97)@42
expRPostExc_uid98_fpSinPiTest_s <= reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q;
expRPostExc_uid98_fpSinPiTest: PROCESS (expRPostExc_uid98_fpSinPiTest_s, expRPostExc1_uid95_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid98_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid98_fpSinPiTest_q <= expRPostExc1_uid95_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid98_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid98_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid90_fpSinPiTest(CONSTANT,89)
oneFracRPostExc2_uid90_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000001";
--fracRComp_uid78_fpSinPiTest(BITSELECT,77)@41
fracRComp_uid78_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(52 downto 0);
fracRComp_uid78_fpSinPiTest_b <= fracRComp_uid78_fpSinPiTest_in(52 downto 1);
--ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor(LOGICAL,989)
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q;
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q <= not (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a or ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b);
--ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top(CONSTANT,985)
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q <= "0100001";
--ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp(LOGICAL,986)
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q;
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q);
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q <= "1" when ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a = ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b else "0";
--ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg(REG,987)
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena(REG,990)
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q = "1") THEN
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd(LOGICAL,991)
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q;
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b <= VCC_q;
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a and ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b;
--reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1(REG,362)@3
reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= excRZero_uid87_fpSinPiTest_q;
END IF;
END PROCESS;
--ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a(DELAY,517)@2
ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q, xout => ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q, clk => clk, aclr => areset );
--or_uid88_fpSinPiTest(LOGICAL,87)@4
or_uid88_fpSinPiTest_a <= ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q;
or_uid88_fpSinPiTest_b <= reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q;
or_uid88_fpSinPiTest_c <= GND_q;
or_uid88_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
or_uid88_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
or_uid88_fpSinPiTest_q <= or_uid88_fpSinPiTest_a or or_uid88_fpSinPiTest_b or or_uid88_fpSinPiTest_c;
END IF;
END PROCESS;
--ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt(COUNTER,981)
-- every=1, low=0, high=33, step=1, init=1
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i = 32 THEN
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i - 33;
ELSE
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i,6));
--ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg(REG,982)
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux(MUX,983)
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s <= VCC_q;
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux: PROCESS (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem(DUALMEM,980)
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia <= or_uid88_fpSinPiTest_q;
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q;
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q;
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq,
address_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa,
data_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia
);
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq(0 downto 0);
--ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg(DELAY,979)
ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q, xout => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset );
--fracRPostExc1_uid89_fpSinPiTest(MUX,88)@41
fracRPostExc1_uid89_fpSinPiTest_s <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q;
fracRPostExc1_uid89_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
CASE fracRPostExc1_uid89_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid89_fpSinPiTest_q <= fracRComp_uid78_fpSinPiTest_b;
WHEN "1" => fracRPostExc1_uid89_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END PROCESS;
--ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor(LOGICAL,1002)
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q;
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q <= not (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a or ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b);
--ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top(CONSTANT,998)
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q <= "0100110";
--ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp(LOGICAL,999)
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q;
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q);
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q <= "1" when ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a = ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b else "0";
--ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg(REG,1000)
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena(REG,1003)
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q = "1") THEN
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd(LOGICAL,1004)
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q;
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b <= VCC_q;
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a and ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b;
--ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg(DELAY,992)
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q, xout => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q, clk => clk, aclr => areset );
--ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt(COUNTER,994)
-- every=1, low=0, high=38, step=1, init=1
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i = 37 THEN
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i - 38;
ELSE
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i,6));
--ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg(REG,995)
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux(MUX,996)
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s <= VCC_q;
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux: PROCESS (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem(DUALMEM,993)
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q;
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q;
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q;
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 39,
width_b => 1,
widthad_b => 6,
numwords_b => 39,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq,
address_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa,
data_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia
);
ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq(0 downto 0);
--fracRPostExc_uid91_fpSinPiTest(MUX,90)@42
fracRPostExc_uid91_fpSinPiTest_s <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q;
fracRPostExc_uid91_fpSinPiTest: PROCESS (fracRPostExc_uid91_fpSinPiTest_s, fracRPostExc1_uid89_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid91_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid91_fpSinPiTest_q <= fracRPostExc1_uid89_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid91_fpSinPiTest_q <= oneFracRPostExc2_uid90_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid91_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid105_fpSinPiTest(BITJOIN,104)@42
R_uid105_fpSinPiTest_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q & expRPostExc_uid98_fpSinPiTest_q & fracRPostExc_uid91_fpSinPiTest_q;
--ld_xIn_v_to_xOut_v_nor(LOGICAL,910)
ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q;
ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b);
--ld_xIn_v_to_xOut_v_mem_top(CONSTANT,906)
ld_xIn_v_to_xOut_v_mem_top_q <= "0100111";
--ld_xIn_v_to_xOut_v_cmp(LOGICAL,907)
ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q;
ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q);
ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0";
--ld_xIn_v_to_xOut_v_cmpReg(REG,908)
ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_sticky_ena(REG,911)
ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN
ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,912)
ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q;
ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q;
ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b;
--ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,902)
-- every=1, low=0, high=39, step=1, init=1
ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39;
ELSE
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6));
--ld_xIn_v_to_xOut_v_replace_rdreg(REG,903)
ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_replace_rdmux(MUX,904)
ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q;
ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q)
BEGIN
CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS
WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,914)
ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset;
ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c;
ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 40,
width_b => 8,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_c_to_xOut_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_c_to_xOut_c_replace_mem_iq,
address_a => ld_xIn_c_to_xOut_c_replace_mem_aa,
data_a => ld_xIn_c_to_xOut_c_replace_mem_ia
);
ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0);
--ld_xIn_c_to_xOut_c_outputreg(DELAY,913)
ld_xIn_c_to_xOut_c_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset );
--ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,901)
ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset;
ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v;
ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_v_to_xOut_v_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_v_to_xOut_v_replace_mem_iq,
address_a => ld_xIn_v_to_xOut_v_replace_mem_aa,
data_a => ld_xIn_v_to_xOut_v_replace_mem_ia
);
ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0);
--ld_xIn_v_to_xOut_v_outputreg(DELAY,900)
ld_xIn_v_to_xOut_v_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset );
--xOut(PORTOUT,4)@42
xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q;
xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q;
xOut_0 <= R_uid105_fpSinPiTest_q;
end normal;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_sgn_mul3s.vhd | 10 | 5383 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_SGN_MUL3S.VHD ***
--*** ***
--*** Function: Signed Multiplier - 3 Pipe ***
--*** Stages ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_sgn_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_sgn_mul3s;
ARCHITECTURE SYN OF fp_sgn_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_tan.vhd | 10 | 24604 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_TAN1.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Tangent ***
--*** ***
--*** 23/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
--*** 1. for very top of range (last 256 mantissa lsbs before pi/2), use seperate ROM, not
--*** calculation
--*** 2. if round up starting when X.49999, errors reduce about 25%, need to tweak this, still getting
--*** all -1 errors with bX.111111111. less errors with less tail bits for smaller exponents (like 122)
--*** more for exponent = 126
ENTITY fp_tan IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
signout : OUT STD_LOGIC;
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_tan;
ARCHITECTURE rtl of fp_tan IS
-- input section
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal argumentff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal topargumentff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal middleargumentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanhighmantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanmiddleff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighexponentff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanlowsumff : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal shiftin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal shiftinbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal argumentbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanmiddle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal deltwo_tailnode : STD_LOGIC_VECTOR (19 DOWNTO 1);
signal tantailnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanlowsumnode : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal tanlowmantissabus : STD_LOGIC_VECTOR (56 DOWNTO 1);
-- numerator section
signal tanlowff : STD_LOGIC_VECTOR (56 DOWNTO 1);
signal numeratorsumff : STD_LOGIC_VECTOR (57 DOWNTO 1);
signal tanlowshift : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal numeratormantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numeratorexponentff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal delone_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal delthr_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal deltwo_tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanlowbus : STD_LOGIC_VECTOR (56 DOWNTO 1);
signal numeratorsum : STD_LOGIC_VECTOR (57 DOWNTO 1);
signal numeratorlead, numeratorleadnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal numeratormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numeratorexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
-- denominator section
signal lowleadff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorleadff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multshiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorproductff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatorff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatormantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal inverseexponentff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lowleadnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multshiftnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorproductbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delone_denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatorlead : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delone_tanlowsum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal lowmantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delthr_tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal delfor_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal deltwo_lowlead : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal inverseexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
-- divider section
signal tanexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanexponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanexponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanmantissanormff : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal roundbitff : STD_LOGIC;
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overff : STD_LOGIC;
signal denominatorinverse : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numeratormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multiplier_tan : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal tanmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanmantissanorm : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal tanmantissatail : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal overcheck : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal del_inverseexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal del_numeratorexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanexponent, tanexponentnorm : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutnode : STD_LOGIC_VECTOR (23 DOWNTO 1);
-- small inputs
signal signff : STD_LOGIC_VECTOR (30 DOWNTO 1);
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (28 DOWNTO 1);
signal mantissabase : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (8 DOWNTO 1);
component fp_tanlut1
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
component fp_tanlut2
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
tanfraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_clz36x6
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft56x20
PORT (
inbus : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (56 DOWNTO 1)
);
end component;
component fp_inv_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- convert to fixed point
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
argumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 9 LOOP
topargumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
middleargumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
tanhighmantissaff(k) <= '0';
tanmiddleff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
tanhighexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
tanlowsumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mantissainff <= mantissain;
exponentinff <= exponentin;
argumentff <= argumentbus;
topargumentff <= argumentff(36 DOWNTO 28);
middleargumentff <= argumentff(27 DOWNTO 20);
tanhighmantissaff <= tanhighmantissa;
tanhighexponentff <= tanhighexponent;
tanmiddleff <= tanmiddle;
tanlowsumff <= tanlowsumnode;
END IF;
END IF;
END PROCESS;
shiftin <= 127 - exponentinff;
shiftinbus <= '1' & mantissainff & zerovec(12 DOWNTO 1);
csftin: fp_rsft36
PORT MAP (inbus=>shiftinbus,shift=>shiftin(6 DOWNTO 1),
outbus=>argumentbus);
chtt: fp_tanlut1
PORT MAP (add=>topargumentff,
mantissa=>tanhighmantissa,
exponent=>tanhighexponent);
cltt: fp_tanlut2
PORT MAP (add=>middleargumentff,
tanfraction=>tanmiddle);
-- in level 2, out level 4
dtail: fp_del
GENERIC MAP (width=>19,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>argumentff(19 DOWNTO 1),
cc=>deltwo_tailnode);
tantailnode <= zerovec(8 DOWNTO 1) & deltwo_tailnode & zerovec(9 DOWNTO 1);
tanlowsumnode <= ('0' & tanmiddleff(36 DOWNTO 1)) + ('0' & tantailnode);
tanlowmantissabus <= tanlowsumff & zerovec(19 DOWNTO 1);
--*********************************************
--*** Align two tangent values for addition ***
--*********************************************
padd: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 56 LOOP
tanlowff(k) <= '0';
END LOOP;
FOR k IN 1 TO 57 LOOP
numeratorsumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
numeratormantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
numeratorexponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
tanlowff <= tanlowbus;
numeratorsumff <= numeratorsum;
numeratormantissaff <= numeratormantissa;
numeratorexponentff <= numeratorexponent;
END IF;
END IF;
END PROCESS;
-- in level 4, out level 5
dhxa: fp_del
GENERIC MAP (width=>5,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanhighexponentff,
cc=>delone_tanhighexponent);
-- in level 5, out level 7
dhxb: fp_del
GENERIC MAP (width=>5,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>delone_tanhighexponent,
cc=>delthr_tanhighexponent);
-- in level 4, out level 6
dhm: fp_del
GENERIC MAP (width=>36,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanhighmantissaff,
cc=>deltwo_tanhighmantissa);
-- tan high mantissa format 1.XXX, tan low mantissa format 0.XXXXX
-- tan high exponent base is 119 (top of middle range)
tanlowshift <= delone_tanhighexponent;
crsadd: fp_rsft56x20
PORT MAP (inbus=>tanlowmantissabus,
shift=>tanlowshift,
outbus=>tanlowbus);
numeratorsum <= ('0' & deltwo_tanhighmantissa & zerovec(20 DOWNTO 1)) + ('0' & tanlowff);
-- level 8
-- no pipe between clz and shift as only 6 bit shift
-- middle exponent is 119, and 2 overflow bits in numerator sum, so this will
-- cover downto (119+2-6) = 115 exponent
-- below 115 exponent, output mantissa = input mantissa
clznuma: fp_clz36x6
PORT MAP (mantissa=>numeratorsumff(57 DOWNTO 22),
leading=>numeratorlead);
numeratorleadnode <= "000" & numeratorlead(3 DOWNTO 1); -- force [6:4] to 0 to optimize away logic in LSFT
clsnuma: fp_lsft36
PORT MAP (inbus=>numeratorsumff(57 DOWNTO 22),shift=>numeratorleadnode,
outbus=>numeratormantissa);
numeratorexponent <= delthr_tanhighexponent - numeratorlead(5 DOWNTO 1) + 1;
--gnnadd: FOR k IN 1 TO 36 GENERATE
-- numeratormantissa(k) <= (numeratorsumff(k+20) AND NOT(numeratorsumff(57))) OR
-- (numeratorsumff(k+21) AND numeratorsumff(57));
--END GENERATE;
--numeratorexponent <= delthr_tanhighexponent + ("0000" & numeratorsumff(57));
--***************************************************
--*** Align two tangent values for multiplication ***
--***************************************************
pmul: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 6 LOOP
lowleadff(k) <= '0';
denominatorleadff(k) <= '0';
inverseexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
multshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
denominatorproductff(k) <= '0';
denominatorff(k) <= '0';
denominatormantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowleadff <= lowleadnode;
multshiftff <= multshiftnode;
denominatorproductff <= denominatorproductbus;
denominatorff <= denominator;
denominatorleadff <= denominatorlead;
denominatormantissaff <= denominatormantissa;
inverseexponentff <= inverseexponent;
END IF;
END IF;
END PROCESS;
clzmula: fp_clz36
PORT MAP (mantissa=>tanlowsumff(37 DOWNTO 2),
leading=>lowleadnode);
-- in level 5, out level 6
dlm: fp_del
GENERIC MAP (width=>36,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanlowsumff(37 DOWNTO 2),
cc=>delone_tanlowsum);
clsmula: fp_lsft36
PORT MAP (inbus=>delone_tanlowsum,shift=>lowleadff,
outbus=>lowmantissabus);
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>deltwo_tanhighmantissa,
databb=>lowmantissabus,
result=>multipliernode);
-- in level 5, out level 8
dhxc: fp_del
GENERIC MAP (width=>5,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>delone_tanhighexponent,
cc=>delfor_tanhighexponent);
-- in level 6, out level 8
dlla: fp_del
GENERIC MAP (width=>6,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>lowleadff,
cc=>deltwo_lowlead);
-- msb of lowmantissa(37) is at exponent 0 for highmantissa
multexponent <= ('0' & delfor_tanhighexponent);
--multshiftnode <= "001000" - multexponent + 8 - 1 + lowlead;
multshiftnode <= "001111" - multexponent + deltwo_lowlead;
-- '1.0' is at exponent 8 compared to highmantissa
crsmul: fp_rsft36
PORT MAP (inbus=>multipliernode(72 DOWNTO 37),shift=>multshiftff,
outbus=>denominatorproductbus);
denominator <= ('1' & zerovec(35 DOWNTO 1)) - denominatorproductff;
-- in level 11, out level 12
dda: fp_del
GENERIC MAP (width=>36,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>denominatorff,
cc=>delone_denominator);
clzmulb: fp_clz36
PORT MAP (mantissa=>denominatorff,
leading=>denominatorlead);
-- denominatormantissa level 12, (denominatormantissaff level 13)
clsmulb: fp_lsft36
PORT MAP (inbus=>delone_denominator,shift=>denominatorleadff,
outbus=>denominatormantissa);
denominatorexponent <= denominatorleadff; -- actually inverse of exponent i.e. 4 => -4, so sign does not have to change after inverting
-- inverseexponentff level 13
inverseexponent <= denominatorexponent - 1;
--****************************
--*** main divider section ***
--****************************
pdiv: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
tanexponentff(k) <= '0';
tanexponentnormff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 24 LOOP
tanmantissanormff(k) <= '0';
END LOOP;
roundbitff <= '0';
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
overff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
tanexponentff <= tanexponent;
tanmantissanormff <= tanmantissanorm; -- level 29
tanexponentnormff <= tanexponentnorm; -- level 29
overff <= overcheck(24);
-- round up if 0.4999
roundbitff <= tanmantissanorm(1) OR
(tanmantissatail(9) AND
tanmantissatail(8) AND tanmantissatail(7) AND
tanmantissatail(6) AND tanmantissatail(5) AND
tanmantissatail(4) AND tanmantissatail(3) AND
tanmantissatail(2) AND tanmantissatail(1));
mantissaoutff <= mantissaoutnode; -- level 30
exponentoutff <= exponentoutnode; -- level 30
END IF;
END IF;
END PROCESS;
-- latency 12
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
-- level 13 in, level 25 out
cinv: fp_inv_core
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>denominatormantissaff,
quotient=>denominatorinverse);
-- level 8 in, level 25 out
dnuma: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>numeratormantissaff,
cc=>del_numeratormantissa);
-- level 25 in, level 28 out
cmt: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numeratormantissa,
databb=>denominatorinverse,
result=>multiplier_tan);
tanmantissa <= multiplier_tan(72 DOWNTO 37);
gmna: FOR k IN 1 TO 24 GENERATE
tanmantissanorm(k) <= (tanmantissa(k+9) AND NOT(tanmantissa(35))) OR
(tanmantissa(k+10) AND tanmantissa(35));
END GENERATE;
gmnb: FOR k IN 1 TO 9 GENERATE
tanmantissatail(k) <= (tanmantissa(k) AND NOT(tanmantissa(35))) OR
(tanmantissa(k+1) AND tanmantissa(35));
END GENERATE;
overcheck(1) <= tanmantissanorm(1);
gova: FOR k IN 2 TO 24 GENERATE
overcheck(k) <= overcheck(k-1) AND tanmantissanorm(k);
END GENERATE;
-- level 13 in, level 27 out
ddena: fp_del
GENERIC MAP (width=>6,pipes=>14)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>inverseexponentff,
cc=>del_inverseexponent);
-- level 8 in, level 27 out
dnumb: fp_del
GENERIC MAP (width=>5,pipes=>19)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>numeratorexponentff,
cc=>del_numeratorexponent);
tanexponent <= "01110111" +
(del_numeratorexponent(5) & del_numeratorexponent(5) & del_numeratorexponent(5) & del_numeratorexponent) +
(del_inverseexponent(6) & del_inverseexponent(6) & del_inverseexponent); -- 119 + exponent
tanexponentnorm <= tanexponentff + tanmantissa(35);
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>29)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>29)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 30 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 28 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= signin;
FOR k IN 2 TO 30 LOOP
signff(k) <= signff(k-1);
END LOOP;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 28 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--mantissabase(1) <= (tanmantissanormff(1) AND NOT(small_inputff(28)));
mantissabase(1) <= (roundbitff AND NOT(small_inputff(28)));
gmba: FOR k IN 2 TO 24 GENERATE
mantissabase(k) <= (small_mantissa(k-1) AND small_inputff(28)) OR
(tanmantissanormff(k) AND NOT(small_inputff(28)));
END GENERATE;
gxba: FOR k IN 1 TO 8 GENERATE
exponentbase(k) <= (small_exponent(k) AND small_inputff(28)) OR
(tanexponentnormff(k) AND NOT(small_inputff(28)));
END GENERATE;
mantissaoutnode <= mantissabase(24 DOWNTO 2) + mantissabase(1);
exponentoutnode <= exponentbase + (overff AND NOT(small_inputff(28)));
--***************
--*** OUTPUTS ***
--***************
signout <= signff(30);
mantissaout <= mantissaoutff;
exponentout <= exponentoutff;
END rtl;
| mit |
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