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PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_v12_0/hdl/builtin/builtin_prim.vhd | 5 | 111502 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 80800)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_defaults.vhd | 11 | 32589 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22384)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_defaults.vhd | 11 | 32589 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22384)
`protect data_block
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`protect end_protected
| mit |
Nic30/hwtHdlParsers | hwtHdlParsers/tests/vhdlCodesign/vhdl/tripleNestedPackage/b.vhd | 1 | 44 | use work.c.all;
package b is
end package;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/blk_mem_gen_v8_2/hdl/blk_mem_gen_mux.vhd | 11 | 97172 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 70192)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_v8_2/hdl/blk_mem_gen_mux.vhd | 11 | 97172 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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8mCAPTmMHA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 70192)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/blk_mem_gen_v8_2/hdl/blk_mem_axi_read_fsm.vhd | 11 | 83900 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
mjgAOmmqpUt1V+Rhx55PcsZFO50ANSJzUkq4iFT2ky0C1WINgCoS9aiI2Aoor0/FtBYKfc1lhyAC
A2yQaY0u8g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 60368)
`protect data_block
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3qoGK+g=
`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/hdl/common/output_blk.vhd | 5 | 27142 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PGHFNiR3BP7XGoNdt+sZaTmGZWIHImrHr96onkZN6M2wSWG6MSzLnz3xTdAOzrEb6GdU/I3SQ1/j
1+lecrUFNA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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zpyCvRauvZTEG5j+scE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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iHmVPY6nZXLj5z0oMk8+Q+8ka0admCYkTIFJLA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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1tAeewMQfrB3dx/2BXQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/rtl/switch_port/aeg_design_switch_port.vhd | 2 | 23193 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 13:56:52
-- Design Name:
-- Module Name: aeg_design_0_switch_port
-- Description: This module describes one port for the Ethernet switch
-- It consists of:
-- - The rx_path: the logic processing the received data before
-- sending to the fabric
-- - The tx_path: the logic receiving data from the fabric and
-- handling the transmission of frames
-- - The TEMAC receives/sends frames
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity aeg_design_0_switch_port is
Generic (
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer;
PORT_ID : integer
);
Port (
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
-- Receiver Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
-- RX Switch Fabric Intrface
------------------------------------------
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- Transmitter Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
-- TX Switch Fabric Intrface
---------------------------------------------
tx_path_clock : in std_logic;
tx_path_resetn : in std_logic;
tx_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
tx_in_valid : in std_logic;
tx_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
tx_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
tx_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_in_req : in std_logic;
tx_in_accept_frame : out std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
phy_interrupt_n : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic
);
end aeg_design_0_switch_port;
architecture rtl of aeg_design_0_switch_port is
component tri_mode_ethernet_mac_block
Generic (
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
-- mac to rxpath interface
------------------------------------------
mac_out_clock : in std_logic;
mac_out_resetn : in std_logic;
mac_out_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
mac_out_valid : out std_logic;
mac_out_last : out std_logic;
mac_out_error : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
-- txpath to mac interface
---------------------------------------------
mac_in_clock : in std_logic;
mac_in_resetn : in std_logic;
mac_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
mac_in_valid : in std_logic;
mac_in_ready : out std_logic;
mac_in_last : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_interrupt : out std_logic
);
end component;
component config_mac_phy_sm
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
phy_interrupt_n : in std_logic;
mac_interrupt : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_awvalid : out std_logic := '0';
s_axi_awready : in std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0) := (others => '0');
s_axi_wvalid : out std_logic := '0';
s_axi_wready : in std_logic;
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic;
s_axi_araddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_arvalid : out std_logic := '0';
s_axi_arready : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic := '0'
);
end component;
component switch_port_rx_path is
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
PORT_ID : integer
);
Port (
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
-- mac to rx_path interface
rx_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_in_valid : in std_logic;
rx_in_last : in std_logic;
rx_in_error : in std_logic;
rx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- rx_path interface to fabric
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0)
);
end component;
component switch_port_tx_path is
Generic (
FABRIC_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
tx_path_clock : in std_logic;
tx_path_resetn : in std_logic;
-- tx_path interface to fabric
tx_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
tx_in_valid : in std_logic;
tx_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
tx_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
tx_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_in_req : in std_logic;
tx_in_accept_frame : out std_logic;
-- timestamp
tx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- tx_path interface to mac
tx_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
tx_out_valid : out std_logic;
tx_out_ready : in std_logic;
tx_out_last : out std_logic
);
end component;
signal mac2rx_data_sig : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
signal mac2rx_valid_sig : std_logic;
signal mac2rx_last_sig : std_logic;
signal mac2rx_error_sig : std_logic;
signal tx2mac_data_sig : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
signal tx2mac_valid_sig : std_logic;
signal tx2mac_ready_sig : std_logic;
signal tx2mac_last_sig : std_logic;
signal s_axi_awaddr : std_logic_vector(11 downto 0) := (others => '0');
signal s_axi_awvalid : std_logic := '0';
signal s_axi_awready : std_logic := '0';
signal s_axi_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_wvalid : std_logic := '0';
signal s_axi_wready : std_logic := '0';
signal s_axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal s_axi_bvalid : std_logic := '0';
signal s_axi_bready : std_logic := '0';
signal s_axi_araddr : std_logic_vector(11 downto 0) := (others => '0');
signal s_axi_arvalid : std_logic := '0';
signal s_axi_arready : std_logic := '0';
signal s_axi_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal s_axi_rvalid : std_logic := '0';
signal s_axi_rready : std_logic := '0';
signal mac_interrupt : std_logic := '0';
-- attribute mark_debug : string;
-- attribute mark_debug of mac2rx_data_sig : signal is "true";
-- attribute mark_debug of mac2rx_valid_sig : signal is "true";
-- attribute mark_debug of mac2rx_last_sig : signal is "true";
-- attribute mark_debug of mac2rx_error_sig : signal is "true";
begin
------------------------------------------------------------------------------
-- Instantiate the TRIMAC core FIFO Block wrapper
------------------------------------------------------------------------------
trimac_block : tri_mode_ethernet_mac_block
Generic map (
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
gtx_clk => gtx_clk,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Reference clock for IDELAYCTRL's
refclk => refclk,
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
-- Receiver => AXI-S Interface
------------------------------------------
mac_out_clock => rx_path_clock,
mac_out_resetn => rx_path_resetn,
mac_out_data => mac2rx_data_sig,
mac_out_valid => mac2rx_valid_sig,
mac_out_last => mac2rx_last_sig,
mac_out_error => mac2rx_error_sig,
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_ifg_delay => tx_ifg_delay,
-- Transmitter => AXI-S Interface
---------------------------------------------
mac_in_clock => tx_path_clock,
mac_in_resetn => tx_path_resetn,
mac_in_data => tx2mac_data_sig,
mac_in_valid => tx2mac_valid_sig,
mac_in_ready => tx2mac_ready_sig,
mac_in_last => tx2mac_last_sig,
-- MAC Control Interface
--------------------------
pause_req => pause_req,
pause_val => pause_val,
-- GMII Interface
-------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
-------------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_interrupt => mac_interrupt
);
config_mac_phy : config_mac_phy_sm
port map(
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
phy_interrupt_n => phy_interrupt_n,
mac_interrupt => mac_interrupt,
mac_speed => "01",
update_speed => '0',
serial_command => '0',
serial_response => open,
debug0_sig => debug0_sig,
debug1_sig => debug1_sig,
debug2_sig => debug2_sig,
debug3_sig => debug3_sig,
-- AXI-Lite Interface
-----------
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
rx_path : switch_port_rx_path
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
NR_PORTS => NR_PORTS,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_IQ_FIFOS => NR_IQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
PORT_ID => PORT_ID
)
Port map(
rx_path_clock => rx_path_clock,
rx_path_resetn => rx_path_resetn,
-- mac to rx_path interface
rx_in_data => mac2rx_data_sig,
rx_in_valid => mac2rx_valid_sig,
rx_in_last => mac2rx_last_sig,
rx_in_error => mac2rx_error_sig,
rx_in_timestamp_cnt => timestamp_cnt,
-- rx_path interface to fabric
rx_out_data => rx_out_data,
rx_out_valid => rx_out_valid,
rx_out_last => rx_out_last,
rx_out_ports_req => rx_out_ports_req,
rx_out_prio => rx_out_prio,
rx_out_timestamp => rx_out_timestamp,
rx_out_length => rx_out_length,
rx_out_ports_gnt => rx_out_ports_gnt
);
tx_path : switch_port_tx_path
Generic map(
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
tx_path_clock => tx_path_clock,
tx_path_resetn => tx_path_resetn,
-- tx_path interface to fabric
tx_in_data => tx_in_data,
tx_in_valid => tx_in_valid,
tx_in_length => tx_in_length,
tx_in_prio => tx_in_prio,
tx_in_timestamp => tx_in_timestamp,
tx_in_req => tx_in_req,
tx_in_accept_frame => tx_in_accept_frame,
-- timestamp
tx_in_timestamp_cnt => timestamp_cnt,
tx_out_latency => latency,
-- tx_path interface to mac
tx_out_data => tx2mac_data_sig,
tx_out_valid => tx2mac_valid_sig,
tx_out_ready => tx2mac_ready_sig,
tx_out_last => tx2mac_last_sig
);
end rtl;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/aeg_design_switch_port.vhd | 2 | 23193 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 13:56:52
-- Design Name:
-- Module Name: aeg_design_0_switch_port
-- Description: This module describes one port for the Ethernet switch
-- It consists of:
-- - The rx_path: the logic processing the received data before
-- sending to the fabric
-- - The tx_path: the logic receiving data from the fabric and
-- handling the transmission of frames
-- - The TEMAC receives/sends frames
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity aeg_design_0_switch_port is
Generic (
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer;
PORT_ID : integer
);
Port (
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
-- Receiver Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
-- RX Switch Fabric Intrface
------------------------------------------
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- Transmitter Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
-- TX Switch Fabric Intrface
---------------------------------------------
tx_path_clock : in std_logic;
tx_path_resetn : in std_logic;
tx_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
tx_in_valid : in std_logic;
tx_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
tx_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
tx_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_in_req : in std_logic;
tx_in_accept_frame : out std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
phy_interrupt_n : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic
);
end aeg_design_0_switch_port;
architecture rtl of aeg_design_0_switch_port is
component tri_mode_ethernet_mac_block
Generic (
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
-- mac to rxpath interface
------------------------------------------
mac_out_clock : in std_logic;
mac_out_resetn : in std_logic;
mac_out_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
mac_out_valid : out std_logic;
mac_out_last : out std_logic;
mac_out_error : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
-- txpath to mac interface
---------------------------------------------
mac_in_clock : in std_logic;
mac_in_resetn : in std_logic;
mac_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
mac_in_valid : in std_logic;
mac_in_ready : out std_logic;
mac_in_last : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_interrupt : out std_logic
);
end component;
component config_mac_phy_sm
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
phy_interrupt_n : in std_logic;
mac_interrupt : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_awvalid : out std_logic := '0';
s_axi_awready : in std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0) := (others => '0');
s_axi_wvalid : out std_logic := '0';
s_axi_wready : in std_logic;
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic;
s_axi_araddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_arvalid : out std_logic := '0';
s_axi_arready : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic := '0'
);
end component;
component switch_port_rx_path is
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
PORT_ID : integer
);
Port (
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
-- mac to rx_path interface
rx_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_in_valid : in std_logic;
rx_in_last : in std_logic;
rx_in_error : in std_logic;
rx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- rx_path interface to fabric
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0)
);
end component;
component switch_port_tx_path is
Generic (
FABRIC_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
tx_path_clock : in std_logic;
tx_path_resetn : in std_logic;
-- tx_path interface to fabric
tx_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
tx_in_valid : in std_logic;
tx_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
tx_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
tx_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_in_req : in std_logic;
tx_in_accept_frame : out std_logic;
-- timestamp
tx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- tx_path interface to mac
tx_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
tx_out_valid : out std_logic;
tx_out_ready : in std_logic;
tx_out_last : out std_logic
);
end component;
signal mac2rx_data_sig : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
signal mac2rx_valid_sig : std_logic;
signal mac2rx_last_sig : std_logic;
signal mac2rx_error_sig : std_logic;
signal tx2mac_data_sig : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
signal tx2mac_valid_sig : std_logic;
signal tx2mac_ready_sig : std_logic;
signal tx2mac_last_sig : std_logic;
signal s_axi_awaddr : std_logic_vector(11 downto 0) := (others => '0');
signal s_axi_awvalid : std_logic := '0';
signal s_axi_awready : std_logic := '0';
signal s_axi_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_wvalid : std_logic := '0';
signal s_axi_wready : std_logic := '0';
signal s_axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal s_axi_bvalid : std_logic := '0';
signal s_axi_bready : std_logic := '0';
signal s_axi_araddr : std_logic_vector(11 downto 0) := (others => '0');
signal s_axi_arvalid : std_logic := '0';
signal s_axi_arready : std_logic := '0';
signal s_axi_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal s_axi_rvalid : std_logic := '0';
signal s_axi_rready : std_logic := '0';
signal mac_interrupt : std_logic := '0';
-- attribute mark_debug : string;
-- attribute mark_debug of mac2rx_data_sig : signal is "true";
-- attribute mark_debug of mac2rx_valid_sig : signal is "true";
-- attribute mark_debug of mac2rx_last_sig : signal is "true";
-- attribute mark_debug of mac2rx_error_sig : signal is "true";
begin
------------------------------------------------------------------------------
-- Instantiate the TRIMAC core FIFO Block wrapper
------------------------------------------------------------------------------
trimac_block : tri_mode_ethernet_mac_block
Generic map (
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
gtx_clk => gtx_clk,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Reference clock for IDELAYCTRL's
refclk => refclk,
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
-- Receiver => AXI-S Interface
------------------------------------------
mac_out_clock => rx_path_clock,
mac_out_resetn => rx_path_resetn,
mac_out_data => mac2rx_data_sig,
mac_out_valid => mac2rx_valid_sig,
mac_out_last => mac2rx_last_sig,
mac_out_error => mac2rx_error_sig,
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_ifg_delay => tx_ifg_delay,
-- Transmitter => AXI-S Interface
---------------------------------------------
mac_in_clock => tx_path_clock,
mac_in_resetn => tx_path_resetn,
mac_in_data => tx2mac_data_sig,
mac_in_valid => tx2mac_valid_sig,
mac_in_ready => tx2mac_ready_sig,
mac_in_last => tx2mac_last_sig,
-- MAC Control Interface
--------------------------
pause_req => pause_req,
pause_val => pause_val,
-- GMII Interface
-------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
-------------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_interrupt => mac_interrupt
);
config_mac_phy : config_mac_phy_sm
port map(
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
phy_interrupt_n => phy_interrupt_n,
mac_interrupt => mac_interrupt,
mac_speed => "01",
update_speed => '0',
serial_command => '0',
serial_response => open,
debug0_sig => debug0_sig,
debug1_sig => debug1_sig,
debug2_sig => debug2_sig,
debug3_sig => debug3_sig,
-- AXI-Lite Interface
-----------
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
rx_path : switch_port_rx_path
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
NR_PORTS => NR_PORTS,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_IQ_FIFOS => NR_IQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
PORT_ID => PORT_ID
)
Port map(
rx_path_clock => rx_path_clock,
rx_path_resetn => rx_path_resetn,
-- mac to rx_path interface
rx_in_data => mac2rx_data_sig,
rx_in_valid => mac2rx_valid_sig,
rx_in_last => mac2rx_last_sig,
rx_in_error => mac2rx_error_sig,
rx_in_timestamp_cnt => timestamp_cnt,
-- rx_path interface to fabric
rx_out_data => rx_out_data,
rx_out_valid => rx_out_valid,
rx_out_last => rx_out_last,
rx_out_ports_req => rx_out_ports_req,
rx_out_prio => rx_out_prio,
rx_out_timestamp => rx_out_timestamp,
rx_out_length => rx_out_length,
rx_out_ports_gnt => rx_out_ports_gnt
);
tx_path : switch_port_tx_path
Generic map(
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
tx_path_clock => tx_path_clock,
tx_path_resetn => tx_path_resetn,
-- tx_path interface to fabric
tx_in_data => tx_in_data,
tx_in_valid => tx_in_valid,
tx_in_length => tx_in_length,
tx_in_prio => tx_in_prio,
tx_in_timestamp => tx_in_timestamp,
tx_in_req => tx_in_req,
tx_in_accept_frame => tx_in_accept_frame,
-- timestamp
tx_in_timestamp_cnt => timestamp_cnt,
tx_out_latency => latency,
-- tx_path interface to mac
tx_out_data => tx2mac_data_sig,
tx_out_valid => tx2mac_valid_sig,
tx_out_ready => tx2mac_ready_sig,
tx_out_last => tx2mac_last_sig
);
end rtl;
| mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@c@o@m@m@s@m@a@t@r@i@x/_primary.vhd | 3 | 7666 | library verilog;
use verilog.vl_types.all;
entity F2DSS_COMMSMATRIX is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_TESTREMAPENABLE: in vl_logic;
F2_TESTESRAM1REMAP: in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_ESRAMFWREMAP: in vl_logic;
COM_ENVMREMAPSIZE: in vl_logic_vector(4 downto 0);
COM_ENVMREMAPBASE: in vl_logic_vector(19 downto 0);
COM_ENVMFABREMAPBASE: in vl_logic_vector(19 downto 0);
COM_PROTREGIONSIZE: in vl_logic_vector(4 downto 0);
COM_PROTREGIONBASE: in vl_logic_vector(31 downto 0);
COM_MASTERENABLE: in vl_logic_vector(2 downto 0);
COM_CLEARSTATUS : in vl_logic_vector(4 downto 0);
COM_WEIGHTEDMODE: in vl_logic;
COM_ERRORSTATUS : out vl_logic_vector(4 downto 0);
COM_ERRORINTERRUPT: out vl_logic;
M3_HADDRI : in vl_logic_vector(31 downto 0);
M3_HTRANSI1 : in vl_logic;
M3_HSIZEI : in vl_logic_vector(2 downto 0);
M3_HADDRD : in vl_logic_vector(31 downto 0);
M3_HTRANSD1 : in vl_logic;
M3_HWRITED : in vl_logic;
M3_HSIZED : in vl_logic_vector(2 downto 0);
M3_HWDATAD : in vl_logic_vector(31 downto 0);
M3_HRDATAI : out vl_logic_vector(31 downto 0);
M3_HREADYI : out vl_logic;
M3_HRESPI : out vl_logic;
M3_HRDATAD : out vl_logic_vector(31 downto 0);
M3_HREADYD : out vl_logic;
M3_HRESPD : out vl_logic;
M3_HADDRS : in vl_logic_vector(31 downto 0);
M3_HTRANSS1 : in vl_logic;
M3_HWRITES : in vl_logic;
M3_HSIZES : in vl_logic_vector(2 downto 0);
M3_HWDATAS : in vl_logic_vector(31 downto 0);
M3_HMASTLOCKS : in vl_logic;
M3_HRDATAS : out vl_logic_vector(31 downto 0);
M3_HREADYS : out vl_logic;
M3_HRESPS : out vl_logic;
DS_FM_HADDR : in vl_logic_vector(31 downto 0);
DS_FM_HMASTLOCK : in vl_logic;
DS_FM_HSIZE : in vl_logic_vector(2 downto 0);
DS_FM_HTRANS1 : in vl_logic;
DS_FM_HWRITE : in vl_logic;
DS_FM_HWDATA : in vl_logic_vector(31 downto 0);
DS_FM_HRDATA : out vl_logic_vector(31 downto 0);
DS_FM_HREADY : out vl_logic;
DS_FM_HRESP : out vl_logic;
MAC_HWRITE : in vl_logic;
MAC_HADDR : in vl_logic_vector(31 downto 0);
MAC_HTRANS1 : in vl_logic;
MAC_HSIZE : in vl_logic_vector(2 downto 0);
MAC_HWDATA : in vl_logic_vector(31 downto 0);
MAC_HRDATA : out vl_logic_vector(31 downto 0);
MAC_HREADY : out vl_logic;
MAC_HRESP : out vl_logic;
PDMA_HADDR : in vl_logic_vector(31 downto 0);
PDMA_HSIZE : in vl_logic_vector(2 downto 0);
PDMA_HTRANS1 : in vl_logic;
PDMA_HWDATA : in vl_logic_vector(31 downto 0);
PDMA_HWRITE : in vl_logic;
PDMA_HRDATA : out vl_logic_vector(31 downto 0);
PDMA_HREADY : out vl_logic;
PDMA_HRESP : out vl_logic;
ESRAM0_HRDATA : in vl_logic_vector(31 downto 0);
ESRAM0_HREADYOUT: in vl_logic;
ESRAM0_HRESP : in vl_logic;
ESRAM0_HADDR : out vl_logic_vector(31 downto 0);
ESRAM0_HSIZE : out vl_logic_vector(2 downto 0);
ESRAM0_HTRANS1 : out vl_logic;
ESRAM0_HWDATA : out vl_logic_vector(31 downto 0);
ESRAM0_HWRITE : out vl_logic;
ESRAM0_HSEL : out vl_logic;
ESRAM0_HREADY : out vl_logic;
ESRAM1_HRDATA : in vl_logic_vector(31 downto 0);
ESRAM1_HREADYOUT: in vl_logic;
ESRAM1_HRESP : in vl_logic;
ESRAM1_HADDR : out vl_logic_vector(31 downto 0);
ESRAM1_HSIZE : out vl_logic_vector(2 downto 0);
ESRAM1_HTRANS1 : out vl_logic;
ESRAM1_HWDATA : out vl_logic_vector(31 downto 0);
ESRAM1_HWRITE : out vl_logic;
ESRAM1_HSEL : out vl_logic;
ESRAM1_HREADY : out vl_logic;
ENVM_HRDATA : in vl_logic_vector(31 downto 0);
ENVM_HREADYOUT : in vl_logic;
ENVM_HRESP : in vl_logic;
ENVM_HADDR : out vl_logic_vector(31 downto 0);
ENVM_HSIZE : out vl_logic_vector(2 downto 0);
ENVM_HTRANS1 : out vl_logic;
ENVM_HWDATA : out vl_logic_vector(31 downto 0);
ENVM_HWRITE : out vl_logic;
ENVM_HSEL : out vl_logic;
ENVM_HREADY : out vl_logic;
EM_HRDATA : in vl_logic_vector(31 downto 0);
EM_HREADYOUT : in vl_logic;
EM_HRESP : in vl_logic;
EM_HADDR : out vl_logic_vector(31 downto 0);
EM_HSIZE : out vl_logic_vector(2 downto 0);
EM_HTRANS1 : out vl_logic;
EM_HWDATA : out vl_logic_vector(31 downto 0);
EM_HWRITE : out vl_logic;
EM_HSEL : out vl_logic;
EM_HREADY : out vl_logic;
ACE_HRDATA : in vl_logic_vector(31 downto 0);
ACE_HREADYOUT : in vl_logic;
ACE_HRESP : in vl_logic;
ACE_HADDR : out vl_logic_vector(31 downto 0);
ACE_HSIZE : out vl_logic_vector(2 downto 0);
ACE_HTRANS1 : out vl_logic;
ACE_HREADY : out vl_logic;
ACE_HWDATA : out vl_logic_vector(31 downto 0);
ACE_HWRITE : out vl_logic;
ACE_HSEL : out vl_logic;
DS_HM_HRDATA : in vl_logic_vector(31 downto 0);
DS_HM_HREADYOUT : in vl_logic;
DS_HM_HRESP : in vl_logic;
DS_HM_HADDR : out vl_logic_vector(31 downto 0);
DS_HM_HSIZE : out vl_logic_vector(2 downto 0);
DS_HM_HTRANS1 : out vl_logic;
DS_HM_HSEL : out vl_logic;
DS_HM_HWRITE : out vl_logic;
DS_HM_HWDATA : out vl_logic_vector(31 downto 0);
DS_HM_HREADY : out vl_logic;
DS_HM_HMASTLOCK : out vl_logic;
PER0_HRDATA : in vl_logic_vector(31 downto 0);
PER0_HREADYOUT : in vl_logic;
PER0_HRESP : in vl_logic;
PER0_HADDR : out vl_logic_vector(31 downto 0);
PER0_HSIZE : out vl_logic_vector(2 downto 0);
PER0_HTRANS1 : out vl_logic;
PER0_HREADY : out vl_logic;
PER0_HWDATA : out vl_logic_vector(31 downto 0);
PER0_HWRITE : out vl_logic;
PER0_HSEL : out vl_logic;
PER1_HRDATA : in vl_logic_vector(31 downto 0);
PER1_HREADYOUT : in vl_logic;
PER1_HRESP : in vl_logic;
PER1_HADDR : out vl_logic_vector(31 downto 0);
PER1_HSIZE : out vl_logic_vector(2 downto 0);
PER1_HTRANS1 : out vl_logic;
PER1_HREADY : out vl_logic;
PER1_HWDATA : out vl_logic_vector(31 downto 0);
PER1_HWRITE : out vl_logic;
PER1_HSEL : out vl_logic
);
end F2DSS_COMMSMATRIX;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/ramfifo/rd_fwft.vhd | 5 | 38466 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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7BwBjMnW9Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26736)
`protect data_block
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BmEN
`protect end_protected
| mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@addr@dec@m2/_primary.vhd | 3 | 691 | library verilog;
use verilog.vl_types.all;
entity AddrDecM2 is
port(
addr : in vl_logic_vector(31 downto 0);
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_ENVMFABREMAPBASE: in vl_logic_vector(19 downto 0);
COM_ENVMREMAPSIZE: in vl_logic_vector(4 downto 0);
COM_PROTREGIONSIZE: in vl_logic_vector(4 downto 0);
COM_PROTREGIONBASE: in vl_logic_vector(31 downto 0);
COM_MASTERENABLE: in vl_logic;
addrDec : out vl_logic_vector(8 downto 0);
absoluteAddr : out vl_logic_vector(31 downto 0)
);
end AddrDecM2;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/hdl/ramfifo/wr_status_flags_ss.vhd | 5 | 27791 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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kVLdV0gL7A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18832)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/ramfifo/wr_status_flags_ss.vhd | 5 | 27791 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18832)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/rx/input_queue_overflow.vhd | 2 | 2174 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 02.01.2014 13:22:29
-- Design Name:
-- Module Name: input_queue_overflow - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.4
--
-- Description:
-- combinatioral path to check for overflow of the iq_memory and iq_fifos
--
-- more detailed information can found in file switch_port_rxpath_input_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity input_queue_overflow is
Generic(
IQ_FIFO_DATA_WIDTH : integer;
IQ_MEM_ADDR_WIDTH : integer;
IQ_FIFO_MEM_PTR_START : integer;
NR_IQ_FIFOS : integer
);
Port (
fifo_full : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
fifo_empty : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
mem_wr_addr : in std_logic_vector(IQ_MEM_ADDR_WIDTH-1 downto 0);
mem_rd_addr : in std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
overflow : out std_logic_vector(NR_IQ_FIFOS-1 downto 0)
);
end input_queue_overflow;
architecture rtl of input_queue_overflow is
begin
-- overflow if the memory currently written to is one address below current fifo word
-- or if fifo is full
overflow_detection_p : process(mem_rd_addr, mem_wr_addr, fifo_empty, fifo_full)
begin
for i in 0 to NR_IQ_FIFOS-1 loop
if fifo_empty(i) = '0' and mem_rd_addr(i*IQ_FIFO_DATA_WIDTH+IQ_FIFO_MEM_PTR_START+IQ_MEM_ADDR_WIDTH-1
downto i*IQ_FIFO_DATA_WIDTH+IQ_FIFO_MEM_PTR_START) - mem_wr_addr = 1 then
overflow(i) <= '1';
elsif fifo_full(i) = '1' then
overflow(i) <= '1';
else
overflow(i) <= '0';
end if;
end loop;
end process;
end rtl;
| mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@b@f@m_@a@h@b2@a@p@b/_primary.vhd | 3 | 3609 | library verilog;
use verilog.vl_types.all;
entity MSS_BFM_AHB2APB is
generic(
TPD : real := 0.100000;
T0 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
T2 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi1);
T345 : vl_logic_vector(2 downto 0) := (Hi1, Hi1, Hi0);
TR0 : vl_logic_vector(2 downto 0) := (Hi1, Hi1, Hi1);
WAIT1 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1);
WAIT2 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0);
WAIT3 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi1);
WAIT4 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi0);
idle : vl_logic_vector(1 downto 0) := (Hi0, Hi0);
waitone : vl_logic_vector(1 downto 0) := (Hi0, Hi1);
waittwo : vl_logic_vector(1 downto 0) := (Hi1, Hi0);
waitthree : vl_logic_vector(1 downto 0) := (Hi1, Hi1)
);
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
HSEL : in vl_logic;
HWRITE : in vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HWDATA : in vl_logic_vector(31 downto 0);
HRDATA : out vl_logic_vector(31 downto 0);
HREADYIN : in vl_logic;
HREADYOUT : out vl_logic;
HTRANS : in vl_logic_vector(1 downto 0);
HSIZE : in vl_logic_vector(2 downto 0);
HBURST : in vl_logic_vector(2 downto 0);
HMASTLOCK : in vl_logic;
HPROT : in vl_logic_vector(3 downto 0);
HRESP : out vl_logic;
PSEL : out vl_logic_vector(15 downto 0);
PADDR : out vl_logic_vector(31 downto 0);
PWRITE : out vl_logic;
PENABLE : out vl_logic;
PWDATA : out vl_logic_vector(31 downto 0);
PRDATA : in vl_logic_vector(31 downto 0);
PREADY : in vl_logic;
PSLVERR : in vl_logic;
PCLK_DIV : in vl_logic_vector(1 downto 0)
);
attribute T0_mti_vect_attrib : integer;
attribute T0_mti_vect_attrib of T0 : constant is 0;
attribute T2_mti_vect_attrib : integer;
attribute T2_mti_vect_attrib of T2 : constant is 5;
attribute T345_mti_vect_attrib : integer;
attribute T345_mti_vect_attrib of T345 : constant is 6;
attribute TR0_mti_vect_attrib : integer;
attribute TR0_mti_vect_attrib of TR0 : constant is 7;
attribute WAIT1_mti_vect_attrib : integer;
attribute WAIT1_mti_vect_attrib of WAIT1 : constant is 1;
attribute WAIT2_mti_vect_attrib : integer;
attribute WAIT2_mti_vect_attrib of WAIT2 : constant is 2;
attribute WAIT3_mti_vect_attrib : integer;
attribute WAIT3_mti_vect_attrib of WAIT3 : constant is 3;
attribute WAIT4_mti_vect_attrib : integer;
attribute WAIT4_mti_vect_attrib of WAIT4 : constant is 4;
attribute idle_mti_vect_attrib : integer;
attribute idle_mti_vect_attrib of idle : constant is 0;
attribute waitone_mti_vect_attrib : integer;
attribute waitone_mti_vect_attrib of waitone : constant is 1;
attribute waittwo_mti_vect_attrib : integer;
attribute waittwo_mti_vect_attrib of waittwo : constant is 2;
attribute waitthree_mti_vect_attrib : integer;
attribute waitthree_mti_vect_attrib of waitthree : constant is 3;
end MSS_BFM_AHB2APB;
| mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/read_39bit_analog_io/_primary.vhd | 3 | 265 | library verilog;
use verilog.vl_types.all;
entity read_39bit_analog_io is
port(
serial_in : in vl_logic;
read_enb : in vl_logic;
parallel_out : out vl_logic_vector(38 downto 0)
);
end read_39bit_analog_io;
| mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f@a@b@r@i@c@i@f_@f@m/_primary.vhd | 3 | 1609 | library verilog;
use verilog.vl_types.all;
entity FABRICIF_FM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
apb32 : in vl_logic;
lastCycle : in vl_logic;
APB16_XHOLD : out vl_logic_vector(15 downto 0);
DS_FM_HADDR : out vl_logic_vector(31 downto 0);
DS_FM_HMASTLOCK : out vl_logic;
DS_FM_HSIZE : out vl_logic_vector(1 downto 0);
DS_FM_HTRANS1 : out vl_logic;
DS_FM_HWRITE : out vl_logic;
DS_FM_HWDATA : out vl_logic_vector(31 downto 0);
DS_FM_HRDATA : in vl_logic_vector(31 downto 0);
DS_FM_HREADY : in vl_logic;
DS_FM_HRESP : in vl_logic;
F_FM_ADDR : in vl_logic_vector(31 downto 0);
F_FM_WDATA : in vl_logic_vector(31 downto 0);
F_FM_RDATA : out vl_logic_vector(31 downto 0);
F_FM_HMASTLOCK : in vl_logic;
F_FM_HSIZE : in vl_logic_vector(1 downto 0);
F_FM_HTRANS1 : in vl_logic;
F_FM_HWRITE : in vl_logic;
F_FM_HSEL : in vl_logic;
F_FM_HREADY : in vl_logic;
F_FM_HREADYOUT : out vl_logic;
F_FM_HRESP : out vl_logic;
F_FM_PSEL : in vl_logic;
F_FM_PENABLE : in vl_logic;
F_FM_PWRITE : in vl_logic;
F_FM_PREADY : out vl_logic;
F_FM_PSLVERR : out vl_logic
);
end FABRICIF_FM;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/rx/rx_path_input_queue.vhd | 2 | 18944 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 26.11.2013 16:32:15
-- Design Name: rx_path_input_queue.vhd
-- Module Name: rx_path_input_queue - structural
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- Input frame scheduling consisting of 5 submodules:
-- input_queue_control: receive frames and line in queue, remove error-frames
-- input_queue_memory: store the received frames
-- input_queue_fifo: store memory pointer, frame length and output ports of the frames located in the memory
-- depending on needs one fifo or two priority fifos can be selected
-- input_queue_overflow: checks for memory overflow and fifo overflow
-- input_queue_scheduling: decide which frame to offer next to switch fabric and control frame transmission
-- depending on NR_IQ_FIFOS priority behaviour (NR_IQ_FIFOS = 2) or best effort (NR_IQ_FIFOS = 1) is considered
--
-- more detailed information can found in file switch_port_rxpath_input_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rx_path_input_queue is
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
IQ_MEM_ADDR_WIDTH_A : integer := 12;
IQ_MEM_ADDR_WIDTH_B : integer := 10 -- 8 bit: 12, 32 bit: 10
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface data
iq_in_mac_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
iq_in_mac_valid : in std_logic;
iq_in_mac_last : in std_logic;
iq_in_mac_error : in std_logic;
-- input interface control
iq_in_lu_ports : in std_logic_vector(NR_PORTS-1 downto 0);
iq_in_lu_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iq_in_lu_skip : in std_logic;
iq_in_lu_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iq_in_lu_valid : in std_logic;
-- output interface arbitration
iq_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
iq_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iq_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iq_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
iq_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- output interface data
iq_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
iq_out_last : out std_logic;
iq_out_valid : out std_logic
);
end rx_path_input_queue;
architecture structural of rx_path_input_queue is
-- memory and fifo data constants
constant IQ_MEM_DATA_WIDTH_RATIO : integer := FABRIC_DATA_WIDTH / RECEIVER_DATA_WIDTH;
constant IQ_FIFO_DATA_WIDTH : integer := VLAN_PRIO_WIDTH+FRAME_LENGTH_WIDTH+TIMESTAMP_WIDTH+NR_PORTS+IQ_MEM_ADDR_WIDTH_A;
-- fifo address constants
constant IQ_FIFO_PRIO_START : integer := 0;
constant IQ_FIFO_FRAME_LEN_START : integer := IQ_FIFO_PRIO_START + VLAN_PRIO_WIDTH;
constant IQ_FIFO_TIMESTAMP_START : integer := IQ_FIFO_FRAME_LEN_START + FRAME_LENGTH_WIDTH;
constant IQ_FIFO_PORTS_START : integer := IQ_FIFO_TIMESTAMP_START + TIMESTAMP_WIDTH;
constant IQ_FIFO_MEM_PTR_START : integer := IQ_FIFO_PORTS_START + NR_PORTS;
component input_queue_control is
Generic (
RECEIVER_DATA_WIDTH : integer;
NR_PORTS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
IQ_MEM_ADDR_WIDTH : integer;
IQ_MEM_DATA_WIDTH_RATIO : integer;
IQ_FIFO_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
IQ_FIFO_PRIO_START : integer;
IQ_FIFO_FRAME_LEN_START : integer;
IQ_FIFO_TIMESTAMP_START : integer;
IQ_FIFO_PORTS_START : integer;
IQ_FIFO_MEM_PTR_START : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface mac
iqctrl_in_mac_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
iqctrl_in_mac_valid : in std_logic;
iqctrl_in_mac_last : in std_logic;
iqctrl_in_mac_error : in std_logic;
-- input interface lookup
iqctrl_in_lu_ports : in std_logic_vector(NR_PORTS-1 downto 0);
iqctrl_in_lu_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iqctrl_in_lu_skip : in std_logic;
iqctrl_in_lu_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iqctrl_in_lu_valid : in std_logic;
-- output interface memory
iqctrl_out_mem_wenable : out std_logic;
iqctrl_out_mem_addr : out std_logic_vector(IQ_MEM_ADDR_WIDTH_A-1 downto 0);
iqctrl_out_mem_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
-- output interface fifo
iqctrl_out_fifo_wenable : out std_logic;
iqctrl_out_fifo_data : out std_logic_vector(IQ_FIFO_DATA_WIDTH-1 downto 0)
);
end component;
component input_queue_memory is
Generic (
IQ_MEM_ADDR_WIDTH_A : integer;
IQ_MEM_ADDR_WIDTH_B : integer;
IQ_MEM_DATA_WIDTH_IN : integer;
IQ_MEM_DATA_WIDTH_OUT : integer
);
Port (
iqmem_in_wenable : in std_logic_vector;
iqmem_in_addr : in std_logic_vector(IQ_MEM_ADDR_WIDTH_A-1 downto 0);
iqmem_in_data : in std_logic_vector(IQ_MEM_DATA_WIDTH_IN-1 downto 0);
iqmem_in_clk : in std_logic;
iqmem_out_enable : in std_logic;
iqmem_out_addr : in std_logic_vector(IQ_MEM_ADDR_WIDTH_B-1 downto 0);
iqmem_out_data : out std_logic_vector(IQ_MEM_DATA_WIDTH_OUT-1 downto 0);
iqmem_out_clk : in std_logic
);
end component;
component input_queue_fifo is
Generic (
IQ_FIFO_DATA_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(IQ_FIFO_DATA_WIDTH-1 downto 0);
wr_priority : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rd_en : in std_logic;
overflow : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
dout : out std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
rd_priority : in std_logic;
full : out std_logic_vector(NR_IQ_FIFOS-1 downto 0);
empty : out std_logic_vector(NR_IQ_FIFOS-1 downto 0)
);
end component;
component input_queue_overflow is
Generic(
IQ_FIFO_DATA_WIDTH : integer;
IQ_MEM_ADDR_WIDTH : integer;
IQ_FIFO_MEM_PTR_START : integer;
NR_IQ_FIFOS : integer
);
Port (
fifo_full : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
fifo_empty : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
mem_wr_addr : in std_logic_vector(IQ_MEM_ADDR_WIDTH_A-1 downto 0);
mem_rd_addr : in std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
overflow : out std_logic_vector(NR_IQ_FIFOS-1 downto 0)
);
end component;
component input_queue_arbitration is
Generic(
FABRIC_DATA_WIDTH : integer;
IQ_FIFO_DATA_WIDTH : integer;
NR_PORTS : integer;
IQ_MEM_ADDR_WIDTH_A : integer;
IQ_MEM_ADDR_WIDTH_B : integer;
FRAME_LENGTH_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
IQ_FIFO_PRIO_START : integer;
IQ_FIFO_FRAME_LEN_START : integer;
IQ_FIFO_TIMESTAMP_START : integer;
IQ_FIFO_PORTS_START : integer;
IQ_FIFO_MEM_PTR_START : integer;
IQ_MEM_DATA_WIDTH_RATIO : integer;
NR_IQ_FIFOS : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface memory
iqarb_in_mem_enable : out std_logic;
iqarb_in_mem_addr : out std_logic_vector(IQ_MEM_ADDR_WIDTH_B-1 downto 0);
iqarb_in_mem_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
-- input interface fifo
iqarb_in_fifo_enable : out std_logic;
iqarb_in_fifo_prio : out std_logic;
iqarb_in_fifo_data : in std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
iqarb_in_fifo_empty : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
iqarb_in_fifo_overflow : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
-- output interface arbitration
iqarb_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
iqarb_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iqarb_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iqarb_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
iqarb_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- output interface data
iqarb_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
iqarb_out_last : out std_logic;
iqarb_out_valid : out std_logic
);
end component;
signal iqctrl2iqmem_data : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
signal iqctrl2iqmem_wenable : std_logic_vector(0 downto 0);
signal iqctrl2iqmem_addr : std_logic_vector(IQ_MEM_ADDR_WIDTH_A-1 downto 0);
signal iqctrl2iqfifo_wenable : std_logic;
signal iqctrl2iqfifo_data : std_logic_vector(IQ_FIFO_DATA_WIDTH-1 downto 0);
signal iqfifo2iqarb_renable : std_logic;
signal iqfifo2iqarb_data : std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
signal iqfifo2iqarb_prio : std_logic;
signal iqfifo2iqarb_empty : std_logic_vector(NR_IQ_FIFOS-1 downto 0);
signal iqfifo2iqovfl_full : std_logic_vector(NR_IQ_FIFOS-1 downto 0);
signal iqovfl2iqarb_overflow : std_logic_vector(NR_IQ_FIFOS-1 downto 0);
signal iqmem2iqarb_data : std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
signal iqmem2iqarb_enable : std_logic;
signal iqmem2iqarb_addr : std_logic_vector(IQ_MEM_ADDR_WIDTH_B-1 downto 0);
-- attribute mark_debug : string;
-- attribute mark_debug of iqctrl2iqmem_data : signal is "true";
-- attribute mark_debug of iqctrl2iqmem_wenable : signal is "true";
-- attribute mark_debug of iqctrl2iqmem_addr : signal is "true";
-- attribute mark_debug of iqctrl2iqfifo_wenable : signal is "true";
-- attribute mark_debug of iqctrl2iqfifo_data : signal is "true";
-- attribute mark_debug of iqfifo2iqarb_renable : signal is "true";
-- attribute mark_debug of iqfifo2iqarb_data : signal is "true";
-- attribute mark_debug of iqfifo2iqarb_empty : signal is "true";
-- attribute mark_debug of iqfifo2iqarb_overflow : signal is "true";
-- attribute mark_debug of iqmem2iqarb_data : signal is "true";
-- attribute mark_debug of iqmem2iqarb_enable : signal is "true";
-- attribute mark_debug of iqmem2iqarb_addr : signal is "true";
begin
iq_control : input_queue_control
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
NR_PORTS => NR_PORTS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
IQ_MEM_ADDR_WIDTH => IQ_MEM_ADDR_WIDTH_A,
IQ_MEM_DATA_WIDTH_RATIO => IQ_MEM_DATA_WIDTH_RATIO,
IQ_FIFO_DATA_WIDTH => IQ_FIFO_DATA_WIDTH,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
IQ_FIFO_PRIO_START => IQ_FIFO_PRIO_START,
IQ_FIFO_FRAME_LEN_START => IQ_FIFO_FRAME_LEN_START,
IQ_FIFO_TIMESTAMP_START => IQ_FIFO_TIMESTAMP_START,
IQ_FIFO_PORTS_START => IQ_FIFO_PORTS_START,
IQ_FIFO_MEM_PTR_START => IQ_FIFO_MEM_PTR_START
)
Port map(
clk => clk,
reset => reset,
-- input interface mac
iqctrl_in_mac_data => iq_in_mac_data,
iqctrl_in_mac_valid => iq_in_mac_valid,
iqctrl_in_mac_last => iq_in_mac_last,
iqctrl_in_mac_error => iq_in_mac_error,
-- input interface lookup
iqctrl_in_lu_ports => iq_in_lu_ports,
iqctrl_in_lu_prio => iq_in_lu_prio,
iqctrl_in_lu_skip => iq_in_lu_skip,
iqctrl_in_lu_timestamp => iq_in_lu_timestamp,
iqctrl_in_lu_valid => iq_in_lu_valid,
-- output interface memory
iqctrl_out_mem_wenable => iqctrl2iqmem_wenable(0),
iqctrl_out_mem_addr => iqctrl2iqmem_addr,
iqctrl_out_mem_data => iqctrl2iqmem_data,
-- output interface fifo
iqctrl_out_fifo_wenable => iqctrl2iqfifo_wenable,
iqctrl_out_fifo_data => iqctrl2iqfifo_data
);
iq_mem : input_queue_memory
Generic map(
IQ_MEM_ADDR_WIDTH_A => IQ_MEM_ADDR_WIDTH_A,
IQ_MEM_ADDR_WIDTH_B => IQ_MEM_ADDR_WIDTH_B,
IQ_MEM_DATA_WIDTH_IN => RECEIVER_DATA_WIDTH,
IQ_MEM_DATA_WIDTH_OUT => FABRIC_DATA_WIDTH
)
Port map(
--Port A -> Control module
iqmem_in_wenable => iqctrl2iqmem_wenable,
iqmem_in_addr => iqctrl2iqmem_addr,
iqmem_in_data => iqctrl2iqmem_data,
iqmem_in_clk => clk,
--Port B -> Scheduling moudle
iqmem_out_enable => iqmem2iqarb_enable,
iqmem_out_addr => iqmem2iqarb_addr,
iqmem_out_data => iqmem2iqarb_data,
iqmem_out_clk => clk
);
iq_fifo : input_queue_fifo
Generic map(
IQ_FIFO_DATA_WIDTH => IQ_FIFO_DATA_WIDTH,
NR_IQ_FIFOS => NR_IQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH
)
Port map(
clk => clk,
reset => reset,
wr_en => iqctrl2iqfifo_wenable,
din => iqctrl2iqfifo_data,
wr_priority => iqctrl2iqfifo_data(IQ_FIFO_PRIO_START+VLAN_PRIO_WIDTH-1 downto IQ_FIFO_PRIO_START),
rd_en => iqfifo2iqarb_renable,
overflow => iqovfl2iqarb_overflow,
dout => iqfifo2iqarb_data,
rd_priority => iqfifo2iqarb_prio,
full => iqfifo2iqovfl_full,
empty => iqfifo2iqarb_empty
);
iq_overflow : input_queue_overflow
Generic map(
IQ_FIFO_DATA_WIDTH => IQ_FIFO_DATA_WIDTH,
IQ_MEM_ADDR_WIDTH => IQ_MEM_ADDR_WIDTH_A,
IQ_FIFO_MEM_PTR_START => IQ_FIFO_MEM_PTR_START,
NR_IQ_FIFOS => NR_IQ_FIFOS
)
Port map(
fifo_full => iqfifo2iqovfl_full,
fifo_empty => iqfifo2iqarb_empty,
mem_wr_addr => iqctrl2iqmem_addr,
mem_rd_addr => iqfifo2iqarb_data,
overflow => iqovfl2iqarb_overflow
);
iq_arbitration : input_queue_arbitration
Generic map(
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
IQ_FIFO_DATA_WIDTH => IQ_FIFO_DATA_WIDTH,
NR_PORTS => NR_PORTS,
IQ_MEM_ADDR_WIDTH_A => IQ_MEM_ADDR_WIDTH_A,
IQ_MEM_ADDR_WIDTH_B => IQ_MEM_ADDR_WIDTH_B,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
IQ_FIFO_PRIO_START => IQ_FIFO_PRIO_START,
IQ_FIFO_FRAME_LEN_START => IQ_FIFO_FRAME_LEN_START,
IQ_FIFO_TIMESTAMP_START => IQ_FIFO_TIMESTAMP_START,
IQ_FIFO_PORTS_START => IQ_FIFO_PORTS_START,
IQ_FIFO_MEM_PTR_START => IQ_FIFO_MEM_PTR_START,
IQ_MEM_DATA_WIDTH_RATIO => IQ_MEM_DATA_WIDTH_RATIO,
NR_IQ_FIFOS => NR_IQ_FIFOS
)
Port map(
clk => clk,
reset => reset,
-- input interface memory
iqarb_in_mem_enable => iqmem2iqarb_enable,
iqarb_in_mem_addr => iqmem2iqarb_addr,
iqarb_in_mem_data => iqmem2iqarb_data,
-- input interface fifo
iqarb_in_fifo_enable => iqfifo2iqarb_renable,
iqarb_in_fifo_prio => iqfifo2iqarb_prio,
iqarb_in_fifo_data => iqfifo2iqarb_data,
iqarb_in_fifo_empty => iqfifo2iqarb_empty,
iqarb_in_fifo_overflow => iqovfl2iqarb_overflow,
-- output interface arbitration
iqarb_out_ports_req => iq_out_ports_req,
iqarb_out_prio => iq_out_prio,
iqarb_out_timestamp => iq_out_timestamp,
iqarb_out_length => iq_out_length,
iqarb_out_ports_gnt => iq_out_ports_gnt,
-- output interface data
iqarb_out_data => iq_out_data,
iqarb_out_last => iq_out_last,
iqarb_out_valid => iq_out_valid
);
end structural;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/ramfifo/wr_pf_sshft.vhd | 5 | 20160 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_v12_0/hdl/ramfifo/wr_pf_sshft.vhd | 5 | 20160 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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t8EfDvBDlA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13184)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/hdl/common/wr_pf_as.vhd | 5 | 27402 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/builtin/builtin_prim_v6.vhd | 5 | 37128 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25744)
`protect data_block
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`protect end_protected
| mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@a@p@b@s@l@a@v@e@s/_primary.vhd | 3 | 1233 | library verilog;
use verilog.vl_types.all;
entity MSS_APBSLAVES is
generic(
AWIDTH : integer := 12;
DEPTH : integer := 256;
DWIDTH : integer := 32;
INITFILE : string := " ";
ID : integer := 0;
TPD : integer := 0;
ENFUNC : integer := 0;
DEBUG : integer := 1
);
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PSEL : in vl_logic_vector(15 downto 0);
PADDR : in vl_logic_vector;
PWDATA : in vl_logic_vector;
PRDATA : out vl_logic_vector;
PREADY : out vl_logic;
PSLVERR : out vl_logic;
GPIO_IN : in vl_logic_vector(31 downto 0);
GPIO_OUT : out vl_logic_vector(31 downto 0);
GPIO_OE : out vl_logic_vector(31 downto 0);
GPIO_INT : out vl_logic_vector(31 downto 0);
SOFTRESETS : in vl_logic_vector(10 downto 0)
);
end MSS_APBSLAVES;
| mit |
gihankarunarathne/vhdl-learn | Behavioral/s5_at_start_process.vhd | 1 | 947 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:54:08 08/28/2013
-- Design Name:
-- Module Name: s5_at_start_process - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity s5_at_start_process is
end s5_at_start_process;
architecture Behavioral of s5_at_start_process is
begin
end Behavioral;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/rtl/switch_fabric/aeg_design_switch_fabric.vhd | 2 | 7462 | --------------------------------------------------------------------------------
-- File : aeg_design_switch_fabric.vhd
-- Author : Andreas Ettner
-- -----------------------------------------------------------------------------
-- Description:
-- the switching fabric consists of one fabric_arbitration module for each output port
-- the arbitration module decides which input port is allowed to transmit data to
-- its output port
-- the switching module instantiates the fabric_arbitration modules and handles the
-- wiring between the input ports and the arbitration modules
--
-- further information can be found in file switch_fabric.svg
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity aeg_design_0_switch_fabric is
generic (
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
ARBITRATION : integer;
FRAME_LENGTH_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
port (
fabric_clk : in std_logic;
fabric_resetn : in std_logic;
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- data from the RX data path
fabric_in_data : in std_logic_vector(NR_PORTS*FABRIC_DATA_WIDTH-1 downto 0);
fabric_in_valid : in std_logic_vector(NR_PORTS-1 downto 0);
fabric_in_last : in std_logic_vector(NR_PORTS-1 downto 0);
fabric_in_ports_req : in std_logic_vector(NR_PORTS*NR_PORTS-1 downto 0);
fabric_in_prio : in std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
fabric_in_timestamp : in std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
fabric_in_length : in std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
fabric_in_ports_gnt : out std_logic_vector(NR_PORTS*NR_PORTS-1 downto 0);
-- data TO the TX data path
fabric_out_prio : out std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
fabric_out_timestamp : out std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
fabric_out_data : out std_logic_vector(NR_PORTS*FABRIC_DATA_WIDTH-1 downto 0);
fabric_out_valid : out std_logic_vector(NR_PORTS-1 downto 0);
fabric_out_length : out std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
fabric_out_req : out std_logic_vector(NR_PORTS-1 downto 0);
fabric_out_accept_frame : in std_logic_vector(NR_PORTS-1 downto 0)
);
end aeg_design_0_switch_fabric;
architecture structural of aeg_design_0_switch_fabric is
component switch_fabric_arbitration is
generic (
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
ARBITRATION : integer;
FRAME_LENGTH_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
port (
clk : in std_logic;
reset : in std_logic;
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- data from the RX data path
farb_in_data : in std_logic_vector(NR_PORTS*FABRIC_DATA_WIDTH-1 downto 0);
farb_in_valid : in std_logic_vector(NR_PORTS-1 downto 0);
farb_in_last : in std_logic_vector(NR_PORTS-1 downto 0);
farb_in_ports_req : in std_logic_vector(NR_PORTS-1 downto 0);
farb_in_prio : in std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
farb_in_timestamp : in std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
farb_in_length : in std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
farb_in_ports_gnt : out std_logic_vector(NR_PORTS-1 downto 0);
-- data TO the TX data path
farb_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
farb_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
farb_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
farb_out_valid : out std_logic;
farb_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
farb_out_req : out std_logic;
farb_out_accept_frame : in std_logic
);
end component;
signal reset : std_logic;
signal ports_req_sig : std_logic_vector(NR_PORTS*NR_PORTS-1 downto 0);
signal ports_gnt_sig : std_logic_vector(NR_PORTS*NR_PORTS-1 downto 0);
begin
reset <= not fabric_resetn;
-- reorder req and grant symbols
-- as one req/gnt signal of each input port should be connected to one arbitration module
assign_p : process(ports_gnt_sig, fabric_in_ports_req)
begin
for i in 0 to NR_PORTS-1 loop
for o in 0 to NR_PORTS-1 loop
ports_req_sig(i*NR_PORTS+o) <= fabric_in_ports_req(o*NR_PORTS+i);
fabric_in_ports_gnt(i*NR_PORTS+o) <= ports_gnt_sig(o*NR_PORTS+i);
end loop;
end loop;
end process;
-- connect the signals from the input port to the arbitration modules
Xarb : for INST in 0 to NR_PORTS-1 generate
fabric_arbitration : switch_fabric_arbitration
generic map(
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
NR_PORTS => NR_PORTS,
ARBITRATION => ARBITRATION,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
port map(
clk => fabric_clk,
reset => reset,
timestamp_cnt => timestamp_cnt,
-- data from the input ports
farb_in_data => fabric_in_data,
farb_in_valid => fabric_in_valid,
farb_in_last => fabric_in_last,
farb_in_ports_req => ports_req_sig((INST+1)*NR_PORTS-1 downto INST*NR_PORTS),
farb_in_prio => fabric_in_prio,
farb_in_timestamp => fabric_in_timestamp,
farb_in_length => fabric_in_length,
farb_in_ports_gnt => ports_gnt_sig((INST+1)*NR_PORTS-1 downto INST*NR_PORTS),
-- data to the output port
farb_out_prio => fabric_out_prio((INST+1)*VLAN_PRIO_WIDTH-1 downto INST*VLAN_PRIO_WIDTH),
farb_out_timestamp => fabric_out_timestamp((INST+1)*TIMESTAMP_WIDTH-1 downto INST*TIMESTAMP_WIDTH),
farb_out_data => fabric_out_data((INST+1)*FABRIC_DATA_WIDTH-1 downto INST*FABRIC_DATA_WIDTH),
farb_out_valid => fabric_out_valid(INST),
farb_out_length => fabric_out_length((INST+1)*FRAME_LENGTH_WIDTH-1 downto INST*FRAME_LENGTH_WIDTH),
farb_out_req => fabric_out_req(INST),
farb_out_accept_frame => fabric_out_accept_frame(INST)
);
end generate Xarb;
end structural;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_v8_2/hdl/blk_mem_input_block.vhd | 11 | 45404 | `protect begin_protected
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/blk_mem_gen_v8_2/hdl/blk_mem_axi_write_fsm.vhd | 11 | 61464 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 43760)
`protect data_block
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`protect end_protected
| mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/read_analog_io/_primary.vhd | 3 | 253 | library verilog;
use verilog.vl_types.all;
entity read_analog_io is
port(
serial_in : in vl_logic;
read_enb : in vl_logic;
parallel_out : out vl_logic_vector(63 downto 0)
);
end read_analog_io;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/hdl/builtin/bin_cntr.vhd | 5 | 8597 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4624)
`protect data_block
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`protect end_protected
| mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@d@s@s@a@b/_primary.vhd | 3 | 6424 | library verilog;
use verilog.vl_types.all;
entity DSSAB is
generic(
DAC_RESOLUTION : integer := 0
);
port(
DIGEN0 : in vl_logic;
DIGEN1 : in vl_logic;
DIGEN2 : in vl_logic;
DIGEN3 : in vl_logic;
DIGEN4 : in vl_logic;
DIGEN5 : in vl_logic;
DIGEN6 : in vl_logic;
DIGEN7 : in vl_logic;
DIGEN8 : in vl_logic;
DIGEN9 : in vl_logic;
DIGEN10 : in vl_logic;
DIGEN11 : in vl_logic;
DIGOUT0 : out vl_logic;
DIGOUT1 : out vl_logic;
DIGOUT2 : out vl_logic;
DIGOUT3 : out vl_logic;
DIGOUT4 : out vl_logic;
DIGOUT5 : out vl_logic;
DIGOUT6 : out vl_logic;
DIGOUT7 : out vl_logic;
DIGOUT8 : out vl_logic;
DIGOUT9 : out vl_logic;
DIGOUT10 : out vl_logic;
DIGOUT11 : out vl_logic;
ADCIN0 : in vl_logic;
ADCIN1 : in vl_logic;
ADCIN2 : in vl_logic;
ADCIN3 : in vl_logic;
ADCIN4 : in vl_logic;
ADCIN5 : in vl_logic;
ADCIN6 : in vl_logic;
ADCIN7 : in vl_logic;
ADCIN8 : in vl_logic;
ADCIN9 : in vl_logic;
ADCIN10 : in vl_logic;
ADCIN11 : in vl_logic;
DACOUT0 : out vl_logic;
DACOUT1 : out vl_logic;
DACOUT2 : out vl_logic;
AV1Q0 : in vl_logic;
AV1Q1 : in vl_logic;
AV1Q2 : in vl_logic;
AV1Q3 : in vl_logic;
AV1Q4 : in vl_logic;
AV1Q5 : in vl_logic;
AV2Q0 : in vl_logic;
AV2Q1 : in vl_logic;
AV2Q2 : in vl_logic;
AV2Q3 : in vl_logic;
AV2Q4 : in vl_logic;
AV2Q5 : in vl_logic;
ATQ0 : in vl_logic;
ATQ1 : in vl_logic;
ATQ2 : in vl_logic;
ATQ3 : in vl_logic;
ATQ4 : in vl_logic;
ATQ5 : in vl_logic;
ACQ0 : in vl_logic;
ACQ1 : in vl_logic;
ACQ2 : in vl_logic;
ACQ3 : in vl_logic;
ACQ4 : in vl_logic;
ACQ5 : in vl_logic;
ATRTN01 : in vl_logic;
ATRTN23 : in vl_logic;
ATRTN45 : in vl_logic;
VAREF0 : in vl_logic;
VAREF1 : in vl_logic;
VAREF2 : in vl_logic;
VAREFOUT : out vl_logic;
GNDREF : in vl_logic;
TVC0 : in vl_logic_vector(7 downto 0);
TVC1 : in vl_logic_vector(7 downto 0);
TVC2 : in vl_logic_vector(7 downto 0);
STC0 : in vl_logic_vector(7 downto 0);
STC1 : in vl_logic_vector(7 downto 0);
STC2 : in vl_logic_vector(7 downto 0);
MODE0 : in vl_logic_vector(3 downto 0);
MODE1 : in vl_logic_vector(3 downto 0);
MODE2 : in vl_logic_vector(3 downto 0);
VAREFSEL : in vl_logic;
START0 : in vl_logic;
START1 : in vl_logic;
START2 : in vl_logic;
PWRDWN0 : in vl_logic;
PWRDWN1 : in vl_logic;
PWRDWN2 : in vl_logic;
ADCRESET0 : in vl_logic;
ADCRESET1 : in vl_logic;
ADCRESET2 : in vl_logic;
CHNUMBER0 : in vl_logic_vector(4 downto 0);
CHNUMBER1 : in vl_logic_vector(4 downto 0);
CHNUMBER2 : in vl_logic_vector(4 downto 0);
BUSY0 : out vl_logic;
BUSY1 : out vl_logic;
BUSY2 : out vl_logic;
CALIBRATE0 : out vl_logic;
CALIBRATE1 : out vl_logic;
CALIBRATE2 : out vl_logic;
DATAVALID0 : out vl_logic;
DATAVALID1 : out vl_logic;
DATAVALID2 : out vl_logic;
SAMPLE0 : out vl_logic;
SAMPLE1 : out vl_logic;
SAMPLE2 : out vl_logic;
RESULT0 : out vl_logic_vector(11 downto 0);
RESULT1 : out vl_logic_vector(11 downto 0);
RESULT2 : out vl_logic_vector(11 downto 0);
ADCCLK0 : in vl_logic;
ADCCLK1 : in vl_logic;
ADCCLK2 : in vl_logic;
OBDIN0 : in vl_logic;
OBDIN1 : in vl_logic;
OBDIN2 : in vl_logic;
OBDCLK0 : in vl_logic;
OBDCLK1 : in vl_logic;
OBDCLK2 : in vl_logic;
OBDEN0 : in vl_logic;
OBDEN1 : in vl_logic;
OBDEN2 : in vl_logic;
ACMPOUT0 : out vl_logic;
ACMPOUT1 : out vl_logic;
ACMPOUT2 : out vl_logic;
ACMPOUT3 : out vl_logic;
ACMPOUT4 : out vl_logic;
ACMPOUT5 : out vl_logic;
ACMPOUT6 : out vl_logic;
ACMPOUT7 : out vl_logic;
ACMPOUT8 : out vl_logic;
ACMPOUT9 : out vl_logic;
ACMPOUT10 : out vl_logic;
ACMPOUT11 : out vl_logic;
ABPWRON : in vl_logic;
ACBRESET : in vl_logic;
ACBADDR : in vl_logic_vector(7 downto 0);
ACBWRE : in vl_logic;
ACBWDATA : in vl_logic_vector(7 downto 0);
ACBRDATA : out vl_logic_vector(7 downto 0)
);
end DSSAB;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_v12_0/hdl/builtin/fifo_generator_v12_0_builtin.vhd | 5 | 55499 | `protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/hdl/ramfifo/rd_handshaking_flags.vhd | 5 | 13954 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8592)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/ramfifo/rd_handshaking_flags.vhd | 5 | 13954 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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ldRRpb3CDQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8592)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/hdl/common/rd_pe_as.vhd | 5 | 25238 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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+7bt9SIT/w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16944)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/blk_mem_gen_v8_2/hdl/blk_mem_gen_top.vhd | 11 | 73440 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52624)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_v8_2/hdl/blk_mem_gen_bindec.vhd | 11 | 10218 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5824)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/builtin/reset_builtin.vhd | 5 | 19078 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12384)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_v12_0/hdl/builtin/reset_builtin.vhd | 5 | 19078 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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hkKu2/ksag==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12384)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_v12_0/hdl/builtin/reset_builtin.vhd | 5 | 19078 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12384)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_v12_0/hdl/common/synchronizer_ff.vhd | 5 | 8637 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4656)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/rtl/switch_port/tx/output_queue_arbitration.vhd | 2 | 8870 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.12.2013 10:00:16
-- Design Name:
-- Module Name: output_queue_arbitration - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: This module forwards the frames in the output queue memory to the transmitter-side of the MAC
-- The output queue fifo provides the start address in the output queue memory and the length in bytes
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity output_queue_arbitration is
Generic (
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
TIMESTAMP_WIDTH : integer;
OQ_MEM_ADDR_WIDTH : integer;
OQ_FIFO_DATA_WIDTH : integer;
OQ_FIFO_LENGTH_START : integer;
OQ_FIFO_TIMESTAMP_START : integer;
OQ_FIFO_MEM_PTR_START : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface fifo
oqarb_in_fifo_enable : out std_logic;
oqarb_in_fifo_prio : out std_logic;
oqarb_in_fifo_empty : in std_logic_vector(NR_OQ_FIFOS-1 downto 0);
oqarb_in_fifo_data : in std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
-- timestamp
oqarb_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
oqarb_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- input interface memory
oqarb_in_mem_data : in std_logic_vector(NR_OQ_FIFOS*TRANSMITTER_DATA_WIDTH-1 downto 0);
oqarb_in_mem_enable : out std_logic;
oqarb_in_mem_addr : out std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
oqarb_in_mem_prio : out std_logic;
-- output interface mac
oqarb_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
oqarb_out_valid : out std_logic;
oqarb_out_last : out std_logic;
oqarb_out_ready : in std_logic
);
end output_queue_arbitration;
architecture rtl of output_queue_arbitration is
-- state machine
type state is (
IDLE,
ARBITRATE,
READ_MEM
);
-- state signals
signal cur_state : state;
signal nxt_state : state;
signal empty_const : std_logic_vector(NR_OQ_FIFOS-1 downto 0) := (others => '1');
-- config_output_state machine signals
signal update_cnt_sig : std_logic;
signal reset_frame_length_sig : std_logic;
signal measure_latency_sig : std_logic;
signal choose_fifo_sig : std_logic;
-- process registers
signal frame_length_cnt : std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
signal latency_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal winner_fifo_reg : std_logic_vector(0 downto 0);
begin
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next data_input_state, combinitorial logic
output_logic_p : process(cur_state, oqarb_in_fifo_empty, oqarb_out_ready, frame_length_cnt, oqarb_in_fifo_data, empty_const, winner_fifo_reg)
begin
-- default signal assignments
nxt_state <= IDLE;
update_cnt_sig <= '0';
measure_latency_sig <= '0';
reset_frame_length_sig <= '0';
oqarb_in_fifo_enable <= '0';
oqarb_out_last <= '0';
oqarb_out_valid <= '0';
oqarb_in_fifo_prio <= '0';
choose_fifo_sig <= '0';
case cur_state is
when IDLE =>
if oqarb_in_fifo_empty /= empty_const and oqarb_out_ready = '1' then
nxt_state <= ARBITRATE;
choose_fifo_sig <= '1'; -- choose_fifo_p
end if;
when ARBITRATE =>
nxt_state <= READ_MEM;
update_cnt_sig <= '1'; -- cnt_frame_length_p
measure_latency_sig <= '1'; -- timestamp_p
when READ_MEM =>
if frame_length_cnt >= oqarb_in_fifo_data(to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_LENGTH_START+FRAME_LENGTH_WIDTH-1
downto to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_LENGTH_START)
and oqarb_out_ready = '1' then
nxt_state <= IDLE;
reset_frame_length_sig <= '1'; -- cnt_frame_length_p
oqarb_in_fifo_enable <= '1';
oqarb_in_fifo_prio <= winner_fifo_reg(0);
oqarb_out_last <= '1';
oqarb_out_valid <= '1';
else
nxt_state <= READ_MEM;
update_cnt_sig <= oqarb_out_ready; -- cnt_frame_length_p
oqarb_out_valid <= oqarb_out_ready;
end if;
end case;
end process output_logic_p;
-- count frame bytes received from fabric
cnt_frame_length_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
frame_length_cnt <= (others => '0');
else
frame_length_cnt <= frame_length_cnt;
if reset_frame_length_sig = '1' then
frame_length_cnt <= (others => '0');
elsif update_cnt_sig = '1' then
frame_length_cnt <= frame_length_cnt + 1;
end if;
end if;
end if;
end process;
-- take transmission timestamp of the message
timestamp_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
latency_reg <= (others => '0');
else
latency_reg <= latency_reg;
if measure_latency_sig = '1' then
latency_reg <= oqarb_in_timestamp_cnt - oqarb_in_fifo_data
(to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_TIMESTAMP_START+TIMESTAMP_WIDTH-1
downto to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_TIMESTAMP_START)
+ 50; -- considering the clock cycles through mac, rx, tx_fifo
end if;
end if;
end if;
end process;
-- determine the fifo to be read from
choose_fifo_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
winner_fifo_reg <= (others => '0');
else
winner_fifo_reg <= winner_fifo_reg;
if choose_fifo_sig = '1' then
if NR_OQ_FIFOS = 2 and oqarb_in_fifo_empty(NR_OQ_FIFOS-1) = '0' then -- high priority fifo
winner_fifo_reg(0) <= '1';
else
winner_fifo_reg(0) <= '0';
end if;
end if;
end if;
end if;
end process;
output_p : process(oqarb_in_mem_data, winner_fifo_reg)
begin
if NR_OQ_FIFOS = 1 then
oqarb_out_data <= oqarb_in_mem_data(TRANSMITTER_DATA_WIDTH-1 downto 0);
else
if winner_fifo_reg(0) = '0' then
oqarb_out_data <= oqarb_in_mem_data(TRANSMITTER_DATA_WIDTH-1 downto 0);
else
oqarb_out_data <= oqarb_in_mem_data(NR_OQ_FIFOS*TRANSMITTER_DATA_WIDTH-1 downto TRANSMITTER_DATA_WIDTH);
end if;
end if;
end process;
oqarb_in_mem_enable <= oqarb_out_ready;
oqarb_in_mem_addr <= oqarb_in_fifo_data(to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1
downto to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START) + frame_length_cnt;
oqarb_out_latency <= latency_reg;
oqarb_in_mem_prio <= winner_fifo_reg(0);
end rtl;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/rtl/switch_port/tx/tx_path_output_queue.vhd | 2 | 17817 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 09.12.2013 16:11:09
-- Design Name:
-- Module Name: tx_path_output_queue - structural
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: The output queue module accepts frames from the switching fabric
-- and forwards them to the transmitter side of the MAC
--
-- This module consists of 5 submodules:
-- oq_control: receives data from switching fabric and stores them in the memory and fifo
-- oq_memory: contains the frame data
-- oq_fifo: contains the memory start address of the corresponding frame as well as its length and arriving timestamp
-- priority fifo can be selected
-- oq_mem_check: checks if another frame can be accepted from the switching fabric based on
-- the status of the fifo and memory
-- oq_arbitration: as soon as the MAC is ready, the next frame will be read from the memory and
-- forwarded to the MAC
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tx_path_output_queue is
Generic (
FABRIC_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
OQ_MEM_ADDR_WIDTH_A : integer := 12; -- 8 bit: 14, 32 bit: 12
OQ_MEM_ADDR_WIDTH_B : integer := 14
);
Port (
clk : in std_logic;
reset : in std_logic;
-- tx_path interface to fabric
oq_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
oq_in_valid : in std_logic;
oq_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
oq_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oq_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
oq_in_req : in std_logic;
oq_in_accept_frame : out std_logic;
-- timestamp
oq_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
oq_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- tx_path interface to mac
oq_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
oq_out_valid : out std_logic;
oq_out_ready : in std_logic;
oq_out_last : out std_logic
);
end tx_path_output_queue;
architecture structural of tx_path_output_queue is
constant OQ_FIFO_DATA_WIDTH : integer := OQ_MEM_ADDR_WIDTH_B + TIMESTAMP_WIDTH + FRAME_LENGTH_WIDTH;
constant OQ_FIFO_LENGTH_START : integer := 0;
constant OQ_FIFO_TIMESTAMP_START : integer := OQ_FIFO_LENGTH_START + FRAME_LENGTH_WIDTH;
constant OQ_FIFO_MEM_PTR_START : integer := OQ_FIFO_TIMESTAMP_START + TIMESTAMP_WIDTH;
constant FABRIC2TRANSMITTER_DATA_WIDTH_RATIO : integer := FABRIC_DATA_WIDTH / TRANSMITTER_DATA_WIDTH;
component output_queue_control
Generic (
FABRIC_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
OQ_MEM_ADDR_WIDTH_A : integer;
OQ_MEM_ADDR_WIDTH_B : integer;
OQ_FIFO_DATA_WIDTH : integer;
FABRIC2TRANSMITTER_DATA_WIDTH_RATIO : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface fabric
oqctrl_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
oqctrl_in_valid : in std_logic;
oqctrl_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
oqctrl_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oqctrl_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- output interface memory check
oqctrl_out_mem_wr_addr : out std_logic_vector(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_B-1 downto 0);
-- output interface memory
oqctrl_out_mem_wenable : out std_logic;
oqctrl_out_mem_addr : out std_logic_vector(OQ_MEM_ADDR_WIDTH_A-1 downto 0);
oqctrl_out_mem_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
-- output interface fifo
oqctrl_out_fifo_wenable : out std_logic;
oqctrl_out_fifo_data : out std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
oqctrl_out_fifo_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0)
);
end component;
component output_queue_memory
Generic (
NR_OQ_MEM : integer;
VLAN_PRIO_WIDTH : integer;
OQ_MEM_ADDR_WIDTH_A : integer;
OQ_MEM_ADDR_WIDTH_B : integer;
OQ_MEM_DATA_WIDTH_IN : integer;
OQ_MEM_DATA_WIDTH_OUT : integer
);
Port (
--Port A -> control module
oqmem_in_wr_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oqmem_in_wenable : in std_logic_vector;
oqmem_in_addr : in std_logic_vector(OQ_MEM_ADDR_WIDTH_A-1 downto 0);
oqmem_in_data : in std_logic_vector(OQ_MEM_DATA_WIDTH_IN-1 downto 0);
oqmem_in_clk : in std_logic;
--Port B -> arbitration module -> mac
oqmem_out_rd_prio : in std_logic;
oqmem_out_enable : in std_logic;
oqmem_out_addr : in std_logic_vector(OQ_MEM_ADDR_WIDTH_B-1 downto 0);
oqmem_out_data : out std_logic_vector(NR_OQ_FIFOS*OQ_MEM_DATA_WIDTH_OUT-1 downto 0);
oqmem_out_clk : in std_logic
);
end component;
component output_queue_fifo
Generic (
OQ_FIFO_DATA_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
oqfifo_in_enable : in std_logic;
oqfifo_in_data : in std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
oqfifo_in_wr_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oqfifo_out_enable : in std_logic;
oqfifo_out_data : out std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
oqfifo_out_rd_prio : in std_logic;
oqfifo_out_full : out std_logic_vector(NR_OQ_FIFOS-1 downto 0);
oqfifo_out_empty : out std_logic_vector(NR_OQ_FIFOS-1 downto 0)
);
end component;
component output_queue_mem_check
Generic (
OQ_FIFO_DATA_WIDTH : integer;
OQ_MEM_ADDR_WIDTH : integer;
OQ_FIFO_MEM_PTR_START : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
req : in std_logic;
req_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
req_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
accept_frame : out std_logic;
mem_wr_ptr : in std_logic_vector(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH-1 downto 0);
fifo_data : in std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
fifo_full : in std_logic_vector(NR_OQ_FIFOS-1 downto 0);
fifo_empty : in std_logic_vector(NR_OQ_FIFOS-1 downto 0)
);
end component;
component output_queue_arbitration
Generic (
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
TIMESTAMP_WIDTH : integer;
OQ_MEM_ADDR_WIDTH : integer;
OQ_FIFO_DATA_WIDTH : integer;
OQ_FIFO_LENGTH_START : integer;
OQ_FIFO_TIMESTAMP_START : integer;
OQ_FIFO_MEM_PTR_START : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface fifo
oqarb_in_fifo_enable : out std_logic;
oqarb_in_fifo_prio : out std_logic;
oqarb_in_fifo_empty : in std_logic_vector(NR_OQ_FIFOS-1 downto 0);
oqarb_in_fifo_data : in std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
-- timestamp
oqarb_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
oqarb_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- input interface memory
oqarb_in_mem_data : in std_logic_vector(NR_OQ_FIFOS*TRANSMITTER_DATA_WIDTH-1 downto 0);
oqarb_in_mem_enable : out std_logic;
oqarb_in_mem_addr : out std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
oqarb_in_mem_prio : out std_logic;
-- output interface mac
oqarb_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
oqarb_out_valid : out std_logic;
oqarb_out_last : out std_logic;
oqarb_out_ready : in std_logic
);
end component;
signal oqctrl2oqmem_data : std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
signal oqctrl2oqmem_wenable : std_logic_vector(0 downto 0);
signal oqctrl2oqmem_addr : std_logic_vector(OQ_MEM_ADDR_WIDTH_A-1 downto 0);
signal oqctrl2oqfifo_wenable : std_logic;
signal oqctrl2oqfifo_data : std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
signal oqctrl2oqfifo_prio : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal oqmem2oqarb_enable : std_logic;
signal oqmem2oqarb_prio : std_logic;
signal oqmem2oqarb_addr : std_logic_vector(OQ_MEM_ADDR_WIDTH_B-1 downto 0);
signal oqmem2oqarb_data : std_logic_vector(NR_OQ_FIFOS*TRANSMITTER_DATA_WIDTH-1 downto 0);
signal oqfifo2oqarb_data : std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
signal oqfifo2oqarb_enable : std_logic;
signal oqfifo2oqarb_empty : std_logic_vector(NR_OQ_FIFOS-1 downto 0);
signal oqfifo2oqarb_prio : std_logic;
signal oqctrl2oqchk_mem_wr_addr : std_logic_vector(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_B-1 downto 0);
signal oqfifo2oqchk_full : std_logic_vector(NR_OQ_FIFOS-1 downto 0);
-- attribute mark_debug : string;
-- attribute mark_debug of oqctrl2oqmem_data: signal is "true";
-- attribute mark_debug of oqctrl2oqmem_wenable: signal is "true";
-- attribute mark_debug of oqctrl2oqmem_addr: signal is "true";
-- attribute mark_debug of oqctrl2oqfifo_data: signal is "true";
-- attribute mark_debug of oqmem2oqarb_enable: signal is "true";
-- attribute mark_debug of oqmem2oqarb_addr: signal is "true";
-- attribute mark_debug of oqmem2oqarb_data: signal is "true";
-- attribute mark_debug of oqfifo2oqarb_data: signal is "true";
-- attribute mark_debug of oqfifo2oqarb_enable: signal is "true";
-- attribute mark_debug of oqfifo2oqarb_empty: signal is "true";
-- attribute mark_debug of oqctrl2oqchk_mem_wr_addr: signal is "true";
-- attribute mark_debug of oqfifo2oqchk_full: signal is "true";
begin
oq_control : output_queue_control
Generic map(
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
OQ_MEM_ADDR_WIDTH_A => OQ_MEM_ADDR_WIDTH_A,
OQ_MEM_ADDR_WIDTH_B => OQ_MEM_ADDR_WIDTH_B,
OQ_FIFO_DATA_WIDTH => OQ_FIFO_DATA_WIDTH,
FABRIC2TRANSMITTER_DATA_WIDTH_RATIO => FABRIC2TRANSMITTER_DATA_WIDTH_RATIO
)
Port map(
clk => clk,
reset => reset,
-- input interface fabric
oqctrl_in_data => oq_in_data,
oqctrl_in_valid => oq_in_valid,
oqctrl_in_length => oq_in_length,
oqctrl_in_prio => oq_in_prio,
oqctrl_in_timestamp => oq_in_timestamp,
-- output interface memory check
oqctrl_out_mem_wr_addr => oqctrl2oqchk_mem_wr_addr,
-- output interface memory
oqctrl_out_mem_wenable => oqctrl2oqmem_wenable(0),
oqctrl_out_mem_addr => oqctrl2oqmem_addr,
oqctrl_out_mem_data => oqctrl2oqmem_data,
-- output interface fifo
oqctrl_out_fifo_wenable => oqctrl2oqfifo_wenable,
oqctrl_out_fifo_data => oqctrl2oqfifo_data,
oqctrl_out_fifo_prio => oqctrl2oqfifo_prio
);
oq_mem : output_queue_memory
Generic map(
NR_OQ_MEM => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
OQ_MEM_ADDR_WIDTH_A => OQ_MEM_ADDR_WIDTH_A,
OQ_MEM_ADDR_WIDTH_B => OQ_MEM_ADDR_WIDTH_B,
OQ_MEM_DATA_WIDTH_IN => FABRIC_DATA_WIDTH,
OQ_MEM_DATA_WIDTH_OUT => TRANSMITTER_DATA_WIDTH
)
Port map(
--Port A -> Control module
oqmem_in_wr_prio => oq_in_prio,
oqmem_in_wenable => oqctrl2oqmem_wenable,
oqmem_in_addr => oqctrl2oqmem_addr,
oqmem_in_data => oqctrl2oqmem_data,
oqmem_in_clk => clk,
--Port B -> Scheduling moudle
oqmem_out_rd_prio => oqmem2oqarb_prio,
oqmem_out_enable => oqmem2oqarb_enable,
oqmem_out_addr => oqmem2oqarb_addr,
oqmem_out_data => oqmem2oqarb_data,
oqmem_out_clk => clk
);
oq_fifo : output_queue_fifo
Generic map(
OQ_FIFO_DATA_WIDTH => OQ_FIFO_DATA_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH
)
Port map(
clk => clk,
reset => reset,
oqfifo_in_enable => oqctrl2oqfifo_wenable,
oqfifo_in_data => oqctrl2oqfifo_data,
oqfifo_in_wr_prio => oqctrl2oqfifo_prio,
oqfifo_out_enable => oqfifo2oqarb_enable,
oqfifo_out_data => oqfifo2oqarb_data,
oqfifo_out_rd_prio => oqfifo2oqarb_prio,
oqfifo_out_full => oqfifo2oqchk_full,
oqfifo_out_empty => oqfifo2oqarb_empty
);
oq_mem_check : output_queue_mem_check
Generic map(
OQ_FIFO_DATA_WIDTH => OQ_FIFO_DATA_WIDTH,
OQ_MEM_ADDR_WIDTH => OQ_MEM_ADDR_WIDTH_B,
OQ_FIFO_MEM_PTR_START => OQ_FIFO_MEM_PTR_START,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH
)
Port map(
clk => clk,
reset => reset,
req => oq_in_req,
req_length => oq_in_length,
req_prio => oq_in_prio,
accept_frame => oq_in_accept_frame,
mem_wr_ptr => oqctrl2oqchk_mem_wr_addr,
fifo_data => oqfifo2oqarb_data,
fifo_full => oqfifo2oqchk_full,
fifo_empty => oqfifo2oqarb_empty
);
oq_arbitration : output_queue_arbitration
Generic map(
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
OQ_MEM_ADDR_WIDTH => OQ_MEM_ADDR_WIDTH_B,
OQ_FIFO_DATA_WIDTH => OQ_FIFO_DATA_WIDTH,
OQ_FIFO_LENGTH_START => OQ_FIFO_LENGTH_START,
OQ_FIFO_TIMESTAMP_START => OQ_FIFO_TIMESTAMP_START,
OQ_FIFO_MEM_PTR_START => OQ_FIFO_MEM_PTR_START
)
Port map(
clk => clk,
reset => reset,
-- input interface fifo
oqarb_in_fifo_enable => oqfifo2oqarb_enable,
oqarb_in_fifo_prio => oqfifo2oqarb_prio,
oqarb_in_fifo_empty => oqfifo2oqarb_empty,
oqarb_in_fifo_data => oqfifo2oqarb_data,
-- timestamp
oqarb_in_timestamp_cnt => oq_in_timestamp_cnt,
oqarb_out_latency => oq_out_latency,
-- input interface memory
oqarb_in_mem_data => oqmem2oqarb_data,
oqarb_in_mem_enable => oqmem2oqarb_enable,
oqarb_in_mem_addr => oqmem2oqarb_addr,
oqarb_in_mem_prio => oqmem2oqarb_prio,
-- output interface mac
oqarb_out_data => oq_out_data,
oqarb_out_valid => oq_out_valid,
oqarb_out_last => oq_out_last,
oqarb_out_ready => oq_out_ready
);
end structural;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_v8_2/hdl/blk_mem_axi_regs_fwd.vhd | 11 | 9545 | `protect begin_protected
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_2/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_synth_comp.vhd | 11 | 18409 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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phBwKO7DKg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11888)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/builtin/fifo_generator_v12_0_comps_builtin.vhd | 5 | 32006 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21952)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/blk_mem_gen_v8_2/hdl/blk_mem_min_area_pkg.vhd | 11 | 20310 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13296)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/blk_mem_gen_v8_2/hdl/blk_mem_min_area_pkg.vhd | 11 | 20310 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13296)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_v12_0/hdl/ramfifo/async_fifo.vhd | 5 | 33343 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22944)
`protect data_block
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`protect end_protected
| mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e/_primary.vhd | 3 | 4083 | library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE is
port(
HCLK : in vl_logic;
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA : out vl_logic_vector(31 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic;
INTERRUPT : out vl_logic_vector(85 downto 0);
ADC0_TVC : out vl_logic_vector(7 downto 0);
ADC1_TVC : out vl_logic_vector(7 downto 0);
ADC2_TVC : out vl_logic_vector(7 downto 0);
ADC0_STC : out vl_logic_vector(7 downto 0);
ADC1_STC : out vl_logic_vector(7 downto 0);
ADC2_STC : out vl_logic_vector(7 downto 0);
ADC0_MODE : out vl_logic_vector(3 downto 0);
ADC1_MODE : out vl_logic_vector(3 downto 0);
ADC2_MODE : out vl_logic_vector(3 downto 0);
ADC_VAREFSEL : out vl_logic;
ABPOWERON : out vl_logic;
ADC0_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC1_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC2_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC0_ADCSTART : out vl_logic;
ADC1_ADCSTART : out vl_logic;
ADC2_ADCSTART : out vl_logic;
ADC0_PWRDWN : out vl_logic;
ADC1_PWRDWN : out vl_logic;
ADC2_PWRDWN : out vl_logic;
ADC0_ADCRESET : out vl_logic;
ADC1_ADCRESET : out vl_logic;
ADC2_ADCRESET : out vl_logic;
ADC0_BUSY : in vl_logic;
ADC1_BUSY : in vl_logic;
ADC2_BUSY : in vl_logic;
ADC0_CALIBRATE : in vl_logic;
ADC1_CALIBRATE : in vl_logic;
ADC2_CALIBRATE : in vl_logic;
ADC0_DATAVALID : in vl_logic;
ADC1_DATAVALID : in vl_logic;
ADC2_DATAVALID : in vl_logic;
ADC0_SAMPLE : in vl_logic;
ADC1_SAMPLE : in vl_logic;
ADC2_SAMPLE : in vl_logic;
ADC0_RESULT : in vl_logic_vector(11 downto 0);
ADC1_RESULT : in vl_logic_vector(11 downto 0);
ADC2_RESULT : in vl_logic_vector(11 downto 0);
ACB_ADDR : out vl_logic_vector(7 downto 0);
ACB_WRE : out vl_logic;
ACB_WDATA : out vl_logic_vector(7 downto 0);
ACB_RDATA : in vl_logic_vector(7 downto 0);
ACB_RESETN : out vl_logic;
COMPARATOR : in vl_logic_vector(11 downto 0);
OBD_DOUT : out vl_logic_vector(2 downto 0);
OBD_CLKOUT : out vl_logic_vector(2 downto 0);
OBD_ENABLE : out vl_logic_vector(2 downto 0);
FPGA_OBD_DOUT : in vl_logic_vector(2 downto 0);
FPGA_OBD_CLKOUT : in vl_logic_vector(2 downto 0);
FPGA_TRIGGER : in vl_logic;
FPGA_FLAGS : out vl_logic_vector(31 downto 0);
ACE_INREADY : out vl_logic;
ACE_OUTREADY : out vl_logic;
TESTMODE : in vl_logic;
RB_TEST : in vl_logic;
PPE_CSBA : in vl_logic;
PPE_CSBB : in vl_logic;
PPE_RWBA : in vl_logic;
PPE_RWBB : in vl_logic;
PPE_ADA : in vl_logic_vector(8 downto 0);
PPE_ADB : in vl_logic_vector(8 downto 0);
PPE_WDA : in vl_logic_vector(31 downto 0);
PPE_WDB : in vl_logic_vector(31 downto 0);
PPE_RDA : out vl_logic_vector(31 downto 0);
PPE_RDB : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_2/blk_mem_gen_2_funcsim.vhdl | 1 | 118209 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:45:06 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_2/blk_mem_gen_2_funcsim.vhdl
-- Design : blk_mem_gen_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_prim_wrapper is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end blk_mem_gen_2blk_mem_gen_prim_wrapper;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_prim_width is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end blk_mem_gen_2blk_mem_gen_prim_width;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.blk_mem_gen_2blk_mem_gen_prim_wrapper
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end blk_mem_gen_2blk_mem_gen_generic_cstr;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.blk_mem_gen_2blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 6) => dina(25 downto 24),
dina(5 downto 4) => dina(17 downto 16),
dina(3 downto 2) => dina(9 downto 8),
dina(1 downto 0) => dina(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 6) => dina(27 downto 26),
dina(5 downto 4) => dina(19 downto 18),
dina(3 downto 2) => dina(11 downto 10),
dina(1 downto 0) => dina(3 downto 2),
doutb(1 downto 0) => doutb(3 downto 2),
enb => enb,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 6) => dina(29 downto 28),
dina(5 downto 4) => dina(21 downto 20),
dina(3 downto 2) => dina(13 downto 12),
dina(1 downto 0) => dina(5 downto 4),
doutb(1 downto 0) => doutb(5 downto 4),
enb => enb,
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 6) => dina(31 downto 30),
dina(5 downto 4) => dina(23 downto 22),
dina(3 downto 2) => dina(15 downto 14),
dina(1 downto 0) => dina(7 downto 6),
doutb(1 downto 0) => doutb(7 downto 6),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_top : entity is "blk_mem_gen_top";
end blk_mem_gen_2blk_mem_gen_top;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_top is
begin
\valid.cstr\: entity work.blk_mem_gen_2blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_v8_2_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end blk_mem_gen_2blk_mem_gen_v8_2_synth;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.blk_mem_gen_2blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "no_coe_file_loaded";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_2.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "READ_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 32;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 32;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 4096;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 4096;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 12;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "READ_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 16384;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 14;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "4";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 10.9418 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(31) <= \<const0>\;
douta(30) <= \<const0>\;
douta(29) <= \<const0>\;
douta(28) <= \<const0>\;
douta(27) <= \<const0>\;
douta(26) <= \<const0>\;
douta(25) <= \<const0>\;
douta(24) <= \<const0>\;
douta(23) <= \<const0>\;
douta(22) <= \<const0>\;
douta(21) <= \<const0>\;
douta(20) <= \<const0>\;
douta(19) <= \<const0>\;
douta(18) <= \<const0>\;
douta(17) <= \<const0>\;
douta(16) <= \<const0>\;
douta(15) <= \<const0>\;
douta(14) <= \<const0>\;
douta(13) <= \<const0>\;
douta(12) <= \<const0>\;
douta(11) <= \<const0>\;
douta(10) <= \<const0>\;
douta(9) <= \<const0>\;
douta(8) <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.blk_mem_gen_2blk_mem_gen_v8_2_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2 is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of blk_mem_gen_2 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_2 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of blk_mem_gen_2 : entity is "blk_mem_gen_v8_2,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of blk_mem_gen_2 : entity is "blk_mem_gen_2,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of blk_mem_gen_2 : entity is "blk_mem_gen_2,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 10.9418 mW}";
end blk_mem_gen_2;
architecture STRUCTURE of blk_mem_gen_2 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 1;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 10.9418 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "blk_mem_gen_2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 4096;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 4096;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(31 downto 0) => dina(31 downto 0),
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(31 downto 0) => NLW_U0_douta_UNCONNECTED(31 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
eccpipece => '0',
ena => '0',
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd | 5 | 613661 | `protect begin_protected
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd | 5 | 613661 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 452528)
`protect data_block
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`protect end_protected
| mit |
gihankarunarathne/vhdl-learn | tute_I/Tutorial_I/Full_Subtractor.vhd | 1 | 1066 | ----------------------------------------------------------------------------------
-- Company: UOM
-- Engineer: Gihan Karunarathne
--
-- Create Date: 11:40:23 08/21/2013
-- Design Name:
-- Module Name: Full_Subtractor - Behavioral
-- Project Name: Tutorial I
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Full_Subtractor is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
D : out STD_LOGIC;
B : out STD_LOGIC);
end Full_Subtractor;
architecture Behavioral of Full_Subtractor is
begin
D <= x xor y xor z;
B <= (z and not(x xor y)) or (not x and y) ;
end Behavioral;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/ramfifo/logic_sshft.vhd | 5 | 30599 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20912)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_v12_0/hdl/builtin/builtin_top_v6.vhd | 5 | 52905 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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td8zI3B0cA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37424)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_2/blk_mem_gen_v8_2/hdl/blk_mem_axi_write_wrapper.vhd | 11 | 66283 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_decoder.vhd | 11 | 24873 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_decoder.vhd | 11 | 24873 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/ramfifo/wr_logic.vhd | 5 | 41428 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 28928)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_v8_2/hdl/blk_mem_gen_prim_width.vhd | 11 | 71859 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 51456)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/blk_mem_gen_v8_2/hdl/blk_mem_gen_prim_width.vhd | 11 | 71859 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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yILZZ+w5TQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 51456)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_v12_0/hdl/common/shft_ram.vhd | 5 | 17157 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960)
`protect data_block
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`protect end_protected
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_v12_0/hdl/builtin/builtin_top.vhd | 5 | 75016 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 53792)
`protect data_block
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`protect end_protected
| mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/acb_96_bit/_primary.vhd | 3 | 2560 | library verilog;
use verilog.vl_types.all;
entity acb_96_bit is
generic(
ANALOG_QUAD_NUM : integer := 6;
ACB_BYTES_NUM_PER_QUAD: integer := 12;
WARNING_MSGS_ON : integer := 1
);
port(
ACB_RST : in vl_logic;
ACB_WEN : in vl_logic;
ACB_ADDR : in vl_logic_vector(7 downto 0);
ACB_WDATA : in vl_logic_vector(7 downto 0);
ACB_RDATA : out vl_logic_vector(7 downto 0);
AQO_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQO_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQO_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQO_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ0_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ1_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ1_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ1_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ1_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ1_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ2_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ2_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ2_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ2_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ2_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ3_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ3_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ3_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ3_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ3_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ4_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ4_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ4_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ4_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ4_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ5_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ5_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ5_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ5_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ5_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
DAC0_CONFIG : out vl_logic_vector(1 downto 0);
DAC1_CONFIG : out vl_logic_vector(1 downto 0);
DAC2_CONFIG : out vl_logic_vector(1 downto 0)
);
end acb_96_bit;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 11 | 19921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/drive_varef_out/_primary.vhd | 3 | 255 | library verilog;
use verilog.vl_types.all;
entity drive_varef_out is
port(
parallel_in : in vl_logic_vector(63 downto 0);
en_out : in vl_logic;
serial_out : out vl_logic
);
end drive_varef_out;
| mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_v8_2/hdl/blk_mem_axi_read_wrapper.vhd | 11 | 57813 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 41056)
`protect data_block
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lNNktTVmxgYUeqweyvYcko/cLFuNn6SQIxpmDj7sfTaWDqM0HIIw/IwJW2bsEq9jNzYIu1eMYLAz
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phQuLfyOnbVCW8DCwo/pKvfphMd0lEe8o+97md4n6Rd14hsOvzldGrJZxBZvs+XnHxI2lKRdietB
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SD0qeWtx1+dZI+2PzMMahgYpRE3TmX1o1dfHZnv7TmAblzxXsnJ5LryzJYo8Sjf6WB9KcsBO4OXA
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aSJ574q+UK7bHr1B8a3eHXvBhcWH4exdfBTJx55HZAbHE+qo3i63uIq8HSt1nnF6kV3wDehfL86i
Nm/i3Cz7n+p8Dd++Gw2YME/YX2zCuZygrjhov3mOK+5gExOhAx5j8imXhjtOXYLGDs1bktA+EIrc
YvTf58MMbC5jYuM20zes+g==
`protect end_protected
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/78a53aabfa0cdc31/dbg_ila_sim_netlist.vhdl | 1 | 4920526 | null | mit |
GOOD-Stuff/srio_test | srio_test.srcs/sources_1/ip/ila_0/ila_0_stub.vhdl | 2 | 2438 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Fri Sep 22 16:52:26 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/ila_0/ila_0_stub.vhdl
-- Design : ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ila_0 is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe19 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end ila_0;
architecture stub of ila_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[7:0],probe20[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/c5918a3d400116a5/ila_0_stub.vhdl | 1 | 2585 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Fri Sep 22 16:52:24 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.vhdl
-- Design : ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe19 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[7:0],probe20[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/1307ce7a11e7d807/vio_0_stub.vhdl | 1 | 1701 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 14 10:23:02 2017
-- Host : PC4719 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_stub.vhdl
-- Design : vio_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[0:0],probe_in2[0:0],probe_in3[0:0],probe_out0[0:0],probe_out1[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2016.3";
begin
end;
| mit |
superboy0712/MIPS | testbench/IFID_register_tb.vhd | 1 | 1765 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY IFID_register_tb IS
END IFID_register_tb;
ARCHITECTURE behavior OF IFID_register_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IFID_register
port
(Clk, reset : in std_logic;
instruction_i, pc_i: in std_logic_vector(31 downto 0);
instruction_o, pc_o : out std_logic_vector(31 downto 0));
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal instruction_i, pc_i : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal instruction_o, pc_o : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IFID_register PORT MAP (
clk => clk,
reset => reset,
instruction_i => instruction_i,
instruction_o => instruction_o,
pc_i => pc_i,
pc_o => pc_o
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
-- write some data
wait for clk_period/2;
pc_i <= x"1000_1000";
instruction_i <= x"0101_0101";
wait for clk_period;
pc_i <= x"FEDC_BA98";
instruction_i <= x"F00F_F00F";
wait for clk_period*2;
assert false report "end of simulation" severity failure;
wait;
end process;
END; | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/01b1ddbaf2a615e4/ila_0_stub.vhdl | 1 | 1615 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Sep 19 16:38:23 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.vhdl
-- Design : ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/fa0e15bef86d4695/dbg_ila_stub.vhdl | 1 | 1921 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 25 09:34:51 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.vhdl
-- Design : dbg_ila
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe3 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[31:0],probe3[31:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_sqrt_s5.vhd | 10 | 96933 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sqrt_s5
-- VHDL created on Thu Mar 7 14:37:27 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (7 downto 0);
signal sBias_uid25_fpSqrtTest_q : std_logic_vector (7 downto 0);
signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (7 downto 0);
signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (7 downto 0);
signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (22 downto 0);
signal prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid61_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid61_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid61_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_fracSelIn_uid46_fpSqrtTest_0_to_fracSel_uid47_fpSqrtTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid61_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid62_sqrtPolynomialEvaluator_0_to_prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_sqrtTableGenerator_lutmem_0_to_prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid60_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid60_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_0_q : std_logic_vector (20 downto 0);
signal reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_0_q : std_logic_vector (28 downto 0);
signal ld_fracX_uid7_fpSqrtTest_b_to_FracX15dto0_uid37_fpSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid60_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_fracX_uid7_fpSqrtTest_b_to_FracX15dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true;
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic;
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpSqrtTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSqrtTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSqrtTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (8 downto 0);
signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (7 downto 0);
signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal FracX15dto0_uid37_fpSqrtTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid37_fpSqrtTest_b : std_logic_vector (15 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0);
signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expREven_uid27_fpSqrtTest_in : std_logic_vector (8 downto 0);
signal expREven_uid27_fpSqrtTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid62_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid62_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid72_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid72_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid72_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal fracR_uid39_fpSqrtTest_in : std_logic_vector (28 downto 0);
signal fracR_uid39_fpSqrtTest_b : std_logic_vector (22 downto 0);
signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (22 downto 0);
signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (31 downto 0);
signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0);
signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid8_fpSqrtTest(BITSELECT,7)@0
signX_uid8_fpSqrtTest_in <= a;
signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(31 downto 31);
--cstAllZWE_uid11_fpSqrtTest(CONSTANT,10)
cstAllZWE_uid11_fpSqrtTest_q <= "00000000";
--expX_uid6_fpSqrtTest(BITSELECT,5)@0
expX_uid6_fpSqrtTest_in <= a(30 downto 0);
expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(30 downto 23);
--expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0
expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b;
expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q;
expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0";
--negZero_uid56_fpSqrtTest(LOGICAL,55)@0
negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q;
negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b;
negZero_uid56_fpSqrtTest_q <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c(DELAY,149)@0
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_notEnable(LOGICAL,192)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,193)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_notEnable_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b);
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_mem_top(CONSTANT,189)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmp(LOGICAL,190)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmp_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_mem_top_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmp_a = ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmpReg(REG,191)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,194)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,195)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b;
--cstAllOWE_uid9_fpSqrtTest(CONSTANT,8)
cstAllOWE_uid9_fpSqrtTest_q <= "11111111";
--sBiasM1_uid28_fpSqrtTest(CONSTANT,27)
sBiasM1_uid28_fpSqrtTest_q <= "01111110";
--expOddSig_uid29_fpSqrtTest(ADD,28)@0
expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b);
expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q);
expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b));
expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(8 downto 0);
--expROdd_uid30_fpSqrtTest(BITSELECT,29)@0
expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q;
expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(8 downto 1);
--sBias_uid25_fpSqrtTest(CONSTANT,24)
sBias_uid25_fpSqrtTest_q <= "01111111";
--expEvenSig_uid26_fpSqrtTest(ADD,25)@0
expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b);
expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q);
expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b));
expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(8 downto 0);
--expREven_uid27_fpSqrtTest(BITSELECT,26)@0
expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q;
expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(8 downto 1);
--expX0_uid31_fpSqrtTest(BITSELECT,30)@0
expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0);
expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0);
--expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0
expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b;
expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a;
--expRMux_uid33_fpSqrtTest(MUX,32)@0
expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q;
expRMux_uid33_fpSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid33_fpSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid33_fpSqrtTest_s IS
WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b;
WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b;
WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0
InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q;
InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a;
--cstAllZWF_uid10_fpSqrtTest(CONSTANT,9)
cstAllZWF_uid10_fpSqrtTest_q <= "00000000000000000000000";
--fracX_uid7_fpSqrtTest(BITSELECT,6)@0
fracX_uid7_fpSqrtTest_in <= a(22 downto 0);
fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(22 downto 0);
--fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0
fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b;
fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q;
fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0";
--expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0
expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b;
expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q;
expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0";
--exc_I_uid18_fpSqrtTest(LOGICAL,17)@0
exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q;
exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q;
exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b;
--InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0
InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q;
InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a;
--InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0
InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q;
InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a;
--exc_R_uid24_fpSqrtTest(LOGICAL,23)@0
exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q;
exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q;
exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q;
exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c;
--minReg_uid42_fpSqrtTest(LOGICAL,41)@0
minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q;
minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b;
minReg_uid42_fpSqrtTest_q <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b;
--minInf_uid43_fpSqrtTest(LOGICAL,42)@0
minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q;
minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b;
minInf_uid43_fpSqrtTest_q <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b;
--InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0
InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q;
InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a;
--exc_N_uid20_fpSqrtTest(LOGICAL,19)@0
exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q;
exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q;
exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b;
--excRNaN_uid44_fpSqrtTest(LOGICAL,43)@0
excRNaN_uid44_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q;
excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q;
excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q;
excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c;
--InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0
InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b;
InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a;
--inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0
inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q;
inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q;
inInfAndNotNeg_uid41_fpSqrtTest_q <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b;
--join_uid45_fpSqrtTest(BITJOIN,44)@0
join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & expXIsZero_uid13_fpSqrtTest_q;
--fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@0
fracSelIn_uid46_fpSqrtTest_q <= signX_uid8_fpSqrtTest_b & join_uid45_fpSqrtTest_q;
--reg_fracSelIn_uid46_fpSqrtTest_0_to_fracSel_uid47_fpSqrtTest_0(REG,83)@0
reg_fracSelIn_uid46_fpSqrtTest_0_to_fracSel_uid47_fpSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid46_fpSqrtTest_0_to_fracSel_uid47_fpSqrtTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid46_fpSqrtTest_0_to_fracSel_uid47_fpSqrtTest_0_q <= fracSelIn_uid46_fpSqrtTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid47_fpSqrtTest(LOOKUP,46)@1
fracSel_uid47_fpSqrtTest: PROCESS (reg_fracSelIn_uid46_fpSqrtTest_0_to_fracSel_uid47_fpSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid46_fpSqrtTest_0_to_fracSel_uid47_fpSqrtTest_0_q) IS
WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01";
WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10";
WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10";
WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN OTHERS =>
fracSel_uid47_fpSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid51_fpSqrtTest(MUX,50)@1
expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q;
expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, expRMux_uid33_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q)
BEGIN
CASE expRPostExc_uid51_fpSqrtTest_s IS
WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q;
WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= expRMux_uid33_fpSqrtTest_q;
WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q;
WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q;
WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,183)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdcnt(COUNTER,185)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdreg(REG,186)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdmux(MUX,187)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,184)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(7 downto 0);
--fracNaN_uid52_fpSqrtTest(CONSTANT,51)
fracNaN_uid52_fpSqrtTest_q <= "00000000000000000000001";
--fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0
fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b;
fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(22 downto 16);
--addrTable_uid36_fpSqrtTest(BITJOIN,35)@0
addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b;
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid61_sqrtTableGenerator_lutmem_0(REG,84)@0
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid61_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid61_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid61_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_sqrtTableGenerator_lutmem(DUALMEM,82)@1
memoryC2_uid61_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid61_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid61_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid61_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid61_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_s5_memoryC2_uid61_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid61_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid61_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid61_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid61_sqrtTableGenerator_lutmem_q <= memoryC2_uid61_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_sqrtTableGenerator_lutmem_0_to_prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_1(REG,86)@3
reg_memoryC2_uid61_sqrtTableGenerator_lutmem_0_to_prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_sqrtTableGenerator_lutmem_0_to_prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_sqrtTableGenerator_lutmem_0_to_prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_1_q <= memoryC2_uid61_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid7_fpSqrtTest_b_to_FracX15dto0_uid37_fpSqrtTest_a_inputreg(DELAY,182)
ld_fracX_uid7_fpSqrtTest_b_to_FracX15dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX15dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid7_fpSqrtTest_b_to_FracX15dto0_uid37_fpSqrtTest_a(DELAY,123)@0
ld_fracX_uid7_fpSqrtTest_b_to_FracX15dto0_uid37_fpSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX15dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX15dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid37_fpSqrtTest(BITSELECT,36)@3
FracX15dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX15dto0_uid37_fpSqrtTest_a_q(15 downto 0);
FracX15dto0_uid37_fpSqrtTest_b <= FracX15dto0_uid37_fpSqrtTest_in(15 downto 0);
--yT1_uid62_sqrtPolynomialEvaluator(BITSELECT,61)@3
yT1_uid62_sqrtPolynomialEvaluator_in <= FracX15dto0_uid37_fpSqrtTest_b;
yT1_uid62_sqrtPolynomialEvaluator_b <= yT1_uid62_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid62_sqrtPolynomialEvaluator_0_to_prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_0(REG,85)@3
reg_yT1_uid62_sqrtPolynomialEvaluator_0_to_prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_sqrtPolynomialEvaluator_0_to_prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_sqrtPolynomialEvaluator_0_to_prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_0_q <= yT1_uid62_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator(MULT,74)@4
prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_b);
prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_a <= reg_yT1_uid62_sqrtPolynomialEvaluator_0_to_prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_0_q;
prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid61_sqrtTableGenerator_lutmem_0_to_prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_1_q;
prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_q <= prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_sqrtPolynomialEvaluator(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_sqrtPolynomialEvaluator_in <= prodXY_uid75_pT1_uid63_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid76_pT1_uid63_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid76_pT1_uid63_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid65_sqrtPolynomialEvaluator(BITSELECT,64)@7
highBBits_uid65_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid76_pT1_uid63_sqrtPolynomialEvaluator_b;
highBBits_uid65_sqrtPolynomialEvaluator_b <= highBBits_uid65_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid60_sqrtTableGenerator_lutmem_0_a(DELAY,176)@0
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid60_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid60_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid60_sqrtTableGenerator_lutmem_0(REG,87)@3
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid60_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid60_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid60_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid60_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid60_sqrtTableGenerator_lutmem(DUALMEM,81)@4
memoryC1_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid60_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid60_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_s5_memoryC1_uid60_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid60_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid60_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid60_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid60_sqrtTableGenerator_lutmem_q <= memoryC1_uid60_sqrtTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_0(REG,88)@6
reg_memoryC1_uid60_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_0_q <= memoryC1_uid60_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_sqrtPolynomialEvaluator(ADD,65)@7
sumAHighB_uid66_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_0_q(20)) & reg_memoryC1_uid60_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid66_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_sqrtPolynomialEvaluator_b(11)) & highBBits_uid65_sqrtPolynomialEvaluator_b);
sumAHighB_uid66_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid66_sqrtPolynomialEvaluator_b));
sumAHighB_uid66_sqrtPolynomialEvaluator_q <= sumAHighB_uid66_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid64_sqrtPolynomialEvaluator(BITSELECT,63)@7
lowRangeB_uid64_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid76_pT1_uid63_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid64_sqrtPolynomialEvaluator_b <= lowRangeB_uid64_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid64_uid67_sqrtPolynomialEvaluator(BITJOIN,66)@7
s1_uid64_uid67_sqrtPolynomialEvaluator_q <= sumAHighB_uid66_sqrtPolynomialEvaluator_q & lowRangeB_uid64_sqrtPolynomialEvaluator_b;
--reg_s1_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_1(REG,90)@7
reg_s1_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_1_q <= s1_uid64_uid67_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,204)
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_nor_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_notEnable_q;
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_nor_b <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_sticky_ena_q;
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_nor_a or ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_nor_b);
--ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_cmpReg(REG,202)
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,205)
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,206)
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_sticky_ena_q;
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en;
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_enaAnd_b;
--ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,196)
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => FracX15dto0_uid37_fpSqrtTest_b, xout => ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,198)
-- every=1, low=0, high=1, step=1, init=1
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,1));
--ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,199)
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,200)
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en;
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q)
BEGIN
CASE ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS
WHEN "0" => ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
WHEN "1" => ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,197)
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_inputreg_q;
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_rdmux_q;
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 1,
numwords_a => 2,
width_b => 16,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_iq,
address_a => ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_aa,
data_a => ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_ia
);
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset;
ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_iq(15 downto 0);
--reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0(REG,89)@7
reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_q <= ld_FracX15dto0_uid37_fpSqrtTest_b_to_reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator(MULT,77)@8
prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_b);
prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_a <= reg_FracX15dto0_uid37_fpSqrtTest_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_0_q;
prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_b <= reg_s1_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_1_q;
prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_q <= prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_sqrtPolynomialEvaluator(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_sqrtPolynomialEvaluator_in <= prodXY_uid78_pT2_uid69_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid79_pT2_uid69_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid79_pT2_uid69_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid71_sqrtPolynomialEvaluator(BITSELECT,70)@11
highBBits_uid71_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid79_pT2_uid69_sqrtPolynomialEvaluator_b;
highBBits_uid71_sqrtPolynomialEvaluator_b <= highBBits_uid71_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,217)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_notEnable_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,213)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "0100";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,214)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_mem_top_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmp_b else "0";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,215)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,218)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,219)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,207)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,209)
-- every=1, low=0, high=4, step=1, init=1
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 3 THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 4;
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,3));
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,210)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,211)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,208)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,91)@7
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,80)@8
memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q;
memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(28 downto 0);
--reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_0(REG,92)@10
reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_sqrtPolynomialEvaluator(ADD,71)@11
sumAHighB_uid72_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_0_q(28)) & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid72_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid71_sqrtPolynomialEvaluator_b(21)) & highBBits_uid71_sqrtPolynomialEvaluator_b);
sumAHighB_uid72_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid72_sqrtPolynomialEvaluator_b));
sumAHighB_uid72_sqrtPolynomialEvaluator_q <= sumAHighB_uid72_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid70_sqrtPolynomialEvaluator(BITSELECT,69)@11
lowRangeB_uid70_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid79_pT2_uid69_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid70_sqrtPolynomialEvaluator_b <= lowRangeB_uid70_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid70_uid73_sqrtPolynomialEvaluator(BITJOIN,72)@11
s2_uid70_uid73_sqrtPolynomialEvaluator_q <= sumAHighB_uid72_sqrtPolynomialEvaluator_q & lowRangeB_uid70_sqrtPolynomialEvaluator_b;
--fracR_uid39_fpSqrtTest(BITSELECT,38)@11
fracR_uid39_fpSqrtTest_in <= s2_uid70_uid73_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(28 downto 6);
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b(DELAY,143)@1
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid55_fpSqrtTest(MUX,54)@11
fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_q;
fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, fracR_uid39_fpSqrtTest_b, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q)
BEGIN
CASE fracRPostExc_uid55_fpSqrtTest_s IS
WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q;
WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= fracR_uid39_fpSqrtTest_b;
WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q;
WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid57_fpSqrtTest(BITJOIN,56)@11
RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q;
--xOut(GPOUT,4)@11
q <= RSqrt_uid57_fpSqrtTest_q;
end normal;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fpc_library_package_sv.vhd | 10 | 48066 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package;
PACKAGE BODY fpc_library_package is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fpc_library_package_sv.vhd | 10 | 48066 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package;
PACKAGE BODY fpc_library_package is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/dp_exp_core.vhd | 10 | 24362 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION EXPONENT(e) - CORE ***
--*** ***
--*** DP_EXP_CORE.VHD ***
--*** ***
--*** Function: Double Precision Exponent Core ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 19 + 2*doublespeed ***
--*** SIII/IV Latency = 17 ***
--***************************************************
ENTITY dp_exp_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aasgn : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (54 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
rangeerror : OUT STD_LOGIC
);
END dp_exp_core;
ARCHITECTURE rtl OF dp_exp_core IS
--SII mullatency = doublespeed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
constant ranlatency : positive := 15+2*doublespeed-device*(2+2*doublespeed);
type expcalcfftype IS ARRAY ((ranlatency-4) DOWNTO 1) OF
STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
-- INPUT BLOCK & SHIFTER
signal signff : STD_LOGIC_VECTOR (ranlatency+3 DOWNTO 1);
signal aamanff, aamandelff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal aaexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal leftshift, rightshift : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal leftshiftff, rightshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal cmpexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal bigexpff : STD_LOGIC_VECTOR(2 DOWNTO 1);
signal smallrightshift : STD_LOGIC;
signal selshiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal powerbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal leftone, lefttwo : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal rightone, righttwo, rightthree : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal leftff, rightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal powerff : STD_LOGIC_VECTOR (65 DOWNTO 1);
signal decimalleft : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal decimalright : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal fractionalleft, fractionalright : STD_LOGIC_VECTOR (54 DOWNTO 1);
-- TABLES
signal addlutposff, addlutnegff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal addluttwoff, addlutthrff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal lutposmanff, lutnegmanff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal luttwomanff, lutthrmanff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal lutposexpff, lutnegexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal luttwoexpff : STD_LOGIC;
signal manpos, manneg, mantwo, manthr : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exppos, expneg : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal exptwo : STD_LOGIC;
signal lutonemanff, luttwomandelff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal lutoneexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal luttwoexpdelff : STD_LOGIC;
signal expcalcff : expcalcfftype;
-- OVER & UNDERFLOW
signal powercheck : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal rangeff : STD_LOGIC_VECTOR (ranlatency DOWNTO 1);
-- TAYLOR SERIES
signal fraction : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal xterm : STD_LOGIC_VECTOR (33 DOWNTO 1);
signal xsquareterm : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal approxff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal lutthrmandel : STD_LOGIC_VECTOR (54 DOWNTO 1);
-- MULTIPLY
signal resultone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultonedel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal resulttwo, resultthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
-- NORMALIZE
signal normshift : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoutff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal expout, expoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
component dp_explutpos
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_explutneg
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_explut10
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
end component;
component dp_explut20
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*******************
--*** INPUT BLOCK ***
--*******************
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO (ranlatency+3) LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
aamanff(k) <= '0';
aamandelff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
aaexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
leftshiftff(k) <= '0';
rightshiftff(k) <= '0';
END LOOP;
selshiftff <= "00";
FOR k IN 1 TO 64 LOOP
leftff(k) <= '0';
rightff(k) <= '0';
powerff(k) <= '0';
END LOOP;
powerff(65) <= '0';
bigexpff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= aasgn;
FOR k IN 2 TO (ranlatency+3) LOOP
signff(k) <= signff(k-1);
END LOOP;
aamanff <= aaman;
aamandelff <= aamanff;
aaexpff <= aaexp;
leftshiftff <= leftshift(10 DOWNTO 1);
rightshiftff <= rightshift(10 DOWNTO 1);
selshiftff(1) <= leftshift(12);
selshiftff(2) <= selshiftff(1);
-- level 3
leftff <= lefttwo;
-- mask out right barrel shifter output when shifting by 64 or more positions
FOR k IN 1 TO 64 LOOP
rightff(k) <= rightthree(k) AND smallrightshift;
END LOOP;
-- overflow of left shifter matters only when the left shifted mantissa result is to be used
bigexpff(2) <= bigexpff(1) AND NOT(selshiftff(2));
bigexpff(1) <= NOT(cmpexp(11));
-- level 4
FOR k IN 1 TO 54 LOOP
powerff(k) <= (fractionalleft(k) AND NOT(selshiftff(2))) OR
(fractionalright(k) AND selshiftff(2));
END LOOP;
FOR k IN 1 TO 10 LOOP
powerff(k+54) <= (decimalleft(k) AND NOT(selshiftff(2))) OR
(decimalright(k) AND selshiftff(2));
END LOOP;
powerff(65) <= (decimalleft(11) AND NOT(selshiftff(2)));
-- overflow bit required to catch exp(-1023.frac) case
END IF;
END IF;
END PROCESS;
leftshift <= ('0' & aaexpff) - "001111111111";
rightshift <= "001111111111" - ('0' & aaexpff);
powerbus <= "0000000001" & aamandelff & "00";
decimalleft <= ('0' & leftff(64 DOWNTO 55)) + ("0000000000" & signff(3));
-- decimalleft may overflow to bit 11 when exp(x), -1024 < x <= -1023
decimalright <= rightff(64 DOWNTO 55) + ("000000000" & signff(3));
gfa: FOR k IN 1 TO 54 GENERATE
fractionalleft(k) <= leftff(k) XOR signff(3);
fractionalright(k) <= rightff(k) XOR signff(3);
END GENERATE;
--**********************
--*** BARREL SHIFTER ***
--**********************
leftone(1) <= powerbus(1) AND NOT(leftshiftff(2)) AND NOT(leftshiftff(1));
leftone(2) <= (powerbus(2) AND NOT(leftshiftff(2)) AND NOT(leftshiftff(1))) OR
(powerbus(1) AND NOT(leftshiftff(2)) AND leftshiftff(1));
leftone(3) <= (powerbus(3) AND NOT(leftshiftff(2)) AND NOT(leftshiftff(1))) OR
(powerbus(2) AND NOT(leftshiftff(2)) AND leftshiftff(1)) OR
(powerbus(1) AND leftshiftff(2) AND NOT(leftshiftff(1)));
gla: FOR k IN 4 TO 64 GENERATE
leftone(k) <= (powerbus(k) AND NOT(leftshiftff(2)) AND NOT(leftshiftff(1))) OR
(powerbus(k-1) AND NOT(leftshiftff(2)) AND leftshiftff(1)) OR
(powerbus(k-2) AND leftshiftff(2) AND NOT(leftshiftff(1))) OR
(powerbus(k-3) AND leftshiftff(2) AND leftshiftff(1));
END GENERATE;
glb: FOR k IN 1 TO 4 GENERATE
lefttwo(k) <= leftone(k) AND NOT(leftshiftff(4)) AND NOT(leftshiftff(3));
END GENERATE;
glc: FOR k IN 5 TO 8 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(leftshiftff(4)) AND NOT(leftshiftff(3))) OR
(leftone(k-4) AND NOT(leftshiftff(4)) AND leftshiftff(3));
END GENERATE;
gld: FOR k IN 9 TO 12 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(leftshiftff(4)) AND NOT(leftshiftff(3))) OR
(leftone(k-4) AND NOT(leftshiftff(4)) AND leftshiftff(3)) OR
(leftone(k-8) AND leftshiftff(4) AND NOT(leftshiftff(3)));
END GENERATE;
gle: FOR k IN 13 TO 64 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(leftshiftff(4)) AND NOT(leftshiftff(3))) OR
(leftone(k-4) AND NOT(leftshiftff(4)) AND leftshiftff(3)) OR
(leftone(k-8) AND leftshiftff(4) AND NOT(leftshiftff(3))) OR
(leftone(k-12) AND leftshiftff(4) AND leftshiftff(3));
END GENERATE;
cmpexp <= ('0' & leftshiftff) - "00000001010";
-- detect when left barrel shifter overflows (i.e. leftshiftff > 9)
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (powerbus(k) AND NOT(rightshiftff(2)) AND NOT(rightshiftff(1))) OR
(powerbus(k+1) AND NOT(rightshiftff(2)) AND rightshiftff(1)) OR
(powerbus(k+2) AND rightshiftff(2) AND NOT(rightshiftff(1))) OR
(powerbus(k+3) AND rightshiftff(2) AND rightshiftff(1));
END GENERATE;
rightone(62) <= (powerbus(62) AND NOT(rightshiftff(2)) AND NOT(rightshiftff(1))) OR
(powerbus(63) AND NOT(rightshiftff(2)) AND rightshiftff(1)) OR
(powerbus(64) AND rightshiftff(2) AND NOT(rightshiftff(1)));
rightone(63) <= (powerbus(63) AND NOT(rightshiftff(2)) AND NOT(rightshiftff(1))) OR
(powerbus(64) AND NOT(rightshiftff(2)) AND rightshiftff(1));
rightone(64) <= powerbus(64) AND NOT(rightshiftff(2)) AND NOT(rightshiftff(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(rightshiftff(4)) AND NOT(rightshiftff(3))) OR
(rightone(k+4) AND NOT(rightshiftff(4)) AND rightshiftff(3)) OR
(rightone(k+8) AND rightshiftff(4) AND NOT(rightshiftff(3))) OR
(rightone(k+12) AND rightshiftff(4) AND rightshiftff(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(rightshiftff(4)) AND NOT(rightshiftff(3))) OR
(rightone(k+4) AND NOT(rightshiftff(4)) AND rightshiftff(3)) OR
(rightone(k+8) AND rightshiftff(4) AND NOT(rightshiftff(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(rightshiftff(4)) AND NOT(rightshiftff(3))) OR
(rightone(k+4) AND NOT(rightshiftff(4)) AND rightshiftff(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(rightshiftff(4)) AND NOT(rightshiftff(3)));
END GENERATE;
grf: FOR k IN 1 TO 16 GENERATE
rightthree(k) <= (righttwo(k) AND NOT(rightshiftff(6)) AND NOT(rightshiftff(5))) OR
(righttwo(k+16) AND NOT(rightshiftff(6)) AND rightshiftff(5)) OR
(righttwo(k+32) AND rightshiftff(6) AND NOT(rightshiftff(5))) OR
(righttwo(k+48) AND rightshiftff(6) AND rightshiftff(5));
END GENERATE;
grg: FOR k IN 17 TO 32 GENERATE
rightthree(k) <= (righttwo(k) AND NOT(rightshiftff(6)) AND NOT(rightshiftff(5))) OR
(righttwo(k+16) AND NOT(rightshiftff(6)) AND rightshiftff(5)) OR
(righttwo(k+32) AND rightshiftff(6) AND NOT(rightshiftff(5)));
END GENERATE;
grh: FOR k IN 33 TO 48 GENERATE
rightthree(k) <= (righttwo(k) AND NOT(rightshiftff(6)) AND NOT(rightshiftff(5))) OR
(righttwo(k+16) AND NOT(rightshiftff(6)) AND rightshiftff(5));
END GENERATE;
gri: FOR k IN 49 TO 64 GENERATE
rightthree(k) <= (righttwo(k) AND NOT(rightshiftff(6)) AND NOT(rightshiftff(5)));
END GENERATE;
-- is rightshiftff < 64, otherwise right barrel shifter output will be masked out
smallrightshift <= NOT(rightshiftff(7) OR rightshiftff(8) OR rightshiftff(9) OR rightshiftff(10));
--******************************************
--*** TABLES - NO RESET, FORCE TO MEMORY ***
--******************************************
-- level: 4 in, 6 out
pla: PROCESS (sysclk)
BEGIN
IF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addlutposff <= powerff(64 DOWNTO 55);
addlutnegff <= powerff(64 DOWNTO 55);
addluttwoff <= powerff(54 DOWNTO 45);
addlutthrff <= powerff(44 DOWNTO 35);
lutposmanff <= '1' & manpos & '0';
lutposexpff <= exppos;
lutnegmanff <= '1' & manneg & '0';
lutnegexpff <= expneg;
luttwomanff <= '1' & mantwo & '0';
luttwoexpff <= exptwo;
lutthrmanff <= '1' & manthr & '0';
END IF;
END IF;
END PROCESS;
declut: dp_explutpos
PORT MAP (add=>addlutposff,
manhi=>manpos(52 DOWNTO 29),manlo=>manpos(28 DOWNTO 1),exponent=>exppos);
neglut: dp_explutneg
PORT MAP (add=>addlutnegff,
manhi=>manneg(52 DOWNTO 29),manlo=>manneg(28 DOWNTO 1),exponent=>expneg);
frachilut: dp_explut10
PORT MAP (add=>addluttwoff,
manhi=>mantwo(52 DOWNTO 29),manlo=>mantwo(28 DOWNTO 1),exponent=>exptwo);
fraclolut: dp_explut20
PORT MAP (add=>addlutthrff,
manhi=>manthr(52 DOWNTO 29),manlo=>manthr(28 DOWNTO 1));
-- level: 6 in, 7 out
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
lutonemanff(k) <= '0';
luttwomandelff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
lutoneexpff(k) <= '0';
END LOOP;
luttwoexpdelff <= '0';
FOR k IN 1 TO (ranlatency-4) LOOP
expcalcff(k)(11 DOWNTO 1) <= "00000000000";
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 54 LOOP
lutonemanff(k) <= (lutposmanff(k) AND NOT(signff(6))) OR (lutnegmanff(k) AND signff(6));
END LOOP;
luttwomandelff <= luttwomanff;
FOR k IN 1 TO 11 LOOP
lutoneexpff(k) <= (lutposexpff(k) AND NOT(signff(6))) OR (lutnegexpff(k) AND signff(6));
END LOOP;
luttwoexpdelff <= luttwoexpff;
-- level: 8 in
-- SII: 19+2*doublespeed out
-- SII: 17+2*doublespeed out
expcalcff(1)(11 DOWNTO 1) <= lutoneexpff + ("0000000000" & luttwoexpdelff);
FOR k IN 2 TO (ranlatency-4) LOOP
expcalcff(k)(11 DOWNTO 1) <= expcalcff(k-1)(11 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************************************
--*** PREDICT OVERFLOW AND UNDERFLOW ***
--**************************************
-- overflow or underflow if power > 709
-- overflow or underflow if power != 0 and explut = 0
powercheck <= powerff(65 DOWNTO 55) - "1011000110"; -- 710
-- level 4 in
-- SII: level 19+2 out
-- SIII/IV: level 17 out
ppca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO ranlatency LOOP
rangeff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
rangeff(1) <= bigexpff(2) OR NOT(powercheck(11));
-- exp(x) -> 0 or Inf, when abs(x)>=710 or has overflowed the left shifter
FOR k IN 2 TO (ranlatency-1) LOOP
rangeff(k) <= rangeff(k-1);
END LOOP;
rangeff(ranlatency) <= rangeff(ranlatency-1) AND NOT(signff(ranlatency+3));
-- overflow only if input x is large and positive, exp(x) -> Inf
END IF;
END IF;
END PROCESS;
--***********************
--*** TAYLOR's SERIES ***
--***********************
-- approximation : sequence = 1 + x + x^2/2 + x^3/6 + x^4/24
-- but x^3/6 term is about 62 bits down, so just try 1 + x + x^2/2
-- ('1' & zero) + (zero(21:1) & x(34:2)) + (zero(42:1) & square(72:61))
fraction <= powerff(34 DOWNTO 1) & "00";
-- level: 4 in, 7 out
mulsqr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>12,
pipes=>3,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>fraction,databb=>fraction,
result=>xsquareterm);
delfrac: fp_del
GENERIC MAP (width=>33,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>powerff(34 DOWNTO 2),
cc=>xterm);
delthr: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>lutthrmanff,
cc=>lutthrmandel);
-- level 8
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
approxff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
approxff <= ('1' & zerovec(20 DOWNTO 1) & xterm) + (zerovec(42 DOWNTO 1) & xsquareterm);
END IF;
END IF;
END PROCESS;
--*************************************
--*** MULTIPLY ALL EXP(X) SUBRANGES ***
--*************************************
-- SII level in 7, level out 12+speed
-- SIII/IV level in 7, level out 11
mulone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,
pipes=>mullatency,accuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>lutonemanff,databb=>luttwomandelff,
result=>resultone);
-- SII level in 12+speed, level out 13+speed
-- SIII/IV level in 11, level out 12
delone: fp_del
GENERIC MAP (width=>54,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>resultone(72 DOWNTO 19),
cc=>resultonedel);
-- SII level in 8, level out 13+speed
-- SIII/IV level in 8, level out 12
multwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,
pipes=>mullatency,accuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>lutthrmandel,databb=>approxff,
result=>resulttwo);
-- SII level in 13+speed, level out 18+2*speed
-- SIII/IV level in 12, level out 16
multhr: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,
pipes=>mullatency,accuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>resultonedel,databb=>resulttwo(72 DOWNTO 19),
result=>resultthr);
--************************
--*** NORMALIZE OUTPUT ***
--************************
pns: PROCESS (resultthr)
BEGIN
CASE resultthr(72 DOWNTO 69) IS
WHEN "0000" => normshift <= "11";
WHEN "0001" => normshift <= "11";
WHEN "0010" => normshift <= "10";
WHEN "0011" => normshift <= "10";
WHEN "0100" => normshift <= "01";
WHEN "0101" => normshift <= "01";
WHEN "0110" => normshift <= "01";
WHEN "0111" => normshift <= "01";
WHEN "1000" => normshift <= "00";
WHEN "1001" => normshift <= "00";
WHEN "1010" => normshift <= "00";
WHEN "1011" => normshift <= "00";
WHEN "1100" => normshift <= "00";
WHEN "1101" => normshift <= "00";
WHEN "1110" => normshift <= "00";
WHEN "1111" => normshift <= "00";
WHEN others => normshift <= "00";
END CASE;
END PROCESS;
pna: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
manoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
expoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII level in 18+2*doublespeed, level out 19+2*doublespeed
-- SIII/IV level in 16, level out 17
FOR k IN 1 TO 54 LOOP
manoutff(k) <= (resultthr(k+18) AND NOT(normshift(2)) AND NOT(normshift(1))) OR
(resultthr(k+17) AND NOT(normshift(2)) AND normshift(1)) OR
(resultthr(k+16) AND normshift(2) AND NOT(normshift(1))) OR
(resultthr(k+15) AND normshift(2) AND normshift(1));
END LOOP;
FOR k IN 1 TO 11 LOOP
expoutff(k) <= expout(k) AND NOT(rangeff(ranlatency-1) AND signff(ranlatency+3));
END LOOP;
-- IEEE exponent field is set to zero when x = large negative, exp(x) -> 0
END IF;
END IF;
END PROCESS;
expout <= expcalcff(ranlatency-4)(11 DOWNTO 1) - ("000000000" & normshift) + "00000000011";
--***************
--*** OUTPUTS ***
--***************
ccman <= manoutff;
ccexp <= expoutff;
rangeerror <= rangeff(ranlatency);
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/fp_cospi_s5.vhd | 10 | 259954 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cospi_s5
-- VHDL created on Wed Feb 27 15:22:33 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShiftMO_uid13_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid14_fpCosPiTest_q : std_logic_vector (12 downto 0);
signal cstZwSwF_uid15_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal cstAllZWE_uid21_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid87_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid99_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid140_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid209_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid16_uid47_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid17_uid52_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cstHalfwSwFP1_uid18_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid23_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid25_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid59_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid59_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid95_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid95_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid207_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid208_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal join_uid94_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal R_uid102_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid37_uid37_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_b : std_logic_vector (5 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal z_uid54_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal z_uid54_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid60_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid60_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal normBit_uid67_fpCosPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid67_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid68_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid68_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid213_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid213_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid219_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal oFracXExt_uid39_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal zAddr_uid62_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid62_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid72_uid73_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid210_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid210_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid142_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid71_uid71_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid74_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid74_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid212_uid215_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid218_uid221_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal FxpX36_uid42_fpCosPiTest_in : std_logic_vector (36 downto 0);
signal FxpX36_uid42_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid58_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid58_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid76_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid76_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal r_uid172_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
begin
--xIn(GPIN,3)@0
--LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest(BITSELECT,131)@1
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest(CONSTANT,130)
leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q <= "000";
--leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest(BITJOIN,132)@1
leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest(BITSELECT,128)@1
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in(34 downto 0);
--leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest(CONSTANT,127)
leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q <= "00";
--leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest(BITJOIN,129)@1
leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest(BITSELECT,125)@1
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest(BITJOIN,126)@1
leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b & GND_q;
--leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest(CONSTANT,110)
leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid109_fxpX_uid41_fpCosPiTest(BITSELECT,108)@0
X4dto0_uid109_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(4 downto 0);
X4dto0_uid109_fxpX_uid41_fpCosPiTest_b <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest(CONSTANT,107)
leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest(BITJOIN,109)@0
leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X20dto0_uid106_fxpX_uid41_fpCosPiTest(BITSELECT,105)@0
X20dto0_uid106_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(20 downto 0);
X20dto0_uid106_fxpX_uid41_fpCosPiTest_b <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest(CONSTANT,104)
leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest(BITJOIN,106)@0
leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--cst01pWShift_uid14_fpCosPiTest(CONSTANT,13)
cst01pWShift_uid14_fpCosPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= a(22 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(22 downto 0);
--oFracX_uid37_uid37_fpCosPiTest(BITJOIN,36)@0
oFracX_uid37_uid37_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid39_fpCosPiTest(BITJOIN,38)@0
oFracXExt_uid39_fpCosPiTest_q <= cst01pWShift_uid14_fpCosPiTest_q & oFracX_uid37_uid37_fpCosPiTest_q;
--biasMwShiftMO_uid13_fpCosPiTest(CONSTANT,12)
biasMwShiftMO_uid13_fpCosPiTest_q <= "01110010";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= a(30 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(30 downto 23);
--shiftValFxPX_uid38_fpCosPiTest(SUB,37)@0
shiftValFxPX_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid13_fpCosPiTest_q);
shiftValFxPX_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_b));
shiftValFxPX_uid38_fpCosPiTest_q <= shiftValFxPX_uid38_fpCosPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpCosPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpCosPiTest_in <= shiftValFxPX_uid38_fpCosPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpCosPiTest_b <= fxpShifterBits_uid40_fpCosPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest(BITSELECT,111)@0
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b;
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest(MUX,112)@0
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b;
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s, en, oFracXExt_uid39_fpCosPiTest_q, leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= oFracXExt_uid39_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest(BITSELECT,120)@0
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest(CONSTANT,119)
leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest(BITJOIN,121)@0
leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5(REG,235)@0
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest(BITSELECT,117)@0
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in(28 downto 0);
--cstAllZWE_uid21_fpCosPiTest(CONSTANT,20)
cstAllZWE_uid21_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest(BITJOIN,118)@0
leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4(REG,234)@0
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest(BITSELECT,114)@0
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest(CONSTANT,113)
leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q <= "0000";
--leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest(BITJOIN,115)@0
leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3(REG,233)@0
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2(REG,232)@0
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest(BITSELECT,122)@0
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1(REG,231)@0
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest(MUX,123)@1
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s, en, reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest(BITSELECT,133)@0
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1(REG,236)@0
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest(MUX,134)@1
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s, en, leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid43_fpCosPiTest(BITSELECT,42)@1
fxpXFrac_uid43_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q(35 downto 0);
fxpXFrac_uid43_fpCosPiTest_b <= fxpXFrac_uid43_fpCosPiTest_in(35 downto 0);
--FxpXFrac35_uid44_fpCosPiTest(BITSELECT,43)@1
FxpXFrac35_uid44_fpCosPiTest_in <= fxpXFrac_uid43_fpCosPiTest_b;
FxpXFrac35_uid44_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_in(35 downto 35);
--FxpX36_uid42_fpCosPiTest(BITSELECT,41)@1
FxpX36_uid42_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q;
FxpX36_uid42_fpCosPiTest_b <= FxpX36_uid42_fpCosPiTest_in(36 downto 36);
--xParityXorHalfParity_uid96_fpCosPiTest(LOGICAL,95)@1
xParityXorHalfParity_uid96_fpCosPiTest_a <= FxpX36_uid42_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_q <= xParityXorHalfParity_uid96_fpCosPiTest_a xor xParityXorHalfParity_uid96_fpCosPiTest_b;
--ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c(DELAY,369)@1
ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid96_fpCosPiTest_q, xout => ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10010110";
--xEvenInt_uid35_fpCosPiTest(COMPARE,34)@0
xEvenInt_uid35_fpCosPiTest_cin <= GND_q;
xEvenInt_uid35_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid35_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid35_fpCosPiTest_cin(0);
xEvenInt_uid35_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid35_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid35_fpCosPiTest_b));
xEvenInt_uid35_fpCosPiTest_c(0) <= xEvenInt_uid35_fpCosPiTest_o(10);
--ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a(DELAY,335)@0
ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid35_fpCosPiTest_c, xout => ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXEvenInt_uid81_fpCosPiTest(LOGICAL,80)@2
InvXEvenInt_uid81_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
InvXEvenInt_uid81_fpCosPiTest_q <= not InvXEvenInt_uid81_fpCosPiTest_a;
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShiftMO_uid13_fpCosPiTest_q) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_c(0) <= cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a(DELAY,332)@0
ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_c, xout => ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid77_fpCosPiTest(LOGICAL,76)@2
InvCosXIsOne_uid77_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
InvCosXIsOne_uid77_fpCosPiTest_q <= not InvCosXIsOne_uid77_fpCosPiTest_a;
--signRComp_uid99_fpCosPiTest(LOGICAL,98)@2
signRComp_uid99_fpCosPiTest_a <= InvCosXIsOne_uid77_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_b <= InvXEvenInt_uid81_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_c <= ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q;
signRComp_uid99_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid99_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid99_fpCosPiTest_q <= signRComp_uid99_fpCosPiTest_a and signRComp_uid99_fpCosPiTest_b and signRComp_uid99_fpCosPiTest_c;
END IF;
END PROCESS;
--cstZwSwF_uid15_fpCosPiTest(CONSTANT,14)
cstZwSwF_uid15_fpCosPiTest_q <= "00000000000000000000000000000000000";
--cstHalfwSwFP1_uid18_fpCosPiTest(BITJOIN,17)@2
cstHalfwSwFP1_uid18_fpCosPiTest_q <= VCC_q & cstZwSwF_uid15_fpCosPiTest_q;
--reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1(REG,237)@1
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= fxpXFrac_uid43_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--fxpXFracHalf_uid46_fpCosPiTest(LOGICAL,45)@2
fxpXFracHalf_uid46_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracHalf_uid46_fpCosPiTest_b <= cstHalfwSwFP1_uid18_fpCosPiTest_q;
fxpXFracHalf_uid46_fpCosPiTest_q <= "1" when fxpXFracHalf_uid46_fpCosPiTest_a = fxpXFracHalf_uid46_fpCosPiTest_b else "0";
--ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a(DELAY,370)@2
ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid46_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFxpXFracHalf_uid100_fpCosPiTest(LOGICAL,99)@3
InvFxpXFracHalf_uid100_fpCosPiTest_a <= ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q;
InvFxpXFracHalf_uid100_fpCosPiTest_q <= not InvFxpXFracHalf_uid100_fpCosPiTest_a;
--signR_uid101_fpCosPiTest(LOGICAL,100)@3
signR_uid101_fpCosPiTest_a <= InvFxpXFracHalf_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRComp_uid99_fpCosPiTest_q;
signR_uid101_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid101_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a and signR_uid101_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c(DELAY,375)@4
ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid101_fpCosPiTest_q, xout => ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111";
--pad_o_uid16_uid47_fpCosPiTest(BITJOIN,46)@1
pad_o_uid16_uid47_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0(REG,244)@1
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= pad_o_uid16_uid47_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid47_fpCosPiTest(SUB,47)@2
oMFxpXFrac_uid47_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q);
oMFxpXFrac_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q);
oMFxpXFrac_uid47_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_b));
oMFxpXFrac_uid47_fpCosPiTest_q <= oMFxpXFrac_uid47_fpCosPiTest_o(37 downto 0);
--oMFxpXFrac_uid49_fpCosPiTest(BITSELECT,48)@2
oMFxpXFrac_uid49_fpCosPiTest_in <= oMFxpXFrac_uid47_fpCosPiTest_q(35 downto 0);
oMFxpXFrac_uid49_fpCosPiTest_b <= oMFxpXFrac_uid49_fpCosPiTest_in(35 downto 0);
--ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c(DELAY,308)@1
ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => fxpXFrac_uid43_fpCosPiTest_b, xout => ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b(DELAY,307)@1
ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid44_fpCosPiTest_b, xout => ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid51_fpCosPiTest(MUX,50)@2
rangeReducedFxPX_uid51_fpCosPiTest_s <= ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q;
rangeReducedFxPX_uid51_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid51_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid51_fpCosPiTest_q <= ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid51_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid17_uid52_fpCosPiTest(BITJOIN,51)@2
pad_half_uid17_uid52_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0(REG,246)@2
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= pad_half_uid17_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid52_fpCosPiTest(SUB,52)@3
z_halfMRRFxPXE_uid52_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid51_fpCosPiTest_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_b));
z_halfMRRFxPXE_uid52_fpCosPiTest_q <= z_halfMRRFxPXE_uid52_fpCosPiTest_o(36 downto 0);
--z_uid54_fpCosPiTest(BITSELECT,53)@3
z_uid54_fpCosPiTest_in <= z_halfMRRFxPXE_uid52_fpCosPiTest_q(34 downto 0);
z_uid54_fpCosPiTest_b <= z_uid54_fpCosPiTest_in(34 downto 0);
--zAddr_uid62_fpCosPiTest(BITSELECT,61)@3
zAddr_uid62_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
zAddr_uid62_fpCosPiTest_b <= zAddr_uid62_fpCosPiTest_in(34 downto 28);
--reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0(REG,263)@3
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= zAddr_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid209_sinPiZTableGenerator(LOOKUP,208)@4
memoryC2_uid209_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid209_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid63_fpCosPiTest(BITSELECT,62)@3
zPPolyEval_uid63_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(27 downto 0);
zPPolyEval_uid63_fpCosPiTest_b <= zPPolyEval_uid63_fpCosPiTest_in(27 downto 12);
--yT1_uid210_sinPiZPolyEval(BITSELECT,209)@3
yT1_uid210_sinPiZPolyEval_in <= zPPolyEval_uid63_fpCosPiTest_b;
yT1_uid210_sinPiZPolyEval_b <= yT1_uid210_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0(REG,264)@3
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= yT1_uid210_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a(DELAY,499)@4
ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid226_pT1_uid211_sinPiZPolyEval(MULT,225)@5
prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_b);
prodXY_uid226_pT1_uid211_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= memoryC2_uid209_sinPiZTableGenerator_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid226_pT1_uid211_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval(BITSELECT,226)@8
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_q;
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid213_sinPiZPolyEval(BITSELECT,212)@8
highBBits_uid213_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b;
highBBits_uid213_sinPiZPolyEval_b <= highBBits_uid213_sinPiZPolyEval_in(14 downto 1);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable(LOGICAL,557)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor(LOGICAL,596)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top(CONSTANT,592)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q <= "010";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp(LOGICAL,593)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg(REG,594)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena(REG,597)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd(LOGICAL,598)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,588)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i = 1 THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i,2));
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg(REG,589)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux(MUX,590)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem(DUALMEM,587)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC1_uid208_sinPiZTableGenerator(LOOKUP,207)@8
memoryC1_uid208_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid208_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid214_sinPiZPolyEval(ADD,213)@8
sumAHighB_uid214_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid208_sinPiZTableGenerator_q(20)) & memoryC1_uid208_sinPiZTableGenerator_q);
sumAHighB_uid214_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid213_sinPiZPolyEval_b(13)) & highBBits_uid213_sinPiZPolyEval_b);
sumAHighB_uid214_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid214_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid214_sinPiZPolyEval_b));
sumAHighB_uid214_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid212_sinPiZPolyEval(BITSELECT,211)@8
lowRangeB_uid212_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid212_sinPiZPolyEval_b <= lowRangeB_uid212_sinPiZPolyEval_in(0 downto 0);
--s1_uid212_uid215_sinPiZPolyEval(BITJOIN,214)@8
s1_uid212_uid215_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_q & lowRangeB_uid212_sinPiZPolyEval_b;
--reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1(REG,267)@8
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= s1_uid212_uid215_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor(LOGICAL,609)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a or ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena(REG,610)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd(LOGICAL,611)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg(DELAY,599)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid63_fpCosPiTest_b, xout => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem(DUALMEM,600)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0(REG,266)@8
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid229_pT2_uid217_sinPiZPolyEval(MULT,228)@9
prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_b);
prodXY_uid229_pT2_uid217_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid229_pT2_uid217_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval(BITSELECT,229)@12
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_q;
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid219_sinPiZPolyEval(BITSELECT,218)@12
highBBits_uid219_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b;
highBBits_uid219_sinPiZPolyEval_b <= highBBits_uid219_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor(LOGICAL,584)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top(CONSTANT,554)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp(LOGICAL,555)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a = ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg(REG,556)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena(REG,585)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd(LOGICAL,586)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,550)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg(REG,551)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux(MUX,552)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem(DUALMEM,575)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid207_sinPiZTableGenerator(LOOKUP,206)@12
memoryC0_uid207_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid207_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid220_sinPiZPolyEval(ADD,219)@12
sumAHighB_uid220_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid207_sinPiZTableGenerator_q(28)) & memoryC0_uid207_sinPiZTableGenerator_q);
sumAHighB_uid220_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid219_sinPiZPolyEval_b(21)) & highBBits_uid219_sinPiZPolyEval_b);
sumAHighB_uid220_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid220_sinPiZPolyEval_b));
sumAHighB_uid220_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid218_sinPiZPolyEval(BITSELECT,217)@12
lowRangeB_uid218_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid218_sinPiZPolyEval_b <= lowRangeB_uid218_sinPiZPolyEval_in(1 downto 0);
--s2_uid218_uid221_sinPiZPolyEval(BITJOIN,220)@12
s2_uid218_uid221_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_q & lowRangeB_uid218_sinPiZPolyEval_b;
--fxpSinRes_uid65_fpCosPiTest(BITSELECT,64)@12
fxpSinRes_uid65_fpCosPiTest_in <= s2_uid218_uid221_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid65_fpCosPiTest_b <= fxpSinRes_uid65_fpCosPiTest_in(29 downto 5);
--reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1(REG,270)@12
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= fxpSinRes_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor(LOGICAL,622)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q <= not (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a or ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena(REG,623)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd(LOGICAL,624)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a and ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest(BITSELECT,201)@7
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest(BITJOIN,202)@7
leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest(BITSELECT,198)@7
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest(BITJOIN,199)@7
leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest(BITSELECT,195)@7
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest(BITJOIN,196)@7
leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b & GND_q;
--vStage_uid141_lzcZ_uid56_fpCosPiTest(BITSELECT,140)@3
vStage_uid141_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(2 downto 0);
vStage_uid141_lzcZ_uid56_fpCosPiTest_b <= vStage_uid141_lzcZ_uid56_fpCosPiTest_in(2 downto 0);
--ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b(DELAY,450)@3
ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid141_lzcZ_uid56_fpCosPiTest_b, xout => ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest(BITJOIN,179)@6
leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q <= ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X18dto0_uid176_alignedZ_uid57_fpCosPiTest(BITSELECT,175)@3
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(18 downto 0);
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b <= X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in(18 downto 0);
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg(DELAY,573)
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b(DELAY,449)@3
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest(BITJOIN,176)@6
leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q <= ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg(DELAY,574)
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid54_fpCosPiTest_b, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c(DELAY,453)@3
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid138_lzcZ_uid56_fpCosPiTest(BITSELECT,137)@3
rVStage_uid138_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
rVStage_uid138_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_in(34 downto 3);
--reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1(REG,247)@3
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid139_lzcZ_uid56_fpCosPiTest(LOGICAL,138)@4
vCount_uid139_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid139_lzcZ_uid56_fpCosPiTest_a = vCount_uid139_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f(DELAY,447)@4
ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid139_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid140_lzcZ_uid56_fpCosPiTest(CONSTANT,139)
mO_uid140_lzcZ_uid56_fpCosPiTest_q <= "11111111111111111111111111111";
--cStage_uid142_lzcZ_uid56_fpCosPiTest(BITJOIN,141)@3
cStage_uid142_lzcZ_uid56_fpCosPiTest_q <= vStage_uid141_lzcZ_uid56_fpCosPiTest_b & mO_uid140_lzcZ_uid56_fpCosPiTest_q;
--reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3(REG,249)@3
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= cStage_uid142_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid144_lzcZ_uid56_fpCosPiTest(MUX,143)@4
vStagei_uid144_lzcZ_uid56_fpCosPiTest_s <= vCount_uid139_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid144_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid144_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q, reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid144_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_lzcZ_uid56_fpCosPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid146_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1(REG,250)@4
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid56_fpCosPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid147_lzcZ_uid56_fpCosPiTest_a = vCount_uid147_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e(DELAY,446)@5
ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid148_lzcZ_uid56_fpCosPiTest(BITSELECT,147)@4
vStage_uid148_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q(15 downto 0);
vStage_uid148_lzcZ_uid56_fpCosPiTest_b <= vStage_uid148_lzcZ_uid56_fpCosPiTest_in(15 downto 0);
--reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3(REG,252)@4
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid148_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid150_lzcZ_uid56_fpCosPiTest(MUX,149)@5
vStagei_uid150_lzcZ_uid56_fpCosPiTest_s <= vCount_uid147_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid150_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid150_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid150_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid152_lzcZ_uid56_fpCosPiTest(BITSELECT,151)@5
rVStage_uid152_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid152_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_in(15 downto 8);
--vCount_uid153_lzcZ_uid56_fpCosPiTest(LOGICAL,152)@5
vCount_uid153_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
vCount_uid153_lzcZ_uid56_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
vCount_uid153_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid153_lzcZ_uid56_fpCosPiTest_a = vCount_uid153_lzcZ_uid56_fpCosPiTest_b else "0";
--reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3(REG,256)@5
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid154_lzcZ_uid56_fpCosPiTest(BITSELECT,153)@5
vStage_uid154_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q(7 downto 0);
vStage_uid154_lzcZ_uid56_fpCosPiTest_b <= vStage_uid154_lzcZ_uid56_fpCosPiTest_in(7 downto 0);
--vStagei_uid156_lzcZ_uid56_fpCosPiTest(MUX,155)@5
vStagei_uid156_lzcZ_uid56_fpCosPiTest_s <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid156_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid156_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid152_lzcZ_uid56_fpCosPiTest_b, vStage_uid154_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid156_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= vStage_uid154_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid158_lzcZ_uid56_fpCosPiTest(BITSELECT,157)@5
rVStage_uid158_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid158_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_in(7 downto 4);
--reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1(REG,253)@5
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid159_lzcZ_uid56_fpCosPiTest(LOGICAL,158)@6
vCount_uid159_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid159_lzcZ_uid56_fpCosPiTest_a = vCount_uid159_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid160_lzcZ_uid56_fpCosPiTest(BITSELECT,159)@5
vStage_uid160_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
vStage_uid160_lzcZ_uid56_fpCosPiTest_b <= vStage_uid160_lzcZ_uid56_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3(REG,255)@5
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid160_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid162_lzcZ_uid56_fpCosPiTest(MUX,161)@6
vStagei_uid162_lzcZ_uid56_fpCosPiTest_s <= vCount_uid159_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid162_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid162_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid162_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid164_lzcZ_uid56_fpCosPiTest(BITSELECT,163)@6
rVStage_uid164_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid164_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_in(3 downto 2);
--vCount_uid165_lzcZ_uid56_fpCosPiTest(LOGICAL,164)@6
vCount_uid165_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
vCount_uid165_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
vCount_uid165_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid165_lzcZ_uid56_fpCosPiTest_a = vCount_uid165_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid166_lzcZ_uid56_fpCosPiTest(BITSELECT,165)@6
vStage_uid166_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
vStage_uid166_lzcZ_uid56_fpCosPiTest_b <= vStage_uid166_lzcZ_uid56_fpCosPiTest_in(1 downto 0);
--vStagei_uid168_lzcZ_uid56_fpCosPiTest(MUX,167)@6
vStagei_uid168_lzcZ_uid56_fpCosPiTest_s <= vCount_uid165_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid168_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid168_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid164_lzcZ_uid56_fpCosPiTest_b, vStage_uid166_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid168_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= vStage_uid166_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid170_lzcZ_uid56_fpCosPiTest(BITSELECT,169)@6
rVStage_uid170_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid168_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid170_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_in(1 downto 1);
--vCount_uid171_lzcZ_uid56_fpCosPiTest(LOGICAL,170)@6
vCount_uid171_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_b;
vCount_uid171_lzcZ_uid56_fpCosPiTest_b <= GND_q;
vCount_uid171_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid171_lzcZ_uid56_fpCosPiTest_a = vCount_uid171_lzcZ_uid56_fpCosPiTest_b else "0";
--r_uid172_lzcZ_uid56_fpCosPiTest(BITJOIN,171)@6
r_uid172_lzcZ_uid56_fpCosPiTest_q <= ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q & ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q & reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q & vCount_uid159_lzcZ_uid56_fpCosPiTest_q & vCount_uid165_lzcZ_uid56_fpCosPiTest_q & vCount_uid171_lzcZ_uid56_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest(BITSELECT,181)@6
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest(MUX,182)@6
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b;
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s, en, ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q, leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q, cstZwSwF_uid15_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= cstZwSwF_uid15_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest(BITSELECT,190)@6
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest(BITJOIN,191)@6
leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5(REG,261)@6
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest(BITSELECT,187)@6
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest(BITJOIN,188)@6
leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4(REG,260)@6
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest(BITSELECT,184)@6
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest(BITJOIN,185)@6
leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3(REG,259)@6
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2(REG,258)@6
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest(BITSELECT,192)@6
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1(REG,257)@6
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest(MUX,193)@7
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s, en, reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest(BITSELECT,203)@6
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1(REG,262)@6
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest(MUX,204)@7
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s, en, leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid58_fpCosPiTest(BITSELECT,57)@7
alignedZLow_uid58_fpCosPiTest_in <= leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q;
alignedZLow_uid58_fpCosPiTest_b <= alignedZLow_uid58_fpCosPiTest_in(34 downto 11);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg(DELAY,612)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid58_fpCosPiTest_b, xout => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem(DUALMEM,613)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0(REG,269)@12
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest(MULT,222)@13
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr <= UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a) * UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b);
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest(BITSELECT,223)@16
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q;
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in(48 downto 23);
--normBit_uid67_fpCosPiTest(BITSELECT,66)@16
normBit_uid67_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b;
normBit_uid67_fpCosPiTest_b <= normBit_uid67_fpCosPiTest_in(25 downto 25);
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "00000000000000000000000";
--rndExpUpdate_uid72_uid73_fpCosPiTest(BITJOIN,72)@16
rndExpUpdate_uid72_uid73_fpCosPiTest_q <= normBit_uid67_fpCosPiTest_b & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor(LOGICAL,558)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a or ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena(REG,559)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd(LOGICAL,560)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b;
--reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1(REG,271)@6
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem(DUALMEM,549)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia <= reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111110";
--expHardCase_uid59_fpCosPiTest(SUB,58)@15
expHardCase_uid59_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid59_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q);
expHardCase_uid59_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid59_fpCosPiTest_a) - UNSIGNED(expHardCase_uid59_fpCosPiTest_b));
expHardCase_uid59_fpCosPiTest_q <= expHardCase_uid59_fpCosPiTest_o(8 downto 0);
--expP_uid60_fpCosPiTest(BITSELECT,59)@15
expP_uid60_fpCosPiTest_in <= expHardCase_uid59_fpCosPiTest_q(7 downto 0);
expP_uid60_fpCosPiTest_b <= expP_uid60_fpCosPiTest_in(7 downto 0);
--reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1(REG,272)@15
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= expP_uid60_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid68_fpCosPiTest(BITSELECT,67)@16
highRes_uid68_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(24 downto 0);
highRes_uid68_fpCosPiTest_b <= highRes_uid68_fpCosPiTest_in(24 downto 1);
--lowRes_uid69_fpCosPiTest(BITSELECT,68)@16
lowRes_uid69_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(23 downto 0);
lowRes_uid69_fpCosPiTest_b <= lowRes_uid69_fpCosPiTest_in(23 downto 0);
--fracRCompPreRnd_uid70_fpCosPiTest(MUX,69)@16
fracRCompPreRnd_uid70_fpCosPiTest_s <= normBit_uid67_fpCosPiTest_b;
fracRCompPreRnd_uid70_fpCosPiTest: PROCESS (fracRCompPreRnd_uid70_fpCosPiTest_s, en, lowRes_uid69_fpCosPiTest_b, highRes_uid68_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid70_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid70_fpCosPiTest_q <= lowRes_uid69_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid70_fpCosPiTest_q <= highRes_uid68_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid70_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid71_uid71_fpCosPiTest(BITJOIN,70)@16
expFracPreRnd_uid71_uid71_fpCosPiTest_q <= reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q & fracRCompPreRnd_uid70_fpCosPiTest_q;
--expFracComp_uid74_fpCosPiTest(ADD,73)@16
expFracComp_uid74_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid71_uid71_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid72_uid73_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid74_fpCosPiTest_a) + UNSIGNED(expFracComp_uid74_fpCosPiTest_b));
expFracComp_uid74_fpCosPiTest_q <= expFracComp_uid74_fpCosPiTest_o(32 downto 0);
--expRComp_uid76_fpCosPiTest(BITSELECT,75)@16
expRComp_uid76_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(31 downto 0);
expRComp_uid76_fpCosPiTest_b <= expRComp_uid76_fpCosPiTest_in(31 downto 24);
--fracXIsZero_uid27_fpCosPiTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid27_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid27_fpCosPiTest_q <= "1" when fracXIsZero_uid27_fpCosPiTest_a = fracXIsZero_uid27_fpCosPiTest_b else "0";
--InvFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
InvFracXIsZero_uid29_fpCosPiTest_a <= fracXIsZero_uid27_fpCosPiTest_q;
InvFracXIsZero_uid29_fpCosPiTest_q <= not InvFracXIsZero_uid29_fpCosPiTest_a;
--expXIsMax_uid25_fpCosPiTest(LOGICAL,24)@0
expXIsMax_uid25_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid25_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid25_fpCosPiTest_q <= "1" when expXIsMax_uid25_fpCosPiTest_a = expXIsMax_uid25_fpCosPiTest_b else "0";
--exc_N_uid30_fpCosPiTest(LOGICAL,29)@0
exc_N_uid30_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_b <= InvFracXIsZero_uid29_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_q <= exc_N_uid30_fpCosPiTest_a and exc_N_uid30_fpCosPiTest_b;
--InvExc_N_uid31_fpCosPiTest(LOGICAL,30)@0
InvExc_N_uid31_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
InvExc_N_uid31_fpCosPiTest_q <= not InvExc_N_uid31_fpCosPiTest_a;
--exc_I_uid28_fpCosPiTest(LOGICAL,27)@0
exc_I_uid28_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_b <= fracXIsZero_uid27_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_q <= exc_I_uid28_fpCosPiTest_a and exc_I_uid28_fpCosPiTest_b;
--InvExc_I_uid32_fpCosPiTest(LOGICAL,31)@0
InvExc_I_uid32_fpCosPiTest_a <= exc_I_uid28_fpCosPiTest_q;
InvExc_I_uid32_fpCosPiTest_q <= not InvExc_I_uid32_fpCosPiTest_a;
--expXIsZero_uid23_fpCosPiTest(LOGICAL,22)@0
expXIsZero_uid23_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid23_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
expXIsZero_uid23_fpCosPiTest_q <= "1" when expXIsZero_uid23_fpCosPiTest_a = expXIsZero_uid23_fpCosPiTest_b else "0";
--InvExpXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvExpXIsZero_uid33_fpCosPiTest_a <= expXIsZero_uid23_fpCosPiTest_q;
InvExpXIsZero_uid33_fpCosPiTest_q <= not InvExpXIsZero_uid33_fpCosPiTest_a;
--exc_R_uid34_fpCosPiTest(LOGICAL,33)@0
exc_R_uid34_fpCosPiTest_a <= InvExpXIsZero_uid33_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_b <= InvExc_I_uid32_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_c <= InvExc_N_uid31_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_q <= exc_R_uid34_fpCosPiTest_a and exc_R_uid34_fpCosPiTest_b and exc_R_uid34_fpCosPiTest_c;
--ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a(DELAY,337)@0
ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => exc_R_uid34_fpCosPiTest_q, xout => ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsHalf_uid83_fpCosPiTest(LOGICAL,82)@2
xIsHalf_uid83_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsHalf_uid83_fpCosPiTest_b <= fxpXFracHalf_uid46_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_c <= InvCosXIsOne_uid77_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_d <= InvXEvenInt_uid81_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_q <= xIsHalf_uid83_fpCosPiTest_a and xIsHalf_uid83_fpCosPiTest_b and xIsHalf_uid83_fpCosPiTest_c and xIsHalf_uid83_fpCosPiTest_d;
--ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b(DELAY,355)@2
ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid83_fpCosPiTest_q, xout => ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid91_fpCosPiTest(MUX,90)@16
expRPostExc1_uid91_fpCosPiTest_s <= ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q;
expRPostExc1_uid91_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid91_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid91_fpCosPiTest_q <= expRComp_uid76_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid91_fpCosPiTest_q <= cstAllZWE_uid21_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor(LOGICAL,570)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q <= not (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a or ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b);
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top(CONSTANT,566)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp(LOGICAL,567)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q <= "1" when ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a = ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b else "0";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg(REG,568)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena(REG,571)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd(LOGICAL,572)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a and ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b;
--ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b(DELAY,359)@0
ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid23_fpCosPiTest_q, xout => ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid45_fpCosPiTest(LOGICAL,44)@2
fxpXFracZero_uid45_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid15_fpCosPiTest_q);
fxpXFracZero_uid45_fpCosPiTest_q <= "1" when fxpXFracZero_uid45_fpCosPiTest_a = fxpXFracZero_uid45_fpCosPiTest_b else "0";
--fracZCosNotOne_uid78_fpCosPiTest(LOGICAL,77)@2
fracZCosNotOne_uid78_fpCosPiTest_a <= fxpXFracZero_uid45_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_b <= InvCosXIsOne_uid77_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_q <= fracZCosNotOne_uid78_fpCosPiTest_a and fracZCosNotOne_uid78_fpCosPiTest_b;
--evenIntCosNotOneFZ_uid79_fpCosPiTest(LOGICAL,78)@2
evenIntCosNotOneFZ_uid79_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_b <= fracZCosNotOne_uid78_fpCosPiTest_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_q <= evenIntCosNotOneFZ_uid79_fpCosPiTest_a or evenIntCosNotOneFZ_uid79_fpCosPiTest_b;
--xIsInt_uid80_fpCosPiTest(LOGICAL,79)@2
xIsInt_uid80_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsInt_uid80_fpCosPiTest_b <= evenIntCosNotOneFZ_uid79_fpCosPiTest_q;
xIsInt_uid80_fpCosPiTest_q <= xIsInt_uid80_fpCosPiTest_a and xIsInt_uid80_fpCosPiTest_b;
--xIntOrXZOrCosOne_uid93_fpCosPiTest(LOGICAL,92)@2
xIntOrXZOrCosOne_uid93_fpCosPiTest_a <= xIsInt_uid80_fpCosPiTest_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_b <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_c <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_a or xIntOrXZOrCosOne_uid93_fpCosPiTest_b or xIntOrXZOrCosOne_uid93_fpCosPiTest_c;
--excRNaN_uid84_fpCosPiTest(LOGICAL,83)@0
excRNaN_uid84_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_b <= exc_I_uid28_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_q <= excRNaN_uid84_fpCosPiTest_a or excRNaN_uid84_fpCosPiTest_b;
--rInfOrNaN_uid92_fpCosPiTest(LOGICAL,91)@0
rInfOrNaN_uid92_fpCosPiTest_a <= GND_q;
rInfOrNaN_uid92_fpCosPiTest_b <= excRNaN_uid84_fpCosPiTest_q;
rInfOrNaN_uid92_fpCosPiTest_q <= rInfOrNaN_uid92_fpCosPiTest_a or rInfOrNaN_uid92_fpCosPiTest_b;
--ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a(DELAY,361)@0
ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rInfOrNaN_uid92_fpCosPiTest_q, xout => ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid94_fpCosPiTest(BITJOIN,93)@2
join_uid94_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_q & ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q;
--reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1(REG,274)@2
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= join_uid94_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt(COUNTER,562)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg(REG,563)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux(MUX,564)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem(DUALMEM,561)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia <= reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia
);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid95_fpCosPiTest(MUX,94)@17
expRPostExc_uid95_fpCosPiTest_s <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid95_fpCosPiTest: PROCESS (expRPostExc_uid95_fpCosPiTest_s, en, expRPostExc1_uid91_fpCosPiTest_q, cstAllOWE_uid8_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid95_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid95_fpCosPiTest_q <= expRPostExc1_uid91_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid95_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid95_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid87_fpCosPiTest(CONSTANT,86)
oneFracRPostExc2_uid87_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid75_fpCosPiTest(BITSELECT,74)@16
fracRComp_uid75_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(23 downto 0);
fracRComp_uid75_fpCosPiTest_b <= fracRComp_uid75_fpCosPiTest_in(23 downto 1);
--reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5(REG,243)@2
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= xIsHalf_uid83_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4(REG,242)@2
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3(REG,241)@2
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= fxpXFracHalf_uid46_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2(REG,240)@2
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= xIsInt_uid80_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1(REG,239)@0
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= cosXIsOne_uid36_fpCosPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a(DELAY,346)@1
ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q, xout => ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--bigCond_uid85_fpCosPiTest(LOGICAL,84)@3
bigCond_uid85_fpCosPiTest_a <= ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q;
bigCond_uid85_fpCosPiTest_b <= reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q;
bigCond_uid85_fpCosPiTest_c <= reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q;
bigCond_uid85_fpCosPiTest_d <= reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q;
bigCond_uid85_fpCosPiTest_f <= reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q;
bigCond_uid85_fpCosPiTest_g <= GND_q;
bigCond_uid85_fpCosPiTest_q <= bigCond_uid85_fpCosPiTest_a or bigCond_uid85_fpCosPiTest_b or bigCond_uid85_fpCosPiTest_c or bigCond_uid85_fpCosPiTest_d or bigCond_uid85_fpCosPiTest_f or bigCond_uid85_fpCosPiTest_g;
--ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b(DELAY,351)@3
ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid85_fpCosPiTest_q, xout => ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid86_fpCosPiTest(MUX,85)@16
fracRPostExc1_uid86_fpCosPiTest_s <= ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q;
fracRPostExc1_uid86_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid86_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid86_fpCosPiTest_q <= fracRComp_uid75_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid86_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1(REG,273)@0
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= excRNaN_uid84_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b(DELAY,353)@1
ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q, xout => ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpCosPiTest(MUX,87)@17
fracRPostExc_uid88_fpCosPiTest_s <= ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q;
fracRPostExc_uid88_fpCosPiTest: PROCESS (fracRPostExc_uid88_fpCosPiTest_s, en, fracRPostExc1_uid86_fpCosPiTest_q, oneFracRPostExc2_uid87_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid88_fpCosPiTest_q <= fracRPostExc1_uid86_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid88_fpCosPiTest_q <= oneFracRPostExc2_uid87_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid102_fpCosPiTest(BITJOIN,101)@17
R_uid102_fpCosPiTest_q <= ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q & expRPostExc_uid95_fpCosPiTest_q & fracRPostExc_uid88_fpCosPiTest_q;
--xOut(GPOUT,4)@17
q <= R_uid102_fpCosPiTest_q;
end normal;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_cospi_s5.vhd | 10 | 259954 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cospi_s5
-- VHDL created on Wed Feb 27 15:22:33 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShiftMO_uid13_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid14_fpCosPiTest_q : std_logic_vector (12 downto 0);
signal cstZwSwF_uid15_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal cstAllZWE_uid21_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid87_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid99_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid140_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid209_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid16_uid47_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid17_uid52_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cstHalfwSwFP1_uid18_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid23_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid25_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid59_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid59_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid95_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid95_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid207_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid208_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal join_uid94_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal R_uid102_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid37_uid37_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_b : std_logic_vector (5 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal z_uid54_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal z_uid54_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid60_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid60_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal normBit_uid67_fpCosPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid67_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid68_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid68_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid213_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid213_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid219_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal oFracXExt_uid39_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal zAddr_uid62_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid62_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid72_uid73_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid210_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid210_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid142_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid71_uid71_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid74_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid74_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid212_uid215_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid218_uid221_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal FxpX36_uid42_fpCosPiTest_in : std_logic_vector (36 downto 0);
signal FxpX36_uid42_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid58_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid58_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid76_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid76_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal r_uid172_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
begin
--xIn(GPIN,3)@0
--LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest(BITSELECT,131)@1
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest(CONSTANT,130)
leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q <= "000";
--leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest(BITJOIN,132)@1
leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest(BITSELECT,128)@1
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in(34 downto 0);
--leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest(CONSTANT,127)
leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q <= "00";
--leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest(BITJOIN,129)@1
leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest(BITSELECT,125)@1
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest(BITJOIN,126)@1
leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b & GND_q;
--leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest(CONSTANT,110)
leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid109_fxpX_uid41_fpCosPiTest(BITSELECT,108)@0
X4dto0_uid109_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(4 downto 0);
X4dto0_uid109_fxpX_uid41_fpCosPiTest_b <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest(CONSTANT,107)
leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest(BITJOIN,109)@0
leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X20dto0_uid106_fxpX_uid41_fpCosPiTest(BITSELECT,105)@0
X20dto0_uid106_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(20 downto 0);
X20dto0_uid106_fxpX_uid41_fpCosPiTest_b <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest(CONSTANT,104)
leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest(BITJOIN,106)@0
leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--cst01pWShift_uid14_fpCosPiTest(CONSTANT,13)
cst01pWShift_uid14_fpCosPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= a(22 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(22 downto 0);
--oFracX_uid37_uid37_fpCosPiTest(BITJOIN,36)@0
oFracX_uid37_uid37_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid39_fpCosPiTest(BITJOIN,38)@0
oFracXExt_uid39_fpCosPiTest_q <= cst01pWShift_uid14_fpCosPiTest_q & oFracX_uid37_uid37_fpCosPiTest_q;
--biasMwShiftMO_uid13_fpCosPiTest(CONSTANT,12)
biasMwShiftMO_uid13_fpCosPiTest_q <= "01110010";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= a(30 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(30 downto 23);
--shiftValFxPX_uid38_fpCosPiTest(SUB,37)@0
shiftValFxPX_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid13_fpCosPiTest_q);
shiftValFxPX_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_b));
shiftValFxPX_uid38_fpCosPiTest_q <= shiftValFxPX_uid38_fpCosPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpCosPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpCosPiTest_in <= shiftValFxPX_uid38_fpCosPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpCosPiTest_b <= fxpShifterBits_uid40_fpCosPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest(BITSELECT,111)@0
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b;
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest(MUX,112)@0
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b;
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s, en, oFracXExt_uid39_fpCosPiTest_q, leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= oFracXExt_uid39_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest(BITSELECT,120)@0
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest(CONSTANT,119)
leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest(BITJOIN,121)@0
leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5(REG,235)@0
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest(BITSELECT,117)@0
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in(28 downto 0);
--cstAllZWE_uid21_fpCosPiTest(CONSTANT,20)
cstAllZWE_uid21_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest(BITJOIN,118)@0
leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4(REG,234)@0
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest(BITSELECT,114)@0
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest(CONSTANT,113)
leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q <= "0000";
--leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest(BITJOIN,115)@0
leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3(REG,233)@0
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2(REG,232)@0
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest(BITSELECT,122)@0
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1(REG,231)@0
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest(MUX,123)@1
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s, en, reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest(BITSELECT,133)@0
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1(REG,236)@0
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest(MUX,134)@1
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s, en, leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid43_fpCosPiTest(BITSELECT,42)@1
fxpXFrac_uid43_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q(35 downto 0);
fxpXFrac_uid43_fpCosPiTest_b <= fxpXFrac_uid43_fpCosPiTest_in(35 downto 0);
--FxpXFrac35_uid44_fpCosPiTest(BITSELECT,43)@1
FxpXFrac35_uid44_fpCosPiTest_in <= fxpXFrac_uid43_fpCosPiTest_b;
FxpXFrac35_uid44_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_in(35 downto 35);
--FxpX36_uid42_fpCosPiTest(BITSELECT,41)@1
FxpX36_uid42_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q;
FxpX36_uid42_fpCosPiTest_b <= FxpX36_uid42_fpCosPiTest_in(36 downto 36);
--xParityXorHalfParity_uid96_fpCosPiTest(LOGICAL,95)@1
xParityXorHalfParity_uid96_fpCosPiTest_a <= FxpX36_uid42_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_q <= xParityXorHalfParity_uid96_fpCosPiTest_a xor xParityXorHalfParity_uid96_fpCosPiTest_b;
--ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c(DELAY,369)@1
ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid96_fpCosPiTest_q, xout => ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10010110";
--xEvenInt_uid35_fpCosPiTest(COMPARE,34)@0
xEvenInt_uid35_fpCosPiTest_cin <= GND_q;
xEvenInt_uid35_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid35_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid35_fpCosPiTest_cin(0);
xEvenInt_uid35_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid35_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid35_fpCosPiTest_b));
xEvenInt_uid35_fpCosPiTest_c(0) <= xEvenInt_uid35_fpCosPiTest_o(10);
--ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a(DELAY,335)@0
ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid35_fpCosPiTest_c, xout => ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXEvenInt_uid81_fpCosPiTest(LOGICAL,80)@2
InvXEvenInt_uid81_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
InvXEvenInt_uid81_fpCosPiTest_q <= not InvXEvenInt_uid81_fpCosPiTest_a;
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShiftMO_uid13_fpCosPiTest_q) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_c(0) <= cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a(DELAY,332)@0
ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_c, xout => ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid77_fpCosPiTest(LOGICAL,76)@2
InvCosXIsOne_uid77_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
InvCosXIsOne_uid77_fpCosPiTest_q <= not InvCosXIsOne_uid77_fpCosPiTest_a;
--signRComp_uid99_fpCosPiTest(LOGICAL,98)@2
signRComp_uid99_fpCosPiTest_a <= InvCosXIsOne_uid77_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_b <= InvXEvenInt_uid81_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_c <= ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q;
signRComp_uid99_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid99_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid99_fpCosPiTest_q <= signRComp_uid99_fpCosPiTest_a and signRComp_uid99_fpCosPiTest_b and signRComp_uid99_fpCosPiTest_c;
END IF;
END PROCESS;
--cstZwSwF_uid15_fpCosPiTest(CONSTANT,14)
cstZwSwF_uid15_fpCosPiTest_q <= "00000000000000000000000000000000000";
--cstHalfwSwFP1_uid18_fpCosPiTest(BITJOIN,17)@2
cstHalfwSwFP1_uid18_fpCosPiTest_q <= VCC_q & cstZwSwF_uid15_fpCosPiTest_q;
--reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1(REG,237)@1
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= fxpXFrac_uid43_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--fxpXFracHalf_uid46_fpCosPiTest(LOGICAL,45)@2
fxpXFracHalf_uid46_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracHalf_uid46_fpCosPiTest_b <= cstHalfwSwFP1_uid18_fpCosPiTest_q;
fxpXFracHalf_uid46_fpCosPiTest_q <= "1" when fxpXFracHalf_uid46_fpCosPiTest_a = fxpXFracHalf_uid46_fpCosPiTest_b else "0";
--ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a(DELAY,370)@2
ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid46_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFxpXFracHalf_uid100_fpCosPiTest(LOGICAL,99)@3
InvFxpXFracHalf_uid100_fpCosPiTest_a <= ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q;
InvFxpXFracHalf_uid100_fpCosPiTest_q <= not InvFxpXFracHalf_uid100_fpCosPiTest_a;
--signR_uid101_fpCosPiTest(LOGICAL,100)@3
signR_uid101_fpCosPiTest_a <= InvFxpXFracHalf_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRComp_uid99_fpCosPiTest_q;
signR_uid101_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid101_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a and signR_uid101_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c(DELAY,375)@4
ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid101_fpCosPiTest_q, xout => ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111";
--pad_o_uid16_uid47_fpCosPiTest(BITJOIN,46)@1
pad_o_uid16_uid47_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0(REG,244)@1
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= pad_o_uid16_uid47_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid47_fpCosPiTest(SUB,47)@2
oMFxpXFrac_uid47_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q);
oMFxpXFrac_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q);
oMFxpXFrac_uid47_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_b));
oMFxpXFrac_uid47_fpCosPiTest_q <= oMFxpXFrac_uid47_fpCosPiTest_o(37 downto 0);
--oMFxpXFrac_uid49_fpCosPiTest(BITSELECT,48)@2
oMFxpXFrac_uid49_fpCosPiTest_in <= oMFxpXFrac_uid47_fpCosPiTest_q(35 downto 0);
oMFxpXFrac_uid49_fpCosPiTest_b <= oMFxpXFrac_uid49_fpCosPiTest_in(35 downto 0);
--ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c(DELAY,308)@1
ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => fxpXFrac_uid43_fpCosPiTest_b, xout => ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b(DELAY,307)@1
ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid44_fpCosPiTest_b, xout => ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid51_fpCosPiTest(MUX,50)@2
rangeReducedFxPX_uid51_fpCosPiTest_s <= ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q;
rangeReducedFxPX_uid51_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid51_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid51_fpCosPiTest_q <= ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid51_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid17_uid52_fpCosPiTest(BITJOIN,51)@2
pad_half_uid17_uid52_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0(REG,246)@2
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= pad_half_uid17_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid52_fpCosPiTest(SUB,52)@3
z_halfMRRFxPXE_uid52_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid51_fpCosPiTest_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_b));
z_halfMRRFxPXE_uid52_fpCosPiTest_q <= z_halfMRRFxPXE_uid52_fpCosPiTest_o(36 downto 0);
--z_uid54_fpCosPiTest(BITSELECT,53)@3
z_uid54_fpCosPiTest_in <= z_halfMRRFxPXE_uid52_fpCosPiTest_q(34 downto 0);
z_uid54_fpCosPiTest_b <= z_uid54_fpCosPiTest_in(34 downto 0);
--zAddr_uid62_fpCosPiTest(BITSELECT,61)@3
zAddr_uid62_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
zAddr_uid62_fpCosPiTest_b <= zAddr_uid62_fpCosPiTest_in(34 downto 28);
--reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0(REG,263)@3
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= zAddr_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid209_sinPiZTableGenerator(LOOKUP,208)@4
memoryC2_uid209_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid209_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid63_fpCosPiTest(BITSELECT,62)@3
zPPolyEval_uid63_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(27 downto 0);
zPPolyEval_uid63_fpCosPiTest_b <= zPPolyEval_uid63_fpCosPiTest_in(27 downto 12);
--yT1_uid210_sinPiZPolyEval(BITSELECT,209)@3
yT1_uid210_sinPiZPolyEval_in <= zPPolyEval_uid63_fpCosPiTest_b;
yT1_uid210_sinPiZPolyEval_b <= yT1_uid210_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0(REG,264)@3
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= yT1_uid210_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a(DELAY,499)@4
ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid226_pT1_uid211_sinPiZPolyEval(MULT,225)@5
prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_b);
prodXY_uid226_pT1_uid211_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= memoryC2_uid209_sinPiZTableGenerator_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid226_pT1_uid211_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval(BITSELECT,226)@8
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_q;
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid213_sinPiZPolyEval(BITSELECT,212)@8
highBBits_uid213_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b;
highBBits_uid213_sinPiZPolyEval_b <= highBBits_uid213_sinPiZPolyEval_in(14 downto 1);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable(LOGICAL,557)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor(LOGICAL,596)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top(CONSTANT,592)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q <= "010";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp(LOGICAL,593)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg(REG,594)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena(REG,597)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd(LOGICAL,598)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,588)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i = 1 THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i,2));
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg(REG,589)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux(MUX,590)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem(DUALMEM,587)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC1_uid208_sinPiZTableGenerator(LOOKUP,207)@8
memoryC1_uid208_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid208_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid214_sinPiZPolyEval(ADD,213)@8
sumAHighB_uid214_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid208_sinPiZTableGenerator_q(20)) & memoryC1_uid208_sinPiZTableGenerator_q);
sumAHighB_uid214_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid213_sinPiZPolyEval_b(13)) & highBBits_uid213_sinPiZPolyEval_b);
sumAHighB_uid214_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid214_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid214_sinPiZPolyEval_b));
sumAHighB_uid214_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid212_sinPiZPolyEval(BITSELECT,211)@8
lowRangeB_uid212_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid212_sinPiZPolyEval_b <= lowRangeB_uid212_sinPiZPolyEval_in(0 downto 0);
--s1_uid212_uid215_sinPiZPolyEval(BITJOIN,214)@8
s1_uid212_uid215_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_q & lowRangeB_uid212_sinPiZPolyEval_b;
--reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1(REG,267)@8
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= s1_uid212_uid215_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor(LOGICAL,609)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a or ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena(REG,610)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd(LOGICAL,611)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg(DELAY,599)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid63_fpCosPiTest_b, xout => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem(DUALMEM,600)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0(REG,266)@8
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid229_pT2_uid217_sinPiZPolyEval(MULT,228)@9
prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_b);
prodXY_uid229_pT2_uid217_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid229_pT2_uid217_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval(BITSELECT,229)@12
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_q;
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid219_sinPiZPolyEval(BITSELECT,218)@12
highBBits_uid219_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b;
highBBits_uid219_sinPiZPolyEval_b <= highBBits_uid219_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor(LOGICAL,584)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top(CONSTANT,554)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp(LOGICAL,555)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a = ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg(REG,556)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena(REG,585)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd(LOGICAL,586)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,550)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg(REG,551)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux(MUX,552)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem(DUALMEM,575)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid207_sinPiZTableGenerator(LOOKUP,206)@12
memoryC0_uid207_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid207_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid220_sinPiZPolyEval(ADD,219)@12
sumAHighB_uid220_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid207_sinPiZTableGenerator_q(28)) & memoryC0_uid207_sinPiZTableGenerator_q);
sumAHighB_uid220_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid219_sinPiZPolyEval_b(21)) & highBBits_uid219_sinPiZPolyEval_b);
sumAHighB_uid220_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid220_sinPiZPolyEval_b));
sumAHighB_uid220_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid218_sinPiZPolyEval(BITSELECT,217)@12
lowRangeB_uid218_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid218_sinPiZPolyEval_b <= lowRangeB_uid218_sinPiZPolyEval_in(1 downto 0);
--s2_uid218_uid221_sinPiZPolyEval(BITJOIN,220)@12
s2_uid218_uid221_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_q & lowRangeB_uid218_sinPiZPolyEval_b;
--fxpSinRes_uid65_fpCosPiTest(BITSELECT,64)@12
fxpSinRes_uid65_fpCosPiTest_in <= s2_uid218_uid221_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid65_fpCosPiTest_b <= fxpSinRes_uid65_fpCosPiTest_in(29 downto 5);
--reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1(REG,270)@12
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= fxpSinRes_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor(LOGICAL,622)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q <= not (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a or ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena(REG,623)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd(LOGICAL,624)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a and ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest(BITSELECT,201)@7
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest(BITJOIN,202)@7
leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest(BITSELECT,198)@7
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest(BITJOIN,199)@7
leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest(BITSELECT,195)@7
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest(BITJOIN,196)@7
leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b & GND_q;
--vStage_uid141_lzcZ_uid56_fpCosPiTest(BITSELECT,140)@3
vStage_uid141_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(2 downto 0);
vStage_uid141_lzcZ_uid56_fpCosPiTest_b <= vStage_uid141_lzcZ_uid56_fpCosPiTest_in(2 downto 0);
--ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b(DELAY,450)@3
ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid141_lzcZ_uid56_fpCosPiTest_b, xout => ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest(BITJOIN,179)@6
leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q <= ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X18dto0_uid176_alignedZ_uid57_fpCosPiTest(BITSELECT,175)@3
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(18 downto 0);
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b <= X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in(18 downto 0);
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg(DELAY,573)
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b(DELAY,449)@3
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest(BITJOIN,176)@6
leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q <= ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg(DELAY,574)
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid54_fpCosPiTest_b, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c(DELAY,453)@3
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid138_lzcZ_uid56_fpCosPiTest(BITSELECT,137)@3
rVStage_uid138_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
rVStage_uid138_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_in(34 downto 3);
--reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1(REG,247)@3
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid139_lzcZ_uid56_fpCosPiTest(LOGICAL,138)@4
vCount_uid139_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid139_lzcZ_uid56_fpCosPiTest_a = vCount_uid139_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f(DELAY,447)@4
ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid139_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid140_lzcZ_uid56_fpCosPiTest(CONSTANT,139)
mO_uid140_lzcZ_uid56_fpCosPiTest_q <= "11111111111111111111111111111";
--cStage_uid142_lzcZ_uid56_fpCosPiTest(BITJOIN,141)@3
cStage_uid142_lzcZ_uid56_fpCosPiTest_q <= vStage_uid141_lzcZ_uid56_fpCosPiTest_b & mO_uid140_lzcZ_uid56_fpCosPiTest_q;
--reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3(REG,249)@3
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= cStage_uid142_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid144_lzcZ_uid56_fpCosPiTest(MUX,143)@4
vStagei_uid144_lzcZ_uid56_fpCosPiTest_s <= vCount_uid139_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid144_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid144_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q, reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid144_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_lzcZ_uid56_fpCosPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid146_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1(REG,250)@4
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid56_fpCosPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid147_lzcZ_uid56_fpCosPiTest_a = vCount_uid147_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e(DELAY,446)@5
ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid148_lzcZ_uid56_fpCosPiTest(BITSELECT,147)@4
vStage_uid148_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q(15 downto 0);
vStage_uid148_lzcZ_uid56_fpCosPiTest_b <= vStage_uid148_lzcZ_uid56_fpCosPiTest_in(15 downto 0);
--reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3(REG,252)@4
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid148_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid150_lzcZ_uid56_fpCosPiTest(MUX,149)@5
vStagei_uid150_lzcZ_uid56_fpCosPiTest_s <= vCount_uid147_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid150_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid150_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid150_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid152_lzcZ_uid56_fpCosPiTest(BITSELECT,151)@5
rVStage_uid152_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid152_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_in(15 downto 8);
--vCount_uid153_lzcZ_uid56_fpCosPiTest(LOGICAL,152)@5
vCount_uid153_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
vCount_uid153_lzcZ_uid56_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
vCount_uid153_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid153_lzcZ_uid56_fpCosPiTest_a = vCount_uid153_lzcZ_uid56_fpCosPiTest_b else "0";
--reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3(REG,256)@5
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid154_lzcZ_uid56_fpCosPiTest(BITSELECT,153)@5
vStage_uid154_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q(7 downto 0);
vStage_uid154_lzcZ_uid56_fpCosPiTest_b <= vStage_uid154_lzcZ_uid56_fpCosPiTest_in(7 downto 0);
--vStagei_uid156_lzcZ_uid56_fpCosPiTest(MUX,155)@5
vStagei_uid156_lzcZ_uid56_fpCosPiTest_s <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid156_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid156_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid152_lzcZ_uid56_fpCosPiTest_b, vStage_uid154_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid156_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= vStage_uid154_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid158_lzcZ_uid56_fpCosPiTest(BITSELECT,157)@5
rVStage_uid158_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid158_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_in(7 downto 4);
--reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1(REG,253)@5
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid159_lzcZ_uid56_fpCosPiTest(LOGICAL,158)@6
vCount_uid159_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid159_lzcZ_uid56_fpCosPiTest_a = vCount_uid159_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid160_lzcZ_uid56_fpCosPiTest(BITSELECT,159)@5
vStage_uid160_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
vStage_uid160_lzcZ_uid56_fpCosPiTest_b <= vStage_uid160_lzcZ_uid56_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3(REG,255)@5
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid160_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid162_lzcZ_uid56_fpCosPiTest(MUX,161)@6
vStagei_uid162_lzcZ_uid56_fpCosPiTest_s <= vCount_uid159_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid162_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid162_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid162_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid164_lzcZ_uid56_fpCosPiTest(BITSELECT,163)@6
rVStage_uid164_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid164_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_in(3 downto 2);
--vCount_uid165_lzcZ_uid56_fpCosPiTest(LOGICAL,164)@6
vCount_uid165_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
vCount_uid165_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
vCount_uid165_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid165_lzcZ_uid56_fpCosPiTest_a = vCount_uid165_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid166_lzcZ_uid56_fpCosPiTest(BITSELECT,165)@6
vStage_uid166_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
vStage_uid166_lzcZ_uid56_fpCosPiTest_b <= vStage_uid166_lzcZ_uid56_fpCosPiTest_in(1 downto 0);
--vStagei_uid168_lzcZ_uid56_fpCosPiTest(MUX,167)@6
vStagei_uid168_lzcZ_uid56_fpCosPiTest_s <= vCount_uid165_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid168_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid168_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid164_lzcZ_uid56_fpCosPiTest_b, vStage_uid166_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid168_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= vStage_uid166_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid170_lzcZ_uid56_fpCosPiTest(BITSELECT,169)@6
rVStage_uid170_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid168_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid170_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_in(1 downto 1);
--vCount_uid171_lzcZ_uid56_fpCosPiTest(LOGICAL,170)@6
vCount_uid171_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_b;
vCount_uid171_lzcZ_uid56_fpCosPiTest_b <= GND_q;
vCount_uid171_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid171_lzcZ_uid56_fpCosPiTest_a = vCount_uid171_lzcZ_uid56_fpCosPiTest_b else "0";
--r_uid172_lzcZ_uid56_fpCosPiTest(BITJOIN,171)@6
r_uid172_lzcZ_uid56_fpCosPiTest_q <= ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q & ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q & reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q & vCount_uid159_lzcZ_uid56_fpCosPiTest_q & vCount_uid165_lzcZ_uid56_fpCosPiTest_q & vCount_uid171_lzcZ_uid56_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest(BITSELECT,181)@6
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest(MUX,182)@6
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b;
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s, en, ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q, leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q, cstZwSwF_uid15_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= cstZwSwF_uid15_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest(BITSELECT,190)@6
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest(BITJOIN,191)@6
leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5(REG,261)@6
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest(BITSELECT,187)@6
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest(BITJOIN,188)@6
leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4(REG,260)@6
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest(BITSELECT,184)@6
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest(BITJOIN,185)@6
leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3(REG,259)@6
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2(REG,258)@6
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest(BITSELECT,192)@6
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1(REG,257)@6
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest(MUX,193)@7
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s, en, reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest(BITSELECT,203)@6
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1(REG,262)@6
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest(MUX,204)@7
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s, en, leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid58_fpCosPiTest(BITSELECT,57)@7
alignedZLow_uid58_fpCosPiTest_in <= leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q;
alignedZLow_uid58_fpCosPiTest_b <= alignedZLow_uid58_fpCosPiTest_in(34 downto 11);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg(DELAY,612)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid58_fpCosPiTest_b, xout => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem(DUALMEM,613)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0(REG,269)@12
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest(MULT,222)@13
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr <= UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a) * UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b);
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest(BITSELECT,223)@16
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q;
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in(48 downto 23);
--normBit_uid67_fpCosPiTest(BITSELECT,66)@16
normBit_uid67_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b;
normBit_uid67_fpCosPiTest_b <= normBit_uid67_fpCosPiTest_in(25 downto 25);
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "00000000000000000000000";
--rndExpUpdate_uid72_uid73_fpCosPiTest(BITJOIN,72)@16
rndExpUpdate_uid72_uid73_fpCosPiTest_q <= normBit_uid67_fpCosPiTest_b & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor(LOGICAL,558)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a or ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena(REG,559)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd(LOGICAL,560)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b;
--reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1(REG,271)@6
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem(DUALMEM,549)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia <= reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111110";
--expHardCase_uid59_fpCosPiTest(SUB,58)@15
expHardCase_uid59_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid59_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q);
expHardCase_uid59_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid59_fpCosPiTest_a) - UNSIGNED(expHardCase_uid59_fpCosPiTest_b));
expHardCase_uid59_fpCosPiTest_q <= expHardCase_uid59_fpCosPiTest_o(8 downto 0);
--expP_uid60_fpCosPiTest(BITSELECT,59)@15
expP_uid60_fpCosPiTest_in <= expHardCase_uid59_fpCosPiTest_q(7 downto 0);
expP_uid60_fpCosPiTest_b <= expP_uid60_fpCosPiTest_in(7 downto 0);
--reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1(REG,272)@15
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= expP_uid60_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid68_fpCosPiTest(BITSELECT,67)@16
highRes_uid68_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(24 downto 0);
highRes_uid68_fpCosPiTest_b <= highRes_uid68_fpCosPiTest_in(24 downto 1);
--lowRes_uid69_fpCosPiTest(BITSELECT,68)@16
lowRes_uid69_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(23 downto 0);
lowRes_uid69_fpCosPiTest_b <= lowRes_uid69_fpCosPiTest_in(23 downto 0);
--fracRCompPreRnd_uid70_fpCosPiTest(MUX,69)@16
fracRCompPreRnd_uid70_fpCosPiTest_s <= normBit_uid67_fpCosPiTest_b;
fracRCompPreRnd_uid70_fpCosPiTest: PROCESS (fracRCompPreRnd_uid70_fpCosPiTest_s, en, lowRes_uid69_fpCosPiTest_b, highRes_uid68_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid70_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid70_fpCosPiTest_q <= lowRes_uid69_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid70_fpCosPiTest_q <= highRes_uid68_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid70_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid71_uid71_fpCosPiTest(BITJOIN,70)@16
expFracPreRnd_uid71_uid71_fpCosPiTest_q <= reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q & fracRCompPreRnd_uid70_fpCosPiTest_q;
--expFracComp_uid74_fpCosPiTest(ADD,73)@16
expFracComp_uid74_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid71_uid71_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid72_uid73_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid74_fpCosPiTest_a) + UNSIGNED(expFracComp_uid74_fpCosPiTest_b));
expFracComp_uid74_fpCosPiTest_q <= expFracComp_uid74_fpCosPiTest_o(32 downto 0);
--expRComp_uid76_fpCosPiTest(BITSELECT,75)@16
expRComp_uid76_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(31 downto 0);
expRComp_uid76_fpCosPiTest_b <= expRComp_uid76_fpCosPiTest_in(31 downto 24);
--fracXIsZero_uid27_fpCosPiTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid27_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid27_fpCosPiTest_q <= "1" when fracXIsZero_uid27_fpCosPiTest_a = fracXIsZero_uid27_fpCosPiTest_b else "0";
--InvFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
InvFracXIsZero_uid29_fpCosPiTest_a <= fracXIsZero_uid27_fpCosPiTest_q;
InvFracXIsZero_uid29_fpCosPiTest_q <= not InvFracXIsZero_uid29_fpCosPiTest_a;
--expXIsMax_uid25_fpCosPiTest(LOGICAL,24)@0
expXIsMax_uid25_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid25_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid25_fpCosPiTest_q <= "1" when expXIsMax_uid25_fpCosPiTest_a = expXIsMax_uid25_fpCosPiTest_b else "0";
--exc_N_uid30_fpCosPiTest(LOGICAL,29)@0
exc_N_uid30_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_b <= InvFracXIsZero_uid29_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_q <= exc_N_uid30_fpCosPiTest_a and exc_N_uid30_fpCosPiTest_b;
--InvExc_N_uid31_fpCosPiTest(LOGICAL,30)@0
InvExc_N_uid31_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
InvExc_N_uid31_fpCosPiTest_q <= not InvExc_N_uid31_fpCosPiTest_a;
--exc_I_uid28_fpCosPiTest(LOGICAL,27)@0
exc_I_uid28_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_b <= fracXIsZero_uid27_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_q <= exc_I_uid28_fpCosPiTest_a and exc_I_uid28_fpCosPiTest_b;
--InvExc_I_uid32_fpCosPiTest(LOGICAL,31)@0
InvExc_I_uid32_fpCosPiTest_a <= exc_I_uid28_fpCosPiTest_q;
InvExc_I_uid32_fpCosPiTest_q <= not InvExc_I_uid32_fpCosPiTest_a;
--expXIsZero_uid23_fpCosPiTest(LOGICAL,22)@0
expXIsZero_uid23_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid23_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
expXIsZero_uid23_fpCosPiTest_q <= "1" when expXIsZero_uid23_fpCosPiTest_a = expXIsZero_uid23_fpCosPiTest_b else "0";
--InvExpXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvExpXIsZero_uid33_fpCosPiTest_a <= expXIsZero_uid23_fpCosPiTest_q;
InvExpXIsZero_uid33_fpCosPiTest_q <= not InvExpXIsZero_uid33_fpCosPiTest_a;
--exc_R_uid34_fpCosPiTest(LOGICAL,33)@0
exc_R_uid34_fpCosPiTest_a <= InvExpXIsZero_uid33_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_b <= InvExc_I_uid32_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_c <= InvExc_N_uid31_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_q <= exc_R_uid34_fpCosPiTest_a and exc_R_uid34_fpCosPiTest_b and exc_R_uid34_fpCosPiTest_c;
--ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a(DELAY,337)@0
ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => exc_R_uid34_fpCosPiTest_q, xout => ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsHalf_uid83_fpCosPiTest(LOGICAL,82)@2
xIsHalf_uid83_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsHalf_uid83_fpCosPiTest_b <= fxpXFracHalf_uid46_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_c <= InvCosXIsOne_uid77_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_d <= InvXEvenInt_uid81_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_q <= xIsHalf_uid83_fpCosPiTest_a and xIsHalf_uid83_fpCosPiTest_b and xIsHalf_uid83_fpCosPiTest_c and xIsHalf_uid83_fpCosPiTest_d;
--ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b(DELAY,355)@2
ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid83_fpCosPiTest_q, xout => ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid91_fpCosPiTest(MUX,90)@16
expRPostExc1_uid91_fpCosPiTest_s <= ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q;
expRPostExc1_uid91_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid91_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid91_fpCosPiTest_q <= expRComp_uid76_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid91_fpCosPiTest_q <= cstAllZWE_uid21_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor(LOGICAL,570)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q <= not (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a or ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b);
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top(CONSTANT,566)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp(LOGICAL,567)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q <= "1" when ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a = ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b else "0";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg(REG,568)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena(REG,571)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd(LOGICAL,572)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a and ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b;
--ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b(DELAY,359)@0
ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid23_fpCosPiTest_q, xout => ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid45_fpCosPiTest(LOGICAL,44)@2
fxpXFracZero_uid45_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid15_fpCosPiTest_q);
fxpXFracZero_uid45_fpCosPiTest_q <= "1" when fxpXFracZero_uid45_fpCosPiTest_a = fxpXFracZero_uid45_fpCosPiTest_b else "0";
--fracZCosNotOne_uid78_fpCosPiTest(LOGICAL,77)@2
fracZCosNotOne_uid78_fpCosPiTest_a <= fxpXFracZero_uid45_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_b <= InvCosXIsOne_uid77_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_q <= fracZCosNotOne_uid78_fpCosPiTest_a and fracZCosNotOne_uid78_fpCosPiTest_b;
--evenIntCosNotOneFZ_uid79_fpCosPiTest(LOGICAL,78)@2
evenIntCosNotOneFZ_uid79_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_b <= fracZCosNotOne_uid78_fpCosPiTest_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_q <= evenIntCosNotOneFZ_uid79_fpCosPiTest_a or evenIntCosNotOneFZ_uid79_fpCosPiTest_b;
--xIsInt_uid80_fpCosPiTest(LOGICAL,79)@2
xIsInt_uid80_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsInt_uid80_fpCosPiTest_b <= evenIntCosNotOneFZ_uid79_fpCosPiTest_q;
xIsInt_uid80_fpCosPiTest_q <= xIsInt_uid80_fpCosPiTest_a and xIsInt_uid80_fpCosPiTest_b;
--xIntOrXZOrCosOne_uid93_fpCosPiTest(LOGICAL,92)@2
xIntOrXZOrCosOne_uid93_fpCosPiTest_a <= xIsInt_uid80_fpCosPiTest_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_b <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_c <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_a or xIntOrXZOrCosOne_uid93_fpCosPiTest_b or xIntOrXZOrCosOne_uid93_fpCosPiTest_c;
--excRNaN_uid84_fpCosPiTest(LOGICAL,83)@0
excRNaN_uid84_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_b <= exc_I_uid28_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_q <= excRNaN_uid84_fpCosPiTest_a or excRNaN_uid84_fpCosPiTest_b;
--rInfOrNaN_uid92_fpCosPiTest(LOGICAL,91)@0
rInfOrNaN_uid92_fpCosPiTest_a <= GND_q;
rInfOrNaN_uid92_fpCosPiTest_b <= excRNaN_uid84_fpCosPiTest_q;
rInfOrNaN_uid92_fpCosPiTest_q <= rInfOrNaN_uid92_fpCosPiTest_a or rInfOrNaN_uid92_fpCosPiTest_b;
--ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a(DELAY,361)@0
ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rInfOrNaN_uid92_fpCosPiTest_q, xout => ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid94_fpCosPiTest(BITJOIN,93)@2
join_uid94_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_q & ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q;
--reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1(REG,274)@2
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= join_uid94_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt(COUNTER,562)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg(REG,563)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux(MUX,564)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem(DUALMEM,561)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia <= reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia
);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid95_fpCosPiTest(MUX,94)@17
expRPostExc_uid95_fpCosPiTest_s <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid95_fpCosPiTest: PROCESS (expRPostExc_uid95_fpCosPiTest_s, en, expRPostExc1_uid91_fpCosPiTest_q, cstAllOWE_uid8_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid95_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid95_fpCosPiTest_q <= expRPostExc1_uid91_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid95_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid95_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid87_fpCosPiTest(CONSTANT,86)
oneFracRPostExc2_uid87_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid75_fpCosPiTest(BITSELECT,74)@16
fracRComp_uid75_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(23 downto 0);
fracRComp_uid75_fpCosPiTest_b <= fracRComp_uid75_fpCosPiTest_in(23 downto 1);
--reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5(REG,243)@2
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= xIsHalf_uid83_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4(REG,242)@2
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3(REG,241)@2
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= fxpXFracHalf_uid46_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2(REG,240)@2
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= xIsInt_uid80_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1(REG,239)@0
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= cosXIsOne_uid36_fpCosPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a(DELAY,346)@1
ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q, xout => ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--bigCond_uid85_fpCosPiTest(LOGICAL,84)@3
bigCond_uid85_fpCosPiTest_a <= ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q;
bigCond_uid85_fpCosPiTest_b <= reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q;
bigCond_uid85_fpCosPiTest_c <= reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q;
bigCond_uid85_fpCosPiTest_d <= reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q;
bigCond_uid85_fpCosPiTest_f <= reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q;
bigCond_uid85_fpCosPiTest_g <= GND_q;
bigCond_uid85_fpCosPiTest_q <= bigCond_uid85_fpCosPiTest_a or bigCond_uid85_fpCosPiTest_b or bigCond_uid85_fpCosPiTest_c or bigCond_uid85_fpCosPiTest_d or bigCond_uid85_fpCosPiTest_f or bigCond_uid85_fpCosPiTest_g;
--ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b(DELAY,351)@3
ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid85_fpCosPiTest_q, xout => ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid86_fpCosPiTest(MUX,85)@16
fracRPostExc1_uid86_fpCosPiTest_s <= ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q;
fracRPostExc1_uid86_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid86_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid86_fpCosPiTest_q <= fracRComp_uid75_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid86_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1(REG,273)@0
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= excRNaN_uid84_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b(DELAY,353)@1
ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q, xout => ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpCosPiTest(MUX,87)@17
fracRPostExc_uid88_fpCosPiTest_s <= ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q;
fracRPostExc_uid88_fpCosPiTest: PROCESS (fracRPostExc_uid88_fpCosPiTest_s, en, fracRPostExc1_uid86_fpCosPiTest_q, oneFracRPostExc2_uid87_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid88_fpCosPiTest_q <= fracRPostExc1_uid86_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid88_fpCosPiTest_q <= oneFracRPostExc2_uid87_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid102_fpCosPiTest(BITJOIN,101)@17
R_uid102_fpCosPiTest_q <= ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q & expRPostExc_uid95_fpCosPiTest_q & fracRPostExc_uid88_fpCosPiTest_q;
--xOut(GPOUT,4)@17
q <= R_uid102_fpCosPiTest_q;
end normal;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/hcc_castftoy.vhd | 10 | 4220 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOY.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single to Internal ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
-- castftoy : float <=> internal double
ENTITY hcc_castftoy IS
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castftoy;
ARCHITECTURE rtl OF hcc_castftoy IS
signal floatnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if ftoy target divider or multiplier, need unsigned output
-- if ftoy target = 1 (internal), ftox target = 0, xtoy target = 1
-- if ftoy target = 0 (multiplier, divider), ftox target = 2 (divider), xtoy target = 0 (mult&div)
gaa: IF (target = 1) GENERATE
one: hcc_castftox
GENERIC MAP(target=>0,roundconvert=>roundconvert,
mantissa=>mantissa,outputpipe=>outputpipe)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>floatnode,ccsat=>satnode,cczip=>zipnode);
two: hcc_castxtoy
GENERIC MAP(target=>1,mantissa=>mantissa)
PORT MAP (aa=>floatnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END GENERATE;
gab: IF (target = 0) GENERATE
one: hcc_castftox
GENERIC MAP(target=>2,roundconvert=>roundconvert,
mantissa=>mantissa,outputpipe=>outputpipe)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>floatnode,ccsat=>satnode,cczip=>zipnode);
two: hcc_castxtoy
GENERIC MAP(target=>0,mantissa=>mantissa)
PORT MAP (aa=>floatnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/dp_addpipe.vhd | 10 | 2509 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - CORE LEVEL ***
--*** ***
--*** DP_ADDPIPE.VHD ***
--*** ***
--*** Function: Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_addpipe;
ARCHITECTURE syn of dp_addpipe IS
component lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
cin : IN STD_LOGIC ;
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0)
);
end component;
BEGIN
addtwo: lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
lpm_pipeline => pipes,
lpm_type => "LPM_ADD_SUB",
lpm_width => width
)
PORT MAP (
dataa => aa,
datab => bb,
cin => carryin,
clken => enable,
aclr => reset,
clock => sysclk,
result => cc
);
END syn;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/SqrtDPStratixVf400_safe_path.vhd | 10 | 432 | -- safe_path for SqrtDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SqrtDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SqrtDPStratixVf400_safe_path;
PACKAGE body SqrtDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END SqrtDPStratixVf400_safe_path;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/SqrtDPStratixVf400_safe_path.vhd | 10 | 432 | -- safe_path for SqrtDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SqrtDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SqrtDPStratixVf400_safe_path;
PACKAGE body SqrtDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END SqrtDPStratixVf400_safe_path;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_lsft36.vhd | 10 | 4582 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT36.VHD ***
--*** ***
--*** Function: 36 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_lsft36;
ARCHITECTURE sft OF fp_lsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
-- shift by 0,16,32
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END sft;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/dp_inv.vhd | 10 | 12634 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** DP_INV.VHD ***
--*** ***
--*** Function: IEEE754 DP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 12/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** ***
--*** Stratix II ***
--*** Latency = 20 + 2*DoubleSpeed + ***
--*** RoundConvert*(1+DoubleSpeed) ***
--*** DoubleSpeed = 0, Roundconvert = 0 : 20 ***
--*** DoubleSpeed = 1, Roundconvert = 0 : 22 ***
--*** DoubleSpeed = 0, Roundconvert = 1 : 21 ***
--*** DoubleSpeed = 1, Roundconvert = 1 : 24 ***
--*** ***
--*** Stratix III/IV ***
--*** Latency = 19 + DoubleSpeed + ***
--*** Roundconvert*(1+DoubleSpeed) ***
--*** DoubleSpeed = 0, Roundconvert = 0 : 19 ***
--*** DoubleSpeed = 1, Roundconvert = 0 : 20 ***
--*** DoubleSpeed = 0, Roundconvert = 1 : 20 ***
--*** DoubleSpeed = 1, Roundconvert = 1 : 22 ***
--*** ***
--***************************************************
ENTITY dp_inv IS
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END dp_inv;
ARCHITECTURE rtl OF dp_inv IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
-- SII Latency = 19 + 2*speed
-- SIII Latency = 18 + speed
constant coredepth : positive := 19+2*doublespeed - device*(1+doublespeed);
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component dp_inv_core
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (55 DOWNTO 1)
);
end component;
component dp_divnornd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
component dp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
component dp_divrndpipe
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- quotient always <1, so decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & '0';
invcore: dp_inv_core
GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
-- quotient always <1
--************************
--*** ROUND AND OUTPUT ***
--************************
-- in depth coredepth+1 (core + normalff)
gra: IF (roundconvert = 0) GENERATE
norndout: dp_divnornd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(53 DOWNTO 1),
nanin=>nanff(coredepth-3),
dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END GENERATE;
grb: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
rndout: dp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(53 DOWNTO 1),
nanin=>nanff(coredepth-3),
dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END GENERATE;
grc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
rndoutpipe: dp_divrndpipe
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(53 DOWNTO 1),
nanin=>nanff(coredepth-3),
dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_mul54us_28s.vhd | 10 | 10055 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE lpm.all;
USE altera_mf.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54US_28S.VHD ***
--*** ***
--*** Function: 5/6 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 28S: Stratix 2, 8 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Identical to HCC_MUL54US_28S, except 5 ***
--*** or 6 pipeline parameter and 72 outputs ***
--***************************************************
ENTITY fp_mul54us_28s IS
GENERIC (latency : positive := 5);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54us_28s;
ARCHITECTURE syn of fp_mul54us_28s IS
signal muloneaa, mulonebb : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multwoaa, multwobb, multhraa, multhrbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulforaa, mulforbb, mulfivaa, mulfivbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout, mulforout, mulfivout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr, vecfor, vecfiv : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal vecsix, vecsev : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal vecegt, vecnin, vecten : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecone, carvecone : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal sumvectwo, carvectwo : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal sumvecthr, carvecthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumoneff, caroneff : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (71 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
muloneaa <= mulaa(54 DOWNTO 19);
mulonebb <= mulbb(54 DOWNTO 19);
multwoaa <= mulaa(18 DOWNTO 1);
multwobb <= mulbb(36 DOWNTO 19);
multhraa <= mulaa(18 DOWNTO 1);
multhrbb <= mulbb(54 DOWNTO 37);
mulforaa <= mulbb(18 DOWNTO 1);
mulforbb <= mulaa(36 DOWNTO 19);
mulfivaa <= mulbb(18 DOWNTO 1);
mulfivbb <= mulaa(54 DOWNTO 37);
-- {A,C) * {B,D}
-- AAC
-- BBD
-- AA*BB 36x36=72, latency 3
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => muloneaa,
datab => mulonebb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => multwoaa,
datab_0 => multwobb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => multhraa,
datab_0 => multhrbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulforaa,
datab_0 => mulforbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulfivaa,
datab_0 => mulfivbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
vecone <= zerovec(22 DOWNTO 1) & multwoout;
vectwo <= zerovec(4 DOWNTO 1) & multhrout & zerovec(18 DOWNTO 1);
vecthr <= zerovec(22 DOWNTO 1) & mulforout;
vecfor <= zerovec(4 DOWNTO 1) & mulfivout & zerovec(18 DOWNTO 1);
gva: FOR k IN 1 TO 58 GENERATE
sumvecone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carvecone(k) <= (vecone(k) AND vectwo(k)) OR
(vectwo(k) AND vecthr(k)) OR
(vecone(k) AND vecthr(k));
END GENERATE;
vecfiv <= vecfor;
vecsix <= sumvecone;
vecsev <= carvecone(57 DOWNTO 1) & '0';
gvb: FOR k IN 1 TO 58 GENERATE
sumvectwo(k) <= vecfiv(k) XOR vecsix(k) XOR vecsev(k);
carvectwo(k) <= (vecfiv(k) AND vecsix(k)) OR
(vecsix(k) AND vecsev(k)) OR
(vecfiv(k) AND vecsev(k));
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 58 LOOP
sumoneff(k) <= '0';
caroneff(k) <= '0';
END LOOP;
FOR k IN 1 TO 72 LOOP
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumoneff <= sumvectwo;
caroneff <= carvectwo(57 DOWNTO 1) & '0';
sumtwoff <= sumvecthr;
cartwoff <= carvecthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
vecegt <= zerovec(32 DOWNTO 1) & sumoneff(58 DOWNTO 19);
vecnin <= zerovec(32 DOWNTO 1) & caroneff(58 DOWNTO 19);
vecten <= muloneout(72 DOWNTO 1);
vecten <= muloneout(72 DOWNTO 1);
gvc: FOR k IN 1 TO 72 GENERATE
sumvecthr(k) <= vecegt(k) XOR vecnin(k) XOR vecten(k);
carvecthr(k) <= (vecegt(k) AND vecnin(k)) OR
(vecnin(k) AND vecten(k)) OR
(vecegt(k) AND vecten(k));
END GENERATE;
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => latency-4,
lpm_type => "LPM_ADD_SUB",
lpm_width => 72
)
PORT MAP (
dataa => sumtwoff(72 DOWNTO 1),
datab => cartwoff(72 DOWNTO 1),
clken => enable,
aclr => reset,
clock => sysclk,
result => resultnode
);
mulcc <= resultnode;
END syn;
| mit |
LorhanSohaky/UFSCar | 2017/lab_cd/aula4/aula4/simulation/qsim/work/@projeto2_vlg_sample_tst/_primary.vhd | 1 | 227 | library verilog;
use verilog.vl_types.all;
entity Projeto2_vlg_sample_tst is
port(
SW : in vl_logic_vector(4 downto 1);
sampler_tx : out vl_logic
);
end Projeto2_vlg_sample_tst;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_atanpi_s5.vhd | 10 | 525003 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atanpi_s5
-- VHDL created on Tue Mar 12 11:23:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0);
signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true;
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true;
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0);
signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0);
signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18)
cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0
fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0);
fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0";
--InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a;
--cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17)
cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111";
--expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0
expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0);
expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0";
--exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0
exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b;
--InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q;
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a;
--singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0
singX_uid17_atanX_uid8_fpArctanPiTest_in <= a;
singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31);
--signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0
signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b;
signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21)
cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111";
--piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45)
piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011";
--cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0);
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35
fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b;
--cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22)
cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110";
--piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46)
piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011";
--cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0);
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35
fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0
exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0);
--constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35
constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q;
constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35
expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68)
cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000";
--reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1
ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230)
cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110";
--expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229)
cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101";
--expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0";
--expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0";
--udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q);
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9);
--InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a;
--InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q;
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a;
--exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c;
--xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b;
--xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b;
--excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0
excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q;
--reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19)
cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001";
--oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0
oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b;
--y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0);
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b;
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15);
--reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1
memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q;
memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid346_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid346_invTabGen_lutmem_iq,
address_a => memoryC2_uid346_invTabGen_lutmem_aa,
data_a => memoryC2_uid346_invTabGen_lutmem_ia
);
memoryC2_uid346_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011)
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0);
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0);
--yT1_uid347_invPolyEval(BITSELECT,346)@3
yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b;
yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3);
--reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4
prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b);
prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q;
prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q;
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q;
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11);
--highBBits_uid350_invPolyEval(BITSELECT,349)@7
highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b;
highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4
memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q;
memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid345_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid345_invTabGen_lutmem_iq,
address_a => memoryC1_uid345_invTabGen_lutmem_aa,
data_a => memoryC1_uid345_invTabGen_lutmem_ia
);
memoryC1_uid345_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid351_invPolyEval(ADD,350)@7
sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q);
sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b);
sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b));
sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0);
--lowRangeB_uid349_invPolyEval(BITSELECT,348)@7
lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0);
lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0);
--s1_uid349_uid352_invPolyEval(BITJOIN,351)@7
s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b;
--reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8
prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b);
prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q;
prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q;
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q;
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14);
--highBBits_uid356_invPolyEval(BITSELECT,355)@11
highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b;
highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8
memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid344_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid344_invTabGen_lutmem_iq,
address_a => memoryC0_uid344_invTabGen_lutmem_aa,
data_a => memoryC0_uid344_invTabGen_lutmem_ia
);
memoryC0_uid344_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid357_invPolyEval(ADD,356)@11
sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q);
sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b);
sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b));
sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0);
--lowRangeB_uid355_invPolyEval(BITSELECT,354)@11
lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0);
lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0);
--s2_uid355_uid358_invPolyEval(BITJOIN,357)@11
s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b;
--fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0);
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5);
--fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0);
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0
ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2
ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12
R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0);
--path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0
path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q;
path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0';
path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0);
path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b));
path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10);
--reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1
ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12
u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q;
u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12
fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12
ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13
oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q;
--oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13
oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
--X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0);
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281)
leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13
leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0);
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13
leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0);
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275)
leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000";
--leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13
leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66)
zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000";
--shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63)
shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010";
--expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12
expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13
shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b));
shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8);
--shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b;
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0);
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b;
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14
ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292)
leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000";
--leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15
leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14
ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289)
leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00";
--leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15
leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14
ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15
leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13
ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15
y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1);
--yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15
yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b;
yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16
memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q;
memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia
);
memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0);
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9);
--yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15
yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062)
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19
prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b);
prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q;
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22
highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b;
highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19
memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q;
memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia
);
memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22
sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q);
sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b);
sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b));
sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22
lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0);
--s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22
s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b;
--reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23
prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b);
prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q;
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26
highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b;
highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23
memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q;
memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia
);
memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26
sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q);
sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b);
sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b));
sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26
lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0);
--s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26
s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b);
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30
normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0);
normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49);
--InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b));
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0);
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25);
--fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0);
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24);
--fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30
expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q;
--reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b));
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0);
--expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31
expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971)
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33
rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333)
rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322)
rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000";
--X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24);
--rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32
rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319)
rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000";
--X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16);
--rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32
rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8);
--rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32
rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30
ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32
oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q;
--cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24)
cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001";
--reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b));
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0);
--shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0);
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23)
cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000";
--shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13
shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q;
shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0';
shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0);
shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b));
shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10);
--ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13
ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q;
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0);
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b;
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32
ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33
rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32
ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33
rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32
ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33
rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31
ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32
ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q;
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33
pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34
path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b));
path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0);
--normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0);
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25);
--expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34
expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0);
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0);
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0);
--fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34
fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34
expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q;
--reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b));
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0);
--expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35
expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b);
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq,
address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa,
data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia
);
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0";
--inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0
inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b;
--arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1
ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61)
biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011";
--atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q;
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0';
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0);
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b));
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10);
--ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0
ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13
pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q;
--reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936)
-- every=1, low=0, high=18, step=1, init=1
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18;
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5));
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36
expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q;
WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20)
cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000";
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35
excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
--reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36
expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b;
--fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia
);
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0);
--fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0);
--fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36
fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36
R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q;
--fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0";
--expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36
expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0";
--exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b;
--cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArctanPiTest_q <= "01111101";
--ooPi_uid9_fpArctanPiTest(CONSTANT,8)
ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36
fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0);
fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36
fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b;
--expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36
expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0);
expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36
ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b;
--fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0);
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36
ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36
ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b;
--expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0";
--excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b;
--ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b;
--InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b;
--ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36
ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b;
--excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q;
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a;
END IF;
END PROCESS;
--signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36
signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q;
signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36
signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q;
signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36
signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37
ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b;
--ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38
ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36
add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36
add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37
prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b);
prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q;
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179)
roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010";
--fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0);
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23);
--fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0);
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22);
--fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b;
WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0);
--Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0);
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22);
--extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0);
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0);
--stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40
stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b;
--stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0";
--sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q;
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a;
--lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40
lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q;
--roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0";
--roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q;
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a;
--roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40
roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q;
--reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162)
biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111";
--ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36
ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0);
--ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38
ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0);
--expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40
expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q;
--reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b));
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0);
--expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q;
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24);
--expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0);
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0);
--ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41
ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37
ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0';
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0);
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b));
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14);
--InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37
ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37
ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c;
--excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37
ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37
ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37
ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d;
--expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0);
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b));
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14);
--excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c;
--excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37
ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37
ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37
ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d;
--concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42
concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q;
--reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS
WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01";
WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10";
WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11";
WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0);
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1);
--ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41
ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43
R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q;
--xOut(GPOUT,4)@43
q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q;
end normal;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/dp_adds.vhd | 10 | 2500 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_ADDS.VHD ***
--*** ***
--*** Function: Synthesizable Fixed Point Adder ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_adds IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_adds;
ARCHITECTURE syn of dp_adds IS
component lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
cin : IN STD_LOGIC ;
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0)
);
end component;
BEGIN
addtwo: lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
lpm_pipeline => pipes,
lpm_type => "LPM_ADD_SUB",
lpm_width => width
)
PORT MAP (
dataa => aa,
datab => bb,
cin => carryin,
clken => enable,
aclr => reset,
clock => sysclk,
result => cc
);
END syn;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/dspba_library_package.vhd | 22 | 1323 | -- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/hcc_mul3236b.vhd | 10 | 2219 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236B.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (behavioral) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236b IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236b;
ARCHITECTURE rtl OF hcc_mul3236b IS
signal aaff, bbff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal mulff, muloutff : STD_LOGIC_VECTOR (2*width DOWNTO 1);
BEGIN
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2*width LOOP
mulff(k) <= '0';
muloutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
mulff <= aaff * bbff;
muloutff <= mulff;
END IF;
END IF;
END PROCESS;
cc <= muloutff;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/dp_log.vhd | 10 | 10521 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** DP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 DP LN() ***
--*** ***
--*** 11/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 27 + 7*DoubleSpeed + ***
--*** RoundConvert*(1+DoubleSpeed) ***
--*** DoubleSpeed = 0, RoundConvert = 0 : 27 ***
--*** DoubleSpeed = 1, RoundConvert = 0 : 34 ***
--*** DoubleSpeed = 0, RoundConvert = 1 : 28 ***
--*** DoubleSpeed = 1, RoundConvert = 1 : 36 ***
--*** ***
--***************************************************
ENTITY dp_log IS
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_log;
ARCHITECTURE rtl OF dp_log IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
constant coredepth : positive := 26 + 7*doublespeed;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component dp_ln_core
GENERIC (
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (53 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component dp_lnnornd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component dp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component dp_lnrndpipe
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: dp_ln_core
GENERIC MAP (doublespeed=>doublespeed,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
gra: IF (roundconvert = 0) GENERATE
norndout: dp_lnnornd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END GENERATE;
grb: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
rndout: dp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END GENERATE;
grc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
rndoutpipe: dp_lnrndpipe
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_rsqrt_s5.vhd | 10 | 93680 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_rsqrt_s5
-- VHDL created on Mon Mar 11 11:49:52 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_rsqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_rsqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid8_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid9_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasM1o2M1_uid10_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasP1o2M1_uid11_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstSel_uid42_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal cstSel_uid42_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid59_invSqrtTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid60_invSqrtTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid61_invSqrtTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q : std_logic_vector (29 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q : std_logic_vector (6 downto 0);
signal ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal exp_uid16_fpInvSqrtTest_in : std_logic_vector (30 downto 0);
signal exp_uid16_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal frac_uid20_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid20_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpInvSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expRExt_uid44_fpInvSqrtTest_a : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_b : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_o : std_logic_vector (8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid53_fpInvSqrtTest_q : std_logic_vector(1 downto 0);
signal signR_uid56_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (23 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_b : std_logic_vector (14 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_in : std_logic_vector (0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expRExt_uid43_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expRExt_uid43_fpInvSqrtTest_b : std_logic_vector (6 downto 0);
signal yAddr_uid35_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid35_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal join_uid41_fpInvSqrtTest_q : std_logic_vector (1 downto 0);
signal excRZero_uid48_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expR_uid45_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expR_uid45_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_invSqrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_invSqrtPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid62_invSqrtPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid62_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal yAddrPEvenOdd_uid36_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_q : std_logic_vector (30 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_invSqrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_invSqrtPolyEval_q : std_logic_vector (32 downto 0);
signal excRConc_uid52_fpInvSqrtTest_q : std_logic_vector (2 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_in : std_logic_vector (29 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_b : std_logic_vector (23 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal R_uid57_fpInvSqrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid31_fpInvSqrtTest(BITSELECT,30)@0
signX_uid31_fpInvSqrtTest_in <= a;
signX_uid31_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_in(31 downto 31);
--cstAllZWE_uid9_fpInvSqrtTest(CONSTANT,8)
cstAllZWE_uid9_fpInvSqrtTest_q <= "00000000";
--exp_uid16_fpInvSqrtTest(BITSELECT,15)@0
exp_uid16_fpInvSqrtTest_in <= a(30 downto 0);
exp_uid16_fpInvSqrtTest_b <= exp_uid16_fpInvSqrtTest_in(30 downto 23);
--expXIsZero_uid17_fpInvSqrtTest(LOGICAL,16)@0
expXIsZero_uid17_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsZero_uid17_fpInvSqrtTest_b <= cstAllZWE_uid9_fpInvSqrtTest_q;
expXIsZero_uid17_fpInvSqrtTest_q <= "1" when expXIsZero_uid17_fpInvSqrtTest_a = expXIsZero_uid17_fpInvSqrtTest_b else "0";
--signR_uid56_fpInvSqrtTest(LOGICAL,55)@0
signR_uid56_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
signR_uid56_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
signR_uid56_fpInvSqrtTest_q <= signR_uid56_fpInvSqrtTest_a and signR_uid56_fpInvSqrtTest_b;
--ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c(DELAY,139)@0
ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid56_fpInvSqrtTest_q, xout => ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable(LOGICAL,182)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor(LOGICAL,183)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q <= not (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a or ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b);
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top(CONSTANT,179)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp(LOGICAL,180)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a = ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg(REG,181)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena(REG,184)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd(LOGICAL,185)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a and ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b;
--cstAllOWE_uid6_fpInvSqrtTest(CONSTANT,5)
cstAllOWE_uid6_fpInvSqrtTest_q <= "11111111";
--expRExt_uid43_fpInvSqrtTest(BITSELECT,42)@0
expRExt_uid43_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b;
expRExt_uid43_fpInvSqrtTest_b <= expRExt_uid43_fpInvSqrtTest_in(7 downto 1);
--ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b(DELAY,116)@0
ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => expRExt_uid43_fpInvSqrtTest_b, xout => ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cst3BiasM1o2M1_uid10_fpInvSqrtTest(CONSTANT,9)
cst3BiasM1o2M1_uid10_fpInvSqrtTest_q <= "10111101";
--cst3BiasP1o2M1_uid11_fpInvSqrtTest(CONSTANT,10)
cst3BiasP1o2M1_uid11_fpInvSqrtTest_q <= "10111110";
--cstAllZWF_uid7_fpInvSqrtTest(CONSTANT,6)
cstAllZWF_uid7_fpInvSqrtTest_q <= "00000000000000000000000";
--frac_uid20_fpInvSqrtTest(BITSELECT,19)@0
frac_uid20_fpInvSqrtTest_in <= a(22 downto 0);
frac_uid20_fpInvSqrtTest_b <= frac_uid20_fpInvSqrtTest_in(22 downto 0);
--fracXIsZero_uid21_fpInvSqrtTest(LOGICAL,20)@0
fracXIsZero_uid21_fpInvSqrtTest_a <= frac_uid20_fpInvSqrtTest_b;
fracXIsZero_uid21_fpInvSqrtTest_b <= cstAllZWF_uid7_fpInvSqrtTest_q;
fracXIsZero_uid21_fpInvSqrtTest_q <= "1" when fracXIsZero_uid21_fpInvSqrtTest_a = fracXIsZero_uid21_fpInvSqrtTest_b else "0";
--evenOddExp_uid33_fpInvSqrtTest(BITSELECT,32)@0
evenOddExp_uid33_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b(0 downto 0);
evenOddExp_uid33_fpInvSqrtTest_b <= evenOddExp_uid33_fpInvSqrtTest_in(0 downto 0);
--join_uid41_fpInvSqrtTest(BITJOIN,40)@0
join_uid41_fpInvSqrtTest_q <= fracXIsZero_uid21_fpInvSqrtTest_q & evenOddExp_uid33_fpInvSqrtTest_b;
--cstSel_uid42_fpInvSqrtTest(MUX,41)@0
cstSel_uid42_fpInvSqrtTest_s <= join_uid41_fpInvSqrtTest_q;
cstSel_uid42_fpInvSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE cstSel_uid42_fpInvSqrtTest_s IS
WHEN "00" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "01" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasM1o2M1_uid10_fpInvSqrtTest_q;
WHEN "10" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "11" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN OTHERS => cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expRExt_uid44_fpInvSqrtTest(SUB,43)@1
expRExt_uid44_fpInvSqrtTest_a <= STD_LOGIC_VECTOR("0" & cstSel_uid42_fpInvSqrtTest_q);
expRExt_uid44_fpInvSqrtTest_b <= STD_LOGIC_VECTOR("00" & ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q);
expRExt_uid44_fpInvSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid44_fpInvSqrtTest_a) - UNSIGNED(expRExt_uid44_fpInvSqrtTest_b));
expRExt_uid44_fpInvSqrtTest_q <= expRExt_uid44_fpInvSqrtTest_o(8 downto 0);
--expR_uid45_fpInvSqrtTest(BITSELECT,44)@1
expR_uid45_fpInvSqrtTest_in <= expRExt_uid44_fpInvSqrtTest_q(7 downto 0);
expR_uid45_fpInvSqrtTest_b <= expR_uid45_fpInvSqrtTest_in(7 downto 0);
--InvExpXIsZero_uid49_fpInvSqrtTest(LOGICAL,48)@0
InvExpXIsZero_uid49_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
InvExpXIsZero_uid49_fpInvSqrtTest_q <= not InvExpXIsZero_uid49_fpInvSqrtTest_a;
--xRegNeg_uid50_fpInvSqrtTest(LOGICAL,49)@0
xRegNeg_uid50_fpInvSqrtTest_a <= InvExpXIsZero_uid49_fpInvSqrtTest_q;
xRegNeg_uid50_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
xRegNeg_uid50_fpInvSqrtTest_q <= xRegNeg_uid50_fpInvSqrtTest_a and xRegNeg_uid50_fpInvSqrtTest_b;
--InvFracXIsZero_uid23_fpInvSqrtTest(LOGICAL,22)@0
InvFracXIsZero_uid23_fpInvSqrtTest_a <= fracXIsZero_uid21_fpInvSqrtTest_q;
InvFracXIsZero_uid23_fpInvSqrtTest_q <= not InvFracXIsZero_uid23_fpInvSqrtTest_a;
--expXIsMax_uid19_fpInvSqrtTest(LOGICAL,18)@0
expXIsMax_uid19_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsMax_uid19_fpInvSqrtTest_b <= cstAllOWE_uid6_fpInvSqrtTest_q;
expXIsMax_uid19_fpInvSqrtTest_q <= "1" when expXIsMax_uid19_fpInvSqrtTest_a = expXIsMax_uid19_fpInvSqrtTest_b else "0";
--exc_N_uid24_fpInvSqrtTest(LOGICAL,23)@0
exc_N_uid24_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_b <= InvFracXIsZero_uid23_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_q <= exc_N_uid24_fpInvSqrtTest_a and exc_N_uid24_fpInvSqrtTest_b;
--xNOxRNeg_uid51_fpInvSqrtTest(LOGICAL,50)@0
xNOxRNeg_uid51_fpInvSqrtTest_a <= exc_N_uid24_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_b <= xRegNeg_uid50_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_a or xNOxRNeg_uid51_fpInvSqrtTest_b;
--exc_I_uid22_fpInvSqrtTest(LOGICAL,21)@0
exc_I_uid22_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_b <= fracXIsZero_uid21_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_q <= exc_I_uid22_fpInvSqrtTest_a and exc_I_uid22_fpInvSqrtTest_b;
--InvSignX_uid47_fpInvSqrtTest(LOGICAL,46)@0
InvSignX_uid47_fpInvSqrtTest_a <= signX_uid31_fpInvSqrtTest_b;
InvSignX_uid47_fpInvSqrtTest_q <= not InvSignX_uid47_fpInvSqrtTest_a;
--excRZero_uid48_fpInvSqrtTest(LOGICAL,47)@0
excRZero_uid48_fpInvSqrtTest_a <= InvSignX_uid47_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_b <= exc_I_uid22_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_q <= excRZero_uid48_fpInvSqrtTest_a and excRZero_uid48_fpInvSqrtTest_b;
--excRConc_uid52_fpInvSqrtTest(BITJOIN,51)@0
excRConc_uid52_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_q & expXIsZero_uid17_fpInvSqrtTest_q & excRZero_uid48_fpInvSqrtTest_q;
--reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0(REG,83)@0
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= excRConc_uid52_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid53_fpInvSqrtTest(LOOKUP,52)@1
outMuxSelEnc_uid53_fpInvSqrtTest: PROCESS (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "100" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "110" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "111" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid53_fpInvSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid55_fpInvSqrtTest(MUX,54)@1
expRPostExc_uid55_fpInvSqrtTest_s <= outMuxSelEnc_uid53_fpInvSqrtTest_q;
expRPostExc_uid55_fpInvSqrtTest: PROCESS (expRPostExc_uid55_fpInvSqrtTest_s, en, cstAllZWE_uid9_fpInvSqrtTest_q, expR_uid45_fpInvSqrtTest_b, cstAllOWE_uid6_fpInvSqrtTest_q, cstAllOWE_uid6_fpInvSqrtTest_q)
BEGIN
CASE expRPostExc_uid55_fpInvSqrtTest_s IS
WHEN "00" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllZWE_uid9_fpInvSqrtTest_q;
WHEN "01" => expRPostExc_uid55_fpInvSqrtTest_q <= expR_uid45_fpInvSqrtTest_b;
WHEN "10" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN "11" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN OTHERS => expRPostExc_uid55_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg(DELAY,173)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid55_fpInvSqrtTest_q, xout => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt(COUNTER,175)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg(REG,176)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux(MUX,177)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem(DUALMEM,174)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid8_fpInvSqrtTest(CONSTANT,7)
cstNaNWF_uid8_fpInvSqrtTest_q <= "00000000000000000000001";
--yAddr_uid35_fpInvSqrtTest(BITSELECT,34)@0
yAddr_uid35_fpInvSqrtTest_in <= frac_uid20_fpInvSqrtTest_b;
yAddr_uid35_fpInvSqrtTest_b <= yAddr_uid35_fpInvSqrtTest_in(22 downto 15);
--yAddrPEvenOdd_uid36_fpInvSqrtTest(BITJOIN,35)@0
yAddrPEvenOdd_uid36_fpInvSqrtTest_q <= evenOddExp_uid33_fpInvSqrtTest_b & yAddr_uid35_fpInvSqrtTest_b;
--reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0(REG,84)@0
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= yAddrPEvenOdd_uid36_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_invSqrtTabGen_lutmem(DUALMEM,82)@1
memoryC2_uid61_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_ab <= reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q;
memoryC2_uid61_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC2_uid61_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_invSqrtTabGen_lutmem_iq,
address_a => memoryC2_uid61_invSqrtTabGen_lutmem_aa,
data_a => memoryC2_uid61_invSqrtTabGen_lutmem_ia
);
memoryC2_uid61_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC2_uid61_invSqrtTabGen_lutmem_q <= memoryC2_uid61_invSqrtTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1(REG,86)@3
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= memoryC2_uid61_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg(DELAY,172)
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid20_fpInvSqrtTest_b, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a(DELAY,109)@0
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid37_fpInvSqrtTest(BITSELECT,36)@3
yPPolyEval_uid37_fpInvSqrtTest_in <= ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q(14 downto 0);
yPPolyEval_uid37_fpInvSqrtTest_b <= yPPolyEval_uid37_fpInvSqrtTest_in(14 downto 0);
--yT1_uid62_invSqrtPolyEval(BITSELECT,61)@3
yT1_uid62_invSqrtPolyEval_in <= yPPolyEval_uid37_fpInvSqrtTest_b;
yT1_uid62_invSqrtPolyEval_b <= yT1_uid62_invSqrtPolyEval_in(14 downto 3);
--reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0(REG,85)@3
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= yT1_uid62_invSqrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_invSqrtPolyEval(MULT,74)@4
prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_b);
prodXY_uid75_pT1_uid63_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_q;
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in(23 downto 11);
--highBBits_uid65_invSqrtPolyEval(BITSELECT,64)@7
highBBits_uid65_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b;
highBBits_uid65_invSqrtPolyEval_b <= highBBits_uid65_invSqrtPolyEval_in(12 downto 1);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a(DELAY,160)@1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid60_invSqrtTabGen_lutmem(DUALMEM,81)@4
memoryC1_uid60_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q;
memoryC1_uid60_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC1_uid60_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_invSqrtTabGen_lutmem_iq,
address_a => memoryC1_uid60_invSqrtTabGen_lutmem_aa,
data_a => memoryC1_uid60_invSqrtTabGen_lutmem_ia
);
memoryC1_uid60_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC1_uid60_invSqrtTabGen_lutmem_q <= memoryC1_uid60_invSqrtTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0(REG,88)@6
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= memoryC1_uid60_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_invSqrtPolyEval(ADD,65)@7
sumAHighB_uid66_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q(20)) & reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q);
sumAHighB_uid66_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_invSqrtPolyEval_b(11)) & highBBits_uid65_invSqrtPolyEval_b);
sumAHighB_uid66_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid66_invSqrtPolyEval_b));
sumAHighB_uid66_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_o(21 downto 0);
--lowRangeB_uid64_invSqrtPolyEval(BITSELECT,63)@7
lowRangeB_uid64_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b(0 downto 0);
lowRangeB_uid64_invSqrtPolyEval_b <= lowRangeB_uid64_invSqrtPolyEval_in(0 downto 0);
--s1_uid64_uid67_invSqrtPolyEval(BITJOIN,66)@7
s1_uid64_uid67_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_q & lowRangeB_uid64_invSqrtPolyEval_b;
--reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1(REG,90)@7
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= s1_uid64_uid67_invSqrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor(LOGICAL,207)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a or ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b);
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg(REG,205)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena(REG,208)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd(LOGICAL,209)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg(DELAY,199)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid37_fpInvSqrtTest_b, xout => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt(COUNTER,201)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg(REG,202)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux(MUX,203)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem(DUALMEM,200)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0(REG,89)@7
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_invSqrtPolyEval(MULT,77)@8
prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_a),16)) * SIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_b);
prodXY_uid78_pT2_uid69_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_q;
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in(37 downto 14);
--highBBits_uid71_invSqrtPolyEval(BITSELECT,70)@11
highBBits_uid71_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b;
highBBits_uid71_invSqrtPolyEval_b <= highBBits_uid71_invSqrtPolyEval_in(23 downto 2);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor(LOGICAL,196)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q <= not (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a or ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top(CONSTANT,192)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q <= "0100";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp(LOGICAL,193)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q <= "1" when ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a = ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b else "0";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg(REG,194)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena(REG,197)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd(LOGICAL,198)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a and ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg(DELAY,186)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt(COUNTER,188)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg(REG,189)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux(MUX,190)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem(DUALMEM,187)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid59_invSqrtTabGen_lutmem(DUALMEM,80)@8
memoryC0_uid59_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q;
memoryC0_uid59_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 9,
numwords_a => 512,
width_b => 30,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC0_uid59_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_invSqrtTabGen_lutmem_iq,
address_a => memoryC0_uid59_invSqrtTabGen_lutmem_aa,
data_a => memoryC0_uid59_invSqrtTabGen_lutmem_ia
);
memoryC0_uid59_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC0_uid59_invSqrtTabGen_lutmem_q <= memoryC0_uid59_invSqrtTabGen_lutmem_iq(29 downto 0);
--reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0(REG,92)@10
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= memoryC0_uid59_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_invSqrtPolyEval(ADD,71)@11
sumAHighB_uid72_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q(29)) & reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q);
sumAHighB_uid72_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid71_invSqrtPolyEval_b(21)) & highBBits_uid71_invSqrtPolyEval_b);
sumAHighB_uid72_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid72_invSqrtPolyEval_b));
sumAHighB_uid72_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_o(30 downto 0);
--lowRangeB_uid70_invSqrtPolyEval(BITSELECT,69)@11
lowRangeB_uid70_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b(1 downto 0);
lowRangeB_uid70_invSqrtPolyEval_b <= lowRangeB_uid70_invSqrtPolyEval_in(1 downto 0);
--s2_uid70_uid73_invSqrtPolyEval(BITJOIN,72)@11
s2_uid70_uid73_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_q & lowRangeB_uid70_invSqrtPolyEval_b;
--fxpInvSqrtRes_uid39_fpInvSqrtTest(BITSELECT,38)@11
fxpInvSqrtRes_uid39_fpInvSqrtTest_in <= s2_uid70_uid73_invSqrtPolyEval_q(29 downto 0);
fxpInvSqrtRes_uid39_fpInvSqrtTest_b <= fxpInvSqrtRes_uid39_fpInvSqrtTest_in(29 downto 6);
--fxpInverseResFrac_uid46_fpInvSqrtTest(BITSELECT,45)@11
fxpInverseResFrac_uid46_fpInvSqrtTest_in <= fxpInvSqrtRes_uid39_fpInvSqrtTest_b(22 downto 0);
fxpInverseResFrac_uid46_fpInvSqrtTest_b <= fxpInverseResFrac_uid46_fpInvSqrtTest_in(22 downto 0);
--ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b(DELAY,131)@1
ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => outMuxSelEnc_uid53_fpInvSqrtTest_q, xout => ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid54_fpInvSqrtTest(MUX,53)@11
fracRPostExc_uid54_fpInvSqrtTest_s <= ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q;
fracRPostExc_uid54_fpInvSqrtTest: PROCESS (fracRPostExc_uid54_fpInvSqrtTest_s, en, cstAllZWF_uid7_fpInvSqrtTest_q, fxpInverseResFrac_uid46_fpInvSqrtTest_b, cstAllZWF_uid7_fpInvSqrtTest_q, cstNaNWF_uid8_fpInvSqrtTest_q)
BEGIN
CASE fracRPostExc_uid54_fpInvSqrtTest_s IS
WHEN "00" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "01" => fracRPostExc_uid54_fpInvSqrtTest_q <= fxpInverseResFrac_uid46_fpInvSqrtTest_b;
WHEN "10" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "11" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstNaNWF_uid8_fpInvSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid54_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid57_fpInvSqrtTest(BITJOIN,56)@11
R_uid57_fpInvSqrtTest_q <= ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q & fracRPostExc_uid54_fpInvSqrtTest_q;
--xOut(GPOUT,4)@11
q <= R_uid57_fpInvSqrtTest_q;
end normal;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/hcc_mullongs.vhd | 10 | 5869 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULLONGS.VHD ***
--*** ***
--*** Function: 3 pipeline stage fixed point ***
--*** (long, signed & unsigned) ***
--*** synthesizable ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mullongs IS
GENERIC (unsigned : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_mullongs;
ARCHITECTURE syn OF hcc_mullongs IS
signal mulnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
gsa: IF (unsigned = 0) GENERATE
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 32,
width_b => 32,
width_result => 64
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulnode
);
END GENERATE;
gua: IF (unsigned = 1) GENERATE
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 32,
width_b => 32,
width_result => 64
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulnode
);
END GENERATE;
mulcc <= mulnode(32 DOWNTO 1);
END syn;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/dp_fabs.vhd | 10 | 3182 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_fabs;
ARCHITECTURE rtl OF dp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/dp_fabs.vhd | 10 | 3182 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_fabs;
ARCHITECTURE rtl OF dp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/hcc_castltod.vhd | 10 | 3294 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOD.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Double ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castltod;
ARCHITECTURE rtl OF hcc_castltod IS
signal fit : STD_LOGIC;
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
yvector(77 DOWNTO 73) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
yvector(77 DOWNTO 73) <= "00000";
END GENERATE;
yvector(72 DOWNTO 41) <= aa;
gza: FOR k IN 14 TO 40 GENERATE
yvector(k) <= '0';
END GENERATE;
yvector(13 DOWNTO 1) <= conv_std_logic_vector (1054,13); -- account for 31bit right shift
core: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
| mit |
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