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lxp32/lxp32-cpu | rtl/lxp32_mul_seq.vhd | 2 | 1633 | ---------------------------------------------------------------------
-- Sequential multiplier
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- The smallest possible multiplier. Implemented using
-- an accumulator. One multiplication takes 34 cycles.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_mul_seq is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ce_i: in std_logic;
op1_i: in std_logic_vector(31 downto 0);
op2_i: in std_logic_vector(31 downto 0);
ce_o: out std_logic;
result_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_mul_seq is
signal reg1: unsigned(op1_i'range);
signal reg2: unsigned(op2_i'range);
signal pp: unsigned(31 downto 0);
signal acc_sum: unsigned(31 downto 0);
signal cnt: integer range 0 to 32:=0;
signal ceo: std_logic:='0';
begin
pp<=reg1 when reg2(0)='1' else (others=>'0');
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
ceo<='0';
cnt<=0;
reg1<=(others=>'-');
reg2<=(others=>'-');
acc_sum<=(others=>'-');
else
if cnt=1 then
ceo<='1';
else
ceo<='0';
end if;
if ce_i='1' then
cnt<=32;
reg1<=unsigned(op1_i);
reg2<=unsigned(op2_i);
acc_sum<=(others=>'0');
else
acc_sum<=acc_sum+pp;
reg1<=reg1(reg1'high-1 downto 0)&"0";
reg2<="0"®2(reg2'high downto 1);
if cnt>0 then
cnt<=cnt-1;
end if;
end if;
end if;
end if;
end process;
result_o<=std_logic_vector(acc_sum);
ce_o<=ceo;
end architecture;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/apbps2.vhd | 2 | 13132 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbps2
-- File: apbps2.vhd
-- Author: Marcus Hellqvist, Jiri Gaisler
-- Description: PS/2 keyboard interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity apbps2 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 1
);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end;
architecture rtl of apbps2 is
constant fifosize : integer := 16;
type rxstates is (idle,start,data,parity,stop);
type txstates is (idle,waitrequest,start,data,parity,stop,ack);
type fifotype is array(0 to fifosize-1) of std_logic_vector(7 downto 0);
type ps2_regs is record
-- status reg
data_ready : std_ulogic; -- data ready
parity_error : std_ulogic; -- parity carry out/ error bit
frame_error : std_ulogic; -- frame error when receiving
kb_inh : std_ulogic; -- keyboard inhibit
rbf : std_ulogic; -- receiver buffer full
tbf : std_ulogic; -- transmitter buffer full
rcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
tcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
-- control reg
rx_en : std_ulogic; -- receive enable
tx_en : std_ulogic; -- transmit enable
rx_irq_en : std_ulogic; -- keyboard interrupt enable
tx_irq_en : std_ulogic; -- transmit interrupt enable
-- others
tx_act : std_ulogic; -- tx active
rxdf : std_logic_vector(4 downto 0); -- rx data filter
rxcf : std_logic_vector(4 downto 0); -- rx clock filter
rx_irq : std_ulogic; -- keyboard interrupt
tx_irq : std_ulogic; -- transmit interrupt
rxfifo : fifotype; -- fifo with 16 bytes
rraddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
rwaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
rxstate : rxstates;
txfifo : fifotype; -- fifo with 16 bytes
traddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
twaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
txstate : txstates;
ps2_clk_syn : std_ulogic; -- ps2 clock synchronized
ps2_data_syn : std_ulogic; -- ps2 data synchronized
ps2_clk_fall : std_ulogic; -- ps2 clock falling edge detector
rshift : std_logic_vector(7 downto 0); -- shift register
rpar : std_ulogic; -- parity check bit
tshift : std_logic_vector(9 downto 0); -- shift register
tpar : std_ulogic; -- transmit parity bit
ps2clk : std_ulogic; -- ps2 clock
ps2data : std_ulogic; -- ps2 data
ps2clkoe : std_ulogic; -- ps2 clock output enable
ps2dataoe : std_ulogic; -- ps2 data output enable
timer : std_logic_vector(13 downto 0); -- timer
reload : std_logic_vector(13 downto 0); -- reload register
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBPS2, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
signal r, rin : ps2_regs;
signal ps2_clk, ps2_data : std_ulogic;
begin
ps2_op : process(r, rst, ps2_clk, ps2_data,apbi)
variable v : ps2_regs;
variable rdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r;
rdata := (others => '0'); v.data_ready := '0'; irq := (others => '0'); irq(pirq) := r.rx_irq or r.tx_irq;
v.rx_irq := '0'; v.tx_irq := '0'; v.rbf := r.rcnt(log2x(fifosize)); v.tbf := r.tcnt(log2x(fifosize));
if r.rcnt /= rcntzero then v.data_ready := '1'; end if;
-- Synchronize and filter ps2 input
v.rxdf(0) := ps2_data; v.rxdf(4 downto 1) := r.rxdf(3 downto 0);
v.rxcf(0) := ps2_clk; v.rxcf(4 downto 1) := r.rxcf(3 downto 0);
if (r.rxdf(4) & r.rxdf(4) & r.rxdf(4) & r.rxdf(4)) = r.rxdf(3 downto 0) then
v.ps2_data_syn := r.rxdf(4);
end if;
if (r.rxcf(4) & r.rxcf(4) & r.rxcf(4) & r.rxcf(4)) = r.rxcf(3 downto 0) then
v.ps2_clk_syn := r.rxcf(4);
end if;
if (v.ps2_clk_syn /= r.ps2_clk_syn) and (v.ps2_clk_syn = '0') then
v.ps2_clk_fall := '1';
else
v.ps2_clk_fall := '0';
end if;
-- read registers
case apbi.paddr(3 downto 2) is
when "00" =>
rdata(7 downto 0) := r.rxfifo(conv_integer(r.rraddr));
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
if r.rcnt /= rcntzero then
v.rxfifo(conv_integer(r.rraddr)) := (others => '0');
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "01" =>
rdata(27 + log2x(fifosize) downto 27) := r.rcnt;
rdata(22 + log2x(fifosize) downto 22) := r.tcnt;
rdata(5 downto 0) := r.tbf & r.rbf & r.kb_inh & r.frame_error & r.parity_error & r.data_ready;
when "10" =>
rdata(3 downto 0) := r.tx_irq_en & r.rx_irq_en & r.tx_en & r.rx_en;
when others =>
if fixed = 0 then rdata(13 downto 0) := r.reload; end if;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
if r.tcnt(log2x(fifosize)) = '0' then
v.txfifo(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
v.twaddr := r.twaddr + 1; v.tcnt := r.tcnt + 1;
end if;
when "01" =>
v.kb_inh := apbi.pwdata(3);
v.frame_error := apbi.pwdata(2);
v.parity_error := apbi.pwdata(1);
when "10" =>
v.tx_irq_en := apbi.pwdata(3);
v.rx_irq_en := apbi.pwdata(2);
v.tx_en := apbi.pwdata(1);
v.rx_en := apbi.pwdata(0);
when "11" =>
if fixed = 0 then
v.reload := apbi.pwdata(13 downto 0);
end if;
when others =>
null;
end case;
end if;
case r.txstate is
when idle =>
if r.tx_en = '1' and r.tcnt /= rcntzero then
v.ps2clk := '0'; v.ps2clkoe := '0'; v.tx_act := '1';
v.ps2data := '1'; v.ps2dataoe := '0'; v.txstate := waitrequest;
end if;
when waitrequest =>
v.timer := r.timer - 1;
if (v.timer(13) and not r.timer(13)) = '1' then
if fixed = 1 then v.timer := conv_std_logic_vector(fKHz/10,14);
else v.timer := r.reload; end if;
v.ps2clk := '1'; v.ps2data := '0'; v.txstate := start;
end if;
when start =>
v.ps2clkoe := '1';
v.tshift := "10" & r.txfifo(conv_integer(r.traddr));
v.traddr := r.traddr + 1; v.tcnt := r.tcnt - 1;
v.tpar := '1';
v.txstate := data;
when data =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tshift(0);
v.tpar := r.tpar xor r.tshift(0);
v.tshift := '1' & r.tshift(9 downto 1);
if v.tshift = "1111111110" then v.txstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tpar; v.txstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
v.ps2data := '1'; v.txstate := ack;
end if;
when ack =>
v.ps2dataoe := '1';
if r.ps2_clk_fall = '1' and r.ps2_data_syn = '0'then
v.ps2data := '1'; v.ps2dataoe := '0'; v.tx_irq := r.tx_irq_en;
v.txstate := idle; v.tx_act := '0';
end if;
end case;
-- receiver state machine
case r.rxstate is
when idle =>
if (r.rx_en and not r.tx_act) = '1' then
v.rshift := (others => '1'); v.rxstate := start;
end if;
when start =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '0' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rxstate := data; v.rpar := '0';
v.parity_error := '0'; v.frame_error := '0';
else v.rxstate := idle; end if;
end if;
when data =>
if r.ps2_clk_fall = '1' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rpar := r.rpar xor r.ps2_data_syn;
if r.rshift(0) = '0' then v.rxstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.parity_error := r.rpar xor (not r.ps2_data_syn);
v.rxstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '1' then
v.rx_irq := r.rx_irq_en; v.rxstate := idle;
if (r.rbf or r.parity_error) = '0' then
v.rxfifo(conv_integer(r.rwaddr)) := r.rshift(7 downto 0);
v.rwaddr := r.rwaddr + 1; v.rcnt := r.rcnt + 1;
end if;
else v.frame_error := '1'; v.rxstate := idle; end if;
end if;
end case;
-- keyboard inhibit / high impedance
if v.tx_act = '0' then
if r.rbf = '1' then
v.kb_inh := '1'; v.ps2clk := '0'; v.ps2data := '1';
v.ps2dataoe := '0'; v.ps2clkoe := '0';
else
v.ps2clk := '1'; v.ps2data := '1'; v.ps2dataoe := '1';
v.ps2clkoe := '1';
end if;
end if;
if r.tx_act = '1' then
v.rxstate := idle;
end if;
-- reset operations
if rst = '0' then
v.data_ready := '0'; v.kb_inh := '0'; v.parity_error := '0';
v.frame_error := '0'; v.rx_en := '0'; v.tx_act := '0';
v.tx_en := '0'; v.rx_irq := '0'; v.tx_irq := '0';
v.ps2_clk_fall := '0'; v.ps2_clk_syn := '0'; v.ps2_data_syn := '0';
v.rshift := (others => '0'); v.rxstate := idle; v.txstate := idle;
v.rraddr := (others => '0'); v.rwaddr := (others => '0');
v.rcnt := (others => '0'); v.traddr := (others => '0');
v.twaddr := (others => '0'); v.tcnt := (others => '0');
v.tshift := (others => '0'); v.tpar := '0';
v.timer := conv_std_logic_vector(fKHz/10,14);
end if;
-- update registers
rin <= v;
-- drive outputs
apbo.prdata <= rdata;
apbo.pirq <= irq;
apbo.pindex <= pindex;
ps2o.ps2_clk_o <= r.ps2clk;
ps2o.ps2_clk_oe <= r.ps2clkoe;
ps2o.ps2_data_o <= r.ps2data;
ps2o.ps2_data_oe <= r.ps2dataoe;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
ps2_data <= to_x01(ps2i.ps2_data_i);
ps2_clk <= to_x01(ps2i.ps2_clk_i);
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbps2_" & tost(pindex) & ": APB PS2 interface rev 0, irq "
& tost(pirq));
-- pragma translate_on
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/tech/ec/orca/mem3.vhd | 5 | 6709 | --
----- package mem3 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
PACKAGE mem3 IS
TYPE mem_type_5 IS array (Integer range <>) OF std_logic_vector(17 downto 0);
TYPE mem_type_6 IS array (Integer range <>) OF std_logic_vector(15 downto 0);
FUNCTION hex2bin (hex: character) RETURN std_logic_vector;
FUNCTION str3_slv12 (hex: string) RETURN std_logic_vector;
FUNCTION data2data (data_w: integer) RETURN integer;
FUNCTION data2addr_w (data_w: integer) RETURN integer;
FUNCTION data2data_w (data_w: integer) RETURN integer;
FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector;
FUNCTION init_ram1 (hex: string) RETURN mem_type_6;
FUNCTION str2slv (str: in string) RETURN std_logic_vector;
FUNCTION Valid_Address (IN_ADDR : in std_logic_vector) return boolean;
END mem3;
PACKAGE BODY mem3 IS
FUNCTION hex2bin (hex: character) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector (3 downto 0);
BEGIN
CASE hex IS
WHEN '0' =>
result := "0000";
WHEN '1' =>
result := "0001";
WHEN '2' =>
result := "0010";
WHEN '3' =>
result := "0011";
WHEN '4' =>
result := "0100";
WHEN '5' =>
result := "0101";
WHEN '6' =>
result := "0110";
WHEN '7' =>
result := "0111";
WHEN '8' =>
result := "1000";
WHEN '9' =>
result := "1001";
WHEN 'A'|'a' =>
result := "1010";
WHEN 'B'|'b' =>
result := "1011";
WHEN 'C'|'c' =>
result := "1100";
WHEN 'D'|'d' =>
result := "1101";
WHEN 'E'|'e' =>
result := "1110";
WHEN 'F'|'f' =>
result := "1111";
WHEN 'X'|'x' =>
result := "XXXX";
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION str5_slv18 (s : string(5 downto 1)) return std_logic_vector is
VARIABLE result : std_logic_vector(17 downto 0);
BEGIN
FOR i in 0 to 3 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
END LOOP;
result(17 downto 16) := hex2bin(s(5))(1 downto 0);
RETURN result;
END;
FUNCTION str4_slv16 (s : string(4 downto 1)) return std_logic_vector is
VARIABLE result : std_logic_vector(15 downto 0);
BEGIN
FOR i in 0 to 3 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
END LOOP;
RETURN result;
END;
FUNCTION str3_slv12 (hex: string) return std_logic_vector is
VARIABLE result : std_logic_vector(11 downto 0);
BEGIN
FOR i in 0 to 2 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(hex(i+1));
END LOOP;
RETURN result;
END;
FUNCTION data2addr_w (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 13;
WHEN 2 =>
result := 12;
WHEN 4 =>
result := 11;
WHEN 9 =>
result := 10;
WHEN 18 =>
result := 9;
WHEN 36 =>
result := 8;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION data2data_w (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 1;
WHEN 2 =>
result := 2;
WHEN 4 =>
result := 4;
WHEN 9 =>
result := 9;
WHEN 18 =>
result := 18;
WHEN 36 =>
result := 18;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION data2data (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 8;
WHEN 2 =>
result := 4;
WHEN 4 =>
result := 2;
WHEN 9 =>
result := 36864;
WHEN 18 =>
result := 36864;
WHEN 36 =>
result := 36864;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector IS
CONSTANT length : integer := hex'length;
VARIABLE result1 : mem_type_5 (0 to ((length/5)-1));
VARIABLE result : std_logic_vector(((length*18)/5)-1 downto 0);
BEGIN
FOR i in 0 to ((length/5)-1) LOOP
result1(i) := str5_slv18(hex((i+1)*5 downto (i*5)+1));
END LOOP;
IF (DATA_WIDTH_A >= 9 and DATA_WIDTH_B >= 9) THEN
FOR j in 0 to 511 LOOP
result(((j*18) + 17) downto (j*18)) := result1(j)(17 downto 0);
END LOOP;
ELSE
FOR j in 0 to 511 LOOP
result(((j*18) + 7) downto (j*18)) := result1(j)(7 downto 0);
result((j*18) + 8) := '0';
result(((j*18) + 16) downto ((j*18) + 9)) := result1(j)(15 downto 8);
result((j*18) + 17) := '0';
END LOOP;
END IF;
RETURN result;
END;
FUNCTION init_ram1 (hex: string) RETURN mem_type_6 IS
CONSTANT length : integer := hex'length;
VARIABLE result : mem_type_6 (0 to ((length/4)-1));
BEGIN
FOR i in 0 to ((length/4)-1) LOOP
result(i) := str4_slv16(hex((i+1)*4 downto (i*4)+1));
END LOOP;
RETURN result;
END;
-- String to std_logic_vector
FUNCTION str2slv (
str : in string
) return std_logic_vector is
variable j : integer := str'length;
variable slv : std_logic_vector (str'length downto 1);
begin
for i in str'low to str'high loop
case str(i) is
when '0' => slv(j) := '0';
when '1' => slv(j) := '1';
when 'X' => slv(j) := 'X';
when 'U' => slv(j) := 'U';
when others => slv(j) := 'X';
end case;
j := j - 1;
end loop;
return slv;
end str2slv;
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
END mem3 ;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/snps/dw02/comp/DW02_components.vhd | 6 | 1601 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package DW02_components is
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
CLK : in std_logic; -- clock for the stage registers.
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end DW02_components;
-- pragma translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity DW02_mult_2_stage is
generic( A_width: POSITIVE;
B_width: POSITIVE);
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end;
architecture behav of DW02_mult_2_stage is
signal P_i : std_logic_vector(A_width+B_width-1 downto 0);
begin
comb : process(A, B, TC)
begin
if notx(A) and notx(B) then
if TC = '1' then
P_i <= signed(A) * signed(B);
else
P_i <= unsigned(A) * unsigned(B);
end if;
else
P_i <= (others => 'X');
end if;
end process;
reg : process(CLK)
begin
if rising_edge(CLK) then
PRODUCT <= P_i;
end if;
end process;
end;
-- pragma translate_on
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/axcelerator/usbhc_axcelerator.vhd | 2 | 19626 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: usbhc_axcelerator
-- File: usbhc_axcelerator.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: tech wrapper for axcelerator usbhc netlist
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axcelerator;
use axcelerator.all;
library techmap;
use techmap.usbhc_axceleratorpkg.all;
entity usbhc_axcelerator is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end usbhc_axcelerator;
architecture rtl of usbhc_axcelerator is
begin
-----------------------------------------------------------------------------
-- Howto add netlist maps:
-- First check the different combination of generics below. If your
-- configuration is not available then add a new one named comb<X+1> (where
-- X is the value of the last combination defined below) by simply copy
-- pasting one exicisting combination and changing the generics and component
-- name. Then add a component decleration for that configuration in the file
-- usbhc_axceleratorpkg.vhd by simply copy pasting the port decleration from
-- the entity above and replacing n_cc, uhcgen, and nports with their actual
-- values. Also add the combination of genercis as valid in the function
-- valid_comb at the bottom of the file usbhc_axceleratorpkg.vhd
-----------------------------------------------------------------------------
comb0 : if nports = 1 and
ehcgen = 0 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_axcelerator_comb0
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb0;
comb1 : if nports = 1 and
ehcgen = 1 and
uhcgen = 0 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_axcelerator_comb1
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb1;
comb2 : if nports = 1 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_axcelerator_comb2
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb2;
comb3 : if nports = 2 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 2 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_axcelerator_comb3
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb3;
-- pragma translate_off
nomap : if not valid_comb(nports,ehcgen,uhcgen,n_cc,n_pcc,prr,portroute1,
portroute2,endian_conv,be_regs,be_desc,uhcblo,bwrd,
utm_type,vbusconf,ramtest,urst_time,oepol) generate
err : process
begin
assert false report "ERROR : Can't map a netlist for this combination" &
"of generics"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end rtl;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/hynix/ddr2/HY5PS121621F.vhd | 2 | 100056 | ------------------------------------------------------
-- Hynix 4BANKS X 8M X 16bits DDR2 SDRAM --
-- --
-- VHDL Modeling --
-- --
-- PART : HY5PS121621F-B400/B533/B667/B800 --
-- --
-- HHHH HHHH --
-- HHHH HHHH --
-- ,O0O. ,O0 .HH ,O0 .HH --
-- (O000O)(O00 )H(O00 )H --
-- `O0O' `O0 'HH `O0 'HH --
-- HHHH HHHH Hynix --
-- HHHH HHHH Semiconductor --
------------------------------------------------------
---------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
library grlib;
use grlib.stdlib.all;
--USE IEEE.STD_LOGIC_ARITH.all;
--USE IEEE.STD_LOGIC_UNSIGNED.all;
USE work.HY5PS121621F_PACK.all;
---------------------------------------------------------------------------------------------------
Entity HY5PS121621F Is
generic (
TimingCheckFlag : boolean := TRUE;
PUSCheckFlag : boolean := FALSE;
Part_Number : PART_NUM_TYPE := B400);
Port ( DQ : inout std_logic_vector(15 downto 0) := (others => 'Z');
LDQS : inout std_logic := 'Z';
LDQSB : inout std_logic := 'Z';
UDQS : inout std_logic := 'Z';
UDQSB : inout std_logic := 'Z';
LDM : in std_logic;
WEB : in std_logic;
CASB : in std_logic;
RASB : in std_logic;
CSB : in std_logic;
BA : in std_logic_vector(1 downto 0);
ADDR : in std_logic_vector(12 downto 0);
CKE : in std_logic;
CLK : in std_logic;
CLKB : in std_logic;
UDM : in std_logic );
End HY5PS121621F;
-----------------------------------------------------------------------------------------------------
Architecture Behavioral_Model_HY5PS121621F Of HY5PS121621F Is
signal RD_PIPE_REG : std_logic_vector(6 downto 0) := "0000000";
signal WT_PIPE_REG : std_logic_vector(12 downto 0) := "0000000000000";
signal ADD_PIPE_REG : ADD_PIPE_TYPE;
signal DLL_reset, DLL_lock_enable : std_logic := '0';
signal yburst, RD_WR_ST, caspwt, casp6_rd, casp6_wt : std_logic := '0';
signal casp_wtI, casp_wtII, wt_stdby : std_logic := '0';
signal udspre_enable, ldspre_enable, udsh_dsl_enable, ldsh_dsl_enable : std_logic := '0';
signal dq_bufferH, dq_bufferL : DATA_BUFFER_TYPE := ("0ZZZZZZZZ", "0ZZZZZZZZ", "0ZZZZZZZZ",
"0ZZZZZZZZ", "0ZZZZZZZZ", "0ZZZZZZZZ", "0ZZZZZZZZ");
signal DQS_S : std_logic := 'Z';
signal dqs_count : integer := 0;
signal dqs_pulse1, dqs_pulse2, dqs_pulse3, dqs_pulse4, dqs_pulse5, dqs_pulse6 : std_logic := '0';
signal cur_time : time := 0 ns;
signal Ref_time, clk_cycle_rising : time := 0 ns;
signal tmp_act_trans0, tmp_act_trans1, tmp_act_trans2, tmp_act_trans3 : std_logic := '0';
signal mrs_cmd_in : std_logic := '0';
signal CKEN : CKE_TYPE := (others => '0');
signal CLK_DLY2, CLK_DLY1, CLK_DLY15 : std_logic := '0';
signal tmp_ref_addr1 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0');
signal tmp_ref_addr2 : std_logic_vector((NUM_OF_ROW_ADD + 1) downto 0) := (others => '0');
signal tmp_ref_addr3_B0 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0');
signal tmp_ref_addr3_B1 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0');
signal tmp_ref_addr3_B2 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0');
signal tmp_ref_addr3_B3 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0');
signal tmp_ref_addr3_0, tmp_ref_addr3_1, tmp_ref_addr3_2, tmp_ref_addr3_3 : std_logic := '0';
signal tmp_ref_addr1_trans, tmp_ref_addr2_trans, tmp_ref_addr3_trans : std_logic := '0';
signal RefChkTimeInit : boolean := FALSE;
signal refresh_check : REF_CHECK;
signal real_col_addr : COL_ADDR_TYPE ;
signal Read_CA, Write_CA : std_logic := '0';
signal tmp_w_trans0, tmp_w_trans1, tmp_w_trans2, tmp_w_trans3 : std_logic := '0';
signal RA_Activated_B0 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U');
signal RA_Activated_B1 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U');
signal RA_Activated_B2 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U');
signal RA_Activated_B3 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U');
signal SA_ARRAY : SA_ARRAY_TYPE;
signal SA_ARRAY_A0 : SA_TYPE;
signal SA_ARRAY_A1 : SA_TYPE;
signal SA_ARRAY_A2 : SA_TYPE;
signal SA_ARRAY_A3 : SA_TYPE;
signal SA_ARRAY_W0 : SA_TYPE;
signal SA_ARRAY_W1 : SA_TYPE;
signal SA_ARRAY_W2 : SA_TYPE;
signal SA_ARRAY_W3 : SA_TYPE;
signal PcgPdExtFlag, ActPdExtFlag, SlowActPdExtFlag : boolean := FALSE;
signal PUSPCGAFlag1, PUSPCGAFlag2 : boolean := FALSE;
signal PUS_DLL_RESET : boolean := FALSE;
signal ModeRegisterSetFlag : boolean := FALSE;
signal ModeRegisterFlag : boolean := FALSE;
signal BankActivateFlag : boolean := FALSE;
signal BankActivateFinFlag : boolean := FALSE;
signal BankActivatedFlag : std_logic_vector ((NUM_OF_BANKS - 1) downto 0) := (others => '0');
signal PcgPdFlag, ReadFlag : boolean := FALSE;
signal WriteFlag : boolean := FALSE;
signal DataBuffer : BUFFER_TYPE;
signal PrechargeFlag : boolean := FALSE;
signal AutoPrechargeFlag : std_logic_vector ((NUM_OF_BANKS - 1) downto 0) := (others => '0');
signal PrechargeFinFlag : boolean := FALSE;
signal PrechargeAllFlag : boolean := FALSE;
signal PrechargeAllFinFlag : boolean := FALSE;
signal ReadFinFlag : boolean := FALSE;
signal WriteFinFlag : boolean := FALSE;
signal AutoRefFlag : boolean := FALSE;
signal SelfRefFlag : boolean := FALSE;
signal SelfRefExt2NRFlag, SelfRefExt2RDFlag : boolean := FALSE;
signal PUSCheckFinFlag : boolean := FALSE;
signal CurrentState : STATE_TYPE := PWRUP;
signal ModeRegister : MODE_REGISTER := (
CAS_LATENCY => 2,
BURST_MODE => SEQUENTIAL,
BURST_LENGTH => 4,
DLL_STATE => NORST,
SAPD => '0',
TWR => 2 );
signal ExtModeRegister : EMR_TYPE := (
DLL_EN => '0',
AL => 0,
QOFF => '0',
DQSB_ENB => '0',
RDQS_EN => '0',
OCD_PGM => CAL_EXIT );
signal ExtModeRegister2 : EMR2_TYPE := (
SREF_HOT => '0' );
signal last_ocd_adjust_cmd, clk_cycle : time := 0 ns;
signal clk_last_rising : time := 0 ns;
signal cke_last_rising : time := 0 ns;
signal clk_last_falling : time := 0 ns;
signal udqs_last_rising : time := 0 ns;
signal udqs_last_falling : time := 0 ns;
signal ldqs_last_rising : time := 0 ns;
signal ldqs_last_falling : time := 0 ns;
signal wr_cmd_time : time := 0 ns;
signal ldm_last_rising : time := 0 ns;
signal udm_last_rising : time := 0 ns;
signal b0_last_activate : time := 0 ns;
signal b1_last_activate : time := 0 ns;
signal b2_last_activate : time := 0 ns;
signal b3_last_activate : time := 0 ns;
signal b0_last_precharge : time := 0 ns;
signal b1_last_precharge : time := 0 ns;
signal b2_last_precharge : time := 0 ns;
signal b3_last_precharge : time := 0 ns;
signal b0_last_column_access : time := 0 ns;
signal b1_last_column_access : time := 0 ns;
signal b2_last_column_access : time := 0 ns;
signal b3_last_column_access : time := 0 ns;
signal b0_last_data_in : time := 0 ns;
signal b1_last_data_in : time := 0 ns;
signal b2_last_data_in : time := 0 ns;
signal b3_last_data_in : time := 0 ns;
signal last_mrs_set : time := 0 ns;
signal last_aref : time := 0 ns;
signal tCH : time := 0 ns;
signal tCL : time := 0 ns;
signal tWPRE : time := 0 ns;
signal tRAS, tRCD, tRP, tRC, tCCD : time := 0 ns;
signal tWTR : time := 0 ns;
signal tDQSH : time := 0 ns;
signal tDQSL : time := 0 ns;
signal tWPSTmin : time := 0 ns;
signal tWPSTmax : time := 0 ns;
signal tDQSSmin : time := 0 ns;
signal tDQSSmax : time := 0 ns;
signal tMRD : time := 0 ns;
signal cke_ch : time := 0 ns;
signal rasb_ch : time := 0 ns;
signal casb_ch : time := 0 ns;
signal web_ch : time := 0 ns;
signal csb_ch : time := 0 ns;
signal udm_ch : time := 0 ns;
signal ldm_ch : time := 0 ns;
signal a0_ch : time := 0 ns;
signal a1_ch : time := 0 ns;
signal a2_ch : time := 0 ns;
signal a3_ch : time := 0 ns;
signal a4_ch : time := 0 ns;
signal a5_ch : time := 0 ns;
signal a6_ch : time := 0 ns;
signal a7_ch : time := 0 ns;
signal a8_ch : time := 0 ns;
signal a9_ch : time := 0 ns;
signal a10_ch : time := 0 ns;
signal a11_ch : time := 0 ns;
signal a12_ch : time := 0 ns;
signal ba0_ch : time := 0 ns;
signal ba1_ch : time := 0 ns;
signal dq0_ch : time := 0 ns;
signal dq1_ch : time := 0 ns;
signal dq2_ch : time := 0 ns;
signal dq3_ch : time := 0 ns;
signal dq4_ch : time := 0 ns;
signal dq5_ch : time := 0 ns;
signal dq6_ch : time := 0 ns;
signal dq7_ch : time := 0 ns;
signal dq8_ch : time := 0 ns;
signal dq9_ch : time := 0 ns;
signal dq10_ch : time := 0 ns;
signal dq11_ch : time := 0 ns;
signal dq12_ch : time := 0 ns;
signal dq13_ch : time := 0 ns;
signal dq14_ch : time := 0 ns;
signal dq15_ch : time := 0 ns;
begin
-----------------------------------------------------------------------------------------------------
CLK_CYCLE_CHECK : process(CLK)
begin
CLK_DLY15 <= transport CLK after 1.5 ns;
CLK_DLY1 <= transport CLK after 1 ns;
CLK_DLY2 <= transport CLK after 2 ns;
if (rising_edge(CLK)) then
clk_cycle <= transport now - clk_cycle_rising;
clk_cycle_rising <= transport now;
end if;
end Process;
-----------------------------------------------------------------------------------------------------
REFRESH_TIME_CHECK : process(tmp_ref_addr1_trans, tmp_ref_addr2_trans, tmp_ref_addr3_trans)
variable i, j : integer := 0;
begin
i := 0;
j := 0;
if (RefChkTimeInit = FALSE) then
loop
exit when (i > NUM_OF_BANKS - 1);
j := 0;
loop
exit when (j >= NUM_OF_ROWS);
refresh_check (i, j) <= 0 ns;
j := j + 1;
end loop;
i := i + 1;
end loop;
RefChkTimeInit <= TRUE;
end if;
if (tmp_ref_addr1_trans'event and tmp_ref_addr1_trans = '1') then
refresh_check (0, conv_integer(tmp_ref_addr1)) <= transport now;
refresh_check (1, conv_integer(tmp_ref_addr1)) <= transport now;
refresh_check (2, conv_integer(tmp_ref_addr1)) <= transport now;
refresh_check (3, conv_integer(tmp_ref_addr1)) <= transport now;
end if;
if (tmp_ref_addr2_trans'event and tmp_ref_addr2_trans = '1') then
refresh_check (conv_integer(tmp_ref_addr2(1 downto 0)), conv_integer(tmp_ref_addr2((NUM_OF_ROW_ADD + 1) downto 2))) <= transport now;
end if;
if (tmp_ref_addr3_trans'event and tmp_ref_addr3_trans = '1') then
if (tmp_ref_addr3_0 = '1') then
refresh_check (0, conv_integer(tmp_ref_addr3_B0)) <= transport now;
end if;
if (tmp_ref_addr3_1 = '1') then
refresh_check (1, conv_integer(tmp_ref_addr3_B1)) <= transport now;
end if;
if (tmp_ref_addr3_2 = '1') then
refresh_check (2, conv_integer(tmp_ref_addr3_B2)) <= transport now;
end if;
if (tmp_ref_addr3_3 = '1') then
refresh_check (3, conv_integer(tmp_ref_addr3_B3)) <= transport now;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
CKE_EVAL : process (CLK, CKE)
begin
if (CKE'EVENT and CKE = '1' and CKE'LAST_VALUE = '0') then
cke_last_rising <= transport now;
end if;
if (CLK'EVENT and CLK = '0' and CLK'LAST_VALUE = '1') then
CKEN(-1) <= CKEN(0);
elsif (CLK'EVENT and CLK = '1' and CLK'LAST_VALUE = '0') then
CKEN(0) <= CKE;
end if;
end process;
-----------------------------------------------------------------------------------------------------
STATE_MACHINE : process (CLK, CKE, BankActivateFinFlag, PrechargeFinFlag, PrechargeAllFinFlag, BankActivatedFlag, PUSCheckFinFlag)
variable ChipSelectBar : std_logic := '0';
variable RowAddrStrobeBar : std_logic := '0';
variable ColAddrStrobeBar : std_logic := '0';
variable WriteEnableBar : std_logic := '0';
variable Address10 : std_logic := '0';
variable ClockEnable : CKE_TYPE := (others => '0');
variable NextState, Cur_State : STATE_TYPE := PWRUP;
variable CurrentCommand : COMMAND_TYPE := NOP;
variable OpCode : MROPCODE_TYPE := (others => 'X');
variable MR : MODE_REGISTER;
variable EMR : EMR_TYPE;
variable EMR2 : EMR2_TYPE;
variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
variable BankActFlag : std_logic_vector((NUM_OF_BANKS - 1) downto 0) := (others => '0');
begin
if (CLK'EVENT and CLK = '1' and CLK'LAST_VALUE = '0') then
ClockEnable(-1) := CKEN(-1);
ClockEnable(0) := CKE;
ChipSelectBar := CSB;
RowAddrStrobeBar := RASB;
ColAddrStrobeBar := CASB;
WriteEnableBar := WEB;
Address10 := ADDR(10);
BkAdd := BA;
BankActFlag := BankActivatedFlag;
Cur_State := CurrentState;
COMMAND_DECODE (ChipSelectBar, RowAddrStrobeBar, ColAddrStrobeBar,
WriteEnableBar, Address10, BkAdd, ClockEnable, CurrentCommand, BankActFlag, Cur_State);
if (DLL_reset = '1' and (CurrentCommand = RD or CurrentCommand = RDAP)) then
if (TimingCheckFlag = TRUE) then
assert false report
"ERROR : (DLL Locking) : 200 clock cycles are needed after DLL reset."
severity ERROR;
end if;
end if;
Case CurrentState Is
When IDLE =>
Case CurrentCommand Is
When DSEL =>
NextState := IDLE;
When NOP =>
NextState := IDLE;
When ACT =>
if (TimingCheckFlag = TRUE) then
assert (PcgPdExtFlag = FALSE) report
"WARNING : (tXP_CHECK) : tXP timing error!"
severity WARNING;
assert (now - last_aref >= tRFC) report
"WARNING : (tRFC_CHECK) : tRFC timing error!"
severity WARNING;
assert (SelfRefExt2NRFlag /= TRUE) report
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
severity error;
end if;
BankActivateFlag <= TRUE;
NextState := RACT;
When PCG =>
if (TimingCheckFlag = TRUE) then
assert (SelfRefExt2NRFlag /= TRUE) report
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
severity error;
assert (PcgPdExtFlag = FALSE) report
"WARNING : (tXP_CHECK) : tXP timing error!"
severity WARNING;
end if;
NextState := IDLE;
When PCGA =>
if (TimingCheckFlag = TRUE) then
assert (SelfRefExt2NRFlag /= TRUE) report
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
severity error;
assert (PcgPdExtFlag = FALSE) report
"WARNING : (tXP_CHECK) : tXP timing error!"
severity WARNING;
end if;
NextState := IDLE;
When AREF =>
if (TimingCheckFlag = TRUE) then
assert (PcgPdExtFlag = FALSE) report
"WARNING : (tXP_CHECK) : tXP timing error!"
severity WARNING;
assert (SelfRefExt2NRFlag /= TRUE) report
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
severity error;
assert (now - last_aref >= tRFC) report
"WARNING : (tRFC_CHECK) : tRFC timing error!"
severity WARNING;
end if;
last_aref <= transport now after 1 ns;
AutoRefFlag <= TRUE, FALSE after 2 ns;
NextState := IDLE;
When SREF =>
if (TimingCheckFlag = TRUE) then
assert (PcgPdExtFlag = FALSE) report
"WARNING : (tXP_CHECK) : tXP timing error!"
severity WARNING;
assert (SelfRefExt2NRFlag /= TRUE) report
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
severity error;
end if;
SelfRefFlag <= TRUE;
NextState := SLFREF;
When PDEN =>
if (TimingCheckFlag = TRUE) then
assert (PcgPdExtFlag = FALSE) report
"WARNING : (tXP_CHECK) : tXP timing error!"
severity WARNING;
assert (SelfRefExt2NRFlag /= TRUE) report
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
severity error;
end if;
PcgPdFlag <= TRUE;
NextState := PWRDN;
When EMRS3 =>
NextState := IDLE;
mrs_cmd_in <= transport '1', '0' after 2 ns;
When EMRS1 =>
OpCode := ADDR(12 downto 0);
EXT_MODE_REGISTER_SET (OpCode, EMR);
ExtModeRegister <= EMR;
NextState := IDLE;
if (ADDR(0) = '0') then
DLL_lock_enable <= '1';
end if;
mrs_cmd_in <= transport '1', '0' after 2 ns;
When EMRS2 =>
OpCode := ADDR(12 downto 0);
EXT_MODE_REGISTER_SET2 (OpCode, EMR2);
ExtModeRegister2 <= EMR2;
NextState := IDLE;
mrs_cmd_in <= transport '1', '0' after 2 ns;
When MRS =>
if (TimingCheckFlag = TRUE) then
assert (PcgPdExtFlag = FALSE) report
"WARNING : (tXP_CHECK) : tXP timing error!"
severity WARNING;
assert (SelfRefExt2NRFlag /= TRUE) report
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
severity error;
end if;
OpCode := ADDR(12 downto 0);
MODE_REGISTER_SET (OpCode, MR);
ModeRegister <= MR;
ModeRegisterSetFlag <= TRUE;
if (ADDR(8) = '1') then
DLL_reset <= transport '1', '0' after 200 * clk_cycle;
end if;
NextState := IDLE;
mrs_cmd_in <= transport '1', '0' after 2 ns;
When others =>
assert false report
"WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored."
severity warning;
NextState := IDLE;
End Case;
When PWRUP =>
Case CurrentCommand Is
When DSEL =>
if (PUSCheckFlag = TRUE) then
NextState := PWRUP;
else
NextState := IDLE;
end if;
When NOP =>
if (PUSCheckFlag = TRUE) then
NextState := PWRUP;
else
NextState := IDLE;
end if;
When EMRS3 =>
NextState := PWRUP;
mrs_cmd_in <= transport '1', '0' after 2 ns;
When EMRS1 =>
if (TimingCheckFlag = TRUE and PUSCheckFlag = TRUE) then
assert (PUSPCGAFlag1 = TRUE) report
"ERROR : (Power Up Sequence) : PCGA Command must be issued before EMRS setting!"
severity error;
end if;
OpCode := ADDR(12 downto 0);
EXT_MODE_REGISTER_SET (OpCode, EMR);
ExtModeRegister <= EMR;
NextState := PWRUP;
if (ADDR(0) = '0') then
DLL_lock_enable <= '1';
end if;
mrs_cmd_in <= transport '1', '0' after 2 ns;
When EMRS2 =>
OpCode := ADDR(12 downto 0);
EXT_MODE_REGISTER_SET2 (OpCode, EMR2);
ExtModeRegister2 <= EMR2;
NextState := PWRUP;
mrs_cmd_in <= transport '1', '0' after 2 ns;
When MRS =>
if (TimingCheckFlag = TRUE) then
assert (DLL_lock_enable = '1') report
"WARNING : (STATE_MACHINE) : EMRS Command (with DLL enable flag) Must be Issued before MRS Command !"
severity warning;
end if;
OpCode := ADDR(12 downto 0);
MODE_REGISTER_SET (OpCode, MR);
ModeRegister <= MR;
ModeRegisterSetFlag <= TRUE;
NextState := PWRUP;
if (ADDR(8) = '1') then
DLL_reset <= transport '1', '0' after 200 * clk_cycle;
end if;
mrs_cmd_in <= transport '1', '0' after 2 ns;
When PCGA =>
PrechargeAllFlag <= TRUE;
NextState := PWRUP;
When AREF =>
AutoRefFlag <= TRUE, FALSE after 2 ns;
if (PUSCheckFinFlag = TRUE) then
NextState := IDLE;
else
NextState := PWRUP;
end if;
last_aref <= transport now after 1 ns;
When others =>
assert false report
"ERROR : (STATE_MACHINE) : Invalid Command Issued during Power Up Sequence."
severity error;
End Case;
When PWRDN =>
Case CurrentCommand Is
When NOP =>
NextState := PWRDN;
When PDEX =>
if (PcgPdFlag = TRUE) then
PcgPdExtFlag <= transport TRUE, FALSE after tXP * clk_cycle;
PcgPdFlag <= FALSE;
NextState := IDLE;
elsif (ModeRegister.SAPD = '0') then
ActPdExtFlag <= transport TRUE, FALSE after tXARD * clk_cycle;
NextState := RACT;
elsif (ModeRegister.SAPD = '1') then
SlowActPdExtFlag <= transport TRUE, FALSE after (6 - ExtModeRegister.AL) * clk_cycle;
NextState := RACT;
end if;
When others =>
assert false report
"WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored."
severity warning;
NextState := PWRDN;
End Case;
When SLFREF =>
Case CurrentCommand Is
When NOP =>
NextState := SLFREF;
When SREX =>
SelfRefExt2NRFlag <= transport TRUE, FALSE after tXSNR;
SelfRefExt2RDFlag <= transport TRUE, FALSE after tXSRD * clk_cycle;
SelfRefFlag <= FALSE;
NextState := IDLE;
When others =>
assert false report
"WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored."
severity warning;
NextState := SLFREF;
End Case;
When RACT =>
Case CurrentCommand Is
When DSEL =>
NextState := RACT;
When NOP =>
NextState := RACT;
When RD =>
if (TimingCheckFlag = TRUE) then
assert (SelfRefExt2RDFlag /= TRUE) report
"ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh."
severity error;
assert (ActPdExtFlag = FALSE) report
"WARNING : (tXARD_CHECK) : tXARD timing error!"
severity WARNING;
assert (SlowActPdExtFlag = FALSE) report
"WARNING : (tXARDS_CHECK) : tXARDS timing error!"
severity WARNING;
end if;
Read_CA <= '1', '0' after 2 ns;
NextState := READ;
When RDAP =>
if (TimingCheckFlag = TRUE) then
assert (SelfRefExt2RDFlag /= TRUE) report
"ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh."
severity error;
assert (ActPdExtFlag = FALSE) report
"WARNING : (tXARD_CHECK) : tXARD timing error!"
severity WARNING;
assert (SlowActPdExtFlag = FALSE) report
"WARNING : (tXARDS_CHECK) : tXARDS timing error!"
severity WARNING;
end if;
AutoPrechargeFlag(conv_integer(BkAdd)) <= transport
'1' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP,
'0' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP + 2 ns;
Read_CA <= '1', '0' after 2 ns;
NextState := READ;
When WR =>
Write_CA <= '1', '0' after 2 ns;
NextState := WRITE;
When WRAP =>
AutoPrechargeFlag(conv_integer(BkAdd)) <= transport
'1' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 +
ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle,
'0' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 +
ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle + 2 ns;
Write_CA <= '1', '0' after 2 ns;
NextState := WRITE;
When ACT =>
BankActivateFlag <= TRUE;
NextState := RACT;
When PCG =>
PrechargeFlag <= TRUE;
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
When PCGA =>
PrechargeAllFlag <= TRUE;
NextState := IDLE;
When PDEN =>
NextState := PWRDN;
When others =>
assert false report
"WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored."
severity warning;
NextState := RACT;
End Case;
When READ =>
Case CurrentCommand Is
When DSEL =>
NextState := READ;
When NOP =>
NextState := READ;
When RD =>
if (TimingCheckFlag = TRUE) then
assert (SelfRefExt2RDFlag /= TRUE) report
"ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh."
severity error;
end if;
Read_CA <= '1', '0' after 2 ns;
NextState := READ;
When RDAP =>
if (TimingCheckFlag = TRUE) then
assert (SelfRefExt2RDFlag /= TRUE) report
"ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh."
severity error;
end if;
AutoPrechargeFlag(conv_integer(BkAdd)) <= transport
'1' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP,
'0' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP + 2 ns;
Read_CA <= '1', '0' after 2 ns;
NextState := READ;
When WR =>
Write_CA <= '1', '0' after 2 ns;
NextState := WRITE;
When WRAP =>
AutoPrechargeFlag(conv_integer(BkAdd)) <= transport
'1' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 +
ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle,
'0' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 +
ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle + 2 ns;
Write_CA <= '1', '0' after 2 ns;
NextState := WRITE;
When ACT =>
BankActivateFlag <= TRUE;
NextState := READ;
When PCG =>
PrechargeFlag <= TRUE;
NextState := READ;
When PCGA =>
PrechargeAllFlag <= TRUE;
NextState := READ;
When others =>
assert false report
"WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored."
severity warning;
NextState := READ;
End Case;
When WRITE =>
Case CurrentCommand Is
When DSEL =>
NextState := WRITE;
When NOP =>
NextState := WRITE;
When RD =>
if (TimingCheckFlag = TRUE) then
assert (SelfRefExt2RDFlag /= TRUE) report
"ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh."
severity error;
end if;
Read_CA <= '1', '0' after 2 ns;
NextState := READ;
When RDAP =>
if (TimingCheckFlag = TRUE) then
assert (SelfRefExt2RDFlag /= TRUE) report
"ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh."
severity error;
end if;
AutoPrechargeFlag(conv_integer(BkAdd)) <= transport
'1' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP,
'0' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP + 2 ns;
Read_CA <= '1', '0' after 2 ns;
NextState := READ;
When WR =>
Write_CA <= '1', '0' after 2 ns;
NextState := WRITE;
When WRAP =>
AutoPrechargeFlag(conv_integer(BkAdd)) <= transport
'1' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 +
ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle,
'0' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 +
ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle + 2 ns;
Write_CA <= '1', '0' after 2 ns;
NextState := WRITE;
When ACT =>
BankActivateFlag <= TRUE;
NextState := WRITE;
When PCG =>
PrechargeFlag <= TRUE;
NextState := WRITE;
When PCGA =>
PrechargeAllFlag <= TRUE;
NextState := WRITE;
When others =>
assert false report
"WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored."
severity warning;
NextState := WRITE;
End Case;
When others =>
assert false report
"ERROR : (STATE_MACHINE) : Invalid Command Issued."
severity error;
End case;
end if;
if (BankActivateFinFlag = TRUE) then
BankActivateFlag <= FALSE;
end if;
if (PrechargeFinFlag = TRUE) then
PrechargeFlag <= FALSE;
end if;
if (PrechargeAllFinFlag = TRUE) then
PrechargeAllFlag <= FALSE;
end if;
if (PUSCheckFinFlag'EVENT and PUSCheckFinFlag = TRUE) then
NextState := IDLE;
end if;
if (BankActivatedFlag'EVENT and BankActivatedFlag /= BankActivatedFlag'LAST_VALUE) then
if (BankActivatedFlag = "0000") then
NextState := IDLE;
else
NextState := RACT;
end if;
end if;
CurrentState <= NextState;
end process;
-----------------------------------------------------------------------------------------------------
MEMORY_BANK_ACTIVATE_PRECHARGE : process (PrechargeFlag, AutoPrechargeFlag, PrechargeAllFlag, BankActivateFlag, CLK)
variable BkAdd : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
variable RA : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'X');
variable MEM_CELL_ARRAY0, MEM_CELL_ARRAY1, MEM_CELL_ARRAY2, MEM_CELL_ARRAY3 : MEM_CELL_TYPE;
variable i, j, k, l, m, u : integer := 0;
begin
if (CLK'EVENT and CLK = '0') then
if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans0 = '1'))) Then
tmp_act_trans0 <= '0';
end if;
if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans1 = '1'))) Then
tmp_act_trans1 <= '0';
end if;
if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans2 = '1'))) Then
tmp_act_trans2 <= '0';
end if;
if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans3 = '1'))) Then
tmp_act_trans3 <= '0';
end if;
end if;
if (BankActivateFlag'EVENT and BankActivateFlag = TRUE) then
BkAdd := (BA);
RA := ADDR(NUM_OF_ROW_ADD - 1 downto 0);
BankActivatedFlag(conv_integer(BkAdd)) <= '1';
i := 0;
j := 0;
u := 0;
if (BankActivatedFlag (conv_integer (BkAdd)) = '1') then
assert false report
"WARNING : (MEMORY_BANK_ACTIVATE) : Activating same bank without precharge. Command Ignored."
severity warning;
BankActivateFinFlag <= TRUE, FALSE after 2 ns;
elsif (BankActivatedFlag (conv_integer (BkAdd)) = '0') then
if (TimingCheckFlag = TRUE) then
if (now - refresh_check(conv_integer(BkAdd), conv_integer(RA)) > tREF) then
assert false report
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms. So, This Row's Data Is Lost."
severity warning;
end if;
end if;
case BkAdd is
when "00" =>
b0_last_activate <= transport now;
RA_Activated_B0 <= RA;
when "01" =>
b1_last_activate <= transport now;
RA_Activated_B1 <= RA;
when "10" =>
b2_last_activate <= transport now;
RA_Activated_B2 <= RA;
when "11" =>
b3_last_activate <= transport now;
RA_Activated_B3 <= RA;
when others =>
assert false report
"WARNING : (MEMORY_REFRESH) : Impossible Bank Address"
severity warning;
end case;
if (conv_integer (BkAdd) = 0) then
if (MEM_CELL_ARRAY0(conv_integer (RA)) = NULL) then
MEM_CELL_ARRAY0(conv_integer (RA)) := NEW ROW_DATA_TYPE;
loop
exit when u >= NUM_OF_COLS;
MEM_CELL_ARRAY0(conv_integer (RA))(u) := 0;
u := u + 1;
end loop;
end if;
loop
exit when i >= NUM_OF_COLS;
SA_ARRAY_A0(i) <= MEM_CELL_ARRAY0(conv_integer (RA))(i);
i := i + 1;
end loop;
tmp_act_trans0 <= '1';
elsif (conv_integer (BkAdd) = 1) then
if (MEM_CELL_ARRAY1(conv_integer (RA)) = NULL) then
MEM_CELL_ARRAY1(conv_integer (RA)) := NEW ROW_DATA_TYPE;
loop
exit when u >= NUM_OF_COLS;
MEM_CELL_ARRAY1(conv_integer (RA))(u) := 0;
u := u + 1;
end loop;
end if;
loop
exit when i >= NUM_OF_COLS;
SA_ARRAY_A1(i) <= MEM_CELL_ARRAY1(conv_integer (RA))(i);
i := i + 1;
end loop;
tmp_act_trans1 <= '1';
elsif (conv_integer (BkAdd) = 2) then
if (MEM_CELL_ARRAY2(conv_integer (RA)) = NULL) then
MEM_CELL_ARRAY2(conv_integer (RA)) := NEW ROW_DATA_TYPE;
loop
exit when u >= NUM_OF_COLS;
MEM_CELL_ARRAY2(conv_integer (RA))(u) := 0;
u := u + 1;
end loop;
end if;
loop
exit when i >= NUM_OF_COLS;
SA_ARRAY_A2(i) <= MEM_CELL_ARRAY2(conv_integer (RA))(i);
i := i + 1;
end loop;
tmp_act_trans2 <= '1';
elsif (conv_integer (BkAdd) = 3) then
if (MEM_CELL_ARRAY3(conv_integer (RA)) = NULL) then
MEM_CELL_ARRAY3(conv_integer (RA)) := NEW ROW_DATA_TYPE;
loop
exit when u >= NUM_OF_COLS;
MEM_CELL_ARRAY3(conv_integer (RA))(u) := 0;
u := u + 1;
end loop;
end if;
loop
exit when i >= NUM_OF_COLS;
SA_ARRAY_A3(i) <= MEM_CELL_ARRAY3(conv_integer (RA))(i);
i := i + 1;
end loop;
tmp_act_trans3 <= '1';
end if;
BankActivateFinFlag <= TRUE, FALSE after 2 ns;
else
end if;
end if;
if ((PrechargeFlag'EVENT and PrechargeFlag = TRUE) or
(AutoPrechargeFlag(0)'EVENT and AutoPrechargeFlag(0) = '1') or
(AutoPrechargeFlag(1)'EVENT and AutoPrechargeFlag(1) = '1') or
(AutoPrechargeFlag(2)'EVENT and AutoPrechargeFlag(2) = '1') or
(AutoPrechargeFlag(3)'EVENT and AutoPrechargeFlag(3) = '1')) then
i := 0;
j := 0;
if (PrechargeFlag = TRUE) then
BkAdd := (BA);
elsif (AutoPrechargeFlag(0) = '1') then
BkAdd := "00";
elsif (AutoPrechargeFlag(1) = '1') then
BkAdd := "01";
elsif (AutoPrechargeFlag(2) = '1') then
BkAdd := "10";
elsif (AutoPrechargeFlag(3) = '1') then
BkAdd := "11";
end if;
if (BkAdd = "00") then
if (AutoPrechargeFlag(0) = '1' and (now - b0_last_activate) < tRAS) then
b0_last_precharge <= transport (tRAS + b0_last_activate) after 1 ns;
else
b0_last_precharge <= transport now after 1 ns;
end if;
if (BankActivatedFlag (0) /= '1') then
assert false report
"WARNING : (MEMORY_PRECHARGE) : Precharging deactivated bank."
severity warning;
else
RA := RA_Activated_B0;
i := 0;
loop
exit when i >= NUM_OF_COLS;
MEM_CELL_ARRAY0(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
i := i + 1;
end loop;
if (AutoPrechargeFlag(0) = '1' and (now - b0_last_activate) < tRAS) then
BankActivatedFlag (0) <= transport '0' after (tRAS - (now - b0_last_activate));
else
BankActivatedFlag (0) <= '0';
end if;
tmp_ref_addr2 <= RA&"00";
end if;
elsif (BkAdd = "01") then
if (AutoPrechargeFlag(1) = '1' and (now - b1_last_activate) < tRAS) then
b1_last_precharge <= transport (tRAS + b1_last_activate) after 1 ns;
else
b1_last_precharge <= transport now after 1 ns;
end if;
if (BankActivatedFlag (1) /= '1') then
assert false report
"WARNING : (MEMORY_PRECHARGE) : Precharging deactivated bank."
severity warning;
else
RA := RA_Activated_B1;
i := 0;
loop
exit when i >= NUM_OF_COLS;
MEM_CELL_ARRAY1(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
i := i + 1;
end loop;
if (AutoPrechargeFlag(1) = '1' and (now - b1_last_activate) < tRAS) then
BankActivatedFlag (1) <= transport '0' after (tRAS - (now - b1_last_activate));
else
BankActivatedFlag (1) <= '0';
end if;
tmp_ref_addr2 <= RA&"01";
end if;
elsif (BkAdd = "10") then
if (AutoPrechargeFlag(2) = '1' and (now - b2_last_activate) < tRAS) then
b2_last_precharge <= transport (tRAS + b2_last_activate) after 1 ns;
else
b2_last_precharge <= transport now after 1 ns;
end if;
if (BankActivatedFlag (2) /= '1') then
assert false report
"WARNING : (MEMORY_PRECHARGE) : Precharging deactivated bank."
severity warning;
else
RA := RA_Activated_B2;
i := 0;
loop
exit when i >= NUM_OF_COLS;
MEM_CELL_ARRAY2(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
i := i + 1;
end loop;
if (AutoPrechargeFlag(2) = '1' and (now - b2_last_activate) < tRAS) then
BankActivatedFlag (2) <= transport '0' after (tRAS - (now - b2_last_activate));
else
BankActivatedFlag (2) <= '0';
end if;
tmp_ref_addr2 <= RA&"10";
end if;
elsif (BkAdd = "11") then
if (AutoPrechargeFlag(3) = '1' and (now - b3_last_activate) < tRAS) then
b3_last_precharge <= transport (tRAS + b3_last_activate) after 1 ns;
else
b3_last_precharge <= transport now after 1 ns;
end if;
if (BankActivatedFlag (3) /= '1') then
assert false report
"WARNING : (MEMORY_PRECHARGE) : Precharging deactivated bank."
severity warning;
else
RA := RA_Activated_B3;
i := 0;
loop
exit when i >= NUM_OF_COLS;
MEM_CELL_ARRAY3(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
i := i + 1;
end loop;
if (AutoPrechargeFlag(3) = '1' and (now - b3_last_activate) < tRAS) then
BankActivatedFlag (3) <= transport '0' after (tRAS - (now - b3_last_activate));
else
BankActivatedFlag (3) <= '0';
end if;
tmp_ref_addr2 <= RA&"11";
end if;
end if;
if (PrechargeFlag = TRUE) then
PrechargeFinFlag <= TRUE, FALSE after 2 ns;
end if;
tmp_ref_addr2_trans <= transport '1', '0' after 1 ns;
end if;
if (PrechargeAllFlag'EVENT and PrechargeAllFlag = TRUE) then
if BankActivatedFlag (0) = '1' then
BkAdd := "00";
RA := RA_Activated_B0;
i := 0;
loop
exit when i >= NUM_OF_COLS;
MEM_CELL_ARRAY0(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
i := i + 1;
end loop;
BankActivatedFlag (0) <= '0';
tmp_ref_addr3_B0 <= RA;
tmp_ref_addr3_0 <= transport '1', '0' after 1 ns;
b0_last_precharge <= transport now after 1 ns;
end if;
if BankActivatedFlag (1) = '1' then
BkAdd := "01";
RA := RA_Activated_B1;
i := 0;
loop
exit when i >= NUM_OF_COLS;
MEM_CELL_ARRAY1(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
i := i + 1;
end loop;
BankActivatedFlag (1) <= '0';
tmp_ref_addr3_B1 <= RA;
tmp_ref_addr3_1 <= transport '1', '0' after 1 ns;
b1_last_precharge <= transport now after 1 ns;
end if;
if BankActivatedFlag (2) = '1' then
BkAdd := "10";
RA := RA_Activated_B2;
i := 0;
loop
exit when i >= NUM_OF_COLS;
MEM_CELL_ARRAY2(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
i := i + 1;
end loop;
BankActivatedFlag (2) <= '0';
tmp_ref_addr3_B2 <= RA;
tmp_ref_addr3_2 <= transport '1', '0' after 1 ns;
b2_last_precharge <= transport now after 1 ns;
end if;
if BankActivatedFlag (3) = '1' then
BkAdd := "11";
RA := RA_Activated_B3;
i := 0;
loop
exit when i >= NUM_OF_COLS;
MEM_CELL_ARRAY3(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
i := i + 1;
end loop;
BankActivatedFlag (3) <= '0';
tmp_ref_addr3_B3 <= RA;
tmp_ref_addr3_3 <= transport '1', '0' after 1 ns;
b3_last_precharge <= transport now after 1 ns;
end if;
tmp_ref_addr3_trans <= transport '1', '0' after 1 ns;
if (BankActivatedFlag = "0000") then
if (PUSCheckFinFlag = TRUE) then
assert false report
"WARNING : (PRECHARGE_ALL) : No Activated Banks, PCGA command ignored."
severity WARNING;
else
BankActivatedFlag (0) <= '0';
BankActivatedFlag (1) <= '0';
BankActivatedFlag (2) <= '0';
BankActivatedFlag (3) <= '0';
end if;
end if;
PrechargeAllFinFlag <= TRUE, FALSE after 2 ns;
end if;
end process;
-----------------------------------------------------------------------------------------------------
SENSE_AMPLIFIER_UPDATE : process (tmp_act_trans0, tmp_act_trans1, tmp_act_trans2, tmp_act_trans3, tmp_w_trans0, tmp_w_trans1, tmp_w_trans2, tmp_w_trans3)
begin
if (tmp_act_trans0'EVENT and tmp_act_trans0 = '1') then
SA_ARRAY(0) <= SA_ARRAY_A0;
elsif (tmp_act_trans1'EVENT and tmp_act_trans1 = '1') then
SA_ARRAY(1) <= SA_ARRAY_A1;
elsif (tmp_act_trans2'EVENT and tmp_act_trans2 = '1') then
SA_ARRAY(2) <= SA_ARRAY_A2;
elsif (tmp_act_trans3'EVENT and tmp_act_trans3 = '1') then
SA_ARRAY(3) <= SA_ARRAY_A3;
elsif (tmp_w_trans0'EVENT and tmp_w_trans0 = '1') then
SA_ARRAY(0) <= SA_ARRAY_W0;
elsif (tmp_w_trans1'EVENT and tmp_w_trans1 = '1') then
SA_ARRAY(1) <= SA_ARRAY_W1;
elsif (tmp_w_trans2'EVENT and tmp_w_trans2 = '1') then
SA_ARRAY(2) <= SA_ARRAY_W2;
elsif (tmp_w_trans3'EVENT and tmp_w_trans3 = '1') then
SA_ARRAY(3) <= SA_ARRAY_W3;
End if;
end process;
-----------------------------------------------------------------------------------------------------
RD_WR_PIPE : process (CLK_DLY1, CLK)
variable CA : std_logic_vector ((NUM_OF_COL_ADD - 1) downto 0) := (others => 'X');
variable BkAdd : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
begin
if (CLK'EVENT and CLK = '1') then
BkAdd := (BA);
CA := ADDR(NUM_OF_COL_ADD - 1 downto 0);
end if;
if (CLK_DLY1'EVENT and CLK_DLY1 = '1') then
RD_PIPE_REG(6 downto 1) <= RD_PIPE_REG(5 downto 0);
WT_PIPE_REG(12 downto 1) <= WT_PIPE_REG(11 downto 0);
ADD_PIPE_REG(12) <= ADD_PIPE_REG(11);
ADD_PIPE_REG(11) <= ADD_PIPE_REG(10);
ADD_PIPE_REG(10) <= ADD_PIPE_REG(9);
ADD_PIPE_REG(9) <= ADD_PIPE_REG(8);
ADD_PIPE_REG(8) <= ADD_PIPE_REG(7);
ADD_PIPE_REG(7) <= ADD_PIPE_REG(6);
ADD_PIPE_REG(6) <= ADD_PIPE_REG(5);
ADD_PIPE_REG(5) <= ADD_PIPE_REG(4);
ADD_PIPE_REG(4) <= ADD_PIPE_REG(3);
ADD_PIPE_REG(3) <= ADD_PIPE_REG(2);
ADD_PIPE_REG(2) <= ADD_PIPE_REG(1);
ADD_PIPE_REG(1) <= ADD_PIPE_REG(0);
if (Read_CA = '1' or Write_CA = '1') then
ADD_PIPE_REG(0) <= BkAdd & CA;
if (Read_CA = '1') then
RD_PIPE_REG(0) <= '1';
else
RD_PIPE_REG(0) <= '0';
end if;
if (Write_CA = '1') then
WT_PIPE_REG(0) <= '1';
else
WT_PIPE_REG(0) <= '0';
end if;
else
ADD_PIPE_REG(0) <= (others => '0');
RD_PIPE_REG(0) <= '0';
WT_PIPE_REG(0) <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
casp6_XX_Gen : process (RD_PIPE_REG, WT_PIPE_REG)
begin
if (RD_PIPE_REG'event and RD_PIPE_REG(ExtModeRegister.AL) = '1') then
casp6_rd <= transport '1' after 0.5 ns, '0' after 2 ns;
elsif (WT_PIPE_REG'event and WT_PIPE_REG(ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 2) = '1') then
caspwt <= transport '1', '0' after 2 ns;
end if;
end process;
-----------------------------------------------------------------------------------------------------
RD_WT_Flag_GEN : process (caspwt, casp6_rd, ReadFinFlag, WriteFinFlag)
begin
if (ReadFinFlag'EVENT and ReadFinFlag = TRUE) then
ReadFlag <= FALSE;
elsif (WriteFinFlag'EVENT and WriteFinFlag = TRUE) then
WriteFlag <= FALSE;
end if;
if (casp6_rd'event and casp6_rd = '1') then
ReadFlag <= TRUE;
elsif (caspwt'event and caspwt = '1') then
WriteFlag <= TRUE;
end if;
end process;
-----------------------------------------------------------------------------------------------------
WRITE_ST_GEN : process(CLK_DLY1, caspwt)
begin
if (caspwt'event and caspwt = '1') then
wt_stdby <= '1';
end if;
if (CLK_DLY1'event and CLK_DLY1 = '1') then
if (casp_wtII = '1') then
casp6_wt <= transport '1' after 0.5 ns, '0' after 2 ns;
end if;
casp_wtII <= casp_wtI;
casp_wtI <= wt_stdby;
wt_stdby <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------
YBURST_GEN : process (casp6_rd, casp6_wt, CLK, ReadFinFlag, WriteFinFlag)
begin
if ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1')) then
RD_WR_ST <= '1';
yburst <= '0';
end if;
if (CLK'event and CLK = '1') then
if (RD_WR_ST = '1' and ModeRegister.BURST_LENGTH = 8) then
yburst <= transport '1' after 2.1 ns;
end if;
RD_WR_ST <= '0';
end if;
if ((ReadFinFlag'event and ReadFinFlag = TRUE) or (WriteFinFlag'event and WriteFinFlag = TRUE)) then
yburst <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------
DQS_PULSE_GEN : process (CLK, casp6_rd)
begin
if (casp6_rd'EVENT and casp6_rd = '1') then
dqs_pulse1 <= '1';
end if;
if (CLK'EVENT and CLK = '1') then
dqs_pulse6 <= dqs_pulse5;
dqs_pulse5 <= dqs_pulse4;
dqs_pulse4 <= dqs_pulse3;
dqs_pulse3 <= dqs_pulse2;
dqs_pulse2 <= dqs_pulse1;
dqs_pulse1 <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------
DQS_GENERATION : process(CLK, dqs_pulse1, dqs_pulse2, dqs_pulse3, dqs_pulse4, dqs_pulse5, dqs_pulse6)
begin
if (CLK'event and CLK = '1') then
if ((ModeRegister.CAS_LATENCY = 2 and dqs_pulse1 = '1') or
(ModeRegister.CAS_LATENCY = 3 and dqs_pulse2 = '1') or
(ModeRegister.CAS_LATENCY = 4 and dqs_pulse3 = '1') or
(ModeRegister.CAS_LATENCY = 5 and dqs_pulse4 = '1') or
(ModeRegister.CAS_LATENCY = 6 and dqs_pulse5 = '1')) then
if (DQS_S = 'Z') then
DQS_S <= '0';
elsif (dqs_count = ModeRegister.BURST_LENGTH) then
DQS_S <= '0';
else
DQS_S <= '1';
end if;
elsif ((ModeRegister.CAS_LATENCY = 2 and dqs_pulse2 = '1') or
(ModeRegister.CAS_LATENCY = 3 and dqs_pulse3 = '1') or
(ModeRegister.CAS_LATENCY = 4 and dqs_pulse4 = '1') or
(ModeRegister.CAS_LATENCY = 5 and dqs_pulse5 = '1') or
(ModeRegister.CAS_LATENCY = 6 and dqs_pulse6 = '1')) then
if (DQS_S = '0') then
DQS_S <= '1';
end if;
dqs_count <= 1;
elsif (dqs_count = ModeRegister.BURST_LENGTH) then
if (DQS_S = '0') then
DQS_S <= 'Z';
end if;
dqs_count <= 0;
elsif (DQS_S = '0') then
DQS_S <= '1';
dqs_count <= dqs_count + 1;
end if;
elsif (CLK'event and CLK = '0') then
if (DQS_S = '1') then
DQS_S <= '0';
dqs_count <= dqs_count + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
DQS_OPERATION : process(DQS_S, ExtModeRegister.OCD_PGM)
begin
if (ExtModeRegister.QOFF = '0') then
if (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = DRIVE0) then
UDQS <= '0';
LDQS <= '0';
if (ExtModeRegister.DQSB_ENB = '1') then
UDQSB <= '1';
LDQSB <= '1';
else
UDQSB <= 'Z';
LDQSB <= 'Z';
end if;
elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = DRIVE1) then
UDQS <= '1';
LDQS <= '1';
if (ExtModeRegister.DQSB_ENB = '1') then
UDQSB <= '0';
LDQSB <= '0';
else
UDQSB <= 'Z';
LDQSB <= 'Z';
end if;
elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = CAL_EXIT) then
UDQS <= 'Z';
LDQS <= 'Z';
UDQSB <= 'Z';
LDQSB <= 'Z';
elsif (DQS_S'event and DQS_S = '1') then
UDQS <= '1';
LDQS <= '1';
if (ExtModeRegister.DQSB_ENB = '0') then
UDQSB <= '0';
LDQSB <= '0';
else
UDQSB <= 'Z';
LDQSB <= 'Z';
end if;
elsif (DQS_S'event and DQS_S = '0') then
UDQS <= '0';
LDQS <= '0';
if (ExtModeRegister.DQSB_ENB = '0') then
UDQSB <= '1';
LDQSB <= '1';
else
UDQSB <= 'Z';
LDQSB <= 'Z';
end if;
elsif (DQS_S'event and DQS_S = 'Z' and DQS_S /= DQS_S'LAST_VALUE) then
UDQS <= 'Z';
LDQS <= 'Z';
UDQSB <= 'Z';
LDQSB <= 'Z';
end if;
else
UDQS <= 'Z';
LDQS <= 'Z';
UDQSB <= 'Z';
LDQSB <= 'Z';
end if;
end process;
-----------------------------------------------------------------------------------------------------
MEMORY_READ : process (DQS_S, CLK_DLY2, ExtModeRegister.OCD_PGM)
variable BkAdd : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
variable CRBI : integer := 0;
variable i, k, l : integer := 0;
begin
if (CLK_DLY2'EVENT and CLK_DLY2 = '1') then
if (casp6_rd = '1' or (ReadFlag = TRUE and yburst = '1')) then
if (casp6_rd = '1') then
BkAdd := ADD_PIPE_REG(ExtModeRegister.AL)(NUM_OF_BANK_ADD + NUM_OF_COL_ADD - 1 downto
NUM_OF_BANK_ADD + NUM_OF_COL_ADD - 2);
CRBI := 0;
end if;
if (BankActivatedFlag (conv_integer(BkAdd)) = '1') then
DataBuffer(i, 0) <= conv_std_logic_vector(SA_ARRAY (conv_integer(BkAdd))(conv_integer(real_col_addr(0))), WORD_SIZE);
DataBuffer(i, 1) <= conv_std_logic_vector(SA_ARRAY (conv_integer(BkAdd))(conv_integer(real_col_addr(1))), WORD_SIZE);
DataBuffer(i, 2) <= conv_std_logic_vector(SA_ARRAY (conv_integer(BkAdd))(conv_integer(real_col_addr(2))), WORD_SIZE);
DataBuffer(i, 3) <= conv_std_logic_vector(SA_ARRAY (conv_integer(BkAdd))(conv_integer(real_col_addr(3))), WORD_SIZE);
i := i + 1;
if (i = NUM_OF_BUFFERS) then
i := 0;
end if;
CRBI := CRBI + 4;
if (CRBI = ModeRegister.BURST_LENGTH) then
ReadFinFlag <= TRUE, FALSE after 2 ns;
CRBI := 0;
end if;
else
assert false report
"WARNING : (MEMORY_READ_PROCESS) : Accessing deactivated bank."
severity WARNING;
CRBI := CRBI + 4;
if (CRBI = ModeRegister.BURST_LENGTH) then
ReadFinFlag <= TRUE, FALSE after 2 ns;
CRBI := 0;
end if;
end if;
end if;
end if;
if (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = DRIVE0) then
DQ <= (others => '0');
elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = DRIVE1) then
DQ <= (others => '1');
elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = CAL_EXIT) then
DQ <= (others => 'Z');
end if;
if (DQS_S'EVENT and DQS_S = '1' and DQS_S'LAST_VALUE = '0' and WriteFlag = FALSE) then
DQ <= transport DataBuffer(k, l), (others => 'Z') after 0.5 * clk_cycle;
l := l + 1;
elsif (DQS_S'EVENT and DQS_S = '0' and DQS_S'LAST_VALUE = '1' and WriteFlag = FALSE) then
DQ <= transport DataBuffer(k, l), (others => 'Z') after 0.5 * clk_cycle;
if (l = 3) then
l := 0;
k := k + 1;
if (k = NUM_OF_BUFFERS) then
k := 0;
end if;
else
l := l + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
BURST_RD_WR_ADDR_GEN : process(CLK_DLY15, casp6_rd, casp6_wt, ReadFlag, WriteFlag)
variable CA : std_logic_vector ((NUM_OF_COL_ADD - 1) downto 0) := (others => 'X');
variable i, j : integer := 0;
variable col_addr_count : integer := 0;
begin
if ((ReadFlag = FALSE) and (WriteFlag = FALSE)) then
real_col_addr(0) <= (others => '0');
real_col_addr(1) <= (others => '0');
real_col_addr(2) <= (others => '0');
real_col_addr(3) <= (others => '0');
col_addr_count := 0;
i := 0;
j := 0;
end if;
if ((casp6_rd'EVENT and casp6_rd = '1') or (casp6_wt'EVENT and casp6_wt = '1') or
(CLK_DLY15'EVENT and CLK_DLY15 = '1' and yburst = '1')) then
if (casp6_rd = '1') then
CA := ADD_PIPE_REG(ExtModeRegister.AL)(NUM_OF_COL_ADD - 1 downto 0);
col_addr_count := 0;
i := 0;
j := 0;
elsif (casp6_wt = '1') then
CA := ADD_PIPE_REG(ExtModeRegister.AL + ModeRegister.CAS_LATENCY + 1)(NUM_OF_COL_ADD - 1 downto 0);
col_addr_count := 0;
i := 0;
j := 0;
end if;
if (col_addr_count < ModeRegister.BURST_LENGTH/4) then
loop
exit when (j > 3);
if ((col_addr_count = 0) and (j = 0)) then
real_col_addr(0) <= CA;
elsif (ModeRegister.BURST_LENGTH = 4) then
if (ModeRegister.BURST_MODE = SEQUENTIAL) then
real_col_addr(j) <= CA((NUM_OF_COL_ADD - 1) downto 2)&
conv_std_logic_vector(remainder((conv_integer(CA(1 downto 0)) + i), 4), 2);
elsif (ModeRegister.BURST_MODE = INTERLEAVE) then
real_col_addr(j) <= CA((NUM_OF_COL_ADD - 1) downto 2)&
xor_func(CA(1 downto 0), conv_std_logic_vector(i, 2));
end if;
elsif (ModeRegister.BURST_LENGTH = 8) then
if (ModeRegister.BURST_MODE = SEQUENTIAL) then
real_col_addr(j) <= CA((NUM_OF_COL_ADD - 1) downto 3)&
conv_std_logic_vector((conv_integer(CA(2)) + col_addr_count), 2)(0)&
conv_std_logic_vector(remainder((conv_integer(CA(1 downto 0)) + i), 4), 2);
elsif (ModeRegister.BURST_MODE = INTERLEAVE) then
real_col_addr(j) <= CA((NUM_OF_COL_ADD - 1) downto 3)&
xor_func(CA(2 downto 0), conv_std_logic_vector(i, 3));
end if;
end if;
i := i + 1;
j := j + 1;
end loop;
end if;
j := 0;
col_addr_count := col_addr_count + 1;
end if;
end process;
-----------------------------------------------------------------------------------------------------
MEMORY_WRITE : process (CLK_DLY2, LDQS, UDQS, CLK)
variable BkAdd : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
variable TMP_VALUE : std_logic_vector ((WORD_SIZE - 1) downto 0) := (others => '0');
variable WriteDriver : SA_TYPE;
variable i, j, k, l, m : integer := 0;
variable CWBI : integer := 0;
variable dq_buffL, dq_buffH : DATA_BUFFER_TYPE;
begin
if (CLK'event and CLK = '1') then
dq_buffL(0) := dq_bufferL(0);
dq_buffL(1) := dq_bufferL(1);
dq_buffL(2) := dq_bufferL(2);
dq_buffL(3) := dq_bufferL(3);
dq_buffH(0) := dq_bufferH(0);
dq_buffH(1) := dq_bufferH(1);
dq_buffH(2) := dq_bufferH(2);
dq_buffH(3) := dq_bufferH(3);
end if;
if (CLK_DLY2'EVENT and CLK_DLY2 = '1') then
if (casp6_wt = '1' or (WriteFlag = TRUE and yburst = '1')) then
if (casp6_wt = '1') then
BkAdd := ADD_PIPE_REG(ExtModeRegister.AL + ModeRegister.CAS_LATENCY + 1)
(NUM_OF_BANK_ADD + NUM_OF_COL_ADD - 1 downto NUM_OF_BANK_ADD + NUM_OF_COL_ADD - 2);
CWBI := 0;
WriteDriver := SA_ARRAY (conv_integer(BkAdd));
end if;
if (BankActivatedFlag (conv_integer(BkAdd)) = '1') then
TMP_VALUE := conv_std_logic_vector(WriteDriver(conv_integer(real_col_addr(0))), WORD_SIZE);
if (dq_buffL(0)(8) = '0' and dq_buffH(0)(8) = '0') then
TMP_VALUE := (dq_buffH(0)(7 downto 0) & dq_buffL(0)(7 downto 0));
elsif (dq_buffL(0)(8) = '0' and dq_buffH(0)(8) = '1') then
TMP_VALUE := (TMP_VALUE(15 downto 8) & dq_buffL(0)(7 downto 0));
elsif (dq_buffL(0)(8) = '1' and dq_buffH(0)(8) = '0') then
TMP_VALUE := (dq_buffH(0)(7 downto 0) & TMP_VALUE(7 downto 0));
elsif (dq_buffL(0)(8) = '1' and dq_buffH(0)(8) = '1') then
TMP_VALUE := (TMP_VALUE);
end if;
WriteDriver (conv_integer(real_col_addr(0))) := conv_integer(TMP_VALUE);
TMP_VALUE := conv_std_logic_vector(WriteDriver(conv_integer(real_col_addr(1))), WORD_SIZE);
if (dq_buffL(1)(8) = '0' and dq_buffH(1)(8) = '0') then
TMP_VALUE := (dq_buffH(1)(7 downto 0) & dq_buffL(1)(7 downto 0));
elsif (dq_buffL(1)(8) = '0' and dq_buffH(1)(8) = '1') then
TMP_VALUE := (TMP_VALUE(15 downto 8) & dq_buffL(1)(7 downto 0));
elsif (dq_buffL(1)(8) = '1' and dq_buffH(1)(8) = '0') then
TMP_VALUE := (dq_buffH(1)(7 downto 0) & TMP_VALUE(7 downto 0));
elsif (dq_buffL(1)(8) = '1' and dq_buffH(1)(8) = '1') then
TMP_VALUE := (TMP_VALUE);
end if;
WriteDriver (conv_integer(real_col_addr(1))) := conv_integer(TMP_VALUE);
TMP_VALUE := conv_std_logic_vector(WriteDriver(conv_integer(real_col_addr(2))), WORD_SIZE);
if (dq_buffL(2)(8) = '0' and dq_buffH(2)(8) = '0') then
TMP_VALUE := (dq_buffH(2)(7 downto 0) & dq_buffL(2)(7 downto 0));
elsif (dq_buffL(2)(8) = '0' and dq_buffH(2)(8) = '1') then
TMP_VALUE := (TMP_VALUE(15 downto 8) & dq_buffL(2)(7 downto 0));
elsif (dq_buffL(2)(8) = '1' and dq_buffH(2)(8) = '0') then
TMP_VALUE := (dq_buffH(2)(7 downto 0) & TMP_VALUE(7 downto 0));
elsif (dq_buffL(2)(8) = '1' and dq_buffH(2)(8) = '1') then
TMP_VALUE := (TMP_VALUE);
end if;
WriteDriver (conv_integer(real_col_addr(2))) := conv_integer(TMP_VALUE);
TMP_VALUE := conv_std_logic_vector(WriteDriver(conv_integer(real_col_addr(3))), WORD_SIZE);
if (dq_buffL(3)(8) = '0' and dq_buffH(3)(8) = '0') then
TMP_VALUE := (dq_buffH(3)(7 downto 0) & dq_buffL(3)(7 downto 0));
elsif (dq_buffL(3)(8) = '0' and dq_buffH(3)(8) = '1') then
TMP_VALUE := (TMP_VALUE(15 downto 8) & dq_buffL(3)(7 downto 0));
elsif (dq_buffL(3)(8) = '1' and dq_buffH(3)(8) = '0') then
TMP_VALUE := (dq_buffH(3)(7 downto 0) & TMP_VALUE(7 downto 0));
elsif (dq_buffL(3)(8) = '1' and dq_buffH(3)(8) = '1') then
TMP_VALUE := (TMP_VALUE);
end if;
WriteDriver (conv_integer(real_col_addr(3))) := conv_integer(TMP_VALUE);
if (conv_integer(BkAdd) = 0) then
SA_ARRAY_W0 <= WriteDriver;
tmp_w_trans0 <= '1', '0' after 2 ns;
b0_last_data_in <= (now - 2 ns);
elsif (conv_integer(BkAdd) = 1) then
SA_ARRAY_W1 <= WriteDriver;
tmp_w_trans1 <= '1', '0' after 2 ns;
b1_last_data_in <= (now - 2 ns);
elsif (conv_integer(BkAdd) = 2) then
SA_ARRAY_W2 <= WriteDriver;
tmp_w_trans2 <= '1', '0' after 2 ns;
b2_last_data_in <= (now - 2 ns);
elsif (conv_integer(BkAdd) = 3) then
SA_ARRAY_W3 <= WriteDriver;
tmp_w_trans3 <= '1', '0' after 2 ns;
b3_last_data_in <= (now - 2 ns);
end if;
CWBI := CWBI + 4;
if (CWBI = ModeRegister.BURST_LENGTH and casp_wtI /= '1' and caspwt /= '1') then
WriteFinFlag <= transport TRUE, FALSE after 2 ns;
CWBI := 0;
end if;
else
assert false report
"WARNING : (MEM_WRITE_PROCESS) : Accessing deactivated bank."
severity WARNING;
CWBI := CWBI + 4;
if (CWBI = ModeRegister.BURST_LENGTH and casp_wtI /= '1' and caspwt /= '1') then
WriteFinFlag <= transport TRUE, FALSE after 2 ns;
CWBI := 0;
end if;
end if;
end if;
end if;
if (LDQS'EVENT and LDQS = '0' and LDQS'LAST_VALUE = '1' and WriteFlag = TRUE) then
dq_bufferL(2) <= transport dq_bufferL(6);
dq_bufferL(1) <= transport dq_bufferL(5);
dq_bufferL(0) <= transport dq_bufferL(4);
dq_bufferL(3) <= transport (LDM & DQ(7 downto 0));
end if;
if (LDQS'EVENT and LDQS = '1' and WriteFlag = TRUE) then
dq_bufferL(5) <= transport dq_bufferL(3);
dq_bufferL(4) <= transport dq_bufferL(2);
dq_bufferL(6) <= transport (LDM & DQ(7 downto 0));
end if;
if (UDQS'EVENT and UDQS = '0' and UDQS'LAST_VALUE = '1' and WriteFlag = TRUE) then
dq_bufferH(2) <= transport dq_bufferH(6);
dq_bufferH(1) <= transport dq_bufferH(5);
dq_bufferH(0) <= transport dq_bufferH(4);
dq_bufferH(3) <= transport (UDM & DQ(15 downto 8));
end if;
if (UDQS'EVENT and UDQS = '1' and WriteFlag = TRUE) then
dq_bufferH(5) <= transport dq_bufferH(3);
dq_bufferH(4) <= transport dq_bufferH(2);
dq_bufferH(6) <= transport (UDM & DQ(15 downto 8));
end if;
end process;
-----------------------------------------------------------------------------------------------------
REFRESH_COUNTER : process(AutoRefFlag, SelfRefFlag, CLK)
variable rc : integer := 0;
begin
if (AutoRefFlag'EVENT and AutoRefFlag = TRUE and TimingCheckFlag = TRUE) then
if (rc >= 8192) then
rc := rc - 8192;
end if;
if (now - refresh_check(0, rc) > tREF) then
assert false report
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank0"
severity warning;
end if;
if (now - refresh_check(1, rc) > tREF) then
assert false report
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank1"
severity warning;
end if;
if (now - refresh_check(2, rc) > tREF) then
assert false report
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank2"
severity warning;
end if;
if (now - refresh_check(3, rc) > tREF) then
assert false report
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank3"
severity warning;
end if;
tmp_ref_addr1 <= conv_std_logic_vector (rc, NUM_OF_ROW_ADD);
tmp_ref_addr1_trans <= transport '1', '0' after 1 ns;
rc := rc + 1;
end if;
if (CLK'EVENT and CLK = '1') then
if (SelfRefFlag = TRUE and TimingCheckFlag = TRUE) then
Ref_time <= Ref_time + clk_cycle;
if (Ref_time >= 7812.5 ns/(conv_integer(ExtModeRegister2.SREF_HOT) + 1)) then
Ref_time <= 0 ns;
if (rc >= 8192) then
rc := rc - 8192;
end if;
if (now - refresh_check(0, rc) > tREF) then
assert false report
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank0"
severity warning;
end if;
if (now - refresh_check(1, rc) > tREF) then
assert false report
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank1"
severity warning;
end if;
if (now - refresh_check(2, rc) > tREF) then
assert false report
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank2"
severity warning;
end if;
if (now - refresh_check(3, rc) > tREF) then
assert false report
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank3"
severity warning;
end if;
tmp_ref_addr1 <= conv_std_logic_vector (rc, NUM_OF_ROW_ADD);
tmp_ref_addr1_trans <= transport '1', '0' after 1 ns;
rc := rc + 1;
end if;
end if;
end if;
if (SelfRefFlag = FALSE) then
Ref_time <= 0 ns;
end if;
end process;
-----------------------------------------------------------------------------------------------------
PUS_CHECK : process(CLK, PrechargeAllFlag, AutoRefFlag, ModeRegister.DLL_STATE)
variable ChipSelectBar : std_logic := '0';
variable RowAddrStrobeBar : std_logic := '0';
variable ColAddrStrobeBar : std_logic := '0';
variable WriteEnableBar : std_logic := '0';
variable Address10 : std_logic := '0';
variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
variable ClockEnable : CKE_TYPE := (others => '0');
variable CurrentCommand : COMMAND_TYPE := NOP;
variable i, j : integer := 0;
variable PUSNOP200USFlag : boolean := FALSE;
variable PUSAREF2Flag : boolean := FALSE;
variable BankActFlag : std_logic_vector((NUM_OF_BANKS - 1) downto 0) := (others => '0');
variable pus_aref : integer := 0;
variable Cur_State : STATE_TYPE := IDLE;
begin
if (PUSCheckFinFlag /= TRUE and PUSCheckFlag = TRUE) then
if (CLK'EVENT and CLK = '1') then
cur_time <= transport now;
-- if (cur_time < 200000 ns) then
-- if (CKE /= '0') then
-- assert false report
-- "ERROR : (Power Up Sequence) : CKE Should Be '0' during initial 200us!"
-- severity error;
-- end if;
-- end if;
end if;
if (ModeRegister.DLL_STATE'EVENT and ModeRegister.DLL_STATE = RST and PUS_DLL_RESET = FALSE) then
PUS_DLL_RESET <= TRUE;
end if;
if (PrechargeAllFlag'EVENT and PrechargeAllFlag = TRUE and CurrentState = PWRUP and TimingCheckFlag = TRUE) then
if (PUSPCGAFlag1 = TRUE) then
assert (PUS_DLL_RESET = TRUE) report
"ERROR : (Power Up Sequence) : The 2nd PCGA Command Should Be Issued after DLL Reset!"
severity error;
else
PUSPCGAFlag1 <= TRUE;
-- assert (cur_time >= tPUS - clk_cycle) report
-- "WARNING : (Power Up Sequence) : PCGA Command Should Be Issued after 200us(Input Stable)!"
-- severity warning;
end if;
end if;
if (AutoRefFlag'EVENT and AutoRefFlag = TRUE) then
assert (PUSPCGAFlag2 = TRUE) report
"WARNING : (Power Up Sequence) : Needs Precharge All Bank Command before Auto Refresh !"
severity warning;
pus_aref := pus_aref + 1;
if (pus_aref >= 2) then
PUSAREF2Flag := TRUE;
end if;
if ((PUSNOP200USFlag = TRUE) and (PUSAREF2Flag = TRUE)) then
PUSCheckFinFlag <= TRUE;
end if;
end if;
ClockEnable := CKEN;
if ClockEnable (-1) = '1' then
ChipSelectBar := CSB;
RowAddrStrobeBar := RASB;
ColAddrStrobeBar := CASB;
WriteEnableBar := WEB;
Address10 := ADDR(10);
BkAdd := (BA);
BankActFlag := BankActivatedFlag;
end if;
COMMAND_DECODE (ChipSelectBar, RowAddrStrobeBar, ColAddrStrobeBar, WriteEnableBar,
Address10, BkAdd, ClockEnable, CurrentCommand, BankActFlag, Cur_State);
if ((PUSNOP200USFlag = FALSE) and (PUSAREF2Flag /= TRUE)) then
if (CLK = '1') then
i := i + 1;
-- if (i * clk_cycle >= tPUS - clk_cycle) then
PUSNOP200USFlag := TRUE;
-- end if;
end if;
elsif ((CurrentCommand = PCGA) and (PUSNOP200USFlag = TRUE) and (PUSPCGAFlag1 = TRUE) and (PUSAREF2Flag /= TRUE)) then
PUSPCGAFlag2 <= TRUE;
end if;
elsif (PUSCheckFinFlag /= TRUE and PUSCheckFlag = FALSE) then
PUSCheckFinFlag <= TRUE;
end if;
end process;
-----------------------------------------------------------------------------------------------------
BUS_CHANGE_DETECT : process(CKE, WEB, CASB, RASB, CSB, LDM, UDM, ADDR, DQ)
begin
if (CKE'EVENT and CKE /= CKE'LAST_VALUE) then
cke_ch <= transport now after 0.1 ns; end if;
if (WEB'EVENT and WEB /= WEB'LAST_VALUE) then
web_ch <= transport now after 0.1 ns; end if;
if (CASB'EVENT and CASB /= CASB'LAST_VALUE) then
casb_ch <= transport now after 0.1 ns; end if;
if (RASB'EVENT and RASB /= RASB'LAST_VALUE) then
rasb_ch <= transport now after 0.1 ns; end if;
if (CSB'EVENT and CSB /= CSB'LAST_VALUE) then
csb_ch <= transport now after 0.1 ns; end if;
if (LDM'EVENT and LDM /= LDM'LAST_VALUE) then
ldm_ch <= transport now after 0.1 ns; end if;
if (UDM'EVENT and UDM /= UDM'LAST_VALUE) then
udm_ch <= transport now after 0.1 ns; end if;
if (ADDR(0)'EVENT and ADDR(0) /= ADDR(0)'LAST_VALUE) then
a0_ch <= transport now after 0.1 ns; end if;
if (ADDR(1)'EVENT and ADDR(1) /= ADDR(1)'LAST_VALUE) then
a1_ch <= transport now after 0.1 ns; end if;
if (ADDR(2)'EVENT and ADDR(2) /= ADDR(2)'LAST_VALUE) then
a2_ch <= transport now after 0.1 ns; end if;
if (ADDR(3)'EVENT and ADDR(3) /= ADDR(3)'LAST_VALUE) then
a3_ch <= transport now after 0.1 ns; end if;
if (ADDR(4)'EVENT and ADDR(4) /= ADDR(4)'LAST_VALUE) then
a4_ch <= transport now after 0.1 ns; end if;
if (ADDR(5)'EVENT and ADDR(5) /= ADDR(5)'LAST_VALUE) then
a5_ch <= transport now after 0.1 ns; end if;
if (ADDR(6)'EVENT and ADDR(6) /= ADDR(6)'LAST_VALUE) then
a6_ch <= transport now after 0.1 ns; end if;
if (ADDR(7)'EVENT and ADDR(7) /= ADDR(7)'LAST_VALUE) then
a7_ch <= transport now after 0.1 ns; end if;
if (ADDR(8)'EVENT and ADDR(8) /= ADDR(8)'LAST_VALUE) then
a8_ch <= transport now after 0.1 ns; end if;
if (ADDR(9)'EVENT and ADDR(9) /= ADDR(9)'LAST_VALUE) then
a9_ch <= transport now after 0.1 ns; end if;
if (ADDR(10)'EVENT and ADDR(10) /= ADDR(10)'LAST_VALUE) then
a10_ch <= transport now after 0.1 ns; end if;
if (ADDR(11)'EVENT and ADDR(11) /= ADDR(11)'LAST_VALUE) then
a11_ch <= transport now after 0.1 ns; end if;
if (ADDR(12)'EVENT and ADDR(12) /= ADDR(12)'LAST_VALUE) then
a12_ch <= transport now after 0.1 ns; end if;
if (BA(0)'EVENT and BA(0) /= BA(0)'LAST_VALUE) then
ba0_ch <= transport now after 0.1 ns; end if;
if (BA(1)'EVENT and BA(1) /= BA(1)'LAST_VALUE) then
ba1_ch <= transport now after 0.1 ns; end if;
if (DQ(0)'EVENT and STD_LOGIC_TO_BIT (DQ(0)) /= STD_LOGIC_TO_BIT (DQ(0)'LAST_VALUE)) then
dq0_ch <= transport now after 0.1 ns; end if;
if (DQ(1)'EVENT and STD_LOGIC_TO_BIT (DQ(1)) /= STD_LOGIC_TO_BIT (DQ(1)'LAST_VALUE)) then
dq1_ch <= transport now after 0.1 ns; end if;
if (DQ(2)'EVENT and STD_LOGIC_TO_BIT (DQ(2)) /= STD_LOGIC_TO_BIT (DQ(2)'LAST_VALUE)) then
dq2_ch <= transport now after 0.1 ns; end if;
if (DQ(3)'EVENT and STD_LOGIC_TO_BIT (DQ(3)) /= STD_LOGIC_TO_BIT (DQ(3)'LAST_VALUE)) then
dq3_ch <= transport now after 0.1 ns; end if;
if (DQ(4)'EVENT and STD_LOGIC_TO_BIT (DQ(4)) /= STD_LOGIC_TO_BIT (DQ(4)'LAST_VALUE)) then
dq4_ch <= transport now after 0.1 ns; end if;
if (DQ(5)'EVENT and STD_LOGIC_TO_BIT (DQ(5)) /= STD_LOGIC_TO_BIT (DQ(5)'LAST_VALUE)) then
dq5_ch <= transport now after 0.1 ns; end if;
if (DQ(6)'EVENT and STD_LOGIC_TO_BIT (DQ(6)) /= STD_LOGIC_TO_BIT (DQ(6)'LAST_VALUE)) then
dq6_ch <= transport now after 0.1 ns; end if;
if (DQ(7)'EVENT and STD_LOGIC_TO_BIT (DQ(7)) /= STD_LOGIC_TO_BIT (DQ(7)'LAST_VALUE)) then
dq7_ch <= transport now after 0.1 ns; end if;
if (DQ(8)'EVENT and STD_LOGIC_TO_BIT (DQ(8)) /= STD_LOGIC_TO_BIT (DQ(8)'LAST_VALUE)) then
dq8_ch <= transport now after 0.1 ns; end if;
if (DQ(9)'EVENT and STD_LOGIC_TO_BIT (DQ(9)) /= STD_LOGIC_TO_BIT (DQ(9)'LAST_VALUE)) then
dq9_ch <= transport now after 0.1 ns; end if;
if (DQ(10)'EVENT and STD_LOGIC_TO_BIT (DQ(10)) /= STD_LOGIC_TO_BIT (DQ(10)'LAST_VALUE)) then
dq10_ch <= transport now after 0.1 ns; end if;
if (DQ(11)'EVENT and STD_LOGIC_TO_BIT (DQ(11)) /= STD_LOGIC_TO_BIT (DQ(11)'LAST_VALUE)) then
dq11_ch <= transport now after 0.1 ns; end if;
if (DQ(12)'EVENT and STD_LOGIC_TO_BIT (DQ(12)) /= STD_LOGIC_TO_BIT (DQ(12)'LAST_VALUE)) then
dq12_ch <= transport now after 0.1 ns; end if;
if (DQ(13)'EVENT and STD_LOGIC_TO_BIT (DQ(13)) /= STD_LOGIC_TO_BIT (DQ(13)'LAST_VALUE)) then
dq13_ch <= transport now after 0.1 ns; end if;
if (DQ(14)'EVENT and STD_LOGIC_TO_BIT (DQ(14)) /= STD_LOGIC_TO_BIT (DQ(14)'LAST_VALUE)) then
dq14_ch <= transport now after 0.1 ns; end if;
if (DQ(15)'EVENT and STD_LOGIC_TO_BIT (DQ(15)) /= STD_LOGIC_TO_BIT (DQ(15)'LAST_VALUE)) then
dq15_ch <= transport now after 0.1 ns; end if;
end process;
-----------------------------------------------------------------------------------------------------
CLK_TIMING : process (CLK)
variable clk_last_cycle : time := 0 ns;
variable i : integer := 0;
begin
if (CLK'event and CLK='1') then
if (Part_Number = B400) then
tRCD <= ModeRegister.CAS_LATENCY * 5 ns;
tRP <= ModeRegister.CAS_LATENCY * 5 ns;
if (ModeRegister.CAS_LATENCY = 3) then
tRAS <= 40 ns;
else
tRAS <= 45 ns;
end if;
elsif (Part_Number = B533) then
tRCD <= ModeRegister.CAS_LATENCY * 3.75 ns;
tRP <= ModeRegister.CAS_LATENCY * 3.75 ns;
tRAS <= 45 ns;
elsif (Part_Number = B667) then
tRCD <= ModeRegister.CAS_LATENCY * 3 ns;
tRP <= ModeRegister.CAS_LATENCY * 3 ns;
tRAS <= 45 ns;
elsif (Part_Number = B800) then
tRCD <= ModeRegister.CAS_LATENCY * 2.5 ns;
tRP <= ModeRegister.CAS_LATENCY * 2.5 ns;
tRAS <= 45 ns;
end if;
tRC <= tRAS + tRP;
tCCD <= 2 * clk_cycle;
tDQSH <= 0.35 * clk_cycle;
tDQSL <= 0.35 * clk_cycle;
tWPSTmin <= 0.4 * clk_cycle;
tWPSTmax <= 0.6 * clk_cycle;
tDQSSmin <= 0.75 * clk_cycle;
tDQSSmax <= 1.25 * clk_cycle;
tMRD <= 2 * clk_cycle;
tWPRE <= 0.25 * clk_cycle;
tCH <= 0.45 * clk_cycle;
tCL <= 0.45 * clk_cycle;
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
assert (clk_cycle >= tCKmin (Part_Number)) report
"ERROR : (CLK_TIMING) : Clock period is too small."
severity error;
assert (clk_cycle <= tCKmax (Part_Number)) report
"ERROR : (CLK_TIMING) : Clock period is too large."
severity error;
end if;
assert (now - clk_last_falling >= tCL) report
"ERROR : (CLK_TIMING) : Clock low time is too small."
severity error;
clk_last_rising <= transport now;
end if;
if (CLK'event and CLK = '0') then
clk_last_falling <= transport now;
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
assert (now - clk_last_rising >= tCH) report
"ERROR : (CLK_TIMING) : Clock high time is too small."
severity error;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
DQS_TIMING : process (LDQS, UDQS, caspwt)
begin
if (caspwt'EVENT and caspwt = '1') then
wr_cmd_time <= transport now - 1 ns;
udspre_enable <= '0';
ldspre_enable <= '0';
udsh_dsl_enable <= '0';
ldsh_dsl_enable <= '0';
end if;
if (TimingCheckFlag = TRUE) then
if (UDQS'EVENT and UDQS = '0' and UDQS'LAST_VALUE = 'Z' and WriteFlag = TRUE) then
udspre_enable <= '1';
end if;
if (LDQS'EVENT and LDQS = '0' and LDQS'LAST_VALUE = 'Z' and WriteFlag = TRUE) then
ldspre_enable <= '1';
end if;
if (UDQS'EVENT and UDQS = '1' and UDQS'LAST_VALUE = '0' and WriteFlag = TRUE) then
udqs_last_rising <= transport now;
if (udspre_enable = '1') then
if ((now - clk_last_falling) < tWPRE) then
assert false report
"WARNING : (tWPRE_CHECK) : tWPRE time violation!"
severity WARNING;
end if;
if ((now - wr_cmd_time) < tDQSSmin) then
assert false report
"WARNING : (tDQSS_CHECK) : Minimum tDQSS time violation!"
severity WARNING;
end if;
if ((now - wr_cmd_time) > tDQSSmax) then
assert false report
"WARNING : (tDQSS_CHECK) : Maximum tDQSS time violation!"
severity WARNING;
end if;
udspre_enable <= '0';
udsh_dsl_enable <= '1';
elsif (udsh_dsl_enable = '1') then
if ((now - udqs_last_falling) < tDQSL) then
assert false report
"ERROR : (tDQSL_CHECK) : Minimum tDQSL time violation!"
severity ERROR;
end if;
end if;
elsif (UDQS'EVENT and UDQS = '0' and UDQS'LAST_VALUE = '1' and WriteFlag = TRUE) then
udqs_last_falling <= transport now;
if (udsh_dsl_enable = '1') then
if ((now - udqs_last_rising) < tDQSH) then
assert false report
"ERROR : (tDQSH_CHECK) : Minimum tDQSH time violation!"
severity ERROR;
end if;
end if;
udspre_enable <= '0';
ldspre_enable <= '0';
end if;
if (LDQS'EVENT and LDQS = '1' and LDQS'LAST_VALUE = '0' and WriteFlag = TRUE) then
ldqs_last_rising <= transport now;
if (ldspre_enable = '1') then
if ((now - clk_last_falling) < tWPRE) then
assert false report
"WARNING : (tWPRE_CHECK) : tWPRE time violation!"
severity WARNING;
end if;
if ((now - wr_cmd_time) < tDQSSmin) then
assert false report
"WARNING : (tDQSS_CHECK) : Minimum tDQSS time violation!"
severity WARNING;
end if;
if ((now - wr_cmd_time) > tDQSSmax) then
assert false report
"WARNING : (tDQSS_CHECK) : Maximum tDQSS time violation!"
severity WARNING;
end if;
ldspre_enable <= '0';
ldsh_dsl_enable <= '1';
elsif (ldsh_dsl_enable = '1') then
if ((now - ldqs_last_falling) < tDQSL) then
assert false report
"ERROR : (tDQSL_CHECK) : Minimum tDQSL time violation!"
severity ERROR;
end if;
end if;
elsif (LDQS'EVENT and LDQS = '0' and LDQS'LAST_VALUE = '1' and WriteFlag = TRUE) then
ldqs_last_falling <= transport now;
if (ldsh_dsl_enable = '1') then
if ((now - ldqs_last_rising) < tDQSH) then
assert false report
"ERROR : (tDQSH_CHECK) : Minimum tDQSH time violation!"
severity ERROR;
end if;
end if;
udspre_enable <= '0';
ldspre_enable <= '0';
end if;
if (LDQS'EVENT and LDQS = 'Z' and LDQS'LAST_VALUE = '0' and WriteFlag = TRUE and caspwt = '0') then
if ((now - ldqs_last_falling) < tWPSTmin) then
assert false report
"WARNING : (tWPST_CHECK) : Minimum tWPST time violation!"
severity WARNING;
end if;
if ((now - ldqs_last_falling) > tWPSTmax) then
assert false report
"WARNING : (tWPST_CHECK) : Maximum tWPST time violation!"
severity WARNING;
end if;
ldspre_enable <= '0';
ldsh_dsl_enable <= '0';
end if;
if (UDQS'EVENT and UDQS = 'Z' and UDQS'LAST_VALUE = '0' and WriteFlag = TRUE and caspwt = '0') then
if ((now - udqs_last_falling) < tWPSTmin) then
assert false report
"WARNING : (tWPST_CHECK) : Minimum tWPST time violation!"
severity WARNING;
end if;
if ((now - udqs_last_falling) > tWPSTmax) then
assert false report
"WARNING : (tWPST_CHECK) : Maximum tWPST time violation!"
severity WARNING;
end if;
udspre_enable <= '0';
udsh_dsl_enable <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
SETUP_CHECK : process (CLK, UDQS, LDQS)
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
if (((UDQS'EVENT and UDQS = '1' and UDQS'LAST_VALUE = '0') or (UDQS'EVENT and UDQS = '0') or
(LDQS'EVENT and LDQS = '1' and LDQS'LAST_VALUE = '0') or (LDQS'EVENT and LDQS = '0')) and
(WriteFlag = TRUE)) then
assert (
((now - dq0_ch) >= tDS (Part_Number)) and
((now - dq1_ch) >= tDS (Part_Number)) and
((now - dq2_ch) >= tDS (Part_Number)) and
((now - dq3_ch) >= tDS (Part_Number)) and
((now - dq4_ch) >= tDS (Part_Number)) and
((now - dq5_ch) >= tDS (Part_Number)) and
((now - dq6_ch) >= tDS (Part_Number)) and
((now - dq7_ch) >= tDS (Part_Number)) and
((now - dq8_ch) >= tDS (Part_Number)) and
((now - dq9_ch) >= tDS (Part_Number)) and
((now - dq10_ch) >= tDS (Part_Number)) and
((now - dq11_ch) >= tDS (Part_Number)) and
((now - dq12_ch) >= tDS (Part_Number)) and
((now - dq13_ch) >= tDS (Part_Number)) and
((now - dq14_ch) >= tDS (Part_Number)) and
((now - dq15_ch) >= tDS (Part_Number))) report
"ERROR : (SETUP_HOLD) : Data input setup/hold time violation."
severity error;
end if;
if (CLK'EVENT and CLK = '1') then
assert (
((now - a0_ch) >= tIS (Part_Number)) and
((now - a1_ch) >= tIS (Part_Number)) and
((now - a2_ch) >= tIS (Part_Number)) and
((now - a3_ch) >= tIS (Part_Number)) and
((now - a4_ch) >= tIS (Part_Number)) and
((now - a5_ch) >= tIS (Part_Number)) and
((now - a6_ch) >= tIS (Part_Number)) and
((now - a7_ch) >= tIS (Part_Number)) and
((now - a8_ch) >= tIS (Part_Number)) and
((now - a9_ch) >= tIS (Part_Number)) and
((now - a10_ch) >= tIS (Part_Number)) and
((now - a11_ch) >= tIS (Part_Number)) and
((now - a12_ch) >= tIS (Part_Number)) and
((now - ba0_ch) >= tIS (Part_Number)) and
((now - ba1_ch) >= tIS (Part_Number))) report
"ERROR : (SETUP_HOLD) : Address input setup time violation."
severity error;
assert (
((now - csb_ch) >= tIS (Part_Number)) and
((now - rasb_ch) >= tIS (Part_Number)) and
((now - casb_ch) >= tIS (Part_Number)) and
((now - web_ch) >= tIS (Part_Number))) report
"ERROR : (SETUP_HOLD) : Command input setup time violation."
severity error;
assert (now - cke_ch >= tIS (Part_Number)) report
"ERROR : (SETUP_HOLD) : Clock enable input setup time violation."
severity error;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
DM_SETUP_HOLD_CHECK : process (LDM, UDM, LDQS, UDQS)
begin
if (TimingCheckFlag = TRUE) then
if (LDM'EVENT and LDM = '1' and WriteFlag = TRUE) then
ldm_last_rising <= transport now;
elsif (LDM'EVENT and LDM = '0' and WriteFlag = TRUE) then
if ((now - ldqs_last_rising) < tDH (Part_Number)) then
assert false report
"ERROR : (tDH_CHECK) : LDM Hold Time Violation!"
severity ERROR;
end if;
end if;
if (UDM'EVENT and UDM = '1' and WriteFlag = TRUE) then
udm_last_rising <= transport now;
elsif (UDM'EVENT and UDM = '0' and WriteFlag = TRUE) then
if ((now - udqs_last_rising) < tDH (Part_Number)) then
assert false report
"ERROR : (tDH_CHECK) : UDM Hold Time Violation!"
severity ERROR;
end if;
end if;
if (LDQS'EVENT and LDQS = '1' and LDQS'LAST_VALUE = '0' and WriteFlag = TRUE) then
if ((now - ldm_last_rising) < tDS (Part_Number)) then
assert false report
"ERROR : (tDS_CHECK) : LDM Setup Time Violation!"
severity ERROR;
end if;
end if;
if (UDQS'EVENT and UDQS = '1' and UDQS'LAST_VALUE = '0' and WriteFlag = TRUE) then
if ((now - udm_last_rising) < tDS (Part_Number)) then
assert false report
"ERROR : (tDS_CHECK) : UDM Setup Time Violation!"
severity ERROR;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
A_HOLD_CHECK : process (ADDR)
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
assert ((now - clk_last_rising) >= tIH (Part_Number)) report
"ERROR : (SETUP_HOLD) : Address hold time violation."
severity error;
end if;
end process;
-----------------------------------------------------------------------------------------------------
UDQ_HOLD_CHECK : process (DQ(15 downto 8))
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE and WriteFlag = TRUE) then
assert ((now - udqs_last_rising) >= tDH (Part_Number)) report
"ERROR : (SETUP_HOLD) : Hold time violation of CLK rising-edge aligned data."
severity error;
assert ((now - udqs_last_falling) >= tDH (Part_Number)) report
"ERROR : (SETUP_HOLD) : Hold time violation of CLK falling-edge aligned data."
severity error;
end if;
end process;
-----------------------------------------------------------------------------------------------------
LDQ_HOLD_CHECK : process (DQ(7 downto 0))
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE and WriteFlag = TRUE) then
assert ((now - ldqs_last_rising) >= tDH (Part_Number)) report
"ERROR : (SETUP_HOLD) : Hold time violation of CLK rising-edge aligned data."
severity error;
assert ((now - udqs_last_falling) >= tDH (Part_Number)) report
"ERROR : (SETUP_HOLD) : Hold time violation of CLK falling-edge aligned data."
severity error;
end if;
end process;
-----------------------------------------------------------------------------------------------------
CMD_HOLD_CHECK : process (CSB, WEB, RASB, CASB)
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
assert ((now - clk_last_rising) >= tIH (Part_Number)) report
"ERROR : (SETUP_HOLD) : Command hold time violation."
severity error;
end if;
end process;
-----------------------------------------------------------------------------------------------------
CKE_HOLD_CHECK : process (CKE)
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
assert ((now - clk_last_rising) >= tIH (Part_Number)) report
"ERROR : (SETUP_HOLD) : Clock enable hold time violation."
severity error;
end if;
end process;
-----------------------------------------------------------------------------------------------------
tRC_CHECK : process (BankActivateFlag)
variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
BkAdd := (BA);
if (BkAdd = "00" and (BankActivateFlag'EVENT and BankActivateFlag = TRUE)) then
assert ((now - b0_last_activate) >= tRC) report
"ERROR : (tRC_CHECK) : Row Address Strobe cycle time violation."
severity error;
elsif (BkAdd = "01" and (BankActivateFlag'EVENT and BankActivateFlag = TRUE)) then
assert ((now - b1_last_activate) >= tRC) report
"ERROR : (tRC_CHECK) : Row Address Strobe cycle time violation."
severity error;
elsif (BkAdd = "10" and (BankActivateFlag'EVENT and BankActivateFlag = TRUE)) then
assert ((now - b2_last_activate) >= tRC) report
"ERROR : (tRC_CHECK) : Row Address Strobe cycle time violation."
severity error;
elsif (BkAdd = "11" and (BankActivateFlag'EVENT and BankActivateFlag = TRUE)) then
assert ((now - b3_last_activate) >= tRC) report
"ERROR : (tRC_CHECK) : Row Address Strobe cycle time violation."
severity error;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
tRCD_CHECK : process (casp6_rd, casp6_wt)
variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
BkAdd := (BA);
if (BkAdd = "00" and ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1'))) then
assert ((now - b0_last_activate - 1.5 ns) >= tRCD) report
"ERROR : (tRCD_CHECK) : Active to column Access delay time violation."
severity error;
b0_last_column_access <= transport now after 1 ns;
elsif (BkAdd = "01" and ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1'))) then
assert ((now - b1_last_activate - 1.5 ns) >= tRCD) report
"ERROR : (tRCD_CHECK) : Active to column Access delay time violation."
severity error;
b1_last_column_access <= transport now after 1 ns;
elsif (BkAdd = "10" and ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1'))) then
assert ((now - b2_last_activate - 1.5 ns) >= tRCD) report
"ERROR : (tRCD_CHECK) : Active to column Access delay time violation."
severity error;
b2_last_column_access <= transport now after 1 ns;
elsif (BkAdd = "11" and ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1'))) then
assert ((now - b3_last_activate - 1.5 ns) >= tRCD) report
"ERROR : (tRCD_CHECK) : Active to column Access delay time violation."
severity error;
b3_last_column_access <= transport now after 1 ns;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
tRAS_CHECK : process (BankActivatedFlag(0), BankActivatedFlag(1), BankActivatedFlag(2), BankActivatedFlag(3))
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
if (BankActivatedFlag(0)'EVENT and BankActivatedFlag(0) = '0' and BankActivatedFlag(0)'LAST_VALUE = '1') then
assert ((now - b0_last_activate) >= tRAS) report
"ERROR : (tRAS_CHECK) : Bank0 active time minimum violation."
severity error;
assert ((now - b0_last_activate) <= tRASmax (Part_Number)) report
"ERROR : (tRAS_CHECK) : Bank0 active time maximum violation."
severity error;
end if;
if (BankActivatedFlag(1)'EVENT and BankActivatedFlag(1) = '0' and BankActivatedFlag(1)'LAST_VALUE = '1') then
assert ((now - b1_last_activate) >= tRAS) report
"ERROR : (tRAS_CHECK) : Bank1 active time minimum violation."
severity error;
assert ((now - b1_last_activate) <= tRASmax (Part_Number)) report
"ERROR : (tRAS_CHECK) : Bank1 active time maximum violation."
severity error;
end if;
if (BankActivatedFlag(2)'EVENT and BankActivatedFlag(2) = '0' and BankActivatedFlag(2)'LAST_VALUE = '1') then
assert ((now - b2_last_activate) >= tRAS) report
"ERROR : (tRAS_CHECK) : Bank2 active time minimum violation."
severity error;
assert ((now - b2_last_activate) <= tRASmax (Part_Number)) report
"ERROR : (tRAS_CHECK) : Bank2 active time maximum violation."
severity error;
end if;
if (BankActivatedFlag(3)'EVENT and BankActivatedFlag(3) = '0' and BankActivatedFlag(3)'LAST_VALUE = '1') then
assert ((now - b3_last_activate) >= tRAS) report
"ERROR : (tRAS_CHECK) : Bank3 active time minimum violation."
severity error;
assert ((now - b3_last_activate) <= tRASmax (Part_Number)) report
"ERROR : (tRAS_CHECK) : Bank3 active time maximum violation."
severity error;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
tRP_CHECK : process (BankActivateFlag)
variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
BkAdd := (BA);
if (BkAdd = "00" and (BankActivateFlag'event and BankActivateFlag = TRUE)) then
assert ((now - b0_last_precharge) >= tRP) report
"ERROR : (tRP_CHECK) : Precharge to active delay time violation."
severity error;
elsif (BkAdd = "01" and (BankActivateFlag'event and BankActivateFlag = TRUE)) then
assert ((now - b1_last_precharge) >= tRP) report
"ERROR : (tRP_CHECK) : Precharge to active delay time violation."
severity error;
elsif (BkAdd = "10" and (BankActivateFlag'event and BankActivateFlag = TRUE)) then
assert ((now - b2_last_precharge) >= tRP) report
"ERROR : (tRP_CHECK) : Precharge to active delay time violation."
severity error;
elsif (BkAdd = "11" and (BankActivateFlag'event and BankActivateFlag = TRUE)) then
assert ((now - b3_last_precharge) >= tRP) report
"ERROR : (tRP_CHECK) : Precharge to active delay time violation."
severity error;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
tRRD_CHECK : process (BankActivateFlag)
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
if (BankActivateFlag'EVENT and BankActivateFlag = TRUE) then
assert ((now - b0_last_activate) >= tRRD) report
"ERROR : (tRRD_CHECK) : Active to the other bank active delay time violation."
severity error;
assert ((now - b1_last_activate) >= tRRD) report
"ERROR : (tRRD_CHECK) : Active to the other bank active delay time violation."
severity error;
assert ((now - b2_last_activate) >= tRRD) report
"ERROR : (tRRD_CHECK) : Active to the other bank active delay time violation."
severity error;
assert ((now - b3_last_activate) >= tRRD) report
"ERROR : (tRRD_CHECK) : Active to the other bank active delay time violation."
severity error;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
tCCD_CHECK : process (casp6_rd, casp6_wt)
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
if ((casp6_rd'EVENT and casp6_rd = '1') or (casp6_wt'EVENT and casp6_wt = '1')) then
assert ((now - b0_last_column_access) >= tCCD) report
"ERROR : (tCCD_CHECK) : Column access to column access delay time violation."
severity error;
assert ((now - b1_last_column_access) >= tCCD) report
"ERROR : (tCCD_CHECK) : Column access to column access delay time violation."
severity error;
assert ((now - b2_last_column_access) >= tCCD) report
"ERROR : (tCCD_CHECK) : Column access to column access delay time violation."
severity error;
assert ((now - b3_last_column_access) >= tCCD) report
"ERROR : (tCCD_CHECK) : Column access to column access delay time violation."
severity error;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
tWR_CHECK : process (PrechargeFlag, PrechargeAllFlag)
variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
BkAdd := (BA);
if (BkAdd = "00" and (PrechargeFlag'EVENT and PrechargeFlag = TRUE)) then
assert ((now - b0_last_data_in) >= tWR(Part_Number)) report
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
severity error;
elsif (BkAdd = "01" and (PrechargeFlag'EVENT and PrechargeFlag = TRUE)) then
assert ((now - b1_last_data_in) >= tWR(Part_Number)) report
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
severity error;
elsif (BkAdd = "10" and (PrechargeFlag'EVENT and PrechargeFlag = TRUE)) then
assert ((now - b2_last_data_in) >= tWR(Part_Number)) report
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
severity error;
elsif (BkAdd = "11" and (PrechargeFlag'EVENT and PrechargeFlag = TRUE)) then
assert ((now - b3_last_data_in) >= tWR(Part_Number)) report
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
severity error;
elsif (PrechargeAllFlag'EVENT and PrechargeAllFlag = TRUE) then
assert ((now - b0_last_data_in) >= tWR(Part_Number)) report
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
severity error;
assert ((now - b1_last_data_in) >= tWR(Part_Number)) report
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
severity error;
assert ((now - b2_last_data_in) >= tWR(Part_Number)) report
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
severity error;
assert ((now - b3_last_data_in) >= tWR(Part_Number)) report
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
severity error;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
tWTR_CHECK : process (casp6_rd)
begin
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
if (casp6_rd'event and casp6_rd = '1') then
assert ((now - b0_last_data_in - 1 ns) >= tWTR) report
"ERROR : (tWTR_CHECK) : Last data in to read command delay violation."
severity error;
assert ((now - b1_last_data_in - 1 ns) >= tWTR) report
"ERROR : (tWTR_CHECK) : Last data in to read command delay violation."
severity error;
assert ((now - b2_last_data_in - 1 ns) >= tWTR) report
"ERROR : (tWTR_CHECK) : Last data in to read command delay violation."
severity error;
assert ((now - b3_last_data_in - 1 ns) >= tWTR) report
"ERROR : (tWTR_CHECK) : Last data in to read command delay violation."
severity error;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
tMRD_CHECK : process (mrs_cmd_in)
begin
if (mrs_cmd_in'event and mrs_cmd_in = '1') then
assert ((now - last_mrs_set) >= tMRD) report
"ERROR : (tMRD_CHECK) : MRS to MRS delay violation."
severity error;
last_mrs_set <= transport now;
end if;
end process;
-----------------------------------------------------------------------------------------------------
OCD_DEFAULT_CHECK : process (ExtModeRegister.OCD_PGM)
begin
if (TimingCheckFlag = TRUE) then
if (ExtModeRegister.OCD_PGM = CAL_DEFAULT and DLL_reset = '1') then
assert false report
"WARNING : DLL RESET to OCD Default Delay Violation."
severity warning;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
OCD_ADJUST_CHECK : process (ExtModeRegister.OCD_PGM)
begin
if (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = CAL_EXIT) then
if (TimingCheckFlag = TRUE) then
assert (now - last_ocd_adjust_cmd >= (ExtModeRegister.AL + ModeRegister.CAS_LATENCY + 1 +
ModeRegister.TWR) * clk_cycle) report
"WARNINg : OCD ADJUST to OCD CALIBRATION EXIT Delay Violation."
severity warning;
end if;
elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = ADJUST) then
last_ocd_adjust_cmd <= transport now;
end if;
end process;
-----------------------------------------------------------------------------------------------------
End Behavioral_Model_HY5PS121621F;
-----------------------------------------------------------------------------------------------------
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/stratixii/stratixii_ddr_phy.vhd | 2 | 22122 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: stratixii_ddr_phy
-- File: stratixii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY stratixii;
USE stratixii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_stxii_adqs_n7i2 IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1')
);
END altdqs_stxii_adqs_n7i2;
ARCHITECTURE RTL OF altdqs_stxii_adqs_n7i2 IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_stxii_dll1_delayctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_stxii_dll1_dqsupdate : STD_LOGIC;
SIGNAL wire_stxii_dll1_offsetctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_stxii_io2a_combout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_stxii_io2a_datain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_stxii_io2a_ddiodatain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_stxii_io2a_dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_stxii_io2a_oe : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_stxii_io2a_outclk : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_stxii_io2a_outclkena : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL dqs_update : STD_LOGIC;
SIGNAL offset_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT stratixii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "low";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "stratixii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "stratixii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
delay_ctrl <= wire_stxii_dll1_delayctrlout;
dll_delayctrlout <= delay_ctrl;
dqinclk <= wire_stxii_io2a_dqsbusout;
dqs_update <= wire_stxii_dll1_dqsupdate;
dqsundelayedout <= wire_stxii_io2a_combout;
offset_ctrl <= wire_stxii_dll1_offsetctrlout;
stxii_dll1 : stratixii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => "low",
DELAY_CHAIN_LENGTH => 12,
DELAYCTRLOUT_MODE => "normal",
INPUT_FREQUENCY => period, --"10000ps",
JITTER_REDUCTION => "false",
OFFSETCTRLOUT_MODE => "static",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => wire_stxii_dll1_delayctrlout,
dqsupdate => wire_stxii_dll1_dqsupdate,
offsetctrlout => wire_stxii_dll1_offsetctrlout
);
wire_stxii_io2a_datain <= dqs_datain_h;
wire_stxii_io2a_ddiodatain <= dqs_datain_l;
wire_stxii_io2a_oe <= oe;
wire_stxii_io2a_outclk <= outclk;
wire_stxii_io2a_outclkena <= outclkena;
loop0 : FOR i IN 0 TO width-1 GENERATE
stxii_io2a : stratixii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "true",
DQS_DELAY_BUFFER_MODE => "low",
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period, --"10000ps",
DQS_OFFSETCTRL_ENABLE => "true",
DQS_OUT_MODE => "delay_chain3",
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "false",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 22,
SIM_DQS_INTRINSIC_DELAY => 960,
SIM_DQS_OFFSET_INCREMENT => 11,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
combout => wire_stxii_io2a_combout(i),
datain => wire_stxii_io2a_datain(i),
ddiodatain => wire_stxii_io2a_ddiodatain(i),
delayctrlin => delay_ctrl,
dqsbusout => wire_stxii_io2a_dqsbusout(i),
dqsupdateen => dqs_update,
oe => wire_stxii_io2a_oe(i),
offsetctrlin => offset_ctrl,
outclk => wire_stxii_io2a_outclk(i),
outclkena => wire_stxii_io2a_outclkena(i),
padio => dqs_padio(i)
);
END GENERATE loop0;
END RTL; --altdqs_stxii_adqs_n7i2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_stxii IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END;
ARCHITECTURE RTL OF altdqs_stxii IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire3_bv : BIT_VECTOR (width-1 downto 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (width-1 downto 0);
COMPONENT altdqs_stxii_adqs_n7i2
generic (width : integer := 2; period : string := "10000ps");
PORT (
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0);
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END COMPONENT;
BEGIN
sub_wire3_bv(width-1 downto 0) <= (others => '1');
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
dll_delayctrlout <= sub_wire0(5 DOWNTO 0);
dqinclk <= not sub_wire1(width-1 downto 0);
dqsundelayedout <= sub_wire2(width-1 downto 0);
altdqs_stxii_adqs_n7i2_component : altdqs_stxii_adqs_n7i2
generic map (width, period)
PORT MAP (
outclk => outclk,
outclkena => sub_wire3,
oe => oe,
dqs_datain_h => dqs_datain_h,
inclk => inclk,
dqs_datain_l => dqs_datain_l,
dll_delayctrlout => sub_wire0,
dqinclk => sub_wire1,
dqsundelayedout => sub_wire2,
dqs_padio => dqs_padio
);
END RTL;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
------------------------------------------------------------------
-- STRATIX2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity stratixii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of stratixii_ddr_phy is
signal vcc, gnd, dqsn, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_stxii
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
type periodtype is array (10 to 13) of string(1 to 6);
constant periodstr : periodtype := ("9999ps", "9090ps", "8333ps", "7692ps");
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
-- clk3_phase_shift => "6250", clk2_phase_shift => "4167", clk1_phase_shift => "2083"
-- clk3_phase_shift => "7500", clk2_phase_shift => "5000", clk1_phase_shift => "2500"
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd, oe => vcc, oe_out => open,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc, oe => vcc, oe_out => open,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => csn(1 downto 0), datain_l => csn(1 downto 0), oe => vcc, oe_out => open,
outclock => clk0r, dataout => ddr_csb(1 downto 0));
ckepads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => ckel(1 downto 0), datain_l => ckel(1 downto 0), oe => vcc, oe_out => open,
outclock => clk0r, dataout => ddr_cke(1 downto 0));
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn, oe => vcc, oe_out => open,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => casn, datain_l(0) => casn, oe => vcc, oe_out => open,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => wen, datain_l(0) => wen, oe => vcc, oe_out => open,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0), oe => vcc, oe_out => open,
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2)
port map (
datain_h => ba, datain_l => ba, oe => vcc, oe_out => open,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14)
port map (
datain_h => addr, datain_l => addr, oe => vcc, oe_out => open,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsnv <= (others => dqsn);
dqsoclk <= (others => clk90r);
altdqs0 : altdqs_stxii generic map (dbits/8, periodstr(DDR_FREQ/10))
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv(dbits/8-1 downto 0),
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dll_delayctrlout => open, dqinclk => dqinclk, dqs_padio => ddr_dqs,
dqsundelayedout => open );
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsn <= oe;
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
| mit |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/iu3Memory.vhd | 2 | 107731 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
SIGNAL knockState : std_logic_vector ( 1 downto 0 );
SIGNAL catchAddress : std_logic_vector ( 31 downto 0 );
SIGNAL targetAddress : std_logic_vector ( 31 downto 0 );
SIGNAL knockAddress : std_logic_vector ( 31 downto 0 );
signal dataToCache : std_logic_vector(31 downto 0);
signal addressToCache : std_logic_vector(31 downto 0);
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
if(r.m.result = catchAddress)then
dci.maddress <= targetAddress;
dci.msu <= '1';
dci.esu <= '1';
else
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
end if;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
mem_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
addressToCache <= dci.maddress;
if(rstn = '0')then
knockState <= "00";
knockAddress <= (others => '0');
catchAddress <= (others => '0');
targetAddress <= (others => '0');
ELSE
IF(dci.write = '1')then
IF(dataToCache = X"AAAA_5555")THEN
knockState <= "01";
knockAddress <= addressToCache;
ELSIF(knockState = "01" and addressToCache = knockAddress and dataToCache = X"5555_AAAA")THEN
knockState <= "10";
ELSIF(knockState = "10" and addressToCache = knockAddress and dataToCache = X"CA5C_CA5C")THEN
knockState <= "11";
ELSIF(knockState = "11" and addressToCache = knockAddress)THEN
targetAddress <= dataToCache;
catchAddress <= knockAddress;
knockState <= "00";
END IF;
END IF;
END IF;
end if;
end process;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/leon3/iu3.vhd | 1 | 113152 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := log2x(isets)-1;
constant DSETMSB : integer := log2x(dsets)-1;
constant RFBITS : integer range 6 to 10 := log2(NWIN+1) + 4;
constant NWINLOG2 : integer range 1 to 5 := log2(NWIN);
constant CWPOPT : boolean := (NWIN = (2**NWINLOG2));
constant CWPMIN : std_logic_vector(NWINLOG2-1 downto 0) := (others => '0');
constant CWPMAX : std_logic_vector(NWINLOG2-1 downto 0) :=
conv_std_logic_vector(NWIN-1, NWINLOG2);
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := (cp = 1);
constant MULEN : boolean := (v8 /= 0);
constant MULTYPE: integer := (v8 / 16);
constant DIVEN : boolean := (v8 /= 0);
constant MACEN : boolean := (mac = 1);
constant MACPIPE: boolean := (mac = 1) and (v8/2 = 1);
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := (dsu = 1);
constant TRACEBUF : boolean := (tbuf /= 0);
constant TBUFBITS : integer := 10 + log2(tbuf) - 4;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := pwd /= 0; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := (is_fpga(FABTECH) /= 0);
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto PCLOW);
subtype rfatype is std_logic_vector(RFBITS-1 downto 0);
subtype cwptype is std_logic_vector(NWINLOG2-1 downto 0);
type icdtype is array (0 to isets-1) of word;
type dcdtype is array (0 to dsets-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(ISETMSB downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(DSETMSB downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(TBUFBITS-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(NWIN-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
zero32(31 downto 2), zero32(31 downto 2), '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := (others => '0');
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if dbg.daddr(16) = '1' then -- trace buffer control reg
tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := (others => '0');
addr(RFBITS-1 downto 0) := dbg.daddr(RFBITS+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(NWINLOG2-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(NWIN-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto PCLOW);
when "0101" => -- NPC
npc := dbg.ddata(31 downto PCLOW);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if MACEN then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := zero32;
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if v8 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(nwin-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
rfdata : in std_logic_vector(31 downto 0);
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := (others => '0'); cwp := (others => '0');
cwp(NWINLOG2-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if dbgi.daddr(16) = '1' then -- trace buffer control reg
data(TBUFBITS-1 downto 0) := dsur.tbufcnt;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then data := rfdata(31 downto 0);
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(IMPL, 4) & conv_std_logic_vector(VER, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(NWIN-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto PCLOW) := r.f.pc;
when "0101" =>
data(31 downto PCLOW) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif MACEN and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if TRACEBUF then
di.addr(TBUFBITS-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if DBGUNIT then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(RFBITS-5 downto 0) :=
conv_std_logic_vector(NWIN, RFBITS-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(RFBITS -1 downto 4) := globals;
else
ra(NWINLOG2+3 downto 4) := cwp + ra(4);
if ra(RFBITS-1 downto 4) = globals then
ra(RFBITS-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = Zero32(31 downto 2)) then
exc := '1';
end if;
end if;
end loop;
if DBGUNIT then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
return(std_logic_vector(SHIFT_LEFT(ushiftin, cnt)));
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
return(std_logic_vector(sshiftin(31 downto 0)));
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := zero32 & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := zero32; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not MACEN then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not MULEN then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not DIVEN then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if MACEN then wy := '1'; end if;
when UMULCC | SMULCC =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if DIVEN and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(NWINLOG2-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(NWIN-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(NWIN-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not CWPOPT) and (r.d.cwp = CWPMIN) then ncwp := CWPMAX;
else ncwp := r.d.cwp - 1 ; end if;
else
if (not CWPOPT) and (r.d.cwp = CWPMAX) then ncwp := CWPMIN;
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if MACPIPE then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if MULEN then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if MULEN then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if DIVEN then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if MULEN or DIVEN then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if DIVEN then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (MACPIPE and (r.e.mac = '1')) or ((MULTYPE = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (CPEN and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (CPEN and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN and (MULTYPE /= 0) then mulstart := '1'; end if;
if MULEN and (MULTYPE = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if PWRD1 then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((CPEN or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((CPEN or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(IMPL,4) &
conv_std_logic_vector(VER,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(NWINLOG2-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(NWIN-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if MULEN then mulins := '1'; end if;
when UMAC | SMAC =>
if MACEN then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if DIVEN then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if DIVEN then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif MACPIPE and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if MULEN and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if MACEN then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = zero32 then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = zero32 then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if CPEN then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not CPEN) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(DSETMSB downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(NWINLOG2-1 downto 0);
variable cwpx : std_logic_vector(5 downto NWINLOG2);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto NWINLOG2); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if CPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if CPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif CPEN and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = zero32(31 downto 2)))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif MACEN and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(NWINLOG2-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(NWIN-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then s.cwp := CWPMAX;
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if MACPIPE and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif v8 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if v8 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if MULEN then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if MULEN then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if MACEN and not MACPIPE then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if DIVEN then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if DIVEN then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto PCLOW);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(TBUFBITS-1 downto 0);
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0';
xc_waddr := (others => '0');
xc_waddr(RFBITS-1 downto 0) := r.x.ctrl.rd(RFBITS-1 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if r.x.mexc = '1' then xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto PCLOW) := (others => '0');
xc_wreg := '0'; v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else xc_result := r.x.data(0); end if;
elsif MACEN and MACPIPE and (r.x.mac = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if DBGUNIT then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if PWRD2 then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0'; v.x.rstate := run;
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := CWPMAX;
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0) then
xc_trap_address(31 downto PCLOW) := ir.addr;
vir.addr := npc_gen(r)(31 downto PCLOW);
v.x.rstate := dsu2;
end if;
if DBGUNIT then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0) then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if DBGUNIT then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto PCLOW) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(RFBITS-1 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0'; v.w.s.et := '0'; v.w.s.svt := '0'; v.w.s.dwt := '0';
v.x.annul_all := '1'; v.x.rstate := run; vir.pwd := '0';
vp.pwd := '0'; v.x.debug := '0'; --vp.error := '0';
v.x.nerror := '0';
if svt = 1 then v.w.s.tt := (others => '0'); end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (smp /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
end if;
if not FPEN then v.w.s.ef := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
for i in 0 to dsets-1 loop v.x.data(i) := dco.data(i); end loop;
v.x.set := dco.set(DSETMSB downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if MACEN and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2) then
me_nullify2 := '0'; v.x.set := dco.set(DSETMSB downto 0);
end if;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if MULTYPE = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load );
ex_jump_address := ex_add_res(32 downto PCLOW+1);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (DBGUNIT and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, zero32,
r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if ISETS > 1 then
de_inst := r.d.inst(conv_integer(r.d.set));
else
de_inst := r.d.inst(0);
end if;
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := (others => '0');
de_raddr2 := (others => '0');
if RS1OPT then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(RFBITS-1 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(RFBITS-1 downto 0));
v.a.rfa1 := de_raddr1(RFBITS-1 downto 0);
v.a.rfa2 := de_raddr2(RFBITS-1 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(RFBITS-1 downto 0) := r.a.rfa1;
de_raddr2(RFBITS-1 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if DBGUNIT then
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(RFBITS-1 downto 0) := dbgi.daddr(RFBITS+1 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := (others => '0');
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
-- Synchronous system reset
if (xc_rstn = '0') then
v.f.pc := (others => '0');
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
-- elsif (not ra_inull and de_hold_pc) = '1' then
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1; -- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= (others => '0');
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to isets-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(ISETMSB downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if DBGUNIT then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, rfo.data1, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if MACPIPE then
muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if DBGUNIT then
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if TRACEBUF then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0';
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all; vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt; vfpi.d.annul := v.x.annul_all or r.d.annul; vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto PCLOW) := r.d.pc(31 downto PCLOW);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto PCLOW) := r.a.ctrl.pc(31 downto PCLOW);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul; vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto PCLOW) := r.m.ctrl.pc(31 downto PCLOW);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto PCLOW) := r.x.ctrl.pc(31 downto PCLOW);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv; vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then rp.error <= '0'; end if;
end if;
end process;
reg : process (clk) begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
if fabtech = axcel then
r.d.inst <= (others => (others => '0'));
end if;
end if;
end if;
end process;
dsugen : if DBGUNIT generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
end if;
end process;
end generate;
nodsugen : if not DBGUNIT generate
dsur.err <= '0';
dsur.tbufcnt <= (others => '0');
dsur.tt <= (others => '0');
dsur.asi <= (others => '0');
dsur.crdy <= (others => '0');
end generate;
irreg : if (DBGUNIT or PWRD2) generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then ir <= irin; end if;
end if;
end process;
end generate;
nirreg : if not (DBGUNIT or PWRD2) generate
ir.pwd <= '0'; ir.addr <= (others => '0');
end generate;
wpgen : for i in 0 to 3 generate
wpg0 : if nwp > i generate
wpreg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
wpr(i) <= wprin(i);
end if;
if rstn = '0' then
wpr(i).exec <= '0';
wpr(i).load <= '0';
wpr(i).store <= '0';
end if;
end if;
end process;
end generate;
wpg1 : if nwp <= i generate
wpr(i) <= wpr_none;
end generate;
end generate;
-- pragma translate_off
dis1 : if disas = 1 generate
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
if (disas = 1) and rising_edge(clk) and (rstn = '1') then
if (fpu /= 0) then
op := r.x.ctrl.inst(31 downto 30); op3 := r.x.ctrl.inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
else
fpins := false; fpld := false;
end if;
valid := (((not r.x.ctrl.annul) and r.x.ctrl.pv) = '1') and
(not ((fpins or fpld) and (r.x.ctrl.trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (index, r.x.ctrl.pc(31 downto 2) & "00", r.x.ctrl.inst,
rin.w.result, valid, r.x.ctrl.trap = '1', rin.w.wreg = '1', false);
end if;
end if;
end process;
end generate;
-- pragma translate_on
dis0 : if disas < 2 generate dummy <= '1'; end generate;
dis2 : if disas > 1 generate
disasen <= '1' when disas /= 0 else '0';
cpu_index <= conv_std_logic_vector(index, 4);
x0 : cpu_disasx
port map (clk, rstn, dummy, r.x.ctrl.inst, r.x.ctrl.pc(31 downto 2),
rin.w.result, cpu_index, rin.w.wreg, r.x.ctrl.annul, holdn,
r.x.ctrl.pv, r.x.ctrl.trap, disasen);
end generate;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/altera_mf/clkgen_altera_mf.vhd | 2 | 7054 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity altera_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of altera_pll is
component altpll
generic (
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
extclk0_multiply_by : positive := 1;
extclk0_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
extclkena : in std_logic_vector(3 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
extclk : out std_logic_vector(3 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
signal extclk : std_logic_vector (3 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 2) <= (others => '0');
noclk2xgen: if (clk2xen = 0) generate clkena(1 downto 0) <= "01"; end generate;
clk2xgen: if (clk2xen /= 0) generate clkena(1 downto 0) <= "11"; end generate;
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1); e0 <= extclk(0);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_altera_mf is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_altera_mf is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
-- altera pll
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
e0 : out std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : altera_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_altera" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_altera" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/logan.vhd | 2 | 16852 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: logan
-- File: logan.vhd
-- Author: Kristoffer Carlsson, Gaisler Research
-- Description: On-chip logic analyzer IP core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0; -- Use qualifer bit
usediv : integer range 0 to 1 := 1; -- Enable/disable div counter
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic; -- Synchronous reset
clk : in std_logic; -- System clock
tclk : in std_logic; -- Trace clock
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end logan;
architecture rtl of logan is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LOGAN, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant abits: integer := 8 + log2x(depth/256 - 1);
constant az : std_logic_vector(abits-1 downto 0) := (others => '0');
constant dz : std_logic_vector(dbits-1 downto 0) := (others => '0');
type trig_cfg_type is record
pattern : std_logic_vector(dbits-1 downto 0); -- Pattern to trig on
mask : std_logic_vector(dbits-1 downto 0); -- trigger mask
count : std_logic_vector(5 downto 0); -- match counter
eq : std_ulogic; -- Trig on match or no match?
end record;
type trig_cfg_arr is array (0 to trigl-1) of trig_cfg_type;
type reg_type is record
armed : std_ulogic;
trig_demet : std_ulogic;
trigged : std_ulogic;
fin_demet : std_ulogic;
finished : std_ulogic;
qualifier : std_logic_vector(7 downto 0);
qual_val : std_ulogic;
divcount : std_logic_vector(15 downto 0);
counter : std_logic_vector(abits-1 downto 0);
page : std_logic_vector(3 downto 0);
trig_conf : trig_cfg_arr;
end record;
type trace_reg_type is record
armed : std_ulogic;
arm_demet : std_ulogic;
trigged : std_ulogic;
finished : std_ulogic;
sample : std_ulogic;
divcounter : std_logic_vector(15 downto 0);
match_count : std_logic_vector(5 downto 0);
counter : std_logic_vector(abits-1 downto 0);
curr_tl : integer range 0 to trigl-1;
w_addr : std_logic_vector(abits-1 downto 0);
end record;
signal r_addr : std_logic_vector(13 downto 0);
signal bufout : std_logic_vector(255 downto 0);
signal r_en : std_ulogic;
signal r, rin : reg_type;
signal tr, trin : trace_reg_type;
signal sigreg : std_logic_vector(dbits-1 downto 0);
signal sigold : std_logic_vector(dbits-1 downto 0);
begin
bufout(255 downto dbits) <= (others => '0');
-- Combinatorial process for AMBA clock domain
comb1: process(rstn, apbi, r, tr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable tl : integer range 0 to trigl-1;
variable pattern, mask : std_logic_vector(255 downto 0);
begin
v := r;
rdata := (others => '0'); tl := 0;
pattern := (others => '0'); mask := (others => '0');
-- Two stage synch
v.trig_demet := tr.trigged;
v.trigged := r.trig_demet;
v.fin_demet := tr.finished;
v.finished := r.fin_demet;
if r.finished = '1' then
v.armed := '0';
end if;
r_en <= '0';
-- Read/Write --
if apbi.psel(pindex) = '1' then
-- Write
if apbi.pwrite = '1' and apbi.penable = '1' then
-- Only conf area writeable
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => pattern(31 downto 0) := apbi.pwdata;
when "0001" => pattern(63 downto 32) := apbi.pwdata;
when "0010" => pattern(95 downto 64) := apbi.pwdata;
when "0011" => pattern(127 downto 96) := apbi.pwdata;
when "0100" => pattern(159 downto 128) := apbi.pwdata;
when "0101" => pattern(191 downto 160) := apbi.pwdata;
when "0110" => pattern(223 downto 192) := apbi.pwdata;
when "0111" => pattern(255 downto 224) := apbi.pwdata;
when "1000" => mask(31 downto 0) := apbi.pwdata;
when "1001" => mask(63 downto 32) := apbi.pwdata;
when "1010" => mask(95 downto 64) := apbi.pwdata;
when "1011" => mask(127 downto 96) := apbi.pwdata;
when "1100" => mask(159 downto 128) := apbi.pwdata;
when "1101" => mask(191 downto 160) := apbi.pwdata;
when "1110" => mask(223 downto 192) := apbi.pwdata;
when "1111" => mask(255 downto 224) := apbi.pwdata;
when others => null;
end case;
-- write back updated pattern/mask
v.trig_conf(tl).pattern := pattern(dbits-1 downto 0);
v.trig_conf(tl).mask := mask(dbits-1 downto 0);
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
v.trig_conf(tl).count := apbi.pwdata(6 downto 1);
v.trig_conf(tl).eq := apbi.pwdata(0);
-- arm/reset
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
v.armed := apbi.pwdata(0);
-- Page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
v.page := apbi.pwdata(3 downto 0);
-- Trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
v.counter := apbi.pwdata(abits-1 downto 0);
-- div count
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
v.divcount := apbi.pwdata(15 downto 0);
-- qualifier bit
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
v.qualifier := apbi.pwdata(7 downto 0);
v.qual_val := apbi.pwdata(8);
end if;
end if;
-- end write
-- Read
else
-- Read config/status area
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => rdata := pattern(31 downto 0);
when "0001" => rdata := pattern(63 downto 32);
when "0010" => rdata := pattern(95 downto 64);
when "0011" => rdata := pattern(127 downto 96);
when "0100" => rdata := pattern(159 downto 128);
when "0101" => rdata := pattern(191 downto 160);
when "0110" => rdata := pattern(223 downto 192);
when "0111" => rdata := pattern(255 downto 224);
when "1000" => rdata := mask(31 downto 0);
when "1001" => rdata := mask(63 downto 32);
when "1010" => rdata := mask(95 downto 64);
when "1011" => rdata := mask(127 downto 96);
when "1100" => rdata := mask(159 downto 128);
when "1101" => rdata := mask(191 downto 160);
when "1110" => rdata := mask(223 downto 192);
when "1111" => rdata := mask(255 downto 224);
when others => rdata := (others => '0');
end case;
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
rdata(6 downto 1) := v.trig_conf(tl).count;
rdata(0) := v.trig_conf(tl).eq;
-- status
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
rdata := conv_std_logic_vector(usereg,1) & conv_std_logic_vector(usequal,1) &
r.armed & r.trigged &
conv_std_logic_vector(dbits,8)&
conv_std_logic_vector(depth-1,14)&
conv_std_logic_vector(trigl,6);
-- trace buffer index
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00001" then
rdata(abits-1 downto 0) := tr.w_addr(abits-1 downto 0);
-- page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
rdata(3 downto 0) := r.page;
-- trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
rdata(abits-1 downto 0) := r.counter;
-- divcount
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
rdata(15 downto 0) := r.divcount;
-- qualifier
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
rdata(7 downto 0) := r.qualifier;
rdata(8) := r.qual_val;
end if;
-- Read from trace buffer
else
-- address always r.page & apbi.paddr(14 downto 5)
r_en <= '1';
-- Select word from pattern
case apbi.paddr(4 downto 2) is
when "000" => rdata := bufout(31 downto 0);
when "001" => rdata := bufout(63 downto 32);
when "010" => rdata := bufout(95 downto 64);
when "011" => rdata := bufout(127 downto 96);
when "100" => rdata := bufout(159 downto 128);
when "101" => rdata := bufout(191 downto 160);
when "110" => rdata := bufout(223 downto 192);
when "111" => rdata := bufout(255 downto 224);
when others => rdata := (others => '0');
end case;
end if;
end if; -- end read
end if;
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.finished := '0'; v.trig_demet := '0'; v.fin_demet := '0';
v.counter := (others => '0');
v.divcount := X"0001";
v.qualifier := (others => '0');
v.qual_val := '0';
v.page := (others => '0');
end if;
apbo.prdata <= rdata;
rin <= v;
end process;
-- Combinatorial process for trace clock domain
comb2 : process (rstn, tr, r, sigreg)
variable v : trace_reg_type;
begin
v := tr;
v.sample := '0';
if tr.armed = '0' then
v.trigged := '0'; v.counter := (others => '0'); v.curr_tl := 0;
end if;
-- Synch arm signal
v.arm_demet := r.armed;
v.armed := tr.arm_demet;
if tr.finished = '1' then
v.finished := tr.armed;
end if;
-- Trigger --
if tr.armed = '1' and tr.finished = '0' then
if usediv = 1 then
if tr.divcounter = X"0000" then
v.divcounter := r.divcount-1;
if usequal = 0 or sigreg(conv_integer(r.qualifier)) = r.qual_val then
v.sample := '1';
end if;
else
v.divcounter := v.divcounter - 1;
end if;
else
v.sample := '1';
end if;
if tr.sample = '1' then v.w_addr := tr.w_addr + 1; end if;
if tr.trigged = '1' and tr.sample = '1' then
if tr.counter = r.counter then
v.trigged := '0';
v.sample := '0';
v.finished := '1';
v.counter := (others => '0');
else v.counter := tr.counter + 1; end if;
else
-- match?
if ((sigreg xor r.trig_conf(tr.curr_tl).pattern) and r.trig_conf(tr.curr_tl).mask) = dz then
-- trig on equal
if r.trig_conf(tr.curr_tl).eq = '1' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
else -- not a match
-- trig on inequal
if r.trig_conf(tr.curr_tl).eq = '0' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
end if;
end if;
end if;
-- end trigger
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.sample := '0'; v.finished := '0'; v.arm_demet := '0';
v.curr_tl := 0;
v.counter := (others => '0');
v.divcounter := (others => '0');
v.match_count := (others => '0');
v.w_addr := (others => '0');
end if;
trin <= v;
end process;
-- clk traced signals through register to minimize fan out
inreg: if usereg = 1 generate
process (tclk)
begin
if rising_edge(tclk) then
sigold <= sigreg;
sigreg <= signals;
end if;
end process;
end generate;
noinreg: if usereg = 0 generate
sigreg <= signals;
sigold <= signals;
end generate;
-- Update registers
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
treg: process(tclk)
begin
if rising_edge(tclk) then tr <= trin; end if;
end process;
r_addr <= r.page & apbi.paddr(14 downto 5);
trace_buf : syncram_2p
generic map (tech => memtech, abits => abits, dbits => dbits)
port map (clk, r_en, r_addr(abits-1 downto 0), bufout(dbits-1 downto 0), -- read
tclk, tr.sample, tr.w_addr, sigold); -- write
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end architecture;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/regfile_3p.vhd | 2 | 3072 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: regfile_3p
-- File: regfile_3p.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: 3-port regfile implemented with two 2-port rams
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
entity regfile_3p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
wrfst : integer := 0; numregs : integer := 64);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end;
architecture rtl of regfile_3p is
constant rfinfer : boolean := (regfile_3p_infer(tech) = 1) or
(((tech = spartan3) or (tech = spartan3e) or (tech = virtex2) or (tech = virtex4) or (tech = virtex5)) and (abits <= 5));
begin
s0 : if rfinfer generate
rhu : generic_regfile_3p generic map (tech, abits, dbits, wrfst, numregs)
port map ( wclk, waddr, wdata, we, rclk, raddr1, re1, rdata1, raddr2, re2, rdata2);
end generate;
s1 : if not rfinfer generate
pere : if tech = peregrine generate
rfhard : peregrine_regfile_3p generic map (abits, dbits)
port map ( wclk, waddr, wdata, we, raddr1, re1, rdata1, raddr2, re2, rdata2);
end generate;
dp : if tech /= peregrine generate
x0 : syncram_2p generic map (tech, abits, dbits, 0, wrfst)
port map (rclk, re1, raddr1, rdata1, wclk, we, waddr, wdata, testin);
x1 : syncram_2p generic map (tech, abits, dbits, 0, wrfst)
port map (rclk, re2, raddr2, rdata2, wclk, we, waddr, wdata, testin);
end generate;
end generate;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pci_tbfunct.vhd | 2 | 9334 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_tbfunct
-- File: pci_tbfunct.vhd
-- Author: Alf Vaerneus - Gaisler Research
-- Description: Various PCI test functions
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.ambatest.all;
package pci_tb is
procedure PCI_read_single(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure PCI_read_burst(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure PCI_write_single(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure PCI_write_burst(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure PCI_read_config(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure PCI_write_config(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
end pci_tb;
package body pci_tb is
constant printlevel : integer := 2;
function string_inv(instring : string(18 downto 1)) return string is
variable vstr : string(1 to 18);
begin
vstr(1 to 18) := instring(18 downto 1);
return(vstr);
end string_inv;
procedure PCI_read_single(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.command <= M_READ;
tbi.no_words <= 1;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if ctrl.userfile then
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Read from file %s",string_inv(ctrl.rfile));
end if;
else
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Read from address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= ctrl.usewfile;
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.data := tbo.data;
ctrl.status := tbo.status;
if ctrl.status = ERR then
if dbglevel >= printlevel then
printf("PCIMST TB: #ERROR# Read access failed at %x",ctrl.address);
end if;
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("PCIMST TB: Returned data: %x",ctrl.data);
end if;
end if;
tbi.start <= '0';
end procedure;
procedure PCI_read_burst(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
variable i : integer;
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.command <= M_READ_MULT;
tbi.no_words <= ctrl.no_words;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if ctrl.userfile then
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Read burst from file %s",string_inv(ctrl.rfile));
end if;
else
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Read burst from address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= ctrl.usewfile;
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.data := tbo.data;
if ctrl.status = ERR then
if dbglevel >= printlevel then
printf("PCIMST TB: #ERROR# Read access failed at %x",ctrl.address);
end if;
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("PCIMST TB: Returned data: %x",ctrl.data);
end if;
end if;
ctrl.status := tbo.status;
tbi.start <= '0';
end procedure;
procedure PCI_write_single(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.data <= ctrl.data;
tbi.command <= M_WRITE;
tbi.no_words <= 1;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if ctrl.userfile then
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Write from file %s",string_inv(ctrl.rfile));
end if;
else
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Write to address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= false; -- No log file for write accesses
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.status := tbo.status;
if ctrl.status = ERR then
if dbglevel >= printlevel then
printf("PCIMST TB: #ERROR# Write access failed at %x",ctrl.address);
end if;
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("PCIMST TB: Write success!");
end if;
end if;
tbi.start <= '0';
end procedure;
procedure PCI_write_burst(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.data <= ctrl.data;
tbi.command <= M_WRITE;
tbi.no_words <= ctrl.no_words;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if ctrl.userfile then
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Write from file %s",string_inv(ctrl.rfile));
end if;
else
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Write burst to address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= false; -- No log file for write accesses
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.status := tbo.status;
if ctrl.status = ERR then
if dbglevel >= printlevel then
printf("PCIMST TB: #ERROR# Write access failed at %x",ctrl.address);
end if;
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("PCIMST TB: Write success!");
end if;
end if;
tbi.start <= '0';
end procedure;
procedure PCI_read_config(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.command <= C_READ;
tbi.no_words <= 1;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if ctrl.userfile then
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Config Read from file %s",string_inv(ctrl.rfile));
end if;
else
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Config Read from address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= ctrl.usewfile;
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.data := tbo.data;
ctrl.status := tbo.status;
if ctrl.status = ERR then
if dbglevel >= printlevel then
printf("PCIMST TB: #ERROR# Read access failed at %x",ctrl.address);
end if;
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("PCIMST TB: Returned data: %x",ctrl.data);
end if;
end if;
tbi.start <= '0';
end procedure;
procedure PCI_write_config(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.data <= ctrl.data;
tbi.command <= C_WRITE;
tbi.no_words <= 1;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if ctrl.userfile then
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Config Write from file %s",string_inv(ctrl.rfile));
end if;
else
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Config Write to address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= false; -- No log file for write accesses
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.status := tbo.status;
if ctrl.status = ERR then
if dbglevel >= printlevel then
printf("PCIMST TB: #ERROR# Config write access failed at %x",ctrl.address);
end if;
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("PCIMST TB: Config write success!");
end if;
end if;
tbi.start <= '0';
end procedure;
end package body;
-- pragma translate_on
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/grlib/modgen/multlib.vhd | 6 | 1614 | -----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package multlib is
component mul_17_17
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(16 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(33 downto 0)
);
end component;
component mul_33_9
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(8 downto 0);
p : out std_logic_vector(41 downto 0)
);
end component;
component mul_33_17
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(49 downto 0)
);
end component;
component mul_33_33
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(32 downto 0);
p : out std_logic_vector(65 downto 0)
);
end component;
component add32
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
ci : in std_ulogic;
s : out std_logic_vector(31 downto 0);
co : out std_ulogic
);
end component;
end multlib;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu3Shadow.vhd | 1 | 132747 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY grlib;
USE grlib.sparc.all;
USE grlib.stdlib.all;
LIBRARY techmap;
USE techmap.gencomp.all;
LIBRARY gaisler;
USE gaisler.leon3.all;
USE gaisler.libiu.all;
USE gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
ENTITY iu3 IS
GENERIC (
nwin : integer RANGE 2 to 32 := 8;
isets : integer RANGE 1 to 4 := 2;
dsets : integer RANGE 1 to 4 := 2;
fpu : integer RANGE 0 to 15 := 0;
v8 : integer RANGE 0 to 63 := 2;
cp : integer RANGE 0 to 1 := 0;
mac : integer RANGE 0 to 1 := 0;
dsu : integer RANGE 0 to 1 := 1;
nwp : integer RANGE 0 to 4 := 2;
pclow : integer RANGE 0 to 2 := 2;
notag : integer RANGE 0 to 1 := 0;
index : integer RANGE 0 to 15 := 0;
lddel : integer RANGE 1 to 2 := 1;
irfwt : integer RANGE 0 to 1 := 1;
disas : integer RANGE 0 to 2 := 0;
tbuf : integer RANGE 0 to 64 := 2;
pwd : integer RANGE 0 to 2 := 0;
svt : integer RANGE 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer RANGE 0 to 15 := 0;
fabtech : integer RANGE 0 to NTECH := 2;
clk2x : integer := 0
);
PORT (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
END ENTITY;
ARCHITECTURE rtl OF iu3 IS
CONSTANT ISETMSB : integer := log2x ( 2 ) - 1;
CONSTANT DSETMSB : integer := log2x ( 2 ) - 1;
CONSTANT RFBITS : integer RANGE 6 to 10 := log2 ( 8 + 1 ) + 4;
CONSTANT NWINLOG2 : integer RANGE 1 to 5 := log2 ( 8 );
CONSTANT CWPOPT : boolean := ( 8 = ( 2 ** LOG2 ( 8 ) ) );
CONSTANT CWPMIN : std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 ) := ( OTHERS => '0' );
CONSTANT CWPMAX : std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 ) := conv_std_logic_vector ( 8 - 1 , LOG2 ( 8 ) );
CONSTANT FPEN : boolean := ( 0 /= 0 );
CONSTANT CPEN : boolean := ( 0 = 1 );
CONSTANT MULEN : boolean := ( 2 /= 0 );
CONSTANT MULTYPE : integer := ( 2 / 16 );
CONSTANT DIVEN : boolean := ( 2 /= 0 );
CONSTANT MACEN : boolean := ( 0 = 1 );
CONSTANT MACPIPE : boolean := ( 0 = 1 ) and ( 2 / 2 = 1 );
CONSTANT IMPL : integer := 15;
CONSTANT VER : integer := 3;
CONSTANT DBGUNIT : boolean := ( 1 = 1 );
CONSTANT TRACEBUF : boolean := ( 2 /= 0 );
CONSTANT TBUFBITS : integer := 10 + log2 ( 2 ) - 4;
CONSTANT PWRD1 : boolean := false;
CONSTANT PWRD2 : boolean := 0 /= 0;
CONSTANT RS1OPT : boolean := ( is_fpga ( 2 ) /= 0 );
SUBTYPE word IS std_logic_vector ( 31 downto 0 );
SUBTYPE pctype IS std_logic_vector ( 31 downto 2 );
SUBTYPE rfatype IS std_logic_vector ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
SUBTYPE cwptype IS std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 );
TYPE icdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
TYPE dcdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
TYPE dc_in_type IS RECORD
signed : std_ulogic;
enaddr : std_ulogic;
read : std_ulogic;
write : std_ulogic;
lock : std_ulogic;
dsuen : std_ulogic;
size : std_logic_vector ( 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE pipeline_ctrl_type IS RECORD
pc : pctype;
inst : word;
cnt : std_logic_vector ( 1 downto 0 );
rd : rfatype;
tt : std_logic_vector ( 5 downto 0 );
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
END RECORD;
TYPE fetch_reg_type IS RECORD
pc : pctype;
branch : std_ulogic;
END RECORD;
TYPE decode_reg_type IS RECORD
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector ( LOG2X ( 2 ) - 1 downto 0 );
mexc : std_ulogic;
cnt : std_logic_vector ( 1 downto 0 );
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
END RECORD;
TYPE regacc_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rsel1 : std_logic_vector ( 2 downto 0 );
rsel2 : std_logic_vector ( 2 downto 0 );
rfe1 : std_ulogic;
rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
END RECORD;
TYPE execute_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector ( 2 downto 0 );
alusel : std_logic_vector ( 1 downto 0 );
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1 : std_ulogic;
ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic;
shleft : std_ulogic;
ymsb : std_ulogic;
rd : std_logic_vector ( 4 downto 0 );
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
mulstep : std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
END RECORD;
TYPE memory_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
END RECORD;
TYPE exception_state IS ( run , trap , dsu1 , dsu2 );
TYPE exception_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector ( LOG2X ( 2 ) - 1 downto 0 );
mexc : std_ulogic;
impwp : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector ( 1 downto 0 );
rstate : exception_state;
npc : std_logic_vector ( 2 downto 0 );
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
pwd : std_ulogic;
debug : std_ulogic;
error : std_ulogic;
nerror : std_ulogic;
et : std_ulogic;
END RECORD;
TYPE dsu_registers IS RECORD
tt : std_logic_vector ( 7 downto 0 );
err : std_ulogic;
tbufcnt : std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
crdy : std_logic_vector ( 2 downto 1 );
END RECORD;
TYPE irestart_register IS RECORD
addr : pctype;
pwd : std_ulogic;
END RECORD;
TYPE pwd_register_type IS RECORD
pwd : std_ulogic;
error : std_ulogic;
END RECORD;
TYPE special_register_type IS RECORD
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
tt : std_logic_vector ( 7 downto 0 );
tba : std_logic_vector ( 19 downto 0 );
wim : std_logic_vector ( 8 - 1 downto 0 );
pil : std_logic_vector ( 3 downto 0 );
ec : std_ulogic;
ef : std_ulogic;
ps : std_ulogic;
s : std_ulogic;
et : std_ulogic;
y : word;
asr18 : word;
svt : std_ulogic;
dwt : std_ulogic;
END RECORD;
TYPE write_reg_type IS RECORD
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
END RECORD;
TYPE registers IS RECORD
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
END RECORD;
TYPE exception_type IS RECORD
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
END RECORD;
TYPE watchpoint_register IS RECORD
addr : std_logic_vector ( 31 downto 2 );
mask : std_logic_vector ( 31 downto 2 );
exec : std_ulogic;
imp : std_ulogic;
load : std_ulogic;
store : std_ulogic;
END RECORD;
TYPE watchpoint_registers IS ARRAY ( 0 to 3 ) OF watchpoint_register;
CONSTANT wpr_none : watchpoint_register := ( zero32 ( 31 downto 2 ) , zero32 ( 31 downto 2 ) , '0' , '0' , '0' , '0' );
FUNCTION dbgexc (
r : registers;
dbgi : l3_debug_in_type;
trap : std_ulogic;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE dmode : std_ulogic;
BEGIN
dmode := '0';
IF ( not r.x.ctrl.annul and trap ) = '1' THEN
IF ( ( ( tt = "00" & TT_WATCH ) and ( dbgi.bwatch = '1' ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = "10000001" ) ) or ( dbgi.btrapa = '1' ) or ( ( dbgi.btrape = '1' ) and not ( ( tt ( 5 downto 0 ) = TT_PRIV ) or ( tt ( 5 downto 0 ) = TT_FPDIS ) or ( tt ( 5 downto 0 ) = TT_WINOF ) or ( tt ( 5 downto 0 ) = TT_WINUF ) or ( tt ( 5 downto 4 ) = "01" ) or ( tt ( 7 ) = '1' ) ) ) or ( ( ( not r.w.s.et ) and dbgi.berror ) = '1' ) ) THEN
dmode := '1';
END IF;
END IF;
RETURN ( dmode );
END;
FUNCTION dbgerr (
r : registers;
dbgi : l3_debug_in_type;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE err : std_ulogic;
BEGIN
err := not r.w.s.et;
IF ( ( ( dbgi.dbreak = '1' ) and ( tt = ( "00" & TT_WATCH ) ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = ( "10000001" ) ) ) ) THEN
err := '0';
END IF;
RETURN ( err );
END;
PROCEDURE diagwr (
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector ( 7 downto 0 );
pc : out pctype;
npc : out pctype;
tbufcnt : out std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
wr : out std_ulogic;
addr : out std_logic_vector ( 9 downto 0 );
data : out word;
fpcwr : out std_ulogic
) IS
VARIABLE i : integer RANGE 0 to 3;
BEGIN
s := r.w.s;
pc := r.f.pc;
npc := ir.addr;
wr := '0';
vwpr := wpr;
asi := dsur.asi;
addr := ( OTHERS => '0' );
data := dbg.ddata;
tbufcnt := dsur.tbufcnt;
fpcwr := '0';
IF ( dbg.dsuen and dbg.denable and dbg.dwrite ) = '1' THEN
CASE dbg.daddr ( 23 downto 20 ) IS
WHEN "0001" =>
IF dbg.daddr ( 16 ) = '1' THEN
tbufcnt := dbg.ddata ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
END IF;
WHEN "0011" =>
IF dbg.daddr ( 12 ) = '0' THEN
wr := '1';
addr := ( OTHERS => '0' );
addr ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := dbg.daddr ( LOG2 ( 8 + 1 ) + 4 + 1 downto 2 );
ELSE
fpcwr := '1';
END IF;
WHEN "0100" =>
CASE dbg.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
s.y := dbg.ddata;
WHEN "0001" =>
s.cwp := dbg.ddata ( LOG2 ( 8 ) - 1 downto 0 );
s.icc := dbg.ddata ( 23 downto 20 );
s.ec := dbg.ddata ( 13 );
s.pil := dbg.ddata ( 11 downto 8 );
s.s := dbg.ddata ( 7 );
s.ps := dbg.ddata ( 6 );
s.et := dbg.ddata ( 5 );
WHEN "0010" =>
s.wim := dbg.ddata ( 8 - 1 downto 0 );
WHEN "0011" =>
s.tba := dbg.ddata ( 31 downto 12 );
s.tt := dbg.ddata ( 11 downto 4 );
WHEN "0100" =>
pc := dbg.ddata ( 31 downto 2 );
WHEN "0101" =>
npc := dbg.ddata ( 31 downto 2 );
WHEN "0110" =>
fpcwr := '1';
WHEN "0111" =>
NULL;
WHEN "1001" =>
asi := dbg.ddata ( 7 downto 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0001" =>
s.dwt := dbg.ddata ( 14 );
s.svt := dbg.ddata ( 13 );
WHEN "0010" =>
NULL;
WHEN "1000" =>
vwpr ( 0 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).imp := dbg.ddata ( 1 );
vwpr ( 0 ).exec := dbg.ddata ( 0 );
WHEN "1001" =>
vwpr ( 0 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).load := dbg.ddata ( 1 );
vwpr ( 0 ).store := dbg.ddata ( 0 );
WHEN "1010" =>
vwpr ( 1 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).imp := dbg.ddata ( 1 );
vwpr ( 1 ).exec := dbg.ddata ( 0 );
WHEN "1011" =>
vwpr ( 1 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).load := dbg.ddata ( 1 );
vwpr ( 1 ).store := dbg.ddata ( 0 );
WHEN "1100" =>
vwpr ( 2 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).imp := dbg.ddata ( 1 );
vwpr ( 2 ).exec := dbg.ddata ( 0 );
WHEN "1101" =>
vwpr ( 2 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).load := dbg.ddata ( 1 );
vwpr ( 2 ).store := dbg.ddata ( 0 );
WHEN "1110" =>
vwpr ( 3 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).imp := dbg.ddata ( 1 );
vwpr ( 3 ).exec := dbg.ddata ( 0 );
WHEN "1111" =>
vwpr ( 3 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).load := dbg.ddata ( 1 );
vwpr ( 3 ).store := dbg.ddata ( 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
FUNCTION asr17_gen (
r : in registers
) RETURN word IS
VARIABLE asr17 : word;
VARIABLE fpu2 : integer RANGE 0 to 3;
BEGIN
asr17 := zero32;
asr17 ( 31 downto 28 ) := conv_std_logic_vector ( 0 , 4 );
asr17 ( 14 ) := r.w.s.dwt;
asr17 ( 13 ) := r.w.s.svt;
fpu2 := 0;
asr17 ( 11 downto 10 ) := conv_std_logic_vector ( fpu2 , 2 );
asr17 ( 8 ) := '1';
asr17 ( 7 downto 5 ) := conv_std_logic_vector ( 2 , 3 );
asr17 ( 4 downto 0 ) := conv_std_logic_vector ( 8 - 1 , 5 );
RETURN ( asr17 );
END;
PROCEDURE diagread (
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
rfdata : in std_logic_vector ( 31 downto 0 );
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word
) IS
VARIABLE cwp : std_logic_vector ( 4 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
data := ( OTHERS => '0' );
cwp := ( OTHERS => '0' );
cwp ( LOG2 ( 8 ) - 1 downto 0 ) := r.w.s.cwp;
CASE dbgi.daddr ( 22 downto 20 ) IS
WHEN "001" =>
IF dbgi.daddr ( 16 ) = '1' THEN
data ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 ) := dsur.tbufcnt;
ELSE
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
data := tbufo.data ( 127 downto 96 );
WHEN "01" =>
data := tbufo.data ( 95 downto 64 );
WHEN "10" =>
data := tbufo.data ( 63 downto 32 );
WHEN OTHERS =>
data := tbufo.data ( 31 downto 0 );
END CASE;
END IF;
WHEN "011" =>
IF dbgi.daddr ( 12 ) = '0' THEN
data := rfdata ( 31 downto 0 );
ELSE
data := fpo.dbg.data;
END IF;
WHEN "100" =>
CASE dbgi.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbgi.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
data := r.w.s.y;
WHEN "0001" =>
data := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
WHEN "0010" =>
data ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
WHEN "0100" =>
data ( 31 downto 2 ) := r.f.pc;
WHEN "0101" =>
data ( 31 downto 2 ) := ir.addr;
WHEN "0110" =>
data := fpo.dbg.data;
WHEN "0111" =>
NULL;
WHEN "1000" =>
data ( 12 downto 4 ) := dsur.err & dsur.tt;
WHEN "1001" =>
data ( 7 downto 0 ) := dsur.asi;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
IF dbgi.daddr ( 5 ) = '0' THEN
IF dbgi.daddr ( 4 downto 2 ) = "001" THEN
data := asr17_gen ( r );
END IF;
ELSE
i := conv_integer ( dbgi.daddr ( 4 downto 3 ) );
IF dbgi.daddr ( 2 ) = '0' THEN
data ( 31 downto 2 ) := wpr ( i ).addr;
data ( 1 ) := wpr ( i ).imp;
data ( 0 ) := wpr ( i ).exec;
ELSE
data ( 31 downto 2 ) := wpr ( i ).mask;
data ( 1 ) := wpr ( i ).load;
data ( 0 ) := wpr ( i ).store;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "111" =>
data := r.x.data ( conv_integer ( r.x.set ) );
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE itrace (
r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
di : out tracebuf_in_type
) IS
VARIABLE meminst : std_ulogic;
BEGIN
di.addr := ( OTHERS => '0' );
di.data := ( OTHERS => '0' );
di.enable := '0';
di.write := ( OTHERS => '0' );
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst ( 31 ) and r.x.ctrl.inst ( 30 );
di.addr ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 ) := dsur.tbufcnt;
di.data ( 127 ) := '0';
di.data ( 126 ) := not r.x.ctrl.pv;
di.data ( 125 downto 96 ) := dbgi.timer ( 29 downto 0 );
di.data ( 95 downto 64 ) := res;
di.data ( 63 downto 34 ) := r.x.ctrl.pc ( 31 downto 2 );
di.data ( 33 ) := trap;
di.data ( 32 ) := error;
di.data ( 31 downto 0 ) := r.x.ctrl.inst;
IF ( dbgi.tenable = '0' ) or ( r.x.rstate = dsu2 ) THEN
IF ( ( dbgi.dsuen and dbgi.denable ) = '1' ) and ( dbgi.daddr ( 23 downto 20 ) & dbgi.daddr ( 16 ) = "00010" ) THEN
di.enable := '1';
di.addr ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 ) := dbgi.daddr ( 10 + LOG2 ( 2 ) - 4 - 1 + 4 downto 4 );
IF dbgi.dwrite = '1' THEN
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
di.write ( 3 ) := '1';
WHEN "01" =>
di.write ( 2 ) := '1';
WHEN "10" =>
di.write ( 1 ) := '1';
WHEN OTHERS =>
di.write ( 0 ) := '1';
END CASE;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
END IF;
END IF;
ELSIF ( not r.x.ctrl.annul and ( r.x.ctrl.pv or meminst ) and not r.x.debug ) = '1' THEN
di.enable := '1';
di.write := ( OTHERS => '1' );
tbufcnt := dsur.tbufcnt + 1;
END IF;
di.diag := dco.testen & "000";
IF dco.scanen = '1' THEN
di.enable := '0';
END IF;
END;
PROCEDURE dbg_cache (
holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) IS
BEGIN
mresult2 := mresult;
dci2 := dci;
dci2.dsuen := '0';
IF r.x.rstate = dsu2 THEN
dci2.asi := dsur.asi;
IF ( dbgi.daddr ( 22 downto 20 ) = "111" ) and ( dbgi.dsuen = '1' ) THEN
dci2.dsuen := ( dbgi.denable or r.m.dci.dsuen ) and not dsur.crdy ( 2 );
dci2.enaddr := dbgi.denable;
dci2.size := "10";
dci2.read := '1';
dci2.write := '0';
IF ( dbgi.denable and not r.m.dci.enaddr ) = '1' THEN
mresult2 := ( OTHERS => '0' );
mresult2 ( 19 downto 2 ) := dbgi.daddr ( 19 downto 2 );
ELSE
mresult2 := dbgi.ddata;
END IF;
IF dbgi.dwrite = '1' THEN
dci2.read := '0';
dci2.write := '1';
END IF;
END IF;
END IF;
END;
PROCEDURE fpexack (
r : in registers;
fpexc : out std_ulogic
) IS
BEGIN
fpexc := '0';
END;
PROCEDURE diagrdy (
denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector ( 2 downto 1 )
) IS
BEGIN
crdy := dsur.crdy ( 1 ) & '0';
IF dci.dsuen = '1' THEN
CASE dsur.asi ( 4 downto 0 ) IS
WHEN ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy ( 2 ) := ico.diagrdy and not dsur.crdy ( 2 );
WHEN ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy ( 1 ) := not denable and dci.enaddr and not dsur.crdy ( 1 );
WHEN OTHERS =>
crdy ( 2 ) := dci.enaddr and denable;
END CASE;
END IF;
END;
SIGNAL r : registers;
SIGNAL rin : registers;
SIGNAL wpr : watchpoint_registers;
SIGNAL wprin : watchpoint_registers;
SIGNAL dsur : dsu_registers;
SIGNAL dsuin : dsu_registers;
SIGNAL ir : irestart_register;
SIGNAL irin : irestart_register;
SIGNAL rp : pwd_register_type;
SIGNAL rpin : pwd_register_type;
CONSTANT EXE_AND : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_XOR : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_OR : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_XNOR : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ANDN : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_ORN : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_DIV : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_PASS1 : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_PASS2 : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_STB : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_STH : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ONES : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_RDY : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_SPR : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_LINK : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT EXE_SLL : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_SRL : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_SRA : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_NOP : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_RES_ADD : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT EXE_RES_SHIFT : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT EXE_RES_LOGIC : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT EXE_RES_MISC : std_logic_vector ( 1 downto 0 ) := "11";
CONSTANT SZBYTE : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT SZHALF : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT SZWORD : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT SZDBL : std_logic_vector ( 1 downto 0 ) := "11";
PROCEDURE regaddr (
cwp : std_logic_vector;
reg : std_logic_vector ( 4 downto 0 );
rao : out rfatype
) IS
VARIABLE ra : rfatype;
CONSTANT globals : std_logic_vector ( LOG2 ( 8 + 1 ) + 4 - 5 downto 0 ) := conv_std_logic_vector ( 8 , LOG2 ( 8 + 1 ) + 4 - 4 );
BEGIN
ra := ( OTHERS => '0' );
ra ( 4 downto 0 ) := reg;
IF reg ( 4 downto 3 ) = "00" THEN
ra ( LOG2 ( 8 + 1 ) + 4 - 1 downto 4 ) := CONV_STD_LOGIC_VECTOR ( 8 , LOG2 ( 8 + 1 ) + 4 - 4 );
ELSE
ra ( LOG2 ( 8 ) + 3 downto 4 ) := cwp + ra ( 4 );
END IF;
rao := ra;
END;
FUNCTION branch_address (
inst : word;
pc : pctype
) RETURN std_logic_vector IS
VARIABLE baddr : pctype;
VARIABLE caddr : pctype;
VARIABLE tmp : pctype;
BEGIN
caddr := ( OTHERS => '0' );
caddr ( 31 downto 2 ) := inst ( 29 downto 0 );
caddr ( 31 downto 2 ) := caddr ( 31 downto 2 ) + pc ( 31 downto 2 );
baddr := ( OTHERS => '0' );
baddr ( 31 downto 24 ) := ( OTHERS => inst ( 21 ) );
baddr ( 23 downto 2 ) := inst ( 21 downto 0 );
baddr ( 31 downto 2 ) := baddr ( 31 downto 2 ) + pc ( 31 downto 2 );
IF inst ( 30 ) = '1' THEN
tmp := caddr;
ELSE
tmp := baddr;
END IF;
RETURN ( tmp );
END;
FUNCTION branch_true (
icc : std_logic_vector ( 3 downto 0 );
inst : word
) RETURN std_ulogic IS
VARIABLE n : std_ulogic;
VARIABLE z : std_ulogic;
VARIABLE v : std_ulogic;
VARIABLE c : std_ulogic;
VARIABLE branch : std_ulogic;
BEGIN
n := icc ( 3 );
z := icc ( 2 );
v := icc ( 1 );
c := icc ( 0 );
CASE inst ( 27 downto 25 ) IS
WHEN "000" =>
branch := inst ( 28 ) xor '0';
WHEN "001" =>
branch := inst ( 28 ) xor z;
WHEN "010" =>
branch := inst ( 28 ) xor ( z or ( n xor v ) );
WHEN "011" =>
branch := inst ( 28 ) xor ( n xor v );
WHEN "100" =>
branch := inst ( 28 ) xor ( c or z );
WHEN "101" =>
branch := inst ( 28 ) xor c;
WHEN "110" =>
branch := inst ( 28 ) xor n;
WHEN OTHERS =>
branch := inst ( 28 ) xor v;
END CASE;
RETURN ( branch );
END;
PROCEDURE su_et_select (
r : in registers;
xc_ps : in std_ulogic;
xc_s : in std_ulogic;
xc_et : in std_ulogic;
su : out std_ulogic;
et : out std_ulogic
) IS
BEGIN
IF ( ( r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett ) = '1' ) and ( r.x.annul_all = '0' ) THEN
su := xc_ps;
et := '1';
ELSE
su := xc_s;
et := xc_et;
END IF;
END;
FUNCTION wphit (
r : registers;
wpr : watchpoint_registers;
debug : l3_debug_in_type
) RETURN std_ulogic IS
VARIABLE exc : std_ulogic;
BEGIN
exc := '0';
IF ( ( wpr ( 0 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 0 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = Zero32 ( 31 downto 2 ) ) THEN
exc := '1';
END IF;
END IF;
IF ( ( wpr ( 1 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 1 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = Zero32 ( 31 downto 2 ) ) THEN
exc := '1';
END IF;
END IF;
IF ( debug.dsuen and not r.a.ctrl.annul ) = '1' THEN
exc := exc or ( r.a.ctrl.pv and ( ( debug.dbreak and debug.bwatch ) or r.a.step ) );
END IF;
RETURN ( exc );
END;
FUNCTION shift3 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE shiftin : unsigned ( 63 downto 0 );
VARIABLE shiftout : unsigned ( 63 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
IF r.e.shleft = '1' THEN
shiftin ( 30 downto 0 ) := ( OTHERS => '0' );
shiftin ( 63 downto 31 ) := '0' & unsigned ( aluin1 );
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => r.e.sari );
shiftin ( 31 downto 0 ) := unsigned ( aluin1 );
END IF;
shiftout := SHIFT_RIGHT ( shiftin , cnt );
RETURN ( std_logic_vector ( shiftout ( 31 downto 0 ) ) );
END;
FUNCTION shift2 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE ushiftin : unsigned ( 31 downto 0 );
VARIABLE sshiftin : signed ( 32 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
ushiftin := unsigned ( aluin1 );
sshiftin := signed ( '0' & aluin1 );
IF r.e.shleft = '1' THEN
RETURN ( std_logic_vector ( SHIFT_LEFT ( ushiftin , cnt ) ) );
ELSE
IF r.e.sari = '1' THEN
sshiftin ( 32 ) := aluin1 ( 31 );
END IF;
sshiftin := SHIFT_RIGHT ( sshiftin , cnt );
RETURN ( std_logic_vector ( sshiftin ( 31 downto 0 ) ) );
END IF;
END;
FUNCTION shift (
r : registers;
aluin1 : word;
aluin2 : word;
shiftcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic
) RETURN word IS
VARIABLE shiftin : std_logic_vector ( 63 downto 0 );
BEGIN
shiftin := zero32 & aluin1;
IF r.e.shleft = '1' THEN
shiftin ( 31 downto 0 ) := zero32;
shiftin ( 63 downto 31 ) := '0' & aluin1;
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => sari );
END IF;
IF shiftcnt ( 4 ) = '1' THEN
shiftin ( 47 downto 0 ) := shiftin ( 63 downto 16 );
END IF;
IF shiftcnt ( 3 ) = '1' THEN
shiftin ( 39 downto 0 ) := shiftin ( 47 downto 8 );
END IF;
IF shiftcnt ( 2 ) = '1' THEN
shiftin ( 35 downto 0 ) := shiftin ( 39 downto 4 );
END IF;
IF shiftcnt ( 1 ) = '1' THEN
shiftin ( 33 downto 0 ) := shiftin ( 35 downto 2 );
END IF;
IF shiftcnt ( 0 ) = '1' THEN
shiftin ( 31 downto 0 ) := shiftin ( 32 downto 1 );
END IF;
RETURN ( shiftin ( 31 downto 0 ) );
END;
PROCEDURE exception_detect (
r : registers;
wpr : watchpoint_registers;
dbgi : l3_debug_in_type;
trapin : in std_ulogic;
ttin : in std_logic_vector ( 5 downto 0 );
trap : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE illegal_inst : std_ulogic;
VARIABLE privileged_inst : std_ulogic;
VARIABLE cp_disabled : std_ulogic;
VARIABLE fp_disabled : std_ulogic;
VARIABLE fpop : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE inst : word;
VARIABLE wph : std_ulogic;
BEGIN
inst := r.a.ctrl.inst;
trap := trapin;
tt := ttin;
IF r.a.ctrl.annul = '0' THEN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
rd := inst ( 29 downto 25 );
illegal_inst := '0';
privileged_inst := '0';
cp_disabled := '0';
fp_disabled := '0';
fpop := '0';
CASE op IS
WHEN CALL =>
NULL;
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI | BICC =>
NULL;
WHEN FBFCC =>
fp_disabled := '1';
WHEN CBCCC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR | XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX | ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC | SAVE | RESTORE | RDY =>
NULL;
WHEN TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
NULL;
WHEN UMAC | SMAC =>
illegal_inst := '1';
WHEN UMUL | SMUL | UMULCC | SMULCC =>
NULL;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
NULL;
WHEN RETT =>
illegal_inst := r.a.et;
privileged_inst := not r.a.su;
WHEN RDPSR | RDTBR | RDWIM =>
privileged_inst := not r.a.su;
WHEN WRY =>
NULL;
WHEN WRPSR =>
privileged_inst := not r.a.su;
WHEN WRWIM | WRTBR =>
privileged_inst := not r.a.su;
WHEN FPOP1 | FPOP2 =>
fp_disabled := '1';
fpop := '0';
WHEN CPOP1 | CPOP2 =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN OTHERS =>
CASE op3 IS
WHEN LDD | ISTD =>
illegal_inst := rd ( 0 );
WHEN LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
NULL;
WHEN LDDA | STDA =>
illegal_inst := inst ( 13 ) or rd ( 0 );
privileged_inst := not r.a.su;
WHEN LDA | LDUBA | LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA | SWAPA =>
illegal_inst := inst ( 13 );
privileged_inst := not r.a.su;
WHEN LDDF | STDF | LDF | LDFSR | STF | STFSR =>
fp_disabled := '1';
WHEN STDFQ =>
privileged_inst := not r.a.su;
fp_disabled := '1';
WHEN STDCQ =>
privileged_inst := not r.a.su;
cp_disabled := '1';
WHEN LDC | LDCSR | LDDC | STC | STCSR | STDC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
END CASE;
wph := wphit ( r , wpr , dbgi );
trap := '1';
IF r.a.ctrl.trap = '1' THEN
tt := TT_IAEX;
ELSIF privileged_inst = '1' THEN
tt := TT_PRIV;
ELSIF illegal_inst = '1' THEN
tt := TT_IINST;
ELSIF fp_disabled = '1' THEN
tt := TT_FPDIS;
ELSIF cp_disabled = '1' THEN
tt := TT_CPDIS;
ELSIF wph = '1' THEN
tt := TT_WATCH;
ELSIF r.a.wovf = '1' THEN
tt := TT_WINOF;
ELSIF r.a.wunf = '1' THEN
tt := TT_WINUF;
ELSIF r.a.ticc = '1' THEN
tt := TT_TICC;
ELSE
trap := '0';
tt := ( OTHERS => '0' );
END IF;
END IF;
END;
PROCEDURE wicc_y_gen (
inst : word;
wicc : out std_ulogic;
wy : out std_ulogic
) IS
BEGIN
wicc := '0';
wy := '0';
IF inst ( 31 downto 30 ) = FMT3 THEN
CASE inst ( 24 downto 19 ) IS
WHEN SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC | ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
WHEN WRY =>
IF r.d.inst ( conv_integer ( r.d.set ) ) ( 29 downto 25 ) = "00000" THEN
wy := '1';
END IF;
WHEN MULSCC =>
wicc := '1';
wy := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UMULCC | SMULCC =>
IF ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wicc := '1';
wy := '1';
END IF;
WHEN UMUL | SMUL =>
IF ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wy := '1';
END IF;
WHEN UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wicc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
PROCEDURE cwp_gen (
r : registers;
v : registers;
annul : std_ulogic;
wcwp : std_ulogic;
ncwp : cwptype;
cwp : out cwptype
) IS
BEGIN
IF ( r.x.rstate = trap ) or ( r.x.rstate = dsu2 ) or ( rstn = '0' ) THEN
cwp := v.w.s.cwp;
ELSIF ( wcwp = '1' ) and ( annul = '0' ) THEN
cwp := ncwp;
ELSIF r.m.wcwp = '1' THEN
cwp := r.m.result ( LOG2 ( 8 ) - 1 downto 0 );
ELSE
cwp := r.d.cwp;
END IF;
END;
PROCEDURE cwp_ex (
r : in registers;
wcwp : out std_ulogic
) IS
BEGIN
IF ( r.e.ctrl.inst ( 31 downto 30 ) = FMT3 ) and ( r.e.ctrl.inst ( 24 downto 19 ) = WRPSR ) THEN
wcwp := not r.e.ctrl.annul;
ELSE
wcwp := '0';
END IF;
END;
PROCEDURE cwp_ctrl (
r : in registers;
xc_wim : in std_logic_vector ( 8 - 1 downto 0 );
inst : word;
de_cwp : out cwptype;
wovf_exc : out std_ulogic;
wunf_exc : out std_ulogic;
wcwp : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE wim : word;
VARIABLE ncwp : cwptype;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
wovf_exc := '0';
wunf_exc := '0';
wim := ( OTHERS => '0' );
wim ( 8 - 1 downto 0 ) := xc_wim;
ncwp := r.d.cwp;
wcwp := '0';
IF ( op = FMT3 ) and ( ( op3 = RETT ) or ( op3 = RESTORE ) or ( op3 = SAVE ) ) THEN
wcwp := '1';
IF ( op3 = SAVE ) THEN
ncwp := r.d.cwp - 1;
ELSE
ncwp := r.d.cwp + 1;
END IF;
IF wim ( conv_integer ( ncwp ) ) = '1' THEN
IF op3 = SAVE THEN
wovf_exc := '1';
ELSE
wunf_exc := '1';
END IF;
END IF;
END IF;
de_cwp := ncwp;
END;
PROCEDURE rs1_gen (
r : registers;
inst : word;
rs1 : out std_logic_vector ( 4 downto 0 );
rs1mod : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
rs1 := inst ( 18 downto 14 );
rs1mod := '0';
IF ( op = LDST ) THEN
IF ( ( r.d.cnt = "01" ) and ( ( op3 ( 2 ) and not op3 ( 3 ) ) = '1' ) ) or ( r.d.cnt = "10" ) THEN
rs1mod := '1';
rs1 := inst ( 29 downto 25 );
END IF;
IF ( ( r.d.cnt = "10" ) and ( op3 ( 3 downto 0 ) = "0111" ) ) THEN
rs1 ( 0 ) := '1';
END IF;
END IF;
END;
PROCEDURE lock_gen (
r : registers;
rs2 : std_logic_vector ( 4 downto 0 );
rd : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rfrd : rfatype;
inst : word;
fpc_lock : std_ulogic;
mulinsn : std_ulogic;
divinsn : std_ulogic;
lldcheck1 : out std_ulogic;
lldcheck2 : out std_ulogic;
lldlock : out std_ulogic;
lldchkra : out std_ulogic;
lldchkex : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE rs1 : std_logic_vector ( 4 downto 0 );
VARIABLE i : std_ulogic;
VARIABLE ldcheck1 : std_ulogic;
VARIABLE ldcheck2 : std_ulogic;
VARIABLE ldchkra : std_ulogic;
VARIABLE ldchkex : std_ulogic;
VARIABLE ldcheck3 : std_ulogic;
VARIABLE ldlock : std_ulogic;
VARIABLE icc_check : std_ulogic;
VARIABLE bicc_hold : std_ulogic;
VARIABLE chkmul : std_ulogic;
VARIABLE y_check : std_ulogic;
VARIABLE lddlock : boolean;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
rs1 := inst ( 18 downto 14 );
lddlock := false;
i := inst ( 13 );
ldcheck1 := '0';
ldcheck2 := '0';
ldcheck3 := '0';
ldlock := '0';
ldchkra := '1';
ldchkex := '1';
icc_check := '0';
bicc_hold := '0';
y_check := '0';
IF ( r.d.annul = '0' ) THEN
CASE op IS
WHEN FMT2 =>
IF ( op2 = BICC ) and ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN FMT3 =>
ldcheck1 := '1';
ldcheck2 := not i;
CASE op3 IS
WHEN TICC =>
IF ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN RDY =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDWIM | RDTBR =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDPSR =>
ldcheck1 := '0';
ldcheck2 := '0';
icc_check := '1';
icc_check := '1';
WHEN SDIV | SDIVCC | UDIV | UDIVCC =>
y_check := '1';
WHEN FPOP1 | FPOP2 =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
ldcheck1 := '1';
ldchkra := '0';
CASE r.d.cnt IS
WHEN "00" =>
ldcheck2 := not i;
ldchkra := '1';
WHEN "01" =>
ldcheck2 := not i;
WHEN OTHERS =>
ldchkex := '0';
END CASE;
IF ( op3 ( 2 downto 0 ) = "011" ) THEN
lddlock := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
chkmul := mulinsn;
bicc_hold := bicc_hold or ( icc_check and r.m.ctrl.wicc and ( r.m.ctrl.cnt ( 0 ) or r.m.mul ) );
bicc_hold := bicc_hold or ( y_check and ( r.a.ctrl.wy or r.e.ctrl.wy ) );
chkmul := chkmul or divinsn;
bicc_hold := bicc_hold or ( icc_check and ( r.a.ctrl.wicc or r.e.ctrl.wicc ) );
IF ( ( ( r.a.ctrl.ld or chkmul ) and r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.a.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.a.ctrl.rd = rfa2 ) ) or ( ( ldcheck3 = '1' ) and ( r.a.ctrl.rd = rfrd ) ) ) THEN
ldlock := '1';
END IF;
IF ( ( ( r.e.ctrl.ld or r.e.mac ) and r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.e.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.e.ctrl.rd = rfa2 ) ) ) THEN
ldlock := '1';
END IF;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1;
lldcheck2 := ldcheck2;
lldlock := ldlock;
lldchkra := ldchkra;
lldchkex := ldchkex;
END;
PROCEDURE fpbranch (
inst : in word;
fcc : in std_logic_vector ( 1 downto 0 );
branch : out std_ulogic
) IS
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE fbres : std_ulogic;
BEGIN
cond := inst ( 28 downto 25 );
CASE cond ( 2 downto 0 ) IS
WHEN "000" =>
fbres := '0';
WHEN "001" =>
fbres := fcc ( 1 ) or fcc ( 0 );
WHEN "010" =>
fbres := fcc ( 1 ) xor fcc ( 0 );
WHEN "011" =>
fbres := fcc ( 0 );
WHEN "100" =>
fbres := ( not fcc ( 1 ) ) and fcc ( 0 );
WHEN "101" =>
fbres := fcc ( 1 );
WHEN "110" =>
fbres := fcc ( 1 ) and not fcc ( 0 );
WHEN OTHERS =>
fbres := fcc ( 1 ) and fcc ( 0 );
END CASE;
branch := cond ( 3 ) xor fbres;
END;
PROCEDURE ic_ctrl (
r : registers;
inst : word;
annul_all : in std_ulogic;
ldlock : in std_ulogic;
branch_true : in std_ulogic;
fbranch_true : in std_ulogic;
cbranch_true : in std_ulogic;
fccv : in std_ulogic;
cccv : in std_ulogic;
cnt : out std_logic_vector ( 1 downto 0 );
de_pc : out pctype;
de_branch : out std_ulogic;
ctrl_annul : out std_ulogic;
de_annul : out std_ulogic;
jmpl_inst : out std_ulogic;
inull : out std_ulogic;
de_pv : out std_ulogic;
ctrl_pv : out std_ulogic;
de_hold_pc : out std_ulogic;
ticc_exception : out std_ulogic;
rett_inst : out std_ulogic;
mulstart : out std_ulogic;
divstart : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE hold_pc : std_ulogic;
VARIABLE annul_current : std_ulogic;
VARIABLE annul_next : std_ulogic;
VARIABLE branch : std_ulogic;
VARIABLE annul : std_ulogic;
VARIABLE pv : std_ulogic;
VARIABLE de_jmpl : std_ulogic;
BEGIN
branch := '0';
annul_next := '0';
annul_current := '0';
pv := '1';
hold_pc := '0';
ticc_exception := '0';
rett_inst := '0';
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
annul := inst ( 29 );
de_jmpl := '0';
cnt := "00";
mulstart := '0';
divstart := '0';
IF r.d.annul = '0' THEN
CASE inst ( 31 downto 30 ) IS
WHEN CALL =>
branch := '1';
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
END IF;
WHEN FMT2 =>
IF ( op2 = BICC ) THEN
branch := branch_true;
IF hold_pc = '0' THEN
IF ( branch = '1' ) THEN
IF ( cond = BA ) and ( annul = '1' ) THEN
annul_next := '1';
END IF;
ELSE
annul_next := annul;
END IF;
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
annul_next := '0';
END IF;
END IF;
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
mulstart := '1';
WHEN "01" =>
IF mulo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
divstart := '1';
WHEN "01" =>
IF divo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN TICC =>
IF branch_true = '1' THEN
ticc_exception := '1';
END IF;
WHEN RETT =>
rett_inst := '1';
WHEN JMPL =>
de_jmpl := '1';
WHEN WRY =>
IF FALSE THEN
IF inst ( 29 downto 25 ) = "10011" THEN
CASE r.d.cnt IS
WHEN "00" =>
pv := '0';
cnt := "00";
hold_pc := '1';
IF r.x.ipend = '1' THEN
cnt := "01";
END IF;
WHEN "01" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.d.cnt IS
WHEN "00" =>
IF ( op3 ( 2 ) = '1' ) or ( op3 ( 1 downto 0 ) = "11" ) THEN
cnt := "01";
hold_pc := '1';
pv := '0';
END IF;
WHEN "01" =>
IF ( op3 ( 2 downto 0 ) = "111" ) or ( op3 ( 3 downto 0 ) = "1101" ) or ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( ( op3 ( 5 ) & op3 ( 2 downto 0 ) ) = "1110" ) ) THEN
cnt := "10";
pv := '0';
hold_pc := '1';
ELSE
cnt := "00";
END IF;
WHEN "10" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END IF;
IF ldlock = '1' THEN
cnt := r.d.cnt;
annul_next := '0';
pv := '1';
END IF;
hold_pc := ( hold_pc or ldlock ) and not annul_all;
IF hold_pc = '1' THEN
de_pc := r.d.pc;
ELSE
de_pc := r.f.pc;
END IF;
annul_current := ( annul_current or ldlock or annul_all );
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ( ( r.d.inull and not hold_pc ) or annul_all );
jmpl_inst := de_jmpl and not annul_current;
annul_next := ( r.d.inull and not hold_pc ) or annul_next or annul_all;
IF ( annul_next = '1' ) or ( rstn = '0' ) THEN
cnt := ( OTHERS => '0' );
END IF;
de_hold_pc := hold_pc;
de_branch := branch;
de_annul := annul_next;
de_pv := pv;
ctrl_pv := r.d.pv and not ( ( r.d.annul and not r.d.pv ) or annul_all or annul_current );
inull := ( not rstn ) or r.d.inull or hold_pc or annul_all;
END;
PROCEDURE rd_gen (
r : registers;
inst : word;
wreg : out std_ulogic;
ld : out std_ulogic;
rdo : out std_logic_vector ( 4 downto 0 )
) IS
VARIABLE write_reg : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
write_reg := '0';
rd := inst ( 29 downto 25 );
ld := '0';
CASE op IS
WHEN CALL =>
write_reg := '1';
rd := "01111";
WHEN FMT2 =>
IF ( op2 = SETHI ) THEN
write_reg := '1';
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
write_reg := '1';
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
write_reg := '1';
END IF;
WHEN RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH =>
NULL;
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
write_reg := '1';
END CASE;
WHEN OTHERS =>
ld := not op3 ( 2 );
IF ( op3 ( 2 ) = '0' ) and not ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( op3 ( 5 ) = '1' ) ) THEN
write_reg := '1';
END IF;
CASE op3 IS
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
IF r.d.cnt = "00" THEN
write_reg := '1';
ld := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF r.d.cnt = "01" THEN
CASE op3 IS
WHEN LDD | LDDA | LDDC | LDDF =>
rd ( 0 ) := '1';
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END CASE;
IF ( rd = "00000" ) THEN
write_reg := '0';
END IF;
wreg := write_reg;
rdo := rd;
END;
FUNCTION imm_data (
r : registers;
insn : word
) RETURN word IS
VARIABLE immediate_data : word;
VARIABLE inst : word;
BEGIN
immediate_data := ( OTHERS => '0' );
inst := insn;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
immediate_data := inst ( 21 downto 0 ) & "0000000000";
WHEN OTHERS =>
immediate_data ( 31 downto 13 ) := ( OTHERS => inst ( 12 ) );
immediate_data ( 12 downto 0 ) := inst ( 12 downto 0 );
END CASE;
RETURN ( immediate_data );
END;
FUNCTION get_spr (
r : registers
) RETURN word IS
VARIABLE spr : word;
BEGIN
spr := ( OTHERS => '0' );
CASE r.e.ctrl.inst ( 24 downto 19 ) IS
WHEN RDPSR =>
spr ( 31 downto 5 ) := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr ( LOG2 ( 8 ) - 1 downto 0 ) := r.e.cwp;
WHEN RDTBR =>
spr ( 31 downto 4 ) := r.w.s.tba & r.w.s.tt;
WHEN RDWIM =>
spr ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( spr );
END;
FUNCTION imm_select (
inst : word
) RETURN boolean IS
VARIABLE imm : boolean;
BEGIN
imm := false;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
CASE inst ( 24 downto 22 ) IS
WHEN SETHI =>
imm := true;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE inst ( 24 downto 19 ) IS
WHEN RDWIM | RDPSR | RDTBR =>
imm := true;
WHEN OTHERS =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
END CASE;
WHEN LDST =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( imm );
END;
PROCEDURE alu_op (
r : in registers;
iop1 : in word;
iop2 : in word;
me_icc : std_logic_vector ( 3 downto 0 );
my : std_ulogic;
ldbp : std_ulogic;
aop1 : out word;
aop2 : out word;
aluop : out std_logic_vector ( 2 downto 0 );
alusel : out std_logic_vector ( 1 downto 0 );
aluadd : out std_ulogic;
shcnt : out std_logic_vector ( 4 downto 0 );
sari : out std_ulogic;
shleft : out std_ulogic;
ymsb : out std_ulogic;
mulins : out std_ulogic;
divins : out std_ulogic;
mulstep : out std_ulogic;
macins : out std_ulogic;
ldbp2 : out std_ulogic;
invop2 : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE y0 : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op2 := r.a.ctrl.inst ( 24 downto 22 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
aop1 := iop1;
aop2 := iop2;
ldbp2 := ldbp;
aluop := "000";
alusel := "11";
aluadd := '1';
shcnt := iop2 ( 4 downto 0 );
sari := '0';
shleft := '0';
invop2 := '0';
ymsb := iop1 ( 0 );
mulins := '0';
divins := '0';
mulstep := '0';
macins := '0';
IF r.e.ctrl.wy = '1' THEN
y0 := my;
ELSIF r.m.ctrl.wy = '1' THEN
y0 := r.m.y ( 0 );
ELSIF r.x.ctrl.wy = '1' THEN
y0 := r.x.y ( 0 );
ELSE
y0 := r.w.s.y ( 0 );
END IF;
IF r.e.ctrl.wicc = '1' THEN
icc := me_icc;
ELSIF r.m.ctrl.wicc = '1' THEN
icc := r.m.icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icc := r.x.icc;
ELSE
icc := r.w.s.icc;
END IF;
CASE op IS
WHEN CALL =>
aluop := "111";
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI =>
aluop := "001";
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE | TICC | JMPL | RETT =>
alusel := "00";
WHEN ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := "00";
aluadd := '0';
aop2 := not iop2;
invop2 := '1';
WHEN MULSCC =>
alusel := "00";
aop1 := ( icc ( 3 ) xor icc ( 1 ) ) & iop1 ( 31 downto 1 );
IF y0 = '0' THEN
aop2 := ( OTHERS => '0' );
ldbp2 := '0';
END IF;
mulstep := '1';
WHEN UMUL | UMULCC | SMUL | SMULCC =>
mulins := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | UDIVCC | SDIV | SDIVCC =>
aluop := "110";
alusel := "10";
divins := '1';
WHEN IAND | ANDCC =>
aluop := "000";
alusel := "10";
WHEN ANDN | ANDNCC =>
aluop := "100";
alusel := "10";
WHEN IOR | ORCC =>
aluop := "010";
alusel := "10";
WHEN ORN | ORNCC =>
aluop := "101";
alusel := "10";
WHEN IXNOR | XNORCC =>
aluop := "011";
alusel := "10";
WHEN XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := "001";
alusel := "10";
WHEN RDPSR | RDTBR | RDWIM =>
aluop := "110";
WHEN RDY =>
aluop := "101";
WHEN ISLL =>
aluop := "001";
alusel := "01";
shleft := '1';
shcnt := not iop2 ( 4 downto 0 );
invop2 := '1';
WHEN ISRL =>
aluop := "010";
alusel := "01";
WHEN ISRA =>
aluop := "100";
alusel := "01";
sari := iop1 ( 31 );
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.a.ctrl.cnt IS
WHEN "00" =>
alusel := "00";
WHEN "01" =>
CASE op3 IS
WHEN LDD | LDDA | LDDC =>
alusel := "00";
WHEN LDDF =>
alusel := "00";
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
alusel := "00";
WHEN STF | STDF =>
NULL;
WHEN OTHERS =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF op3 ( 1 downto 0 ) = "01" THEN
aluop := "010";
ELSIF op3 ( 1 downto 0 ) = "10" THEN
aluop := "011";
END IF;
END IF;
END CASE;
WHEN "10" =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF ( op3 ( 3 ) and not op3 ( 1 ) ) = '1' THEN
aluop := "100";
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END;
FUNCTION ra_inull_gen (
r : registers;
v : registers
) RETURN std_ulogic IS
VARIABLE de_inull : std_ulogic;
BEGIN
de_inull := '0';
IF ( ( v.e.jmpl or v.e.ctrl.rett ) and not v.e.ctrl.annul and not ( r.e.jmpl and not r.e.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
IF ( ( v.a.jmpl or v.a.ctrl.rett ) and not v.a.ctrl.annul and not ( r.a.jmpl and not r.a.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
RETURN ( de_inull );
END;
PROCEDURE op_mux (
r : in registers;
rfd : in word;
ed : in word;
md : in word;
xd : in word;
im : in word;
rsel : in std_logic_vector ( 2 downto 0 );
ldbp : out std_ulogic;
d : out word
) IS
BEGIN
ldbp := '0';
CASE rsel IS
WHEN "000" =>
d := rfd;
WHEN "001" =>
d := ed;
WHEN "010" =>
d := md;
ldbp := r.m.ctrl.ld;
WHEN "011" =>
d := xd;
WHEN "100" =>
d := im;
WHEN "101" =>
d := ( OTHERS => '0' );
WHEN "110" =>
d := r.w.result;
WHEN OTHERS =>
d := ( OTHERS => '-' );
END CASE;
END;
PROCEDURE op_find (
r : in registers;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
rs1 : std_logic_vector ( 4 downto 0 );
ra : rfatype;
im : boolean;
rfe : out std_ulogic;
osel : out std_logic_vector ( 2 downto 0 );
ldcheck : std_ulogic
) IS
BEGIN
rfe := '0';
IF im THEN
osel := "100";
ELSIF rs1 = "00000" THEN
osel := "101";
ELSIF ( ( r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ra = r.a.ctrl.rd ) THEN
osel := "001";
ELSIF ( ( r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ra = r.e.ctrl.rd ) THEN
osel := "010";
ELSIF r.m.ctrl.wreg = '1' and ( ra = r.m.ctrl.rd ) THEN
osel := "011";
ELSE
osel := "000";
rfe := ldcheck;
END IF;
END;
PROCEDURE cin_gen (
r : registers;
me_cin : in std_ulogic;
cin : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE ncin : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
IF r.e.ctrl.wicc = '1' THEN
ncin := me_cin;
ELSE
ncin := r.m.icc ( 0 );
END IF;
cin := '0';
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN ISUB | SUBCC | TSUBCC | TSUBCCTV =>
cin := '1';
WHEN ADDX | ADDXCC =>
cin := ncin;
WHEN SUBX | SUBXCC =>
cin := not ncin;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE logic_op (
r : registers;
aluin1 : word;
aluin2 : word;
mey : word;
ymsb : std_ulogic;
logicres : out word;
y : out word
) IS
VARIABLE logicout : word;
BEGIN
CASE r.e.aluop IS
WHEN "000" =>
logicout := aluin1 and aluin2;
WHEN "100" =>
logicout := aluin1 and not aluin2;
WHEN "010" =>
logicout := aluin1 or aluin2;
WHEN "101" =>
logicout := aluin1 or not aluin2;
WHEN "001" =>
logicout := aluin1 xor aluin2;
WHEN "011" =>
logicout := aluin1 xor not aluin2;
WHEN "110" =>
logicout := aluin2;
WHEN OTHERS =>
logicout := ( OTHERS => '-' );
END CASE;
IF ( r.e.ctrl.wy and r.e.mulstep ) = '1' THEN
y := ymsb & r.m.y ( 31 downto 1 );
ELSIF r.e.ctrl.wy = '1' THEN
y := logicout;
ELSIF r.m.ctrl.wy = '1' THEN
y := mey;
ELSIF r.x.ctrl.wy = '1' THEN
y := r.x.y;
ELSE
y := r.w.s.y;
END IF;
logicres := logicout;
END;
PROCEDURE misc_op (
r : registers;
wpr : watchpoint_registers;
aluin1 : word;
aluin2 : word;
ldata : word;
mey : word;
mout : out word;
edata : out word
) IS
VARIABLE miscout : word;
VARIABLE bpdata : word;
VARIABLE stdata : word;
VARIABLE wpi : integer;
BEGIN
wpi := 0;
miscout := r.e.ctrl.pc ( 31 downto 2 ) & "00";
edata := aluin1;
bpdata := aluin1;
IF ( ( r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul ) = '1' ) and ( r.x.ctrl.rd = r.e.ctrl.rd ) and ( r.e.ctrl.inst ( 31 downto 30 ) = LDST ) and ( r.e.ctrl.cnt /= "10" ) THEN
bpdata := ldata;
END IF;
CASE r.e.aluop IS
WHEN "010" =>
miscout := bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 );
edata := miscout;
WHEN "011" =>
miscout := bpdata ( 15 downto 0 ) & bpdata ( 15 downto 0 );
edata := miscout;
WHEN "000" =>
miscout := bpdata;
edata := miscout;
WHEN "001" =>
miscout := aluin2;
WHEN "100" =>
miscout := ( OTHERS => '1' );
edata := miscout;
WHEN "101" =>
IF ( r.m.ctrl.wy = '1' ) THEN
miscout := mey;
ELSE
miscout := r.m.y;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "11" ) THEN
wpi := conv_integer ( r.e.ctrl.inst ( 16 downto 15 ) );
IF r.e.ctrl.inst ( 14 ) = '0' THEN
miscout := wpr ( wpi ).addr & '0' & wpr ( wpi ).exec;
ELSE
miscout := wpr ( wpi ).mask & wpr ( wpi ).load & wpr ( wpi ).store;
END IF;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "10" ) and ( r.e.ctrl.inst ( 14 ) = '1' ) THEN
miscout := asr17_gen ( r );
END IF;
WHEN "110" =>
miscout := get_spr ( r );
WHEN OTHERS =>
NULL;
END CASE;
mout := miscout;
END;
PROCEDURE alu_select (
r : registers;
addout : std_logic_vector ( 32 downto 0 );
op1 : word;
op2 : word;
shiftout : word;
logicout : word;
miscout : word;
res : out word;
me_icc : std_logic_vector ( 3 downto 0 );
icco : out std_logic_vector ( 3 downto 0 );
divz : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE aluresult : word;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
icc := ( OTHERS => '0' );
CASE r.e.alusel IS
WHEN "00" =>
aluresult := addout ( 32 downto 1 );
IF r.e.aluadd = '0' THEN
icc ( 0 ) := ( ( not op1 ( 31 ) ) and not op2 ( 31 ) ) or ( addout ( 32 ) and ( ( not op1 ( 31 ) ) or not op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and ( op2 ( 31 ) ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and not op2 ( 31 ) );
ELSE
icc ( 0 ) := ( op1 ( 31 ) and op2 ( 31 ) ) or ( ( not addout ( 32 ) ) and ( op1 ( 31 ) or op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and op2 ( 31 ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and ( not op2 ( 31 ) ) );
END IF;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN TADDCC | TADDCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or op2 ( 0 ) or op2 ( 1 ) or icc ( 1 );
WHEN TSUBCC | TSUBCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or ( not op2 ( 0 ) ) or ( not op2 ( 1 ) ) or icc ( 1 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF aluresult = zero32 THEN
icc ( 2 ) := '1';
END IF;
WHEN "01" =>
aluresult := shiftout;
WHEN "10" =>
aluresult := logicout;
IF aluresult = zero32 THEN
icc ( 2 ) := '1';
END IF;
WHEN OTHERS =>
aluresult := miscout;
END CASE;
IF r.e.jmpl = '1' THEN
aluresult := r.e.ctrl.pc ( 31 downto 2 ) & "00";
END IF;
icc ( 3 ) := aluresult ( 31 );
divz := icc ( 2 );
IF r.e.ctrl.wicc = '1' THEN
IF ( op = FMT3 ) and ( op3 = WRPSR ) THEN
icco := logicout ( 23 downto 20 );
ELSE
icco := icc;
END IF;
ELSIF r.m.ctrl.wicc = '1' THEN
icco := me_icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icco := r.x.icc;
ELSE
icco := r.w.s.icc;
END IF;
res := aluresult;
END;
PROCEDURE dcache_gen (
r : registers;
v : registers;
dci : out dc_in_type;
link_pc : out std_ulogic;
jump : out std_ulogic;
force_a2 : out std_ulogic;
load : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE su : std_ulogic;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
dci.signed := '0';
dci.lock := '0';
dci.dsuen := '0';
dci.size := "10";
IF op = LDST THEN
CASE op3 IS
WHEN LDUB | LDUBA =>
dci.size := "00";
WHEN LDSTUB | LDSTUBA =>
dci.size := "00";
dci.lock := '1';
WHEN LDUH | LDUHA =>
dci.size := "01";
WHEN LDSB | LDSBA =>
dci.size := "00";
dci.signed := '1';
WHEN LDSH | LDSHA =>
dci.size := "01";
dci.signed := '1';
WHEN LD | LDA | LDF | LDC =>
dci.size := "10";
WHEN SWAP | SWAPA =>
dci.size := "10";
dci.lock := '1';
WHEN LDD | LDDA | LDDF | LDDC =>
dci.size := "11";
WHEN STB | STBA =>
dci.size := "00";
WHEN STH | STHA =>
dci.size := "01";
WHEN ST | STA | STF =>
dci.size := "10";
WHEN ISTD | STDA =>
dci.size := "11";
WHEN STDF | STDFQ =>
NULL;
WHEN STDC | STDCQ =>
NULL;
WHEN OTHERS =>
dci.size := "10";
dci.lock := '0';
dci.signed := '0';
END CASE;
END IF;
link_pc := '0';
jump := '0';
force_a2 := '0';
load := '0';
dci.write := '0';
dci.enaddr := '0';
dci.read := not op3 ( 2 );
IF ( r.e.ctrl.annul = '0' ) THEN
CASE op IS
WHEN CALL =>
link_pc := '1';
WHEN FMT3 =>
CASE op3 IS
WHEN JMPL =>
jump := '1';
link_pc := '1';
WHEN RETT =>
jump := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
CASE r.e.ctrl.cnt IS
WHEN "00" =>
dci.read := op3 ( 3 ) or not op3 ( 2 );
load := op3 ( 3 ) or not op3 ( 2 );
dci.enaddr := '1';
WHEN "01" =>
force_a2 := not op3 ( 2 );
load := not op3 ( 2 );
dci.enaddr := not op3 ( 2 );
IF op3 ( 3 downto 2 ) = "01" THEN
dci.write := '1';
END IF;
IF op3 ( 3 downto 2 ) = "11" THEN
dci.enaddr := '1';
END IF;
WHEN "10" =>
dci.write := '1';
WHEN OTHERS =>
NULL;
END CASE;
IF ( r.e.ctrl.trap or ( v.x.ctrl.trap and not v.x.ctrl.annul ) ) = '1' THEN
dci.enaddr := '0';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( ( r.x.ctrl.rett and not r.x.ctrl.annul ) = '1' ) THEN
su := r.w.s.ps;
ELSE
su := r.w.s.s;
END IF;
IF su = '1' THEN
dci.asi := "00001011";
ELSE
dci.asi := "00001010";
END IF;
IF ( op3 ( 4 ) = '1' ) and ( ( op3 ( 5 ) = '0' ) or not ( 0 = 1 ) ) THEN
dci.asi := r.e.ctrl.inst ( 12 downto 5 );
END IF;
END;
PROCEDURE fpstdata (
r : in registers;
edata : in word;
eres : in word;
fpstdata : in std_logic_vector ( 31 downto 0 );
edata2 : out word;
eres2 : out word
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
edata2 := edata;
eres2 := eres;
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
END;
FUNCTION ld_align (
data : dcdtype;
set : std_logic_vector ( LOG2X ( 2 ) - 1 downto 0 );
size : std_logic_vector ( 1 downto 0 );
laddr : std_logic_vector ( 1 downto 0 );
signed : std_ulogic
) RETURN word IS
VARIABLE align_data : word;
VARIABLE rdata : word;
BEGIN
align_data := data ( conv_integer ( set ) );
rdata := ( OTHERS => '0' );
CASE size IS
WHEN "00" =>
CASE laddr IS
WHEN "00" =>
rdata ( 7 downto 0 ) := align_data ( 31 downto 24 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 31 ) );
END IF;
WHEN "01" =>
rdata ( 7 downto 0 ) := align_data ( 23 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 23 ) );
END IF;
WHEN "10" =>
rdata ( 7 downto 0 ) := align_data ( 15 downto 8 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 15 ) );
END IF;
WHEN OTHERS =>
rdata ( 7 downto 0 ) := align_data ( 7 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 7 ) );
END IF;
END CASE;
WHEN "01" =>
IF laddr ( 1 ) = '1' THEN
rdata ( 15 downto 0 ) := align_data ( 15 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 15 ) );
END IF;
ELSE
rdata ( 15 downto 0 ) := align_data ( 31 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 31 ) );
END IF;
END IF;
WHEN OTHERS =>
rdata := align_data;
END CASE;
RETURN ( rdata );
END;
PROCEDURE mem_trap (
r : registers;
wpr : watchpoint_registers;
annul : in std_ulogic;
holdn : in std_ulogic;
trapout : out std_ulogic;
iflush : out std_ulogic;
nullify : out std_ulogic;
werrout : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE cwp : std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 );
VARIABLE cwpx : std_logic_vector ( 5 downto LOG2 ( 8 ) );
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE nalign_d : std_ulogic;
VARIABLE trap : std_ulogic;
VARIABLE werr : std_ulogic;
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op2 := r.m.ctrl.inst ( 24 downto 22 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
cwpx := r.m.result ( 5 downto LOG2 ( 8 ) );
cwpx ( 5 ) := '0';
iflush := '0';
trap := r.m.ctrl.trap;
nullify := annul;
tt := r.m.ctrl.tt;
werr := ( dco.werr or r.m.werr ) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result ( 2 );
IF ( ( annul or trap ) /= '1' ) and ( r.m.ctrl.pv = '1' ) THEN
IF ( werr and holdn ) = '1' THEN
trap := '1';
tt := TT_DSEX;
werr := '0';
IF op = LDST THEN
nullify := '1';
END IF;
END IF;
END IF;
IF ( ( annul or trap ) /= '1' ) THEN
CASE op IS
WHEN FMT2 =>
CASE op2 IS
WHEN FBFCC =>
NULL;
WHEN CBCCC =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN WRPSR =>
IF ( orv ( cwpx ) = '1' ) THEN
trap := '1';
tt := TT_IINST;
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF r.m.divz = '1' THEN
trap := '1';
tt := TT_DIV;
END IF;
WHEN JMPL | RETT =>
IF r.m.nalign = '1' THEN
trap := '1';
tt := TT_UNALA;
END IF;
WHEN TADDCCTV | TSUBCCTV =>
IF ( r.m.icc ( 1 ) = '1' ) THEN
trap := '1';
tt := TT_TAG;
END IF;
WHEN FLUSH =>
iflush := '1';
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
IF r.m.ctrl.cnt = "00" THEN
CASE op3 IS
WHEN LDDF | STDF | STDFQ =>
NULL;
WHEN LDDC | STDC | STDCQ =>
NULL;
WHEN LDD | ISTD | LDDA | STDA =>
IF r.m.result ( 2 downto 0 ) /= "000" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDF | LDFSR | STFSR | STF =>
NULL;
WHEN LDC | LDCSR | STCSR | STC =>
NULL;
WHEN LD | LDA | ST | STA | SWAP | SWAPA =>
IF r.m.result ( 1 downto 0 ) /= "00" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
IF r.m.result ( 0 ) /= '0' THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF ( ( ( ( wpr ( 0 ).load and not op3 ( 2 ) ) or ( wpr ( 0 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 0 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = zero32 ( 31 downto 2 ) ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
IF ( ( ( ( wpr ( 1 ).load and not op3 ( 2 ) ) or ( wpr ( 1 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 1 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = zero32 ( 31 downto 2 ) ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( rstn = '0' ) or ( r.x.rstate = dsu2 ) THEN
werr := '0';
END IF;
trapout := trap;
werrout := werr;
END;
PROCEDURE irq_trap (
r : in registers;
ir : in irestart_register;
irl : in std_logic_vector ( 3 downto 0 );
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector ( 5 downto 0 );
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2 : out std_ulogic;
ipend : out std_ulogic;
tt2 : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE pend : std_ulogic;
BEGIN
nullify2 := nullify;
trap2 := trap;
tt2 := tt;
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
irqen := '1';
irqen2 := r.m.irqen;
IF ( annul or trap ) = '0' THEN
IF ( ( op = FMT3 ) and ( op3 = WRPSR ) ) THEN
irqen := '0';
END IF;
END IF;
IF ( irl = "1111" ) or ( irl > r.w.s.pil ) THEN
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
ELSE
pend := '0';
END IF;
ipend := pend;
IF ( ( not annul ) and pv and ( not trap ) and pend ) = '1' THEN
trap2 := '1';
tt2 := "01" & irl;
IF op = LDST THEN
nullify2 := '1';
END IF;
END IF;
END;
PROCEDURE irq_intack (
r : in registers;
holdn : in std_ulogic;
intack : out std_ulogic
) IS
BEGIN
intack := '0';
IF r.x.rstate = trap THEN
IF r.w.s.tt ( 7 downto 4 ) = "0001" THEN
intack := '1';
END IF;
END IF;
END;
PROCEDURE sp_write (
r : registers;
wpr : watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op2 := r.x.ctrl.inst ( 24 downto 22 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
s := r.w.s;
rd := r.x.ctrl.inst ( 29 downto 25 );
vwpr := wpr;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN WRY =>
IF rd = "00000" THEN
s.y := r.x.result;
ELSIF ( rd = "10001" ) THEN
s.dwt := r.x.result ( 14 );
s.svt := r.x.result ( 13 );
ELSIF rd ( 4 downto 3 ) = "11" THEN
CASE rd ( 2 downto 0 ) IS
WHEN "000" =>
vwpr ( 0 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 0 ).imp := r.x.result ( 1 );
vwpr ( 0 ).exec := r.x.result ( 0 );
WHEN "001" =>
vwpr ( 0 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 0 ).load := r.x.result ( 1 );
vwpr ( 0 ).store := r.x.result ( 0 );
WHEN "010" =>
vwpr ( 1 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 1 ).imp := r.x.result ( 1 );
vwpr ( 1 ).exec := r.x.result ( 0 );
WHEN "011" =>
vwpr ( 1 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 1 ).load := r.x.result ( 1 );
vwpr ( 1 ).store := r.x.result ( 0 );
WHEN "100" =>
vwpr ( 2 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 2 ).imp := r.x.result ( 1 );
vwpr ( 2 ).exec := r.x.result ( 0 );
WHEN "101" =>
vwpr ( 2 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 2 ).load := r.x.result ( 1 );
vwpr ( 2 ).store := r.x.result ( 0 );
WHEN "110" =>
vwpr ( 3 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 3 ).imp := r.x.result ( 1 );
vwpr ( 3 ).exec := r.x.result ( 0 );
WHEN OTHERS =>
vwpr ( 3 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 3 ).load := r.x.result ( 1 );
vwpr ( 3 ).store := r.x.result ( 0 );
END CASE;
END IF;
WHEN WRPSR =>
s.cwp := r.x.result ( LOG2 ( 8 ) - 1 downto 0 );
s.icc := r.x.result ( 23 downto 20 );
s.ec := r.x.result ( 13 );
s.pil := r.x.result ( 11 downto 8 );
s.s := r.x.result ( 7 );
s.ps := r.x.result ( 6 );
s.et := r.x.result ( 5 );
WHEN WRWIM =>
s.wim := r.x.result ( 8 - 1 downto 0 );
WHEN WRTBR =>
s.tba := r.x.result ( 31 downto 12 );
WHEN SAVE =>
s.cwp := r.w.s.cwp - 1;
WHEN RESTORE =>
s.cwp := r.w.s.cwp + 1;
WHEN RETT =>
s.cwp := r.w.s.cwp + 1;
s.s := r.w.s.ps;
s.et := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF r.x.ctrl.wicc = '1' THEN
s.icc := r.x.icc;
END IF;
IF r.x.ctrl.wy = '1' THEN
s.y := r.x.y;
END IF;
END;
FUNCTION npc_find (
r : registers
) RETURN std_logic_vector IS
VARIABLE npc : std_logic_vector ( 2 downto 0 );
BEGIN
npc := "011";
IF r.m.ctrl.pv = '1' THEN
npc := "000";
ELSIF r.e.ctrl.pv = '1' THEN
npc := "001";
ELSIF r.a.ctrl.pv = '1' THEN
npc := "010";
ELSIF r.d.pv = '1' THEN
npc := "011";
ELSE
npc := "100";
END IF;
RETURN ( npc );
END;
FUNCTION npc_gen (
r : registers
) RETURN word IS
VARIABLE npc : std_logic_vector ( 31 downto 0 );
BEGIN
npc := r.a.ctrl.pc ( 31 downto 2 ) & "00";
CASE r.x.npc IS
WHEN "000" =>
npc ( 31 downto 2 ) := r.x.ctrl.pc ( 31 downto 2 );
WHEN "001" =>
npc ( 31 downto 2 ) := r.m.ctrl.pc ( 31 downto 2 );
WHEN "010" =>
npc ( 31 downto 2 ) := r.e.ctrl.pc ( 31 downto 2 );
WHEN "011" =>
npc ( 31 downto 2 ) := r.a.ctrl.pc ( 31 downto 2 );
WHEN OTHERS =>
npc ( 31 downto 2 ) := r.d.pc ( 31 downto 2 );
END CASE;
RETURN ( npc );
END;
PROCEDURE mul_res (
r : registers;
asr18in : word;
result : out word;
y : out word;
asr18 : out word;
icc : out std_logic_vector ( 3 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
result := r.m.result;
y := r.m.y;
icc := r.m.icc;
asr18 := asr18in;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL =>
result := mulo.result ( 31 downto 0 );
y := mulo.result ( 63 downto 32 );
WHEN UMULCC | SMULCC =>
result := mulo.result ( 31 downto 0 );
icc := mulo.icc;
y := mulo.result ( 63 downto 32 );
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | SDIV =>
result := divo.result ( 31 downto 0 );
WHEN UDIVCC | SDIVCC =>
result := divo.result ( 31 downto 0 );
icc := divo.icc;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
FUNCTION powerdwn (
r : registers;
trap : std_ulogic;
rp : pwd_register_type
) RETURN std_ulogic IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE pd : std_ulogic;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
rd := r.x.ctrl.inst ( 29 downto 25 );
pd := '0';
IF ( not ( r.x.ctrl.annul or trap ) and r.x.ctrl.pv ) = '1' THEN
IF ( ( op = FMT3 ) and ( op3 = WRY ) and ( rd = "10011" ) ) THEN
pd := '1';
END IF;
pd := pd or rp.pwd;
END IF;
RETURN ( pd );
END;
SIGNAL dummy : std_ulogic;
SIGNAL cpu_index : std_logic_vector ( 3 downto 0 );
SIGNAL disasen : std_ulogic;
BEGIN
comb : PROCESS ( ico , dco , rfo , r , wpr , ir , dsur , rstn , holdn , irqi , dbgi , fpo , cpo , tbo , mulo , divo , dummy , rp )
VARIABLE v : registers;
VARIABLE vp : pwd_register_type;
VARIABLE vwpr : watchpoint_registers;
VARIABLE vdsu : dsu_registers;
VARIABLE npc : std_logic_vector ( 31 downto 2 );
VARIABLE de_raddr1 : std_logic_vector ( 9 downto 0 );
VARIABLE de_raddr2 : std_logic_vector ( 9 downto 0 );
VARIABLE de_rs2 : std_logic_vector ( 4 downto 0 );
VARIABLE de_rd : std_logic_vector ( 4 downto 0 );
VARIABLE de_hold_pc : std_ulogic;
VARIABLE de_branch : std_ulogic;
VARIABLE de_fpop : std_ulogic;
VARIABLE de_ldlock : std_ulogic;
VARIABLE de_cwp : cwptype;
VARIABLE de_cwp2 : cwptype;
VARIABLE de_inull : std_ulogic;
VARIABLE de_ren1 : std_ulogic;
VARIABLE de_ren2 : std_ulogic;
VARIABLE de_wcwp : std_ulogic;
VARIABLE de_inst : word;
VARIABLE de_branch_address : pctype;
VARIABLE de_icc : std_logic_vector ( 3 downto 0 );
VARIABLE de_fbranch : std_ulogic;
VARIABLE de_cbranch : std_ulogic;
VARIABLE de_rs1mod : std_ulogic;
VARIABLE ra_op1 : word;
VARIABLE ra_op2 : word;
VARIABLE ra_div : std_ulogic;
VARIABLE ex_jump : std_ulogic;
VARIABLE ex_link_pc : std_ulogic;
VARIABLE ex_jump_address : pctype;
VARIABLE ex_add_res : std_logic_vector ( 32 downto 0 );
VARIABLE ex_shift_res : word;
VARIABLE ex_logic_res : word;
VARIABLE ex_misc_res : word;
VARIABLE ex_edata : word;
VARIABLE ex_edata2 : word;
VARIABLE ex_dci : dc_in_type;
VARIABLE ex_force_a2 : std_ulogic;
VARIABLE ex_load : std_ulogic;
VARIABLE ex_ymsb : std_ulogic;
VARIABLE ex_op1 : word;
VARIABLE ex_op2 : word;
VARIABLE ex_result : word;
VARIABLE ex_result2 : word;
VARIABLE mul_op2 : word;
VARIABLE ex_shcnt : std_logic_vector ( 4 downto 0 );
VARIABLE ex_dsuen : std_ulogic;
VARIABLE ex_ldbp2 : std_ulogic;
VARIABLE ex_sari : std_ulogic;
VARIABLE me_inull : std_ulogic;
VARIABLE me_nullify : std_ulogic;
VARIABLE me_nullify2 : std_ulogic;
VARIABLE me_iflush : std_ulogic;
VARIABLE me_newtt : std_logic_vector ( 5 downto 0 );
VARIABLE me_asr18 : word;
VARIABLE me_signed : std_ulogic;
VARIABLE me_size : std_logic_vector ( 1 downto 0 );
VARIABLE me_laddr : std_logic_vector ( 1 downto 0 );
VARIABLE me_icc : std_logic_vector ( 3 downto 0 );
VARIABLE xc_result : word;
VARIABLE xc_df_result : word;
VARIABLE xc_waddr : std_logic_vector ( 9 downto 0 );
VARIABLE xc_exception : std_ulogic;
VARIABLE xc_wreg : std_ulogic;
VARIABLE xc_trap_address : pctype;
VARIABLE xc_vectt : std_logic_vector ( 7 downto 0 );
VARIABLE xc_trap : std_ulogic;
VARIABLE xc_fpexack : std_ulogic;
VARIABLE xc_rstn : std_ulogic;
VARIABLE xc_halt : std_ulogic;
VARIABLE diagdata : word;
VARIABLE tbufi : tracebuf_in_type;
VARIABLE dbgm : std_ulogic;
VARIABLE fpcdbgwr : std_ulogic;
VARIABLE vfpi : fpc_in_type;
VARIABLE dsign : std_ulogic;
VARIABLE pwrd : std_ulogic;
VARIABLE sidle : std_ulogic;
VARIABLE vir : irestart_register;
VARIABLE icnt : std_ulogic;
VARIABLE tbufcntx : std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
BEGIN
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := r.x.ctrl.rd ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
IF r.x.mexc = '1' THEN
xc_vectt := "00" & TT_DAEX;
ELSIF r.x.ctrl.tt = TT_TICC THEN
xc_vectt := '1' & r.x.result ( 6 downto 0 );
ELSE
xc_vectt := "00" & r.x.ctrl.tt;
END IF;
IF r.w.s.svt = '0' THEN
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & xc_vectt;
ELSE
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & "00000000";
END IF;
xc_trap_address ( 3 downto 2 ) := ( OTHERS => '0' );
xc_wreg := '0';
v.x.annul_all := '0';
IF ( r.x.ctrl.ld = '1' ) THEN
xc_result := r.x.data ( 0 );
ELSE
xc_result := r.x.result;
END IF;
xc_df_result := xc_result;
dbgm := dbgexc ( r , dbgi , xc_trap , xc_vectt );
IF ( dbgi.dsuen and dbgi.dbreak ) = '0' THEN
v.x.debug := '0';
END IF;
pwrd := '0';
CASE r.x.rstate IS
WHEN run =>
IF ( not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug ) = '1' THEN
icnt := holdn;
END IF;
IF dbgm = '1' THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find ( r );
vdsu.tt := xc_vectt;
vdsu.err := dbgerr ( r , dbgi , xc_vectt );
ELSIF ( pwrd = '1' ) and ( ir.pwd = '0' ) THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find ( r );
vp.pwd := '1';
ELSIF ( r.x.ctrl.annul or xc_trap ) = '0' THEN
xc_wreg := r.x.ctrl.wreg;
sp_write ( r , wpr , v.w.s , vwpr );
vir.pwd := '0';
ELSIF ( ( not r.x.ctrl.annul ) and xc_trap ) = '1' THEN
xc_exception := '1';
xc_result := r.x.ctrl.pc ( 31 downto 2 ) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := ( OTHERS => '0' );
xc_waddr ( LOG2 ( 8 ) + 3 downto 0 ) := r.w.s.cwp & "0001";
v.x.npc := npc_find ( r );
fpexack ( r , xc_fpexack );
IF r.w.s.et = '0' THEN
xc_wreg := '0';
END IF;
END IF;
WHEN trap =>
xc_result := npc_gen ( r );
xc_wreg := '1';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( LOG2 ( 8 ) + 3 downto 0 ) := r.w.s.cwp & "0010";
IF ( r.w.s.et = '1' ) THEN
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
ELSE
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
END IF;
WHEN dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
xc_trap_address ( 31 downto 2 ) := ir.addr;
vir.addr := npc_gen ( r ) ( 31 downto 2 );
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
WHEN dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
sidle := ( rp.pwd or rp.error ) and ico.idle and dco.idle and not r.x.debug;
IF dbgi.reset = '1' THEN
vp.pwd := '0';
vp.error := '0';
END IF;
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.debug := '1';
END IF;
diagwr ( r , dsur , ir , dbgi , wpr , v.w.s , vwpr , vdsu.asi , xc_trap_address , vir.addr , vdsu.tbufcnt , xc_wreg , xc_waddr , xc_result , fpcdbgwr );
xc_halt := dbgi.halt;
IF r.x.ipend = '1' THEN
vp.pwd := '0';
END IF;
IF ( rp.error or rp.pwd or r.x.debug or xc_halt ) = '0' THEN
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address ( 31 downto 2 ) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
irq_intack ( r , holdn , v.x.intack );
itrace ( r , dsur , vdsu , xc_result , xc_exception , dbgi , rp.error , xc_trap , tbufcntx , tbufi );
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
IF ( r.x.rstate = dsu2 ) THEN
v.w.except := '0';
END IF;
v.w.wa := xc_waddr ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= ( xc_wreg and holdn ) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt ( 3 downto 0 );
irqo.pwd <= rp.pwd;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
IF ( xc_rstn = '0' ) THEN
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
v.w.s.tt := ( OTHERS => '0' );
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.rstate := dsu1;
v.x.debug := '1';
END IF;
END IF;
v.w.s.ef := '0';
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result ( 1 downto 0 );
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res ( r , v.w.s.asr18 , v.x.result , v.x.y , me_asr18 , me_icc );
mem_trap ( r , wpr , v.x.ctrl.annul , holdn , v.x.ctrl.trap , me_iflush , me_nullify , v.m.werr , v.x.ctrl.tt );
me_newtt := v.x.ctrl.tt;
irq_trap ( r , ir , irqi.irl , v.x.ctrl.annul , v.x.ctrl.pv , v.x.ctrl.trap , me_newtt , me_nullify , v.m.irqen , v.m.irqen2 , me_nullify2 , v.x.ctrl.trap , v.x.ipend , v.x.ctrl.tt );
IF ( r.m.ctrl.ld or not dco.mds ) = '1' THEN
v.x.data ( 0 ) := dco.data ( 0 );
v.x.data ( 1 ) := dco.data ( 1 );
v.x.set := dco.set ( LOG2X ( 2 ) - 1 downto 0 );
IF dco.mds = '0' THEN
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
ELSE
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
END IF;
v.x.data ( 0 ) := ld_align ( v.x.data , v.x.set , me_size , me_laddr , me_signed );
END IF;
v.x.mexc := dco.mexc;
v.x.impwp := '0';
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
IF ( r.x.rstate = dsu2 ) THEN
me_nullify2 := '0';
v.x.set := dco.set ( LOG2X ( 2 ) - 1 downto 0 );
END IF;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
IF r.e.ldbp1 = '1' THEN
ex_op1 := r.x.data ( 0 );
ex_sari := r.x.data ( 0 ) ( 31 ) and r.e.ctrl.inst ( 19 ) and r.e.ctrl.inst ( 20 );
END IF;
IF r.e.ldbp2 = '1' THEN
ex_op2 := r.x.data ( 0 );
ex_ymsb := r.x.data ( 0 ) ( 0 );
mul_op2 := ex_op2;
ex_shcnt := r.x.data ( 0 ) ( 4 downto 0 );
IF r.e.invop2 = '1' THEN
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
END IF;
END IF;
ex_add_res := ( ex_op1 & '1' ) + ( ex_op2 & r.e.alucin );
IF ex_add_res ( 2 downto 1 ) = "00" THEN
v.m.nalign := '0';
ELSE
v.m.nalign := '1';
END IF;
dcache_gen ( r , v , ex_dci , ex_link_pc , ex_jump , ex_force_a2 , ex_load );
ex_jump_address := ex_add_res ( 32 downto 2 + 1 );
logic_op ( r , ex_op1 , ex_op2 , v.x.y , ex_ymsb , ex_logic_res , v.m.y );
ex_shift_res := shift ( r , ex_op1 , ex_op2 , ex_shcnt , ex_sari );
misc_op ( r , wpr , ex_op1 , ex_op2 , xc_df_result , v.x.y , ex_misc_res , ex_edata );
ex_add_res ( 3 ) := ex_add_res ( 3 ) or ex_force_a2;
alu_select ( r , ex_add_res , ex_op1 , ex_op2 , ex_shift_res , ex_logic_res , ex_misc_res , ex_result , me_icc , v.m.icc , v.m.divz );
dbg_cache ( holdn , dbgi , r , dsur , ex_result , ex_dci , ex_result2 , v.m.dci );
fpstdata ( r , ex_edata , ex_result2 , fpo.data , ex_edata2 , v.m.result );
cwp_ex ( r , v.m.wcwp );
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
IF ( r.x.rstate = dsu2 ) THEN
v.m.ctrl.ld := '1';
END IF;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res ( 32 downto 1 );
dci.edata <= ex_edata2;
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect ( r , wpr , dbgi , r.a.ctrl.trap , r.a.ctrl.tt , v.e.ctrl.trap , v.e.ctrl.tt );
op_mux ( r , rfo.data1 , v.m.result , v.x.result , xc_df_result , zero32 , r.a.rsel1 , v.e.ldbp1 , ra_op1 );
op_mux ( r , rfo.data2 , v.m.result , v.x.result , xc_df_result , r.a.imm , r.a.rsel2 , ex_ldbp2 , ra_op2 );
alu_op ( r , ra_op1 , ra_op2 , v.m.icc , v.m.y ( 0 ) , ex_ldbp2 , v.e.op1 , v.e.op2 , v.e.aluop , v.e.alusel , v.e.aluadd , v.e.shcnt , v.e.sari , v.e.shleft , v.e.ymsb , v.e.mul , ra_div , v.e.mulstep , v.e.mac , v.e.ldbp2 , v.e.invop2 );
cin_gen ( r , v.m.icc ( 0 ) , v.e.alucin );
de_inst := r.d.inst ( conv_integer ( r.d.set ) );
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select ( r , v.w.s.ps , v.w.s.s , v.w.s.et , v.a.su , v.a.et );
wicc_y_gen ( de_inst , v.a.ctrl.wicc , v.a.ctrl.wy );
cwp_ctrl ( r , v.w.s.wim , de_inst , de_cwp , v.a.wovf , v.a.wunf , de_wcwp );
rs1_gen ( r , de_inst , v.a.rs1 , de_rs1mod );
de_rs2 := de_inst ( 4 downto 0 );
de_raddr1 := ( OTHERS => '0' );
de_raddr2 := ( OTHERS => '0' );
IF de_rs1mod = '1' THEN
regaddr ( r.d.cwp , de_inst ( 29 downto 26 ) & v.a.rs1 ( 0 ) , de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) );
ELSE
regaddr ( r.d.cwp , de_inst ( 18 downto 15 ) & v.a.rs1 ( 0 ) , de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) );
END IF;
regaddr ( r.d.cwp , de_rs2 , de_raddr2 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) );
v.a.rfa1 := de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
v.a.rfa2 := de_raddr2 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
rd_gen ( r , de_inst , v.a.ctrl.wreg , v.a.ctrl.ld , de_rd );
regaddr ( de_cwp , de_rd , v.a.ctrl.rd );
fpbranch ( de_inst , fpo.cc , de_fbranch );
fpbranch ( de_inst , cpo.cc , de_cbranch );
v.a.imm := imm_data ( r , de_inst );
lock_gen ( r , de_rs2 , de_rd , v.a.rfa1 , v.a.rfa2 , v.a.ctrl.rd , de_inst , fpo.ldlock , v.e.mul , ra_div , v.a.ldcheck1 , v.a.ldcheck2 , de_ldlock , v.a.ldchkra , v.a.ldchkex );
ic_ctrl ( r , de_inst , v.x.annul_all , de_ldlock , branch_true ( de_icc , de_inst ) , de_fbranch , de_cbranch , fpo.ccv , cpo.ccv , v.d.cnt , v.d.pc , de_branch , v.a.ctrl.annul , v.d.annul , v.a.jmpl , de_inull , v.d.pv , v.a.ctrl.pv , de_hold_pc , v.a.ticc , v.a.ctrl.rett , v.a.mulstart , v.a.divstart );
cwp_gen ( r , v , v.a.ctrl.annul , de_wcwp , de_cwp , v.d.cwp );
v.d.inull := ra_inull_gen ( r , v );
op_find ( r , v.a.ldchkra , v.a.ldchkex , v.a.rs1 , v.a.rfa1 , false , v.a.rfe1 , v.a.rsel1 , v.a.ldcheck1 );
op_find ( r , v.a.ldchkra , v.a.ldchkex , de_rs2 , v.a.rfa2 , imm_select ( de_inst ) , v.a.rfe2 , v.a.rsel2 , v.a.ldcheck2 );
de_branch_address := branch_address ( de_inst , r.d.pc );
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
IF holdn = '0' THEN
de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := r.a.rfa1;
de_raddr2 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
ELSE
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
END IF;
IF ( ( dbgi.denable and not dbgi.dwrite ) = '1' ) and ( r.x.rstate = dsu2 ) THEN
de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := dbgi.daddr ( LOG2 ( 8 + 1 ) + 4 + 1 downto 2 );
de_ren1 := '1';
END IF;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
IF ( xc_rstn = '0' ) THEN
v.d.cnt := ( OTHERS => '0' );
END IF;
npc := r.f.pc;
IF ( xc_rstn = '0' ) THEN
v.f.pc := ( OTHERS => '0' );
v.f.branch := '0';
v.f.pc ( 31 downto 12 ) := conv_std_logic_vector ( 16#00000# , 20 );
ELSIF xc_exception = '1' THEN
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
ELSIF de_hold_pc = '1' THEN
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
IF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
END IF;
ELSIF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
ELSIF de_branch = '1' THEN
v.f.pc := branch_address ( de_inst , r.d.pc );
v.f.branch := '1';
npc := v.f.pc;
ELSE
v.f.branch := '0';
v.f.pc ( 31 downto 2 ) := r.f.pc ( 31 downto 2 ) + 1;
npc := v.f.pc;
END IF;
ici.dpc <= r.d.pc ( 31 downto 2 ) & "00";
ici.fpc <= r.f.pc ( 31 downto 2 ) & "00";
ici.rpc <= npc ( 31 downto 2 ) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= ( OTHERS => '0' );
ici.flushl <= '0';
IF ( ico.mds and de_hold_pc ) = '0' THEN
v.d.inst ( 0 ) := ico.data ( 0 );
v.d.inst ( 1 ) := ico.data ( 1 );
v.d.set := ico.set ( LOG2X ( 2 ) - 1 downto 0 );
v.d.mexc := ico.mexc;
END IF;
diagread ( dbgi , r , dsur , ir , wpr , rfo.data1 , dco , tbo , diagdata );
diagrdy ( dbgi.denable , dsur , r.m.dci , dco.mds , ico , vdsu.crdy );
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst ( 19 );
muli.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
muli.op2 <= ( mul_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & mul_op2;
muli.mac <= r.e.ctrl.inst ( 24 );
muli.acc ( 39 downto 32 ) <= r.x.y ( 7 downto 0 );
muli.acc ( 31 downto 0 ) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst ( 19 );
divi.flush <= r.x.annul_all;
divi.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
divi.op2 <= ( ex_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op2;
IF ( r.a.divstart and not r.a.ctrl.annul ) = '1' THEN
dsign := r.a.ctrl.inst ( 19 );
ELSE
dsign := r.e.ctrl.inst ( 19 );
END IF;
divi.y <= ( r.m.y ( 31 ) and dsign ) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy ( 2 );
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
END PROCESS;
preg : PROCESS ( sclk )
BEGIN
IF rising_edge ( sclk ) THEN
rp <= rpin;
IF rstn = '0' THEN
rp.error <= '0';
END IF;
END IF;
END PROCESS;
reg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF ( holdn = '1' ) THEN
r <= rin;
ELSE
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
IF ( holdn or ico.mds ) = '0' THEN
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
END IF;
IF ( holdn or dco.mds ) = '0' THEN
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.impwp <= rin.x.impwp;
r.x.set <= rin.x.set;
END IF;
END IF;
IF rstn = '0' THEN
r.x.error <= '0';
r.w.s.s <= '1';
END IF;
END IF;
END PROCESS;
dsureg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
dsur <= dsuin;
ELSE
dsur.crdy <= dsuin.crdy;
END IF;
END IF;
END PROCESS;
dsureg2 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
ir <= irin;
END IF;
END IF;
END PROCESS;
wpreg0 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 0 ) <= wprin ( 0 );
END IF;
IF rstn = '0' THEN
wpr ( 0 ).exec <= '0';
wpr ( 0 ).load <= '0';
wpr ( 0 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpreg1 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 1 ) <= wprin ( 1 );
END IF;
IF rstn = '0' THEN
wpr ( 1 ).exec <= '0';
wpr ( 1 ).load <= '0';
wpr ( 1 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpr ( 2 ) <= ( ZERO32 ( 31 DOWNTO 2 ) , ZERO32 ( 31 DOWNTO 2 ) , '0' , '0' , '0' , '0' );
wpr ( 3 ) <= ( ZERO32 ( 31 DOWNTO 2 ) , ZERO32 ( 31 DOWNTO 2 ) , '0' , '0' , '0' , '0' );
dummy <= '1';
END ARCHITECTURE;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/memctrl/memctrl.vhd | 1 | 29070 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package memctrl is
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
edac : std_logic;
end record;
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
vcdrive : std_logic_vector(7 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(7 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
end record;
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(15 downto 0);
end record;
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
vbdrive : std_logic_vector(31 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(15 downto 0);
ce : std_ulogic;
ba : std_logic_vector ( 1 downto 0); -- bank address
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0);
end record;
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
component sdctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
edacen : integer := 1;
errcnt : integer := 0;
cntbits : integer range 1 to 8 := 1;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component srctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
type sdram_in_type is record
haddr : std_logic_vector(31 downto 0); -- memory address
rhaddr : std_logic_vector(31 downto 0); -- latched memory address
hready : std_ulogic;
hsize : std_logic_vector(1 downto 0);
hsel : std_ulogic;
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
rhtrans : std_logic_vector(1 downto 0);
nhtrans : std_logic_vector(1 downto 0);
idle : std_ulogic;
enable : std_ulogic;
error : std_ulogic;
brmw : std_ulogic;
edac : std_ulogic;
srdis : std_logic;
end record;
type sdram_mctrl_out_type is record
address : std_logic_vector(16 downto 2);
busy : std_ulogic;
aload : std_ulogic;
bdrive : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
bsel : std_ulogic;
hresp : std_logic_vector (1 downto 0);
vhready : std_ulogic;
prdata : std_logic_vector (31 downto 0);
end record;
type wprot_out_type is record
wprothit : std_ulogic;
end record;
component sdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftsdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
syncrst : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftmctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
netlist : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
component ssrctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer := 0;
bus16 : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
type ddrmem_in_type is record
cke : std_ulogic;
cs : std_logic_vector(1 downto 0);
control : std_logic_vector(2 downto 0); --RAS,CAS,WE
ba : std_logic_vector(1 downto 0);
adr : std_logic_vector(13 downto 0);
dq : std_logic_vector(63 downto 0);
dm : std_logic_vector(15 downto 0);
dqs : std_logic_vector(15 downto 0);
dq_oe : std_logic_vector(63 downto 0);
dqs_oe : std_logic_vector(15 downto 0);
end record;
type ddrmem_out_type is record
dq : std_logic_vector(63 downto 0);
dqs : std_logic_vector(15 downto 0);
end record;
component ddrctrl
generic (
hindex1 : integer := 0;
haddr1 : integer := 0;
hmask1 : integer := 16#f80#;
hindex2 : integer := 0;
haddr2 : integer := 0;
hmask2 : integer := 16#f80#;
pindex : integer := 3;
paddr : integer := 0;
numahb : integer := 1; -- Allowed: 1, 2
ahb1sepclk : integer := 0; -- Allowed: 0, 1
ahb2sepclk : integer := 0; -- Allowed: 0, 1
modbanks : integer := 1; -- Allowed: 1, 2
numchips : integer := 8; -- Allowed: 1, 2, 4, 8, 16
chipbits : integer := 8; -- Allowed: 4, 8, 16
chipsize : integer := 128; -- Allowed: 64, 128, 256, 512, 1024 (MB)
plldelay : integer := 0; -- Allowed: 0, 1 (Use 200us start up delay)
tech : integer := 0;
clkperiod : integer := 10); -- 100 Mhz
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk1 : in std_ulogic;
hclk2 : in std_ulogic;
pclk : in std_ulogic;
ahb1si : in ahb_slv_in_type;
ahb1so : out ahb_slv_out_type;
ahb2si : in ahb_slv_in_type;
ahb2so : out ahb_slv_out_type;
apbsi : in apb_slv_in_type;
apbso : out apb_slv_out_type;
-- dapbso : out apb_slv_out_type;
ddsi : out ddrmem_in_type;
ddso : in ddrmem_out_type);
end component;
component ftsrctrl_v1
generic (
hindex: Integer := 1;
romaddr: Integer := 16#000#;
rommask: Integer := 16#ff0#;
ramaddr: Integer := 16#400#;
rammask: Integer := 16#ff0#;
ioaddr: Integer := 16#200#;
iomask: Integer := 16#ff0#;
ramws: Integer := 0;
romws: Integer := 0;
iows: Integer := 0;
rmw: Integer := 1;
srbanks: Integer range 1 to 8 := 8;
banksz: Integer range 0 to 13 := 0;
rombanks: Integer range 1 to 8 := 8;
rombanksz: Integer range 0 to 13 := 0;
rombankszdef: Integer range 0 to 13 := 6;
romasel: Integer range 0 to 28 := 0;
pindex: Integer := 0;
paddr: Integer := 16#000#;
pmask: Integer := 16#fff#;
edacen: Integer range 0 to 1 := 1;
errcnt: Integer range 0 to 1 := 0;
cntbits: Integer range 1 to 8 := 1;
wsreg: Integer := 1;
oepol: Integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbit : integer := 256;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp64a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp32a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp16a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkread : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrspa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data
);
end component;
component ddr2sp16a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddr2sp32a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddr2sp64a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddr2spa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
readdly : integer := 1;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkref200 : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
-- ddr_clk_fb_out : out std_logic;
-- ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0)
);
end component;
component ddr_phy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkread : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out sdctrl_in_type;
sdo : in sdctrl_out_type);
end component;
component ddr2_phy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
sdi : out sdctrl_in_type;
sdo : in sdctrl_out_type);
end component;
component ftsrctrl8 is
generic (
hindex : integer := 0;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
iows : integer := 2;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 1;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/altera_mf/memory_altera_mf.vhd | 2 | 4606 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_altera_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Altera altsynram
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of altera_syncram_dp is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
address_b : in std_logic_vector(widthad_b-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
data_b : in std_logic_vector(width_b-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
q_b : out std_logic_vector(width_b-1 downto 0);
rden_b : in std_logic;
wren_a : in std_logic;
wren_b : in std_logic
);
end component;
begin
u0 : altsyncram
generic map (
WIDTH_A => dbits, WIDTHAD_A => abits,
WIDTH_B => dbits, WIDTHAD_B => abits)
port map (
address_a => address1, address_b => address2, clock0 => clk1,
clock1 => clk2, data_a => datain1, data_b => datain2,
q_a => dataout1, q_b => dataout2, rden_b => enable2,
wren_a => write1, wren_b => write2);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity altera_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of altera_syncram is
component altera_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(dbits-1 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
u0: altera_syncram_dp
generic map (abits, dbits)
port map (
clk1 => clk, address1 => address, datain1 => datain,
dataout1 => dataout, enable1 => enable, write1 => write,
clk2 => clk, address2 => agnd, datain2 => dgnd,
dataout2 => open, enable2 => agnd(0), write2 => agnd(0));
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/designs/myDemo/ahbrom.vhd | 2 | 7078 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 368;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hcache <= '1';
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"83480000";
when 16#0002D# => romdata <= X"8330600C";
when 16#0002E# => romdata <= X"80886001";
when 16#0002F# => romdata <= X"02800019";
when 16#00030# => romdata <= X"01000000";
when 16#00031# => romdata <= X"07000000";
when 16#00032# => romdata <= X"8610E118";
when 16#00033# => romdata <= X"C108C000";
when 16#00034# => romdata <= X"C118C000";
when 16#00035# => romdata <= X"C518C000";
when 16#00036# => romdata <= X"C918C000";
when 16#00037# => romdata <= X"CD18E008";
when 16#00038# => romdata <= X"D118C000";
when 16#00039# => romdata <= X"D518C000";
when 16#0003A# => romdata <= X"D918C000";
when 16#0003B# => romdata <= X"DD18C000";
when 16#0003C# => romdata <= X"E118C000";
when 16#0003D# => romdata <= X"E518C000";
when 16#0003E# => romdata <= X"E918C000";
when 16#0003F# => romdata <= X"ED18C000";
when 16#00040# => romdata <= X"F118C000";
when 16#00041# => romdata <= X"F518C000";
when 16#00042# => romdata <= X"F918C000";
when 16#00043# => romdata <= X"10800005";
when 16#00044# => romdata <= X"FD18C000";
when 16#00045# => romdata <= X"01000000";
when 16#00046# => romdata <= X"00000000";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"05000008";
when 16#00049# => romdata <= X"82100000";
when 16#0004A# => romdata <= X"3D1003FF";
when 16#0004B# => romdata <= X"BC17A3E0";
when 16#0004C# => romdata <= X"BC278001";
when 16#0004D# => romdata <= X"9C27A060";
when 16#0004E# => romdata <= X"03100000";
when 16#0004F# => romdata <= X"81C04000";
when 16#00050# => romdata <= X"01000000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"01000000";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"00000000";
when 16#00059# => romdata <= X"00000000";
when 16#0005A# => romdata <= X"00000000";
when 16#0005B# => romdata <= X"00000000";
when 16#0005C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/altera/simprims/altera_primitives_components.vhd | 2 | 14224 | -- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 7.1 Build 156 04/30/2007
----------------------------------------------------------------------------
-- ALtera Primitives Component Declaration File
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package dffeas_pack is
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
end dffeas_pack;
library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.dffeas_pack.all;
package altera_primitives_components is
component carry
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component cascade
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component global
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component tri
port(
a_in : in std_logic;
oe : in std_logic;
a_out : out std_logic);
end component;
component carry_sum
port (
sin : in std_logic;
cin : in std_logic;
sout : out std_logic;
cout : out std_logic );
end component;
component exp
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component soft
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component opndrn
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component row_global
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component lut_input
port(
a_in : in std_logic;
a_out : out std_logic);
end component;
component lut_output
port(
a_in : in std_logic;
a_out : out std_logic);
end component;
component dlatch
port(
d : in std_logic;
ena : in std_logic;
clrn : in std_logic;
prn : in std_logic;
q : out std_logic);
end component;
component latch
port(
d : in std_logic;
ena : in std_logic;
q : out std_logic);
end component;
component dff
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component dffe
port(
d, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component dffea
port(
d, clk, ena, clrn, prn, aload, adata : in std_logic;
q : out std_logic);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*" );
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic );
end component;
component tff
port(
t, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component tffe
port(
t, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component jkff
port(
j, k, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component jkffe
port(
j, k, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component srff
port(
s, r, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component srffe
port(
s, r, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component clklock
generic(
input_frequency : natural := 10000;
clockboost : natural := 1);
port(
inclk : in std_logic;
outclk : out std_logic);
end component;
component alt_inbuf
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf" );
port(
i : in std_logic;
o : out std_logic);
end component;
component alt_outbuf
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf" );
port(
i : in std_logic;
o : out std_logic);
end component;
component alt_outbuf_tri
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic);
end component;
component alt_iobuf
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
o : out std_logic);
end component;
component alt_inbuf_diff
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf_diff" );
port(
i : in std_logic;
ibar : in std_logic;
o : out std_logic);
end component;
component alt_outbuf_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_diff" );
port(
i : in std_logic;
o : out std_logic;
obar : out std_logic );
end component;
component alt_outbuf_tri_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri_diff" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic;
obar : out std_logic );
end component;
component alt_iobuf_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf_diff" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
iobar : inout std_logic;
o : out std_logic );
end component;
component alt_bidir_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_diff" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic;
iobar : inout std_logic );
end component;
component alt_bidir_buf
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_buf" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic );
end component;
end altera_primitives_components;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/gencomp/clkgen.in.vhd | 6 | 343 | -- Clock generator
constant CFG_CLKTECH : integer := CFG_CLK_TECH;
constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/ambatest/ahb_tbfunct.vhd | 2 | 6721 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.ambatest.all;
package ahb_tb is
procedure AHB_read_single(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure AHB_read_burst(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure AHB_write_single(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure AHB_write_burst(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
end ahb_tb;
package body ahb_tb is
constant printlevel : integer := 2;
function string_inv(instring : string(18 downto 1)) return string is
variable vstr : string(1 to 18);
begin
vstr(1 to 18) := instring(18 downto 1);
return(vstr);
end string_inv;
procedure AHB_read_single(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.command <= RD_SINGLE;
tbi.no_words <= 1;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if dbglevel >= printlevel then
if ctrl.userfile then
printf("AHBMST TB: AHB Read from file %s",string_inv(ctrl.rfile));
else
printf("AHBMST TB: AHB Read from address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= ctrl.usewfile;
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.data := tbo.data;
ctrl.status := tbo.status;
if ctrl.status = ERR then
printf("AHBMST TB: #ERROR# Read access failed at %x",ctrl.address);
elsif ctrl.status = TIMEOUT then
printf("AHBMST TB: #ERROR# Timeout received for read access at %x",ctrl.address);
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("AHBMST TB: Returned data: %x",ctrl.data);
end if;
end if;
tbi.start <= '0';
end procedure;
procedure AHB_read_burst(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
variable i : integer;
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.command <= RD_INCR;
tbi.no_words <= ctrl.no_words;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if dbglevel >= printlevel then
if ctrl.userfile then
printf("AHBMST TB: AHB Read burst from file %s",string_inv(ctrl.rfile));
else
printf("AHBMST TB: AHB Read burst from address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= ctrl.usewfile;
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.data := tbo.data;
ctrl.status := tbo.status;
if ctrl.status = ERR then
printf("AHBMST TB: #ERROR# Read access failed at %x",ctrl.address);
elsif ctrl.status = TIMEOUT then
printf("AHBMST TB: #ERROR# Timeout received for read access at %x",ctrl.address);
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("AHBMST TB: Returned data: %x",ctrl.data);
end if;
end if;
ctrl.status := tbo.status;
tbi.start <= '0';
end procedure;
procedure AHB_write_single(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.data <= ctrl.data;
tbi.command <= WR_SINGLE;
tbi.no_words <= 1;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if dbglevel >= printlevel then
if ctrl.userfile then
printf("AHBMST TB: AHB Write from file %s",string_inv(ctrl.rfile));
else
printf("AHBMST TB: AHB Write to address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= false; -- No log file for write accesses
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.status := tbo.status;
if ctrl.status = ERR then
printf("AHBMST TB: #ERROR# Write access failed at %x",ctrl.address);
elsif ctrl.status = TIMEOUT then
printf("AHBMST TB: #ERROR# Timeout received for write access at %x",ctrl.address);
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("AHBMST TB: Write success!");
end if;
end if;
tbi.start <= '0';
end procedure;
procedure AHB_write_burst(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.data <= ctrl.data;
tbi.command <= WR_INCR;
tbi.no_words <= ctrl.no_words;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if dbglevel >= printlevel then
if ctrl.userfile then
printf("AHBMST TB: AHB Write from file %s",string_inv(ctrl.rfile));
else
printf("AHBMST TB: AHB Write burst to address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= false; -- No log file for write accesses
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.status := tbo.status;
if ctrl.status = ERR then
printf("AHBMST TB: #ERROR# Write access failed at %x",ctrl.address);
elsif ctrl.status = TIMEOUT then
printf("AHBMST TB: #ERROR# Timeout received for write access at %x",ctrl.address);
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("AHBMST TB: Write success!");
end if;
end if;
tbi.start <= '0';
end procedure;
end package body;
-- pragma translate_on
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gsi/ssram/functions.vhd | 6 | 97832 | -----------------------------------------------------------
-- VHDL file for FUNCTIONs used in verilog2vhdl files
-- DO NOT MODIFY THIS FILE
-- Author : S.O
-- Date : March 14, 1995
-- Modification History --
-- 3/31/95 Added shift operations (S.O)
-- 4/6/95 Added arithmetic operations for std_logic_vectors (S.O)
-- 4/11/95 Added conversion functions
-- 10/5/95 added to_boolean conversions
-- 1/31/96 added funcs. for std_logic and std_logic
-- 2/28/96 added funcs. for TERNARY combinations
-- 4/18/96 added logical operations bet. std_logic_vector and integer/boolean
-- 7/9/96 modified all TERNARY functions with *ulogic* conditional
-----------------------------------------------------------
library ieee;
library GSI;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
package FUNCTIONS is
-- TYPE used in conversion function
TYPE direction is (LITTLE_ENDIAN, BIG_ENDIAN);
TYPE hex_digit IS ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A',
'B', 'C', 'D', 'E', 'F', 'a', 'b', 'c', 'd', 'e', 'f');
TYPE hex_number IS array (POSITIVE range <>) OF hex_digit;
TYPE hexstdlogic IS ARRAY (hex_digit'LOW TO hex_digit'HIGH) of std_logic_vector(3 DOWNTO 0);
-- This conversion table would not accept X or Z.
-- To convert a hex number with X or Z use to_stdlogicvector(hex : STRING).
--CONSTANT hex_to_stdlogic : hexstdlogic := (x"0", x"1", x"2", x"3", x"4", x"5",
-- x"6", x"7", x"8", x"9", x"A", x"B", x"C", x"D", x"E", x"F", x"A", x"B",
-- x"C", x"D", x"E", x"F");
-- Signals used for v2v
--SIGNAL v2v_std_logic : std_logic;
--SIGNAL v2v_sig_integer : integer;
--SIGNAL v2v_boolean : boolean;
--SIGNAL v2v_real : real;
-- FUNCTIONs for unary operations
FUNCTION U_AND(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_AND(a : std_logic_vector) return std_logic;
FUNCTION U_NAND(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_NAND(a : std_logic_vector) return std_logic;
FUNCTION U_OR(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_OR(a : std_logic_vector) return std_logic;
FUNCTION U_NOR(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_NOR(a : std_logic_vector) return std_logic;
FUNCTION U_XOR(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_XOR(a : std_logic_vector) return std_logic;
FUNCTION U_XNOR(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_XNOR(a : std_logic_vector) return std_logic;
-- FUNCTIONs for ternary operations
FUNCTION TERNARY(a,b,c : boolean) return boolean;
FUNCTION TERNARY(a : boolean; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : boolean; b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : boolean; b,c : std_logic_vector) return std_logic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : boolean; b,c : real) return real;
FUNCTION TERNARY(a : boolean; b,c : time) return time;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : integer) return integer;
FUNCTION TERNARY(a : integer; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : integer; b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : integer; b,c : std_logic_vector) return std_logic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : integer; b,c : real) return real;
FUNCTION TERNARY(a : integer; b,c : time) return time;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : std_ulogic; b,c : integer) return integer;
FUNCTION TERNARY(a : std_ulogic; b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : std_ulogic; b,c : std_logic_vector) return std_logic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : std_ulogic; b,c : real) return real;
FUNCTION TERNARY(a : std_ulogic; b,c : time) return time;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : integer) return integer;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : std_logic_vector) return std_logic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : std_ulogic_vector; b,c : real) return real;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : time) return time;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_logic_vector) return std_logic_vector;
FUNCTION TERNARY(a : std_logic_vector; b,c : integer) return integer;
FUNCTION TERNARY(a : std_logic_vector; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : std_logic_vector; b,c : std_ulogic_vector) return std_ulogic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : std_logic_vector; b,c : real) return real;
FUNCTION TERNARY(a : std_logic_vector; b,c : time) return time;
FUNCTION TERNARY(a,b,c : real) return real;
FUNCTION TERNARY(a : real; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : real; b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : real; b,c : std_logic_vector) return std_logic_vector;
FUNCTION TERNARY(a : real; b,c : integer) return integer;
FUNCTION TERNARY(a : real; b,c : time) return time;
--pragma synthesis_on
-- functions for TERNARY combination
FUNCTION TERNARY(a : std_ulogic; b : std_logic_vector; c: std_ulogic) return
std_logic_vector;
FUNCTION TERNARY(a : std_ulogic; b : std_ulogic; c: std_logic_vector) return
std_logic_vector;
FUNCTION TERNARY(a : std_ulogic; b : integer; c: std_ulogic) return
integer;
FUNCTION TERNARY(a : std_ulogic; b : std_ulogic; c: integer) return
integer;
FUNCTION TERNARY(a : integer; b : integer; c: std_ulogic) return
integer;
FUNCTION TERNARY(a : integer; b : std_ulogic; c: integer) return
integer;
FUNCTION TERNARY(a : integer; b : std_logic_vector; c: std_ulogic) return
std_logic_vector;
FUNCTION TERNARY(a : integer; b : std_ulogic; c: std_logic_vector) return
std_logic_vector;
--end functions for TERNARY combination
-- FUNCTIONS for shift operations
FUNCTION "sll" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "sll" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "srl" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "srl" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "sla" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "sla" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "sra" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "sra" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "rol" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "rol" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "ror" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "ror" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
-- FUNCTIONs for integer operations
FUNCTION "not" (l: integer) return integer;
FUNCTION "and" (l,r: integer) return integer;
FUNCTION "nand" (l,r: integer) return integer;
FUNCTION "or" (l,r: integer) return integer;
FUNCTION "nor" (l,r: integer) return integer;
FUNCTION "xor" (l,r: integer) return integer;
FUNCTION "xnor" (l,r: integer) return integer;
FUNCTION "sll" (l,r: integer) return integer;
FUNCTION "srl" (l,r: integer) return integer;
-- FUNCTIONs for std_logic/std_ulogic_vector/std_logic_vector operations
-- FUNCTIONs for combination of Boolean and ints
FUNCTION "=" ( l : Boolean; r : natural ) RETURN boolean;
FUNCTION "/=" ( l : Boolean; r : natural ) RETURN boolean;
FUNCTION "=" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION "/=" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION "<" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION ">" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION "<=" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION ">=" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION "=" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION "/=" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION "<" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION ">" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION "<=" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION ">=" ( l : std_logic_vector; r : integer ) RETURN boolean;
--logical functions between std_logic_vector and integer, std_logic_vector and boolean
FUNCTION "and" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "nand" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "or" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "nor" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "xor" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "and" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "nand" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "or" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "nor" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "xor" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "and" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "nand" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "or" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "nor" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "xor" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "and" ( l : boolean; r : std_logic_vector ) RETURN boolean;
FUNCTION "nand" ( l : boolean; r : std_logic_vector ) RETURN boolean;
FUNCTION "or" ( l : boolean; r : std_logic_vector ) RETURN boolean;
FUNCTION "nor" ( l : boolean; r : std_logic_vector ) RETURN boolean;
FUNCTION "xor" ( l : boolean; r : std_logic_vector ) RETURN boolean;
--logical functions between std_logic_vector and integer, std_logic_vector and boolean
-- Added functions for std_logic, integer
FUNCTION "=" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION "/=" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION "<" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION ">" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION "<=" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION ">=" ( l : std_logic; r : integer ) RETURN boolean;
-- Functions for std_logic, integer
--pragma synthesis_off
-- arithmetic operations for real and int and int and real
FUNCTION "+" ( l : real; r : integer ) RETURN real;
FUNCTION "-" ( l : real; r : integer ) RETURN real;
FUNCTION "/" ( l : real; r : integer ) RETURN real;
FUNCTION "*" ( l : real; r : integer ) RETURN real;
FUNCTION "+" ( l : integer; r : real ) RETURN real;
FUNCTION "-" ( l : integer; r : real ) RETURN real;
FUNCTION "/" ( l : integer; r : real ) RETURN real;
FUNCTION "*" ( l : integer; r : real ) RETURN real;
-- end arithmetic operations for real and int and int and real
FUNCTION "=" ( l : real; r : integer ) RETURN boolean;
FUNCTION "/=" ( l : real; r : integer ) RETURN boolean;
FUNCTION "<" ( l : real; r : integer ) RETURN boolean;
FUNCTION ">" ( l : real; r : integer ) RETURN boolean;
FUNCTION "<=" ( l : real; r : integer ) RETURN boolean;
FUNCTION ">=" ( l : real; r : integer ) RETURN boolean;
FUNCTION "=" ( l : integer; r : real ) RETURN boolean;
FUNCTION "/=" ( l : integer; r : real ) RETURN boolean;
FUNCTION "<" ( l : integer; r : real ) RETURN boolean;
FUNCTION ">" ( l : integer; r : real ) RETURN boolean;
FUNCTION "<=" ( l : integer; r : real ) RETURN boolean;
FUNCTION ">=" ( l : integer; r : real ) RETURN boolean;
--pragma synthesis_on
FUNCTION "+" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "-" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "*" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "/" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "REM" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "+" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "-" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "*" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "/" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "REM" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "&" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "&" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
-- need logical functions bet. std_logic_vector and std_logic
FUNCTION "and" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "nand" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "or" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "nor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "xor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
--FUNCTION "xnor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "and" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nand" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "or" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "xor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
--FUNCTION "xnor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
-- end logical functions for std_logic_vector and std_logic
-- need arith functions bet std_logic and std_logic
-- used only when the int can be 0 or 1
-- need arithmetic functions bet. std_logic_vector and std_logic
FUNCTION "+" ( l : std_logic; r : std_logic ) RETURN std_logic;
FUNCTION "-" ( l : std_logic; r : std_logic ) RETURN std_logic;
FUNCTION "*" ( l : std_logic; r : std_logic ) RETURN std_logic;
FUNCTION "/" ( l : std_logic; r : std_logic ) RETURN std_logic;
FUNCTION "REM" ( l : std_logic; r : std_logic ) RETURN std_logic;
-- need arithmetic functions bet. std_logic_vector and std_logic
FUNCTION "+" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "-" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "*" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "/" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "REM" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
-- need arithmetic func. between std_logic and std_logic_vector, caveat, returns type of 'r'
FUNCTION "+" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "-" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "*" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "/" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "REM" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "+" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "-" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "*" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "/" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "REM" ( l : integer; r : std_logic_vector ) RETURN integer;
-- need arith. functions bet std_logic and integer
FUNCTION "+" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "-" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "*" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "/" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "REM" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "and" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "nand" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "or" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "nor" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "xor" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "&" ( l : std_logic; r : integer ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "and" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "nand" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "or" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "nor" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "xor" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "&" ( l : integer; r : std_logic ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : integer; r : std_logic ) RETURN integer;
-- need functions for operations between std_logic and integer
FUNCTION "+" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "-" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "*" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "/" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "REM" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "and" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "nand" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "or" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "nor" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "xor" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "&" ( l : std_logic; r : boolean ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "and" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "nand" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "or" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "nor" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "xor" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "&" ( l : boolean; r : std_logic ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "and" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "nand" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "or" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "nor" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "xor" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "&" ( l : integer; r : boolean ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "and" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "nand" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "or" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "nor" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "xor" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "&" ( l : boolean; r : integer ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : boolean; r : integer ) RETURN boolean;
-- Overloaded function for text output
FUNCTION to_bitvector ( a : bit ) RETURN bit_vector;
FUNCTION to_bitvector ( a : std_ulogic ) RETURN bit_vector;
FUNCTION to_bitvector ( a : integer ) RETURN bit_vector;
--Conversion functions
FUNCTION to_stdlogicvector(l : integer; size : natural; dir : direction := LITTLE_ENDIAN) RETURN std_logic_vector;
FUNCTION to_stdlogicvector(l : std_logic_vector) RETURN std_logic_vector;
FUNCTION to_stdlogicvector(l : std_logic_vector; size : natural;dir : direction := little_endian ) RETURN std_logic_vector;
FUNCTION to_stdlogicvector ( hex : STRING ) RETURN std_logic_vector;
FUNCTION to_stdlogicvector(l : std_logic; size : natural) RETURN std_logic_vector;
FUNCTION to_stdlogicvector(l : boolean; size : natural) RETURN std_logic_vector;
FUNCTION to_integer(l : std_logic_vector; dir : direction := little_endian) RETURN integer;
FUNCTION to_integer(l : integer) RETURN integer;
FUNCTION to_integer(l : std_logic) RETURN integer;
FUNCTION to_integer(l : boolean) RETURN integer;
-- functions for resolving ambiguity
FUNCTION v2v_to_integer(l : std_logic_vector; dir : direction := little_endian) RETURN integer;
FUNCTION v2v_to_integer(l : integer) RETURN integer;
FUNCTION v2v_to_integer(l : std_logic) RETURN integer;
FUNCTION v2v_to_integer(l : boolean) RETURN integer;
FUNCTION to_stdlogic(l : integer) RETURN std_logic;
FUNCTION to_stdlogic(l : Boolean) RETURN std_logic;
FUNCTION to_stdlogic(l : std_logic) RETURN std_logic;
FUNCTION to_stdlogic(l : std_logic_vector) RETURN std_logic;
--pragma synthesis_off
FUNCTION to_real(l : integer) RETURN real;
FUNCTION to_real (l : real) RETURN real;
--pragma synthesis_on
FUNCTION to_boolean(l : std_logic) RETURN boolean;
FUNCTION to_boolean(l : integer) RETURN boolean;
FUNCTION to_boolean(l : std_logic_vector) RETURN boolean;
FUNCTION to_boolean(l : boolean) RETURN boolean;
end FUNCTIONS;
library ieee;
library GSI;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
Package body FUNCTIONS is
--============= Local Subprograms (from numeric_std.vhd)=====================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
-- unary operations
TYPE stdlogic_boolean_table is array(std_ulogic, std_ulogic) of boolean;
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
FUNCTION U_AND(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '1';
begin
FOR i in a'RANGE LOOP
result := result and a(i);
END LOOP;
return result;
end U_AND;
FUNCTION U_AND(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '1';
begin
FOR i in a'RANGE LOOP
result := result and a(i);
END LOOP;
return result;
end U_AND;
FUNCTION U_NAND(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '1';
begin
FOR i in a'RANGE LOOP
result := result and a(i);
END LOOP;
return not(result);
end U_NAND;
FUNCTION U_NAND(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '1';
begin
FOR i in a'RANGE LOOP
result := result and a(i);
END LOOP;
return not(result);
end U_NAND;
FUNCTION U_OR(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '0';
begin
FOR i in a'RANGE LOOP
result := result or a(i);
END LOOP;
return result;
end U_OR;
FUNCTION U_OR(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '0';
begin
FOR i in a'RANGE LOOP
result := result or a(i);
END LOOP;
return result;
end U_OR;
FUNCTION U_NOR(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '0';
begin
FOR i in a'RANGE LOOP
result := result or a(i);
END LOOP;
return not(result);
end U_NOR;
FUNCTION U_NOR(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '0';
begin
FOR i in a'RANGE LOOP
result := result or a(i);
END LOOP;
return not(result);
end U_NOR;
FUNCTION U_XOR(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '0';
begin
FOR i in a'RANGE LOOP
result := result xor a(i);
END LOOP;
return result;
end U_XOR;
FUNCTION U_XOR(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '0';
begin
FOR i in a'RANGE LOOP
result := result xor a(i);
END LOOP;
return result;
end U_XOR;
FUNCTION U_XNOR(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '0';
begin
FOR i in a'RANGE LOOP
result := result xor a(i);
END LOOP;
return not(result);
end U_XNOR;
FUNCTION U_XNOR(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '0';
begin
FOR i in a'RANGE LOOP
result := result xor a(i);
END LOOP;
return not(result);
end U_XNOR;
-- ternary operations
FUNCTION TERNARY(a,b,c : boolean) return boolean IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : std_ulogic) return std_ulogic IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : std_ulogic_vector) return std_ulogic_vector IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : std_logic_vector) return std_logic_vector IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
--pragma synthesis_off
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : real) return real IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : time) return time IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
--pragma synthesis_on
---------------------------------------------------
FUNCTION TERNARY(a,b,c : integer) return integer is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : integer; b,c : std_ulogic) return std_ulogic is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : integer; b,c : std_ulogic_vector) return std_ulogic_vector is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : integer; b,c : std_logic_vector) return std_logic_vector is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_off
FUNCTION TERNARY(a : integer; b,c : real) return real is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : integer; b,c : time) return time is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_ulogic) return std_ulogic is
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b = c AND NOT Is_X(b)) THEN
return b;
ELSE
return 'X';
--pragma synthesis_on
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic; b,c : integer) return integer is
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b = c) THEN
return b;
ELSE
return 0;
--pragma synthesis_on
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic; b,c : std_ulogic_vector) return std_ulogic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_ulogic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b = c AND NOT Is_X(b)) THEN
return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
--pragma synthesis_on
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic; b,c : std_logic_vector) return std_logic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_logic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b = c AND NOT Is_X(b)) THEN
return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
--pragma synthesis_on
END IF;
end TERNARY;
--pragma synthesis_off
FUNCTION TERNARY(a : std_ulogic; b,c : real) return real is
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
ELSIF (b = c) THEN
return b;
ELSE
return 0.0;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic; b,c : time) return time is
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
ELSIF (b = c) THEN
return b;
ELSE
return 0 ns;
END IF;
end TERNARY;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_ulogic_vector) return std_ulogic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_ulogic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : integer) return integer is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : std_ulogic) return std_ulogic is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 'X';
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : std_logic_vector) return std_logic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_logic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_off
FUNCTION TERNARY(a : std_ulogic_vector; b,c : real) return real is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0.0;
END IF;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : time) return time is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0 ns;
END IF;
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_logic_vector) return std_logic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_logic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_logic_vector; b,c : integer) return integer is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_logic_vector; b,c : std_ulogic) return std_ulogic is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 'X';
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_logic_vector; b,c : std_ulogic_vector) return std_ulogic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_ulogic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_off
FUNCTION TERNARY(a : std_logic_vector; b,c : real) return real is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0.0;
END IF;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_logic_vector; b,c : time) return time is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0 ns;
END IF;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a,b,c : real) return real is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : std_ulogic) return std_ulogic is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : std_ulogic_vector) return std_ulogic_vector is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : std_logic_vector) return std_logic_vector is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : integer) return integer is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : time) return time is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_on
-- functions for TERNARY combination
FUNCTION TERNARY(a : std_ulogic; b : std_logic_vector; c: std_ulogic) return
std_logic_vector IS
variable c01 : std_logic_vector(b'LENGTH-1 downto 0) := (OTHERS => '0');
--pragma synthesis_off
variable b01 : std_logic_vector(b'LENGTH-1 downto 0) := b;
variable result : std_logic_vector(b'LENGTH-1 downto 0);
--pragma synthesis_on
BEGIN
c01(0) := c;
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c01;
--pragma synthesis_off
ELSIF (b01 = c01 AND NOT Is_X(b)) THEN
return b;
ELSE
FOR I IN b'LENGTH-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
--pragma synthesis_on
END IF;
END TERNARY;
FUNCTION TERNARY(a : std_ulogic; b : std_ulogic; c: std_logic_vector) return
std_logic_vector IS
variable b01 : std_logic_vector(c'LENGTH-1 downto 0) := (OTHERS => '0');
--pragma synthesis_off
variable c01 : std_logic_vector(c'LENGTH-1 downto 0) := c;
variable result : std_logic_vector(c'LENGTH-1 downto 0);
--pragma synthesis_on
BEGIN
b01(0) := b;
IF (a = '1') THEN
return b01;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b01 = c01 AND NOT Is_X(b01)) THEN
return b01;
ELSE
FOR I IN c'LENGTH-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
--pragma synthesis_on
END IF;
END TERNARY;
FUNCTION TERNARY(a : std_ulogic; b : integer; c: std_ulogic) return
integer IS
BEGIN
IF (a = '0') THEN
return to_integer(c);
ELSIF (a = '1') THEN
return b;
--pragma synthesis_off
ELSIF (b = to_integer(c) AND NOT Is_X(c)) THEN
return b;
ELSE
return 0;
--pragma synthesis_on
END IF;
END TERNARY;
FUNCTION TERNARY(a : std_ulogic; b : std_ulogic; c: integer) return
integer IS
BEGIN
IF (a = '0') THEN
return c;
ELSIF (a = '1') THEN
return to_integer(b);
--pragma synthesis_off
ELSIF (to_integer(b) = c AND NOT Is_X(b)) THEN
return c;
ELSE
return 0;
--pragma synthesis_on
END IF;
END TERNARY;
FUNCTION TERNARY(a : integer; b : integer; c: std_ulogic) return
integer IS
BEGIN
IF (a /= 0) THEN
return b;
ELSE
return to_integer(c);
END IF;
END TERNARY;
FUNCTION TERNARY(a : integer; b : std_ulogic; c: integer) return
integer IS
BEGIN
IF (a /= 0) THEN
return to_integer(b);
ELSE
return c;
END IF;
END TERNARY;
FUNCTION TERNARY(a : integer; b : std_logic_vector; c: std_ulogic) return
std_logic_vector IS
VARIABLE temp : std_logic_vector(0 downto 0);
BEGIN
IF (a /= 0) THEN
return b;
ELSE
temp(0) := c;
return temp;
END IF;
END TERNARY;
FUNCTION TERNARY(a : integer; b : std_ulogic; c: std_logic_vector) return
std_logic_vector IS
VARIABLE temp : std_logic_vector(0 downto 0);
BEGIN
IF (a /= 0) THEN
temp(0) := b;
return temp;
ELSE
return c;
END IF;
END TERNARY;
--end functions for TERNARY combination
-- FUNCTIONS for integer operations
FUNCTION "not" (l: integer) return integer is
VARIABLE temp : SIGNED(31 downto 0) := TO_SIGNED(l,32);
begin
return TO_INTEGER(NOT(temp));
end "not";
FUNCTION "and" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 AND temp2);
end "and";
FUNCTION "nand" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 NAND temp2);
end "nand";
FUNCTION "or" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 OR temp2);
end "or";
FUNCTION "nor" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 NOR temp2);
end "nor";
FUNCTION "xor" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 XOR temp2);
end "xor";
FUNCTION "xnor" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 XNOR temp2);
end "xnor";
FUNCTION "sll" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
begin
return TO_INTEGER(temp1 SLL r);
end "sll";
FUNCTION "srl" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
begin
return TO_INTEGER(temp1 SRL r);
end "srl";
-- functions for std_ulogic operations
-- first add all the tables needed
-- truth table for "=" function
CONSTANT eq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for "/=" function
CONSTANT neq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for "<" function
CONSTANT ltb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for ">" function
CONSTANT gtb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for "<=" function
CONSTANT leb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | X |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | W |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ) -- | D |
);
-- truth table for ">=" function
CONSTANT geb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 1 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | H |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ) -- | D |
);
CONSTANT lt_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for ">" function
CONSTANT gt_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for "<=" function
CONSTANT le_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D |
);
-- truth table for ">=" function
CONSTANT ge_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', '1', 'U', 'U', 'U', '1', 'U', 'U' ), -- | U |
( 'U', 'X', '1', 'X', 'X', 'X', '1', 'X', 'X' ), -- | X |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', '1', 'X', 'X', 'X', '1', 'X', 'X' ), -- | Z |
( 'U', 'X', '1', 'X', 'X', 'X', '1', 'X', 'X' ), -- | W |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', '1', 'X', 'X', 'X', '1', 'X', 'X' ) -- | D |
);
FUNCTION "=" ( l : Boolean; r : natural ) RETURN Boolean is
begin
IF l = TRUE AND r = 1 THEN
return TRUE;
ELSIF l = FALSE AND r = 0 THEN
return TRUE;
ELSE
return FALSE;
END IF;
end "=";
FUNCTION "/=" ( l : Boolean; r : natural ) RETURN Boolean is
begin
return NOT (l = r);
end "/=";
-----------------------------------------------------------------
FUNCTION "=" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l = SIGNED(r);
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l /= SIGNED(r);
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l < SIGNED(r);
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l > SIGNED(r);
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l <= SIGNED(r);
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l >= SIGNED(r);
END ">=";
-----------------------------------------------------------------
FUNCTION "=" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) = r;
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) /= r;
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) < r;
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) > r;
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) <= r;
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) >= r;
END ">=";
-----------------------------------------------------------------
--logical functions between std_logic_vector and integer, std_logic_vector and boolean
FUNCTION "and" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
BEGIN
RETURN l and to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "nand" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l nand to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "or" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l or to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "nor" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l nor to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "xor" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l xor to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "and" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l and v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "nand" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l nand v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "or" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l or v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "nor" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l nor v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "xor" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l xor v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "and" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l and to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "nand" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l nand to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "or" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l or to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "nor" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l nor to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "xor" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l xor to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "and" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l and to_boolean(r);
END;
-----------------------------------------------------------------
FUNCTION "nand" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l nand to_boolean(r);
END;
-----------------------------------------------------------------
FUNCTION "or" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l or to_boolean(r);
END;
-----------------------------------------------------------------
FUNCTION "nor" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l nor to_boolean(r);
END;
-----------------------------------------------------------------
FUNCTION "xor" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l xor to_boolean(r);
END;
--logical functions between std_logic_vector and integer, std_logic_vector and boolean
-----------------------------------------------------------------
-- Added functions for std_logic, integer
FUNCTION "=" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) = r;
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) /= r;
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) < r;
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) > r;
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) <= r;
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) >= r;
END ">=";
-----------------------------------------------------------------
-- Functions for std_logic, integer
-----------------------------------------------------------------
--pragma synthesis_off
-- arithmetic operations for real and int and int and real
FUNCTION "+" ( l : real; r : integer ) RETURN real IS
BEGIN
RETURN l + to_real(r);
END;
FUNCTION "-" ( l : real; r : integer ) RETURN real IS
BEGIN
RETURN l - to_real(r);
END;
FUNCTION "/" ( l : real; r : integer ) RETURN real IS
BEGIN
RETURN l / to_real(r);
END;
FUNCTION "*" ( l : real; r : integer ) RETURN real IS
BEGIN
RETURN l * to_real(r);
END ;
FUNCTION "+" ( l : integer; r : real ) RETURN real IS
BEGIN
RETURN to_real(l) + r;
END;
FUNCTION "-" ( l : integer; r : real ) RETURN real IS
BEGIN
RETURN to_real(l) - r;
END;
FUNCTION "/" ( l : integer; r : real ) RETURN real IS
BEGIN
RETURN to_real(l) / l;
END;
FUNCTION "*" ( l : integer; r : real ) RETURN real IS
BEGIN
RETURN to_real(l) * r;
END;
-- end arithmetic operations for real and int and int and real
-----------------------------------------------------------------
FUNCTION "=" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) = r;
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) /= r;
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) < r;
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) > r;
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) <= r;
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) >= r;
END ">=";
-----------------------------------------------------------------
FUNCTION "=" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l = INTEGER(r);
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l /= INTEGER(r);
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l < INTEGER(r);
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l > INTEGER(r);
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l <= INTEGER(r);
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l >= INTEGER(r);
END ">=";
--pragma synthesis_on
-----------------------------------------------------------------
FUNCTION "+" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) + UNSIGNED(r));
end "+";
------------------------------------------------------------------
FUNCTION "-" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) - UNSIGNED(r));
end "-";
------------------------------------------------------------------
FUNCTION "*" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) * UNSIGNED(r));
end "*";
------------------------------------------------------------------
FUNCTION "/" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) / UNSIGNED(r));
end "/";
------------------------------------------------------------------
FUNCTION "REM" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) rem UNSIGNED(r));
end "REM";
------------------------------------------------------------------
FUNCTION "+" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) + r);
end "+";
------------------------------------------------------------------
FUNCTION "-" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) - r);
end "-";
------------------------------------------------------------------
FUNCTION "*" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) * r);
end "*";
------------------------------------------------------------------
FUNCTION "/" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) / r);
end "/";
------------------------------------------------------------------
FUNCTION "REM" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) rem r);
end "REM";
------------------------------------------------------------------
FUNCTION "&" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return l & to_stdlogic(r);
end "&";
------------------------------------------------------------------
FUNCTION "&" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector is
begin
return l & to_stdlogic(r);
end "&";
------------------------------------------------------------------
FUNCTION "+" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) + to_integer(r));
end "+";
------------------------------------------------------------------
FUNCTION "-" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) - to_integer(r));
end "-";
------------------------------------------------------------------
FUNCTION "*" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) * to_integer(r));
end "*";
------------------------------------------------------------------
FUNCTION "/" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) / to_integer(r));
end "/";
------------------------------------------------------------------
FUNCTION "REM" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) rem to_integer(r));
end "REM";
------------------------------------------------------------------
FUNCTION "+" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) + SIGNED(r));
END "+";
------------------------------------------------------------------
FUNCTION "-" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) - SIGNED(r));
END "-";
------------------------------------------------------------------
FUNCTION "*" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) * SIGNED(r));
END "*";
------------------------------------------------------------------
FUNCTION "/" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) / SIGNED(r));
END "/";
------------------------------------------------------------------
FUNCTION "REM" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) REM SIGNED(r));
END "REM";
-------------------------------------------------------------
-- need logical functions bet. std_logic_vector and std_logic
FUNCTION "and" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l and to_stdlogicvector(r, l'length);
END "and";
--------------------------------------------------------------
FUNCTION "nand" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l nand to_stdlogicvector(r, l'length);
END "nand";
--------------------------------------------------------------
FUNCTION "or" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l or to_stdlogicvector(r, l'length);
END "or";
--------------------------------------------------------------
FUNCTION "nor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l nor to_stdlogicvector(r, l'length);
END "nor";
--------------------------------------------------------------
FUNCTION "xor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l xor to_stdlogicvector(r, l'length);
END "xor";
--------------------------------------------------------------
FUNCTION "xnor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN NOT(l xor to_stdlogicvector(r, l'length));
END "xnor";
--------------------------------------------------------------
FUNCTION "and" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) and r;
END "and";
--------------------------------------------------------------
FUNCTION "nand" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) nand r;
END "nand";
--------------------------------------------------------------
FUNCTION "or" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) or r;
END "or";
--------------------------------------------------------------
FUNCTION "nor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) nor r;
END "nor";
--------------------------------------------------------------
FUNCTION "xor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) xor r;
END "xor";
--------------------------------------------------------------
FUNCTION "xnor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN NOT(to_stdlogicvector(l, r'length) xor r);
END "xnor";
--------------------------------------------------------------
-- end logical functions for std_logic_vector and std_logic
------------------------------------------------------------------
-- need arith functions bet std_logic and std_logic
-- used only when the int can be 0 or 1
-- need arithmetic functions bet. std_logic_vector and std_logic
FUNCTION "+" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) + to_integer(r));
END "+";
FUNCTION "-" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) - to_integer(r));
END "-";
FUNCTION "*" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) * to_integer(r));
END "*";
FUNCTION "/" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) / to_integer(r));
END "/";
FUNCTION "REM" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) REM to_integer(r));
END "REM";
------- Arithmatic operations between std_logic and integer
-- caveat, functions below return integer
FUNCTION "+" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) + r;
END "+";
-------------------------------------------------------
FUNCTION "-" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) - r;
END "-";
-------------------------------------------------------
FUNCTION "*" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) * r;
END "*";
-------------------------------------------------------
FUNCTION "/" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) / r;
END "/";
-------------------------------------------------------
FUNCTION "REM" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) REM r;
END "REM";
-------------------------------------------------------
-------------------------------------------------------
FUNCTION "+" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l + to_integer(r);
END "+";
-------------------------------------------------------
FUNCTION "-" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l - to_integer(r);
END "-";
-------------------------------------------------------
FUNCTION "*" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l * to_integer(r);
END "*";
-------------------------------------------------------
FUNCTION "/" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l / to_integer(r);
END "/";
-------------------------------------------------------
FUNCTION "REM" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l REM to_integer(r);
END "REM";
-------------------------------------------------------
FUNCTION "+" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l + SIGNED(r));
END "+";
------------------------------------------------------------------
FUNCTION "-" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l - SIGNED(r));
END "-";
------------------------------------------------------------------
FUNCTION "*" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l * SIGNED(r));
END "*";
------------------------------------------------------------------
FUNCTION "/" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l / SIGNED(r));
END "/";
------------------------------------------------------------------
FUNCTION "REM" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l REM SIGNED(r));
END "REM";
------------------------------------------------------------------
FUNCTION "and" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l and to_stdlogic(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l nand to_stdlogic(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l or to_stdlogic(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l nor to_stdlogic(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l xor to_stdlogic(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : std_logic; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l & to_stdlogic(r);
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN not(l xor to_stdlogic(r));
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l and to_integer(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l nand to_integer(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l or to_integer(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l nor to_integer(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l xor to_integer(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : integer; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogic(l) & r;
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l xnor to_integer(r);
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l AND to_stdlogic(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l NAND to_stdlogic(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l OR to_stdlogic(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l NOR to_stdlogic(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l XOR to_stdlogic(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : std_logic; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l & to_stdlogic(r);
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN NOT(l XOR to_stdlogic(r));
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) AND r;
RETURN to_boolean(tmp);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) NAND r;
RETURN to_boolean(tmp);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) OR r;
RETURN to_boolean(tmp);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) NOR r;
RETURN to_boolean(tmp);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) XOR r;
RETURN to_boolean(tmp);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : boolean ; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogic(l) & r;
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := NOT(to_stdlogic(l) XOR r);
RETURN to_boolean(tmp);
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l and to_integer(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l nand to_integer(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l or to_integer(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l nor to_integer(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l xor to_integer(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : integer; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogic(l) & to_stdlogic(r);
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l xnor to_integer(r);
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l AND to_boolean(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l NAND to_boolean(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l or to_boolean(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l nor to_boolean(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l xor to_boolean(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : boolean; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogic(l) & to_stdlogic(r);
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l xnor to_boolean(r);
END "xnor";
------------------------------------------------------------------
-- Overloaded function for text output
FUNCTION to_bitvector ( a : bit ) RETURN bit_vector IS
VARIABLE s : bit_vector ( 1 TO 1 );
BEGIN
s(1) := a;
RETURN s;
END to_bitvector;
------------------------------------------------------------------
FUNCTION to_bitvector ( a : std_ulogic ) RETURN bit_vector IS
VARIABLE s : bit_vector ( 1 TO 1 );
BEGIN
s(1) := to_bit(a);
RETURN s;
END to_bitvector;
------------------------------------------------------------------
FUNCTION to_bitvector ( a : integer ) RETURN bit_vector IS
VARIABLE s : bit_vector ( 31 DOWNTO 0 );
BEGIN
s := to_bitvector(STD_LOGIC_VECTOR(to_signed(a, 32)));
RETURN s;
END to_bitvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : integer; size : natural; dir : direction := little_endian) RETURN std_logic_vector IS
BEGIN
IF dir = little_endian THEN
RETURN STD_LOGIC_VECTOR(to_signed(l,size));
ELSE
RETURN STD_LOGIC_VECTOR(to_signed(l,size) ROL size); -- rotate left by size times
END IF;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN l;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : std_logic_vector; size : natural; dir : direction := little_endian )
RETURN std_logic_vector IS
VARIABLE tmp1 : UNSIGNED(l'length-1 downto 0);
VARIABLE tmp2 : UNSIGNED(size-1 downto 0);
BEGIN
IF dir = little_endian THEN
RETURN STD_LOGIC_VECTOR(resize(UNSIGNED(l),size));
ELSE
-- using function ROTATE_LEFT to make it both 87 and 93 compliant
-- first get eqiv. in descending range
-- second resize
-- finally, rotate and return
tmp1 := ROTATE_LEFT(UNSIGNED(l),l'length);
tmp2 := resize(UNSIGNED(tmp1),size);
RETURN STD_LOGIC_VECTOR(ROTATE_LEFT(UNSIGNED(tmp2),size));
END IF;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : std_logic; size : natural) RETURN std_logic_vector IS
VARIABLE tmp : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp(0) := l;
RETURN tmp;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : boolean; size : natural) RETURN std_logic_vector IS
VARIABLE tmp : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp(0) := to_stdlogic(l);
RETURN tmp;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_integer(l : integer) RETURN integer IS
BEGIN
RETURN l;
END to_integer;
------------------------------------------------------------------
FUNCTION to_integer(l : std_logic) RETURN integer IS
BEGIN
IF ( l = '0') THEN
RETURN 0;
ELSIF (l = '1') THEN
RETURN 1;
ELSE
ASSERT FALSE REPORT("Std_logic values other than '0' and '1' cannot be converted to integer type")
SEVERITY WARNING;
RETURN 0;
END IF;
END to_integer;
------------------------------------------------------------------
FUNCTION to_integer(l : boolean) RETURN integer IS
BEGIN
IF ( l = TRUE) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END to_integer;
------------------------------------------------------------------
FUNCTION to_stdlogic(l : integer) RETURN std_logic IS
VARIABLE ret_val : std_logic := '0';
BEGIN
IF l = 0 THEN
ret_val := '0';
ELSIF l = 1 THEN
ret_val := '1';
ELSE
ASSERT FALSE REPORT("Integers other than 0 and 1 cannot be converted to std_logic type")
SEVERITY WARNING;
END IF;
RETURN ret_val;
END to_stdlogic;
------------------------------------------------------------------
FUNCTION to_stdlogic(l : Boolean) RETURN std_logic IS
VARIABLE ret_val : std_logic := '0';
BEGIN
IF l = FALSE THEN
ret_val := '0';
ELSE
ret_val := '1';
END IF;
RETURN ret_val;
END to_stdlogic;
------------------------------------------------------------------
FUNCTION to_stdlogic(l : std_logic) RETURN std_logic IS
BEGIN
RETURN l;
END to_stdlogic;
------------------------------------------------------------------
FUNCTION to_stdlogic(l : std_logic_vector) RETURN std_logic IS
BEGIN
RETURN l(l'LOW);
END to_stdlogic;
------------------------------------------------------------------
FUNCTION to_integer(l : std_logic_vector; dir : direction := little_endian) RETURN integer IS
BEGIN
IF dir = little_endian THEN
-- RETURN to_integer(SIGNED(l));
RETURN to_integer(UNSIGNED(l));
ELSE
-- RETURN to_integer(SIGNED(l) ROR l'LENGTH);
RETURN to_integer(UNSIGNED(l) ROR l'LENGTH);
END IF;
END to_integer;
------------------------------------------------------------------
FUNCTION v2v_to_integer(l : std_logic_vector; dir : direction := little_endian) RETURN integer IS
BEGIN
IF dir = little_endian THEN
-- RETURN to_integer(SIGNED(l));
RETURN to_integer(UNSIGNED(l));
ELSE
--NOTE, since ROR is not available in 87, we will use ROTATE_RIGHT
RETURN to_integer(ROTATE_RIGHT(UNSIGNED(l) , l'LENGTH));
-- RETURN to_integer(UNSIGNED(l) ROR l'LENGTH);
END IF;
END v2v_to_integer;
------------------------------------------------------------------
FUNCTION v2v_to_integer(l : integer) RETURN integer IS
BEGIN
RETURN l;
END v2v_to_integer;
------------------------------------------------------------------
FUNCTION v2v_to_integer(l : std_logic) RETURN integer IS
BEGIN
IF ( l = '0') THEN
RETURN 0;
ELSIF (l = '1') THEN
RETURN 1;
ELSE
ASSERT FALSE REPORT("Std_logic values other than '0' and '1' cannot be converted to integer type")
SEVERITY WARNING;
RETURN 0;
END IF;
END v2v_to_integer;
------------------------------------------------------------------
FUNCTION v2v_to_integer(l : boolean) RETURN integer IS
BEGIN
IF ( l = TRUE) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END v2v_to_integer;
------------------------------------------------------------------
--pragma synthesis_off
------------------------------------------------------------------
FUNCTION to_real(l : integer) RETURN real IS
BEGIN
RETURN REAL(l);
END to_real;
------------------------------------------------------------------
FUNCTION to_real(l : real) RETURN real IS
BEGIN
RETURN l;
END to_real;
--pragma synthesis_on
------------------------------------------------------------------
FUNCTION to_boolean(l : std_logic) RETURN boolean IS
BEGIN
IF ( l = '0' ) THEN
RETURN FALSE;
ELSIF (l = '1') THEN
RETURN TRUE;
ELSE
ASSERT FALSE REPORT("Std_logic values other than '0' and '1' cannot be converted to boolean type")
SEVERITY WARNING;
RETURN FALSE;
END IF;
END to_boolean;
------------------------------------------------------------------
FUNCTION to_boolean(l : std_logic_vector) RETURN boolean IS
VARIABLE tmp : std_logic_vector(l'RANGE);
BEGIN
tmp := (OTHERS=>'1');
if to_integer(l AND tmp) /= 0 THEN
RETURN TRUE;
END IF;
RETURN FALSE;
END to_boolean;
------------------------------------------------------------------
FUNCTION to_boolean(l : boolean) RETURN boolean IS
BEGIN
IF ( l) THEN
RETURN TRUE;
END IF;
RETURN FALSE;
END to_boolean;
------------------------------------------------------------------
FUNCTION to_boolean(l : integer) RETURN boolean IS
BEGIN
IF ( l = 0 ) THEN
RETURN FALSE;
ELSE
RETURN TRUE;
END IF;
END to_boolean;
------------------------------------------------------------------
FUNCTION "sll" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(l'RANGE) := (others=>'0');
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "srl"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i) := l(i+r);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i) := l(i-r);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sll" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(l'RANGE) := (others=>'0');
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "srl"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i) := l(i+r);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i) := l(i-r);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "srl" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(l'RANGE) := (others=>'0');
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sll"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i+r) := l(i);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i-r) := l(i);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "srl" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(l'RANGE) := (others=>'0');
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sll"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i+r) := l(i);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i-r) := l(i);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sla" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(l'RANGE) := (others=>l(l'RIGHT));
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sra"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i) := l(i+r);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i) := l(i-r);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sla" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(l'RANGE) := (others=>l(l'RIGHT));
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sra"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i) := l(i+r);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i) := l(i-r);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sra" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(l'RANGE) := (others=>l(l'RIGHT));
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sla"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i+r) := l(i);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i-r) := l(i);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sra" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(l'RANGE) := (others=>l(l'RIGHT));
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sla"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i+r) := l(i);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i-r) := l(i);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "rol" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(0 TO l'LENGTH*2-1);
VARIABLE v1 : std_logic_vector(l'RANGE);
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "ror"(l,-r);
ELSE
v(0 TO l'LENGTH-1) := l;
v(l'LENGTH TO v'LENGTH-1) := l;
v1 := v(r TO r+l'LENGTH-1);
RETURN v1;
END IF;
END;
FUNCTION "rol" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(0 TO l'LENGTH*2-1);
VARIABLE v1 : std_ulogic_vector(l'RANGE);
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "ror"(l,-r);
ELSE
v(0 TO l'LENGTH-1) := l;
v(l'LENGTH TO v'LENGTH-1) := l;
v1 := v(r TO r+l'LENGTH-1);
RETURN v1;
END IF;
END;
FUNCTION "ror" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(0 TO l'LENGTH*2-1);
VARIABLE v1 : std_logic_vector(l'RANGE);
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "rol"(l,-r);
ELSE
v(0 TO l'LENGTH-1) := l;
v(l'LENGTH TO v'LENGTH-1) := l;
v1 := v(l'LENGTH-r TO v'LENGTH-r-1);
RETURN v1;
END IF;
END;
FUNCTION "ror" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(0 TO l'LENGTH*2-1);
VARIABLE v1 : std_ulogic_vector(l'RANGE);
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "rol"(l,-r);
ELSE
v(0 TO l'LENGTH-1) := l;
v(l'LENGTH TO v'LENGTH-1) := l;
v1 := v(l'LENGTH-r TO v'LENGTH-r-1);
RETURN v1;
END IF;
END;
FUNCTION to_stdlogicvector(hex : STRING) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(4 * hex'LENGTH DOWNTO 1);
BEGIN
-- Note: The hex parameter can have a range with hex'LOW > 1.
-- For these cases, variable index i in assignments in the FOR loop is normalized
-- to 1 by subtracting hex'LOW ** sas 2/13/96 **
FOR i in hex'RANGE LOOP
CASE hex(i) IS
WHEN '0' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"0";
WHEN '1' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"1";
WHEN '2' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"2";
WHEN '3' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"3";
WHEN '4' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"4";
WHEN '5' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"5";
WHEN '6' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"6";
WHEN '7' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"7";
WHEN '8' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"8";
WHEN '9' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"9";
WHEN 'A' | 'a' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"A";
WHEN 'B' | 'b' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"B";
WHEN 'C' | 'c' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"C";
WHEN 'D' | 'd' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"D";
WHEN 'E' | 'e' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"E";
WHEN 'F' | 'f' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"F";
WHEN 'X' | 'x' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := "XXXX";
WHEN 'Z' | 'z' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := "ZZZZ";
WHEN OTHERS =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := "XXXX";
END CASE;
END LOOP;
RETURN result;
END to_stdlogicvector;
end FUNCTIONS;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/arith/mul32.vhd | 2 | 14212 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mul
-- File: mul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implements signed/unsigned 32-bit multiply module,
-- producing a 64-bit result.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.multlib.all;
library gaisler;
use gaisler.arith.all;
entity mul32 is
generic (
infer : integer range 0 to 1 := 1;
multype : integer range 0 to 3 := 0;
pipe : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
muli : in mul32_in_type;
mulo : out mul32_out_type
);
end;
architecture rtl of mul32 is
--attribute sync_set_reset : string;
--attribute sync_set_reset of rst : signal is "true";
constant m16x16 : integer := 0;
constant m32x8 : integer := 1;
constant m32x16 : integer := 2;
constant m32x32 : integer := 3;
constant MULTIPLIER : integer := multype;
constant MULPIPE : boolean := ((multype = 0) or (multype = 3)) and (pipe = 1);
constant MACEN : boolean := (multype = 0) and (mac = 1);
type mul_regtype is record
acc : std_logic_vector(63 downto 0);
state : std_logic_vector(1 downto 0);
start : std_logic;
ready : std_logic;
nready : std_logic;
end record;
type mac_regtype is record
mmac, xmac : std_logic;
msigned, xsigned : std_logic;
end record;
signal rm, rmin : mul_regtype;
signal mm, mmin : mac_regtype;
signal ma, mb : std_logic_vector(32 downto 0);
signal prod : std_logic_vector(65 downto 0);
signal mreg : std_logic_vector(49 downto 0);
begin
mulcomb : process(rst, rm, muli, mreg, prod, mm)
variable mop1, mop2 : std_logic_vector(32 downto 0);
variable acc, acc1, acc2 : std_logic_vector(48 downto 0);
variable zero, rsigned, rmac : std_logic;
variable v : mul_regtype;
variable w : mac_regtype;
constant CZero: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
begin
v := rm; w := mm; v.start := muli.start; v.ready := '0'; v.nready := '0';
mop1 := muli.op1; mop2 := muli.op2;
acc1 := (others => '0'); acc2 := (others => '0'); zero := '0';
w.mmac := muli.mac; w.xmac := mm.mmac;
w.msigned := muli.signed; w.xsigned := mm.msigned;
if MULPIPE then rsigned := mm.xsigned; rmac := mm.xmac;
else rsigned := mm.msigned; rmac := mm.mmac; end if;
-- select input 2 to accumulator
case MULTIPLIER is
when m16x16 =>
acc2(32 downto 0) := mreg(32 downto 0);
when m32x8 =>
acc2(40 downto 0) := mreg(40 downto 0);
when m32x16 =>
acc2(48 downto 0) := mreg(48 downto 0);
when others => null;
end case;
-- state machine + inputs to multiplier and accumulator input 1
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
if MULPIPE and (rm.ready = '1' ) then
acc1(32 downto 0) := rm.acc(48 downto 16);
else acc1(32 downto 0) := '0' & rm.acc(63 downto 32); end if;
when m32x8 =>
mop1 := muli.op1;
mop2(8 downto 0) := '0' & muli.op2(7 downto 0);
acc1(40 downto 0) := '0' & rm.acc(63 downto 24);
when m32x16 =>
mop1 := muli.op1;
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
acc1(48 downto 0) := '0' & rm.acc(63 downto 16);
when others => null;
end case;
if (rm.start = '1') then v.state := "01"; end if;
when "01" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
if MULPIPE then acc1(32 downto 0) := '0' & rm.acc(63 downto 32); end if;
v.state := "10";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(15 downto 8);
v.state := "10";
when m32x16 =>
mop1 := muli.op1; mop2(16 downto 0) := muli.op2(32 downto 16);
v.state := "00";
when others => null;
end case;
when "10" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := muli.op2(32 downto 16);
if MULPIPE then acc1 := (others => '0'); acc2 := (others => '0');
else acc1(32 downto 0) := rm.acc(48 downto 16); end if;
v.state := "11";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(23 downto 16);
acc1(40 downto 0) := rm.acc(48 downto 8);
v.state := "11";
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := muli.op2(32 downto 16);
if MULPIPE then acc1(32 downto 0) := rm.acc(48 downto 16);
else acc1(32 downto 0) := rm.acc(48 downto 16); end if;
v.state := "00";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := muli.op2(32 downto 24);
acc1(40 downto 0) := rm.acc(56 downto 16);
v.state := "00";
when others => null;
end case;
end case;
-- optional UMAC/SMAC support
if MACEN then
if ((muli.mac and muli.signed) = '1') then
mop1(16) := muli.op1(15); mop2(16) := muli.op2(15);
end if;
if rmac = '1' then
acc1(32 downto 0) := muli.acc(32 downto 0);--muli.y(0) & muli.asr18;
if rsigned = '1' then acc2(39 downto 32) := (others => mreg(31));
else acc2(39 downto 32) := (others => '0'); end if;
end if;
acc1(39 downto 33) := muli.acc(39 downto 33);--muli.y(7 downto 1);
end if;
-- accumulator for iterative multiplication (and MAC)
-- pragma translate_off
if not (is_x(acc1 & acc2)) then
-- pragma translate_on
case MULTIPLIER is
when m16x16 =>
if MACEN then
acc(39 downto 0) := acc1(39 downto 0) + acc2(39 downto 0);
else
acc(32 downto 0) := acc1(32 downto 0) + acc2(32 downto 0);
end if;
when m32x8 =>
acc(40 downto 0) := acc1(40 downto 0) + acc2(40 downto 0);
when m32x16 =>
acc(48 downto 0) := acc1(48 downto 0) + acc2(48 downto 0);
when m32x32 =>
v.acc(31 downto 0) := prod(63 downto 32);
when others => null;
end case;
-- pragma translate_off
end if;
-- pragma translate_on
-- save intermediate result to accumulator
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE and (rm.ready = '1' ) then
v.acc(48 downto 16) := acc(32 downto 0);
if rsigned = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
else
v.acc(63 downto 32) := acc(31 downto 0);
end if;
when m32x8 => v.acc(63 downto 24) := acc(39 downto 0);
when m32x16 => v.acc(63 downto 16) := acc(47 downto 0);
when others => null;
end case;
when "01" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then v.acc := (others => '0');
else v.acc := CZero(31 downto 0) & mreg(31 downto 0); end if;
when m32x8 =>
v.acc := CZero(23 downto 0) & mreg(39 downto 0);
if muli.signed = '1' then v.acc(48 downto 40) := (others => acc(40)); end if;
when m32x16 =>
v.acc := CZero(15 downto 0) & mreg(47 downto 0); v.ready := '1';
if muli.signed = '1' then v.acc(63 downto 48) := (others => acc(48)); end if;
when others => null;
end case;
v.nready := '1';
when "10" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then
v.acc := CZero(31 downto 0) & mreg(31 downto 0);
else
v.acc(48 downto 16) := acc(32 downto 0);
end if;
when m32x8 => v.acc(48 downto 8) := acc(40 downto 0);
if muli.signed = '1' then v.acc(56 downto 49) := (others => acc(40)); end if;
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then
v.acc(48 downto 16) := acc(32 downto 0);
else
v.acc(48 downto 16) := acc(32 downto 0);
if rsigned = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
end if;
v.ready := '1';
when m32x8 => v.acc(56 downto 16) := acc(40 downto 0); v.ready := '1';
if muli.signed = '1' then v.acc(63 downto 57) := (others => acc(40)); end if;
when others => null;
end case;
end case;
-- drive result and condition codes
if (muli.flush = '1') then v.state := "00"; v.start := '0'; end if;
if (rst = '0') then v.nready := '0'; v.ready := '0'; v.state := "00"; v.start := '0'; end if;
rmin <= v; ma <= mop1; mb <= mop2; mmin <= w;
if MULPIPE then mulo.ready <= rm.ready; mulo.nready <= rm.nready;
else mulo.ready <= v.ready; mulo.nready <= v.nready; end if;
case MULTIPLIER is
when m16x16 =>
if rm.acc(31 downto 0) = CZero(31 downto 0) then zero := '1'; end if;
if MACEN and (rmac = '1') then
mulo.result(39 downto 0) <= acc(39 downto 0);
if rsigned = '1' then
mulo.result(63 downto 40) <= (others => acc(39));
else
mulo.result(63 downto 40) <= (others => '0');
end if;
else
mulo.result(39 downto 0) <= v.acc(39 downto 32) & rm.acc(31 downto 0);
mulo.result(63 downto 40) <= v.acc(63 downto 40);
end if;
mulo.icc <= rm.acc(31) & zero & "00";
when m32x8 =>
if (rm.acc(23 downto 0) = CZero(23 downto 0)) and
(v.acc(31 downto 24) = CZero(7 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 24) & rm.acc(23 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x16 =>
if (rm.acc(15 downto 0) = CZero(15 downto 0)) and
(v.acc(31 downto 16) = CZero(15 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 16) & rm.acc(15 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x32 =>
-- mulo.result <= rm.acc(31 downto 0) & prod(31 downto 0);
mulo.result <= prod(63 downto 0);
mulo.icc(1 downto 0) <= "00";
if prod(31 downto 0) = zero32 then mulo.icc(2) <= '1' ;
else mulo.icc(2) <= '0'; end if;
mulo.icc(3) <= prod(31);
when others => null;
mulo.result <= (others => '-');
mulo.icc <= (others => '-');
end case;
end process;
xm1616 : if MULTIPLIER = m16x16 generate
i0 : if (infer = 1) and (pipe = 0) generate
prod(33 downto 0) <= smult (ma(16 downto 0), mb(16 downto 0));
end generate;
i1 : if (infer = 1) and (pipe = 1) generate
reg : process(clk) begin
if rising_edge(clk) then
if (holdn = '1') then
prod(33 downto 0) <= smult (ma(16 downto 0), mb(16 downto 0));
end if;
end if;
end process;
end generate;
i2 : if infer = 0 generate
m0 : mul_17_17
generic map (pipe)
port map (clk, holdn, ma(16 downto 0), mb(16 downto 0), prod(33 downto 0));
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
mm <= mmin;
mreg(33 downto 0) <= prod(33 downto 0);
end if;
end if;
end process;
end generate;
xm3208 : if MULTIPLIER = m32x8 generate
i0 : if infer = 1 generate
prod(41 downto 0) <= smult (ma(32 downto 0), mb(8 downto 0));
end generate;
i1 : if infer = 0 generate
m0 : mul_33_9
port map (ma(32 downto 0), mb(8 downto 0), prod(41 downto 0));
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
mreg(41 downto 0) <= prod(41 downto 0);
end if;
end if;
end process;
end generate;
xm3216 : if MULTIPLIER = m32x16 generate
i1 : if infer = 1 generate
prod(49 downto 0) <= smult (ma(32 downto 0), mb(16 downto 0));
end generate;
i2 : if infer = 0 generate
m0 : mul_33_17
port map (ma(32 downto 0), mb(16 downto 0), prod(49 downto 0));
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
mreg(49 downto 0) <= prod(49 downto 0);
end if;
end if;
end process;
end generate;
xm3232 : if MULTIPLIER = m32x32 generate
i1 : if (infer = 1) and (pipe = 1) generate
reg : process(clk) begin
if rising_edge(clk) then
if (holdn = '1') then
prod(65 downto 0) <= smult (ma(32 downto 0), mb(32 downto 0));
end if;
end if;
end process;
end generate;
i0 : if (infer = 1) and (pipe = 0) generate
prod(65 downto 0) <= smult (ma(32 downto 0), mb(32 downto 0));
end generate;
i2 : if infer = 0 generate
m0 : mul_33_33 generic map (pipe)
port map (clk, holdn, ma(32 downto 0), mb(32 downto 0), prod(65 downto 0));
end generate;
end generate;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then rm <= rmin; end if;
if (rst = '0') then -- needed to preserve sync resets in synopsys ...
rm.nready <= '0'; rm.ready <= '0'; rm.state <= "00"; rm.start <= '0';
end if;
end if;
end process;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gleichmann/miscellaneous/clockgenerator.vhd | 2 | 3312 | --------------------------------------------------------------------------------
-- Project : Sandbox
-- Module : ClockGenerator
-- File : ClockGenerator.vhd
-- Description : Generate the clocks for the AudioCodec.
--------------------------------------------------------------------------------
-- Author : Andreas Voggeneder
-- Organisation : FH-Hagenberg
-- Department : Hardware/Software Systems Engineering
-- Language : VHDL'87
--------------------------------------------------------------------------------
-- Copyright (c) 2003 by Andreas Voggeneder
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.CodecGlobal.all;
entity ClockGenerator is
port (
Clk : in std_ulogic;
Reset : in std_ulogic;
oMCLK : out std_ulogic; -- 12 MHz
oBCLK : out std_ulogic; -- I2S bit clk
oSCLK : out std_ulogic; -- SPI Data Clk
oLRCOUT : out std_ulogic);
end ClockGenerator;
architecture rtl of ClockGenerator is
constant cResetActive : std_ulogic := '0';
begin -- rtl
createclock : process (Clk, Reset)
-- variable cntMCLK : std_ulogic; -- counter MCLK
variable cntBCLK : std_ulogic; -- counter BCLK
variable cntLRC : unsigned(5 downto 0); -- counter LRC
variable internalMCLK : std_ulogic;
variable internalBCLK : std_ulogic;
variable internalSCLK : std_ulogic; --_vector(1 downto 0);
variable internalLRCOUT : std_ulogic;
begin -- process createclock
if Reset = cResetActive then -- asynchronous reset
internalMCLK := '0';
internalBCLK := '0';
internalSCLK := '0'; --"00";
internalLRCOUT := '1';
-- cntMCLK := '0';
cntBCLK := '0';
cntLRC := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
internalSCLK := not (internalSCLK);
-- internalSCLK := std_ulogic_vector(unsigned(internalSCLK)+1);
-- if (cntMCLK = '1') then
-- cntMCLK := '0';
internalMCLK := not internalMCLK; -- 25/2
if (internalMCLK = '1') then
-- == 25/2
if (cntBCLK = '1') then
-- == 25/4
internalBCLK := not internalBCLK; --25/8
cntBCLK := '0';
if (internalBCLK = '0') then
if (cntLRC = "100001") then -- 33
internalLRCOUT := not internalLRCOUT;
cntLRC := (others => '0');
else
cntLRC := cntLRC + 1;
end if;
end if;
else
cntBCLK := '1';
end if;
end if;
-- else
-- cntMCLK := '1';
-- end if;
end if;
oMCLK <= internalMCLK;
oBCLK <= internalBCLK;
oSCLK <= internalSCLK; --(1);
oLRCOUT <= internalLRCOUT;
end process createclock;
end rtl;
-- 44,1kHz: Fs=44100
-- MCLK = 256*Fs = 11.2896 MHz. Gewählt 12.5 MHz
-- BCLK = Fs*2*32 = 2.82 MHz. Gewählt 3.125 MHz
-- => Fs real = 48.8 kHz
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/techmap/maps/outpad.vhd | 2 | 4148 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad
-- File: outpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end;
architecture rtl of outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i after 2 ns when slew = 0 else i;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
(tech = virtex4) or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
x0 : axcel_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
um : if (tech = umc) generate
x0 : umc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength) port map (padx, i, gnd, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity outpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0));
end;
architecture rtl of outpadv is
begin
v : for j in width-1 downto 0 generate
x0 : outpad generic map (tech, level, slew, voltage, strength)
port map (pad(j), i(j));
end generate;
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/synplify/sim/synplify.vhd | 5 | 9340 | -----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Primitive library for post synthesis simulation --
-- These models are not intended for efficient synthesis --
-- --
-----------------------------------------------------------------------------
--pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
entity prim_counter is
generic (w : integer := 8);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end prim_counter;
architecture beh of prim_counter is
signal nextq : std_logic_vector(w - 1 downto 0);
begin
nxt: process (q, cin, updn)
variable i : integer;
variable nextc, c : std_logic;
begin
nextc := cin;
for i in 0 to w - 1 loop
c := nextc;
nextq(i) <= c xor (not updn) xor q(i);
nextc := (c and (not updn)) or
(c and q(i)) or
((not updn) and q(i));
end loop;
cout <= nextc;
end process;
ff : process (clk, rst)
begin
if rst = '1' then
q <= (others => '0');
elsif rising_edge(clk) then
q <= nextq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_dff is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_dff;
architecture beh of prim_dff is
begin
ff : process (clk, r, s)
begin
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
entity prim_sdff is
port (q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_sdff;
architecture beh of prim_sdff is
begin
ff : process(c)
begin
if rising_edge(c) then
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
else
q <= d;
end if;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_latch is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_latch;
architecture beh of prim_latch is
begin
q <= '0' when r = '1' else
'1' when s = '1' else
d when clk = '1';
end beh;
----------------------------------------------------------------------------
-- Zero ohm resistors: Hardi's solution to connect two inout ports.
----------------------------------------------------------------------------
-- Copyright (c) 1995, Ben Cohen. All rights reserved.
-- This model can be used in conjunction with the Kluwer Academic book
-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
-- which discusses guidelines and testbench design issues.
--
-- This source file for the ZERO Ohm resistor model may be used and
-- distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work
-- contains this copyright notice.
-- File name : Zohm_ea.vhd
-- Description: This package, entity, and architecture provide
-- the definition of a zero ohm component (A, B).
--
-- The applications of this component include:
-- . Normal operation of a jumper wire (data flowing in both directions)
--
-- The component consists of 2 ports:
-- . Port A: One side of the pass-through switch
-- . Port B: The other side of the pass-through switch
-- The model is sensitive to transactions on all ports. Once a
-- transaction is detected, all other transactions are ignored
-- for that simulation time (i.e. further transactions in that
-- delta time are ignored).
--
-- The width of the pass-through switch is defined through the
-- generic "width_g". The pass-through control and operation
-- is defined on a per bit basis (i.e. one process per bit).
--
-- Model Limitations and Restrictions:
-- Signals asserted on the ports of the error injector should not have
-- transactions occuring in multiple delta times because the model
-- is sensitive to transactions on port A, B ONLY ONCE during
-- a simulation time. Thus, once fired, a process will
-- not refire if there are multiple transactions occuring in delta times.
-- This condition may occur in gate level simulations with
-- ZERO delays because transactions may occur in multiple delta times.
--
--
-- Acknowledgement: The author thanks Steve Schoessow and Johan Sandstrom
-- for their contributions and discussions in the enhancement and
-- verification of this model.
--
--=================================================================
-- Revisions:
-- Date Author Revision Comment
-- 07-13-95 Ben Cohen Rev A Creation
-- [email protected]
-------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
entity ZeroOhm1 is
port
(A : inout Std_Logic;
B : inout Std_Logic
);
end ZeroOhm1;
architecture ZeroOhm1_a of ZeroOhm1 is
-- attribute syn_black_box : boolean;
-- attribute syn_feedthrough : boolean;
-- attribute syn_black_box of all : architecture is true;
-- attribute syn_feedthrough of all : architecture is true;
begin
ABC0_Lbl: process
variable ThenTime_v : time;
begin
wait on A'transaction, B'transaction
until ThenTime_v /= now;
-- Break
ThenTime_v := now;
A <= 'Z';
B <= 'Z';
wait for 0 ns;
-- Make
A <= B;
B <= A;
end process ABC0_Lbl;
end ZeroOhm1_a;
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end prim_ramd;
architecture beh of prim_ramd is
constant depth : integer := 2** addr_width;
type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
signal mem: mem_type;
begin
dout <= mem(conv_integer(aout));
process (clk)
begin
if rising_edge(clk) then
if (we = '1') then
mem(conv_integer(ain)) <= din;
end if;
end if;
end process;
end beh ;
library ieee;
use ieee.std_logic_1164.all;
package components is
component prim_counter
generic (w : integer);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end component;
component prim_dff
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_sdff
port(q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_latch
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end component;
end components;
-- pragma translate_on
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/misc/ahbtrace.vhd | 2 | 11104 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace
-- File: ahbtrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
entity ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbtrace is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant TIMEBITS : integer := 32;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBTRACE, 0, 0, irq),
4 => ahb_iobar (ioaddr, iomask),
others => zero32);
type tracebuf_in_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
type regtype is record
haddr : std_logic_vector(31 downto 0);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
hmastlock : std_logic;
hsel : std_logic;
hready : std_logic;
hready2 : std_logic;
hready3 : std_logic;
ahbactive : std_logic;
timer : std_logic_vector(TIMEBITS-1 downto 0);
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
enable : std_logic; -- trace enable
bahb : std_logic; -- break on AHB watchpoint hit
bhit : std_logic; -- breakpoint hit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
end record;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal enable : std_logic_vector(1 downto 0);
signal r, rin : regtype;
begin
ctrl : process(rst, ahbmi, ahbsi, r, tbo)
variable v : regtype;
variable vabufi : tracebuf_in_type;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable bphit : std_logic;
variable bufdata : std_logic_vector(127 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; regsd := (others => '0'); vabufi.enable := '0';
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); bphit := '0';
v.hready := r.hready2; v.hready2 := r.hready3; v.hready3 := '0';
bufdata := tbo.data;
hirq := (others => '0'); hirq(irq) := r.bhit;
-- trace buffer index and delay counters
if r.enable = '1' then v.timer := r.timer + 1; end if;
aindex := r.aindex + 1;
-- check for AHB watchpoints
if (ahbsi.hready and r.ahbactive ) = '1' then
if ((((r.tbreg1.addr xor r.haddr(31 downto 2)) and r.tbreg1.mask) = zero32(29 downto 0)) and
(((r.tbreg1.read and not r.hwrite) or (r.tbreg1.write and r.hwrite)) = '1'))
or ((((r.tbreg2.addr xor r.haddr(31 downto 2)) and r.tbreg2.mask) = zero32(29 downto 0)) and
(((r.tbreg2.read and not r.hwrite) or (r.tbreg2.write and r.hwrite)) = '1'))
then
if (r.enable = '1') and (r.dcnten = '0') and
(r.delaycnt /= zero32(TBUFABITS-1 downto 0))
then v.dcnten := '1';
else bphit := '1'; v.enable := '0'; end if;
end if;
end if;
-- generate buffer inputs
vabufi.write := "0000";
if r.enable = '1' then
vabufi.addr(TBUFABITS-1 downto 0) := r.aindex;
vabufi.data(127 downto 96) := r.timer;
vabufi.data(95) := bphit;
vabufi.data(94 downto 80) := ahbmi.hirq(15 downto 1);
vabufi.data(79) := r.hwrite;
vabufi.data(78 downto 77) := r.htrans;
vabufi.data(76 downto 74) := r.hsize;
vabufi.data(73 downto 71) := r.hburst;
vabufi.data(70 downto 67) := r.hmaster;
vabufi.data(66) := r.hmastlock;
vabufi.data(65 downto 64) := ahbmi.hresp;
if r.hwrite = '1' then
vabufi.data(63 downto 32) := ahbsi.hwdata;
else
vabufi.data(63 downto 32) := ahbmi.hrdata;
end if;
vabufi.data(31 downto 0) := r.haddr;
else
vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+3 downto 4);
vabufi.data := ahbsi.hwdata & ahbsi.hwdata &
ahbsi.hwdata & ahbsi.hwdata;
end if;
-- write trace buffer
if r.enable = '1' then
if (r.ahbactive and ahbsi.hready) = '1' then
v.aindex := aindex;
vabufi.enable := '1'; vabufi.write := "1111";
end if;
end if;
-- trace buffer delay counter handling
if (r.dcnten = '1') then
if (r.delaycnt = zero32(TBUFABITS-1 downto 0)) then
v.enable := '0'; v.dcnten := '0';
end if;
v.delaycnt := r.delaycnt - 1;
end if;
-- save AHB transfer parameters
if (ahbsi.hready = '1' ) then
v.haddr := ahbsi.haddr; v.hwrite := ahbsi.hwrite; v.htrans := ahbsi.htrans;
v.hsize := ahbsi.hsize; v.hburst := ahbsi.hburst;
v.hmaster := ahbsi.hmaster; v.hmastlock := ahbsi.hmastlock;
end if;
if r.hsel = '1' then v.hwdata := ahbsi.hwdata; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex);
v.ahbactive := ahbsi.htrans(1);
end if;
-- AHB slave access to DSU registers and trace buffers
if (r.hsel and not r.hready) = '1' then
if r.haddr(16) = '0' then -- registers
v.hready := '1';
case r.haddr(4 downto 2) is
when "000" =>
regsd((TBUFABITS + 15) downto 16) := r.delaycnt;
regsd(1 downto 0) := r.dcnten & r.enable;
if r.hwrite = '1' then
v.delaycnt := ahbsi.hwdata((TBUFABITS+ 15) downto 16);
v.dcnten := ahbsi.hwdata(1);
v.enable := ahbsi.hwdata(0);
end if;
when "001" =>
regsd((TBUFABITS - 1 + 4) downto 4) := r.aindex;
if r.hwrite = '1' then
v.aindex := ahbsi.hwdata((TBUFABITS- 1) downto 0);
end if;
when "010" =>
regsd((TIMEBITS - 1) downto 0) := r.timer;
if r.hwrite = '1' then
v.timer := ahbsi.hwdata((TIMEBITS- 1) downto 0);
end if;
when "100" =>
regsd(31 downto 2) := r.tbreg1.addr;
if r.hwrite = '1' then
v.tbreg1.addr := ahbsi.hwdata(31 downto 2);
end if;
when "101" =>
regsd := r.tbreg1.mask & r.tbreg1.read & r.tbreg1.write;
if r.hwrite = '1' then
v.tbreg1.mask := ahbsi.hwdata(31 downto 2);
v.tbreg1.read := ahbsi.hwdata(1);
v.tbreg1.write := ahbsi.hwdata(0);
end if;
when "110" =>
regsd(31 downto 2) := r.tbreg2.addr;
if r.hwrite = '1' then
v.tbreg2.addr := ahbsi.hwdata(31 downto 2);
end if;
when others =>
regsd := r.tbreg2.mask & r.tbreg2.read & r.tbreg2.write;
if r.hwrite = '1' then
v.tbreg2.mask := ahbsi.hwdata(31 downto 2);
v.tbreg2.read := ahbsi.hwdata(1);
v.tbreg2.write := ahbsi.hwdata(0);
end if;
end case;
v.hwdata := regsd;
else -- read/write access to trace buffer
if r.hwrite = '1' then v.hready := '1'; else v.hready2 := not (r.hready2 or r.hready); end if;
vabufi.enable := not r.enable;
bufdata := tbo.data;
case r.haddr(3 downto 2) is
when "00" =>
v.hwdata := bufdata(127 downto 96);
if r.hwrite = '1' then
vabufi.write(3) := vabufi.enable;
end if;
when "01" =>
v.hwdata := bufdata(95 downto 64);
if r.hwrite = '1' then
vabufi.write(2) := vabufi.enable;
end if;
when "10" =>
v.hwdata := bufdata(63 downto 32);
if r.hwrite = '1' then
vabufi.write(1) := vabufi.enable;
end if;
when others =>
v.hwdata := bufdata(31 downto 0);
if r.hwrite = '1' then
vabufi.write(0) := vabufi.enable;
end if;
end case;
end if;
end if;
if ((ahbsi.hsel(hindex) and ahbsi.hready) = '1') and
((ahbsi.htrans = HTRANS_BUSY) or (ahbsi.htrans = HTRANS_IDLE))
then v.hready := '1'; end if;
if rst = '0' then
v.ahbactive := '0'; v.enable := '0'; v.timer := (others => '0');
v.hsel := '0'; v.dcnten := '0'; v.bhit := '0';
v.tbreg1.read := '0'; v.tbreg1.write := '0';
v.tbreg2.read := '0'; v.tbreg2.write := '0';
end if;
tbi <= vabufi;
rin <= v;
ahbso.hconfig <= hconfig;
ahbso.hirq <= hirq;
ahbso.hsplit <= (others => '0');
ahbso.hcache <= '0';
ahbso.hrdata <= r.hwdata;
ahbso.hready <= r.hready;
ahbso.hindex <= hindex;
end process;
ahbso.hresp <= HRESP_OKAY;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- mem0 : tbufmem
-- generic map (tech => tech, tbuf => kbytes) port map (clk, tbi, tbo);
enable <= tbi.enable & tbi.enable;
mem0 : for i in 0 to 1 generate
ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS)
port map (clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data(((i*64)+63) downto (i*64)),
tbo.data(((i*64)+63) downto (i*64)), enable, tbi.write(i*2+1 downto i*2));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbtrace" & tost(hindex) &
": AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/leon3/mmu_dcache.vhd | 2 | 60138 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcache
-- File: dcache.vhd
-- Author: Jiri Gaisler, Konrad Eisele - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_dcache is
generic (
dsu : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0);
port (
rst : in std_logic;
clk : in std_logic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_logic;
mmudci : out mmudc_in_type;
mmudco : in mmudc_out_type;
sclk : in std_ulogic
);
end;
architecture rtl of mmu_dcache is
constant DSNOOP2 : integer := conv_integer(conv_std_logic_vector(dsnoop,3) and conv_std_logic_vector(3,3));
constant DSNOOP4 : integer := conv_integer(conv_std_logic_vector(dsnoop,3) and conv_std_logic_vector(4,3));
constant M_TLB_TYPE : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2)); -- eather split or combined
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
constant SETBITS : integer := log2x(DSETS);
constant DLRUBITS : integer := lru_table(DSETS);
constant lram : integer range 0 to 1 := 0;
constant lramsize : integer range 1 to 64 := 1;
constant lramstart : integer range 0 to 255 := 16#00#;
constant LOCAL_RAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8);
constant DREAD_FAST : boolean := false;
constant DWRITE_FAST : boolean := false;
constant DCLOCK_BIT : integer := dsetlock;
constant M_EN : boolean := true;
constant DCREPLACE : integer range 0 to 2 := drepl;
constant DLINE_SIZE : integer := dlinesize;
constant DEST_RW : boolean := (syncram_dp_dest_rw_collision(memtech) = 1);
type rdatatype is (dtag, ddata, dddata, dctx, icache, memory, sysr , misc, mmusnoop_dtag); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_logic;
lock : std_logic;
end record;
type dstatetype is (idle, wread, rtrans, wwrite, wtrans, wflush,
asi_idtag,dblwrite, loadpend);
type dcache_control_type is record -- all registers
read : std_logic; -- access direction
size : std_logic_vector(1 downto 0); -- access size
req, burst, holdn, nomds, stpend : std_logic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
paddress : std_logic_vector(31 downto 0); -- physical address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
valid : valid_type; --std_logic_vector(DLINE_SIZE - 1 downto 0); -- registered valid bits
dstate : dstatetype; -- FSM
hit : std_logic;
flush : std_logic; -- flush in progress
flush2 : std_logic; -- flush in progress
mexc : std_logic; -- latched mexc
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(4 downto 0);
icenable : std_logic; -- icache diag access
rndcnt : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter
setrepl : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace
lrr : std_logic;
dsuset : std_logic_vector(log2x(DSETS)-1 downto 0);
lock : std_logic;
lramrd : std_ulogic;
cctrl : cctrltype;
cctrlwr : std_ulogic;
mmctrl1 : mmctrl_type1;
mmctrl1wr : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
vaddr : std_logic_vector(31 downto 0);
ready : std_logic;
wbinit : std_logic;
cache : std_logic;
su : std_logic;
dblwdata : std_logic;
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_logic; -- snoop access to tags
writebp : std_logic_vector(0 to DSETS-1); -- snoop write bypass
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag
readbpx : std_logic_vector(0 to DSETS-1); -- possible write/read contention
end record;
type snoop_hit_bits_type is array (0 to 2**DOFFSET_BITS-1) of std_logic_vector(0 to DSETS-1);
type snoop_hit_reg_type is record
hit : snoop_hit_bits_type; -- snoop hit bits
taddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW); -- saved tag address
set : std_logic_vector(log2x(DSETS)-1 downto 0); -- saved set
end record;
subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);
type lru_array is array (0 to 2**DOFFSET_BITS-1) of lru_type; -- lru registers
type par_type is array (0 to DSETS-1) of std_logic_vector(1 downto 0);
type lru_reg_type is record
write : std_logic;
waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to DSETS-1;
lru : lru_array;
end record;
subtype lock_type is std_logic_vector(0 to DSETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to DSETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(DLRUBITS-1 downto 0) := lru;
if dsetlock = 1 then
unlocked := DSETS-1;
for i in DSETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case DSETS is
when 2 =>
if dsetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
end if;
when 4 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; set : integer) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
begin
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;
case DSETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
when others =>
end case;
new_lru := xnew_lru(DLRUBITS-1 downto 0);
return(new_lru);
end;
subtype word is std_logic_vector(31 downto 0);
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rh, ch : snoop_hit_reg_type; -- rs is registers, cs is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
begin
dctrl : process(rst, r, rs, rh, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn, mmudco)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_logic;
variable twrite, tpwrite, tdiagwrite, ddiagwrite, dwrite : std_logic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable newptag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatainv, rdatav, align_datav : cdatatype;
variable rdata : std_logic_vector(31 downto 0);
variable vmaskraw : std_logic_vector((dlinesize -1) downto 0);
variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);
variable ivalid : std_logic_vector((dlinesize -1) downto 0);
variable vmaskdbl : std_logic_vector((dlinesize/2 -1) downto 0);
variable enable, senable, scanen : std_logic_vector(0 to 3);
variable mds : std_logic;
variable mexc : std_logic;
variable hit, valid, validraw, forcemiss : std_logic;
variable flush : std_logic;
variable iflush : std_logic;
variable v : dcache_control_type;
variable eholdn : std_logic; -- external hold
variable tparerr, dparerr : std_logic_vector(0 to DSETS-1);
variable snoopwe : std_logic;
variable hcache : std_logic;
variable snoopaddr: std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable vh : snoop_hit_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
variable set : integer range 0 to DSETS-1;
variable ddset : integer range 0 to MAXSETS-1;
variable snoopset : integer range 0 to DSETS-1;
variable validv, hitv, validrawv : std_logic_vector(0 to MAXSETS-1);
variable csnoopwe : std_logic_vector(0 to MAXSETS-1);
variable ctwrite, ctpwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);
variable vset, setrepl : std_logic_vector(log2x(DSETS)-1 downto 0);
variable wlrr : std_logic_vector(0 to MAXSETS-1);
variable vl : lru_reg_type;
variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);
variable lock : std_logic_vector(0 to DSETS-1);
variable wlock : std_logic_vector(0 to MAXSETS-1);
variable snoopset2, rdsuset : integer range 0 to DSETS-1;
variable snoophit : std_logic_vector(0 to DSETS-1);
variable snoopval : std_logic;
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable ptag : cdatatype; --std_logic_vector(31 downto 0);
variable ctx : ctxdatatype;
variable miscdata : std_logic_vector(31 downto 0);
variable mmudiagaddr : std_logic_vector(2 downto 0);
variable pflush : std_logic;
variable pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
variable pflushtyp : std_logic;
variable pftag : std_logic_vector(31 downto 2);
variable mmuwdata : std_logic_vector(31 downto 0);
variable mmudci_fsread, tagclear : std_logic;
variable mmudci_trans_op : std_logic;
variable mmudci_flush_op : std_logic;
variable mmudci_wb_op : std_logic;
variable mmudci_diag_op : std_logic;
variable mmudci_su : std_logic;
variable mmudci_read : std_logic;
variable mmuregw, su : std_logic;
variable mmuisdis : std_logic;
variable readbp : std_logic_vector(0 to DSETS-1);
variable rbphit, sidle : std_logic;
variable mmudci_transdata_data : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(31 downto 0); -- physical address buffer
begin
-- init local variables
v := r; vs := rs; vh := rh; dcramov := dcramo; vl := rl;
vl.write := '0'; v.cctrlwr := '0'; v.mmctrl1wr := '0';
v.flush2 := r.flush; sidle := '0';
if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= idle) or
((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1') or
(is_fpga(memtech) = 1)
then
enable := (others => '1');
else enable := (others => '0'); end if;
tagclear := '0'; mmuisdis := '0';
if (not M_EN) or ((r.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
mmuisdis := '1';
end if;
if (mmuisdis = '1') then paddress := r.xaddress;
else paddress := r.paddress; end if;
mds := '1'; dwrite := '0'; twrite := '0'; tpwrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn; ddset := 0; vset := (others => '0');
tparerr := (others => '0'); dparerr := (others => '0');
vs.snoop := '0'; vs.writebp := (others => '0'); snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0'; rdsuset := 0;
validv := (others => '0'); validrawv := (others => '0');
hitv := (others => '0'); ivalid := (others => '0');
miscdata := (others => '0'); pflush := '0';
pflushaddr := dci.maddress(VA_I_U downto VA_I_D); pflushtyp := PFLUSH_PAGE;
pftag := (others => '0');
mmudiagaddr := (others => '0'); mmuregw := '0'; mmuwdata := (others => '0');
mmudci_fsread := '0';
ddatainv := (others => (others => '0')); tag := (others => (others => '0')); ptag := (others => (others => '0'));
ctx := (others => (others => '0')); vs.readbpx := (others => '0'); rbphit := '0';
newptag(TAG_HIGH downto TAG_LOW) := (others => '0');
v.trans_op := r.trans_op and (not mmudco.grant);
v.flush_op := r.flush_op and (not mmudco.grant);
v.diag_op := r.diag_op and (not mmudco.grant);
mmudci_trans_op := r.trans_op;
mmudci_flush_op := r.flush_op;
mmudci_diag_op := r.diag_op;
mmudci_wb_op := '0';
mmudci_transdata_data := r.vaddr;
mmudci_su := '0'; mmudci_read := '0'; su := '0';
if (not M_EN) or (r.mmctrl1.e = '0') then v.cache := '1'; end if;
rdatasel := ddata; -- read data from cache as default
senable := (others => '0'); scanen := (others => mcdo.scanen);
set := 0; snoopset := 0; csnoopwe := (others => '0');
ctwrite := (others => '0'); ctpwrite := (others => '0'); cdwrite := (others => '0');
wlock := (others => '0');
for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
wlrr := (others => '0');
for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;
if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
-- random replacement counter
if DSETS > 1 then
if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
lock := (others => '0');
if DCLOCK_BIT = 1 then
for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
end if;
-- AHB snoop handling
if DSNOOP2 /= 0 then
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and not mcdo.bg) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := r.cctrl.dsnoop;-- and not r.mmctrl1.e;
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
end if;
for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;
readbp := (others => '0');
if (paddress(TAG_HIGH downto OFFSET_LOW) = rs.addr(TAG_HIGH downto OFFSET_LOW)) then rbphit := '1'; end if;
for i in 0 to DSETS-1 loop
if (rs.readbpx(i) and rbphit) = '1' then readbp(i) := '1'; end if;
end loop;
-- clear valid bits on snoop hit (or set hit bits)
for i in DSETS-1 downto 0 loop
if ((rs.snoop and (not mcdo.ba) and not r.flush) = '1')
and ((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW)) or (readbp(i) = '1'))
then
if DSNOOP2 = 2 then
vh.hit(conv_integer(rs.addr(OFFSET_HIGH downto OFFSET_LOW)))(i) := '1';
else
snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);
snoopwe := '1'; snoopset := i;
end if;
end if;
-- bypass tag data on read/write contention
if (DSNOOP2 /= 2) and (rs.writebp(i) = '1') then
dcramov.tag(i)(TAG_HIGH downto TAG_LOW) := rs.addr(TAG_HIGH downto TAG_LOW);
dcramov.tag(i)(dlinesize-1 downto 0) := zero32(dlinesize-1 downto 0);
end if;
end loop;
end if;
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0); --signed := r.signed;
read := r.read; size := r.size; edata := dci.maddress;
mmudci_su := r.su; mmudci_read := r.read;
else
maddress := dci.maddress(31 downto 0); --signed := dci.signed;
read := dci.read; size := dci.size; edata := dci.edata;
mmudci_su := dci.msu; mmudci_read := dci.read;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
newptag := dci.maddress(TAG_HIGH downto TAG_LOW);
vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW); -- lru write address
-- generate cache hit and valid bits
if cached /= 0 then hcache := ctbl(conv_integer(dci.maddress(31 downto 28)));
else hcache := '1'; end if;
forcemiss := not dci.asi(3); hit := '0'; set := 0;
snoophit := (others => '0'); snoopval := '1';
for i in DSETS-1 downto 0 loop
if DSNOOP2 = 2 then
snoophit(i) := rh.hit(conv_integer(rh.taddr))(i);
end if;
if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))
and ((dcramov.ctx(i) = r.mmctrl1.ctx) or (r.mmctrl1.e = '0'))
then hitv(i) := hcache; end if;
validrawv(i) := hitv(i) and (not r.flush) and (not r.flush2) and (not snoophit(i)) and
genmux(dci.maddress(LINE_HIGH downto LINE_LOW), dcramov.tag(i)(dlinesize-1 downto 0));
validv(i) := validrawv(i);
snoopval := snoopval and not snoophit(i);
end loop;
hit := orv(hitv) and not r.flush and (not r.flush2);
-- cache hit disabled if mmu-enabled but off or BYPASS
if (M_EN) and (dci.asi(4 downto 0) = ASI_MMU_BP) then -- or (r.mmctrl1.e = '0')
hit := '0';
end if;
validraw := orv(validrawv);
valid := orv(validv);
if DSETS > 1 then
for i in DSETS-1 downto 0 loop
if hitv(i) = '1' then
vset := vset or conv_std_logic_vector(i, SETBITS);
end if;
end loop;
set := conv_integer(vset);
else set := 0; end if;
if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;
case DSETS is
when 1 => ddset := 0;
when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;
when others => ddset := conv_integer(diagset);
end case;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = idle) then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(4 downto 0);
--v.signed := dci.signed;
v.su := dci.msu;
end if;
-- Store buffer
if mcdo.ready = '1' then
v.wb.addr(2) := r.wb.addr(2) or (r.wb.size(0) and r.wb.size(1));
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;
-- cache freeze operation
if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then
v.cctrl.ics := "01";
end if;
if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then
v.cctrl.dcs := "01";
end if;
if r.cctrlwr = '1' then
if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then
v.cctrl.dsnoop := dci.maddress(23);
flush := dci.maddress(22);
iflush := dci.maddress(21);
v.cctrl.burst:= dci.maddress(16);
v.cctrl.dfrz := dci.maddress(5);
v.cctrl.ifrz := dci.maddress(4);
v.cctrl.dcs := dci.maddress(3 downto 2);
v.cctrl.ics := dci.maddress(1 downto 0);
end if;
end if;
if (dsu = 1) and (dci.dsuen = '1') then
mmuwdata := dci.maddress;
else
mmuwdata := dci.edata;
end if;
mmudiagaddr := dci.maddress(CNR_U downto CNR_D);
if r.mmctrl1wr = '1' then
mmudiagaddr := r.xaddress(CNR_U downto CNR_D); -- defer match sram out
if (dci.read = '0') then
mmuwdata := dci.maddress;
mmuregw := '1';
end if;
end if;
-- main Dcache state machine
case r.dstate is
when idle => -- Idle state
if (M_TLB_FASTWRITE /= 0) then
mmudci_transdata_data := dci.maddress;
end if;
sidle := '1';
if (snoopval = '1') then
for i in 0 to DSETS-1 loop
v.valid(i) := dcramov.tag(i)(dlinesize-1 downto 0);
end loop;
else v.valid := (others => (others => '0')); end if;
v.nomds := r.nomds and not eholdn; --v.valid := dcramov.dtramout(set).valid;
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock;
v.wb.asi := dci.asi(3 downto 0);
if ((M_EN) and (dci.asi(4 downto 0) /= ASI_MMU_BP) and (r.mmctrl1.e = '1') and (M_TLB_FASTWRITE /= 0) ) then
v.wb.addr := mmudco.wbtransdata.data;
newptag := mmudco.wbtransdata.data(TAG_HIGH downto TAG_LOW);
end if;
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
case dci.asi(4 downto 0) is
when ASI_SYSR => rdatasel := sysr;
when ASI_DTAG => rdatasel := dtag;
when ASI_DDATA => rdatasel := dddata;
when ASI_DCTX => rdatasel := dctx;
when ASI_MMUREGS => rdatasel := misc;
when ASI_MMUSNOOP_DTAG => rdatasel := mmusnoop_dtag;
when others =>
end case;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(4 downto 0) is
when ASI_SYSR => -- system registers
if (dsu = 0) or (dci.dsuen = '0') then
if (dci.maddress(7 downto 2) = "000000") and (dci.read = '0') then
v.cctrl.dsnoop := dci.edata(23);
flush := dci.edata(22);
iflush := dci.edata(21);
v.cctrl.burst:= dci.edata(16);
v.cctrl.dfrz := dci.edata(5);
v.cctrl.ifrz := dci.edata(4);
v.cctrl.dcs := dci.edata(3 downto 2);
v.cctrl.ics := dci.edata(1 downto 0);
end if;
else
v.cctrlwr := not dci.read;
end if;
when ASI_MMUREGS =>
if (dsu = 0) or dci.dsuen = '0' then
if M_EN then
-- rdatasel := misc;
-- clean fault valid bit
if dci.read = '1' then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_F =>
mmudci_fsread := '1';
when others => null;
end case;
else
mmuregw := '1';
end if;
end if;
else
v.mmctrl1wr := not dci.read and not (r.mmctrl1wr and dci.dsuen);
end if;
when ASI_ITAG | ASI_IDATA | ASI_ICTX => -- Read/write Icache tags
-- CTX write has to be done through ctxnr & ASI_ITAG
if (ico.flush = '1') or (dci.asi(4) = '1') then mexc := '1';
else v.dstate := asi_idtag; v.holdn := '0'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when ASI_MMUSNOOP_DTAG => -- Read/write MMU physical snoop tags
if M_EN then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
tpwrite := '1'; tdiagwrite := '1';
end if;
end if;
when ASI_DCTX =>
-- write has to be done through ctxnr & ASI_DTAG
if (dci.size /= "10") or (r.flush = '1') or (dci.read = '0') then -- allow only word access
mexc := '1';
end if;
when ASI_FLUSH_PAGE => -- i/dcache flush page
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_PAGE;
end if;
end if;
when ASI_FLUSH_CTX => -- i/dcache flush ctx
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_CTX;
end if;
end if;
when ASI_MMUFLUSHPROBE =>
if M_EN then
if dci.read = '0' then -- flush
mmudci_flush_op := '1';
v.flush_op := not mmudco.grant;
v.dstate := wflush;
v.vaddr := dci.maddress; v.holdn := '0'; flush := '1'; iflush := '1';
end if;
end if;
when ASI_MMU_DIAG =>
if dci.read = '0' then -- diag access
mmudci_diag_op := '1';
v.diag_op := not mmudco.grant;
v.vaddr := dci.maddress;
end if;
when others =>
if dci.read = '1' then -- read access
--if (not ((mcdo.dcs(0) = '1')
if (not ((r.cctrl.dcs(0) = '1')
and ((hit and valid and not forcemiss) = '1')))
then -- read miss
v.holdn := '0'; v.dstate := wread; v.ready := '0'; v.cache := '1';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0'))
then
-- cache disabled if mmu-enabled but off or BYPASS
if (M_EN) then v.cache := '0'; end if;
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1'))
then -- wait for store queue
v.req := '1';
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
end if;
else
-- ## mmu case >
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress;
v.dstate := rtrans;
-- ## < mmu case
end if;
else -- read hit
if (DSETS > 1) and (DCREPLACE = lru) then vl.write := '1'; end if;
end if;
else -- write access
v.ready := '0';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
else -- wait for store queue
v.dstate := wwrite; v.holdn := '0';
end if;
else
-- ## mmu case > false and
--if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and ( mmudco.wbtransdata.accexc = '0' ) and (dci.size /= "11") and (M_TLB_FASTWRITE /= 0)
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and ( mmudco.wbtransdata.accexc = '0' ) and (M_TLB_FASTWRITE /= 0)
then
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
else
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0);
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress; v.holdn := '0';
v.dstate := wtrans;
v.dblwdata := dci.size(0) or dci.size(1); -- "11"
-- ## < mmu case
end if;
end if;
-- note: cache hit disabled if BYPASS
if (r.cctrl.dcs(0) = '1') and ((hit and (dci.size(1) or validraw)) = '1')
then -- write hit
twrite := '1'; dwrite := '1';
if (DSETS > 1) and (DCREPLACE = lru) then vl.write := '1'; end if;
setrepl := conv_std_logic_vector(set, SETBITS);
if DSNOOP2 /= 0 then
if ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then v.xaddress := dci.maddress; else v.xaddress := dci.eaddress; end if;
vs.readbpx(set) := '1';
end if;
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
if (DSETS > 1) then
vl.set := conv_std_logic_vector(set, SETBITS);
v.setrepl := conv_std_logic_vector(set, SETBITS);
if ((not hit) and (not dparerr(set)) and (not r.flush)) = '1' then
case DCREPLACE is
when rnd =>
if DCLOCK_BIT = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(DSETS-1, SETBITS);
for i in DSETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(dci.maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));
when lrr =>
v.setrepl := (others => '0');
if DCLOCK_BIT = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then
v.lrr := not dcramov.tag(0)(CTAG_LRRPOS);
else
v.lrr := dcramov.tag(0)(CTAG_LRRPOS);
end if;
end case;
end if;
if (DCLOCK_BIT = 1) then
if (hit and (not dparerr(set)) and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
end case;
end if;
when rtrans =>
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
-- translation error, i.e. page fault
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
else
v.dstate := wread;
v.cache := r.cache and mmudco.transdata.cache;
--v.xaddress := mmudco.data;
v.paddress := mmudco.transdata.data;
if v.wbinit = '1' then
v.wb.addr := mmudco.transdata.data;
v.req := '1';
end if;
end if;
end if;
end if;
when wread => -- read miss, wait for memory data
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
newptag := paddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;
for i in 0 to 1 loop wlrr(i) := r.lrr; end loop;
if (r.stpend = '0') and (r.ready = '0') then
if mcdo.ready = '1' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
if (r.cctrl.dcs = "01") then
v.hit := mcdo.cache and r.hit and r.cache; twrite := v.hit;
elsif (r.cctrl.dcs(1) = '1') then
v.hit := mcdo.cache and (r.hit or (r.asi(3) and not r.asi(2))) and r.cache; twrite := v.hit;
end if;
dwrite := twrite; rdatasel := memory;
mexc := mcdo.mexc;
tpwrite := twrite;
if r.req = '0' then
if (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
else v.dstate := idle; end if;
else v.nomds := '1'; end if;
end if;
v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;
else
if (r.ready or (mcdo.ready and not r.req)) = '1' then -- wait for store queue
v.burst := r.size(1) and r.size(0) and not r.xaddress(2);
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi(3 downto 0); v.ready := '0';
end if;
end if;
if DSNOOP2 /= 0 then vs.readbpx(conv_integer(setrepl)) := '1'; end if;
when loadpend => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
v.dstate := idle;
when dblwrite => -- second part of double store cycle
v.dstate := idle; v.wb.data2 := dci.edata;
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;
when asi_idtag => -- icache diag access
rdatasel := icache; v.icenable := '1'; v.holdn := dci.dsuen;
if ico.diagrdy = '1' then
v.dstate := loadpend; v.icenable := '0'; mds := not r.read;
end if;
when wtrans =>
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
-- fetch dblwrite data 2, does the same as state dblwrite,
-- except that init of data2 is omitted to end of translation or in wwrite
if ((r.dblwdata) = '1') and ((r.size) = "11") then
v.dblwdata := '0';
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
tagclear := r.cctrl.dcs(0) and r.hit;
twrite := tagclear;
if (twrite = '1') and (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
end if;
else
v.dstate := wwrite;
v.cache := mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
if (r.wbinit) = '1' then
v.wb.data2 := dci.edata;
v.wb.addr := mmudco.transdata.data;
v.dstate := idle; v.holdn := '1';
v.req := '1'; v.stpend := '1';
v.burst := r.size(1) and r.size(0) and not v.wb.addr(2);
--if (mcdo.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
dwrite := '1';
end if;
end if;
end if;
else
-- mmudci_trans_op := '1'; -- start translation
end if;
end if;
when wwrite => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if (v.ready or (mcdo.ready and not r.req)) = '1' then -- store queue emptied
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';
end if;
v.dstate := idle;
v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi(3 downto 0);
if r.size = "11" then v.wb.addr(2) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when wflush =>
v.holdn := '0';
if mmudco.transdata.finish = '1' then
v.dstate := idle; v.holdn := '1';
end if;
when others => v.dstate := idle;
end case;
-- select data to return on read access
-- align if byte/half word read from cache or memory.
--mmudiagaddr := dci.maddress(CNR_U downto CNR_D); mmuwdata := dci.edata;
if (dsu = 1) and (dci.dsuen = '1') then
v.dsuset := conv_std_logic_vector(ddset, SETBITS);
case dci.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA =>
v.icenable := not ico.diagrdy;
rdatasel := icache;
when ASI_DTAG =>
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
twrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dtag;
when ASI_MMUSNOOP_DTAG =>
if M_EN then
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
tpwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := mmusnoop_dtag;
end if;
when ASI_DDATA =>
ddiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
dwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dddata;
when ASI_MMUREGS =>
mmuregw := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := misc;
when others =>
end case;
end if;
-- note: mmudiagaddr is (10 downto 8) (000,001, ...)
-- read
case mmudiagaddr is
when CNR_CTRL =>
miscdata(MMCTRL_E) := r.mmctrl1.e;
miscdata(MMCTRL_NF) := r.mmctrl1.nf;
miscdata(MMCTRL_PSO) := r.mmctrl1.pso;
miscdata(MMCTRL_VER_U downto MMCTRL_VER_D) := "0000";
miscdata(MMCTRL_IMPL_U downto MMCTRL_IMPL_D) := "0000";
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_ILOG,3);
miscdata(20 downto 18) := conv_std_logic_vector(M_ENT_DLOG,3);
if M_TLB_TYPE = 0 then miscdata(17) := '1'; else
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_CLOG,3);
miscdata(20 downto 18) := (others => '0');
end if;
miscdata(MMCTRL_TLBDIS) := r.mmctrl1.tlbdis;
--custom
when CNR_CTXP =>
miscdata(MMCTXP_U downto MMCTXP_D) := r.mmctrl1.ctxp;
when CNR_CTX =>
miscdata(MMCTXNR_U downto MMCTXNR_D) := r.mmctrl1.ctx;
when CNR_F =>
miscdata(FS_OW) := mmudco.mmctrl2.fs.ow;
miscdata(FS_FAV) := mmudco.mmctrl2.fs.fav;
miscdata(FS_FT_U downto FS_FT_D) := mmudco.mmctrl2.fs.ft;
miscdata(FS_AT_LS) := mmudco.mmctrl2.fs.at_ls;
miscdata(FS_AT_ID) := mmudco.mmctrl2.fs.at_id;
miscdata(FS_AT_SU) := mmudco.mmctrl2.fs.at_su;
miscdata(FS_L_U downto FS_L_D) := mmudco.mmctrl2.fs.l;
miscdata(FS_EBE_U downto FS_EBE_D) := mmudco.mmctrl2.fs.ebe;
when CNR_FADDR =>
miscdata(VA_I_U downto VA_I_D) := mmudco.mmctrl2.fa;
when others => null;
end case;
rdata := (others => '0'); rdatav := (others => (others => '0'));
align_data := (others => '0'); align_datav := (others => (others => '0'));
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when misc =>
set := 0;
rdatav(0) := miscdata;
when dddata =>
rdatav := dcramov.data;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dtag =>
rdatav := dcramov.tag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when mmusnoop_dtag =>
rdatav := dcramov.stag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dctx =>
--rdata(M_CTX_SZ-1 downto 0) := dcramov.dtramout(ddset).ctx;
when icache =>
rdatav(0) := ico.diagdata; set := 0;
when ddata | memory =>
if rdatasel = memory then
rdatav(0) := mcdo.data; set := 0; --FIXME
else
for i in 0 to DSETS-1 loop rdatav(i) := dcramov.data(i); end loop;
end if;
when sysr =>
set := 0;
case dci.maddress(3 downto 2) is
when "00" | "01" =>
rdatav(0)(23) := r.cctrl.dsnoop;
rdatav(0)(16 downto 14) := r.cctrl.burst & ico.flush & r.flush;
rdatav(0)(5 downto 0) :=
r.cctrl.dfrz & r.cctrl.ifrz & r.cctrl.dcs & r.cctrl.ics;
when "10" =>
rdatav(0) := ico.cfg;
when others =>
rdatav(0) := cache_cfg(drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, lram, lramsize, lramstart, 1);
end case;
end case;
-- select which data to update the data cache with
for i in 0 to DSETS-1 loop
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatainv(i) := edata(7 downto 0) & dcramov.data(i)(23 downto 0);
when "01" =>
ddatainv(i) := dcramov.data(i)(31 downto 24) & edata(7 downto 0) &
dcramov.data(i)(15 downto 0);
when "10" =>
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(7 downto 0) &
dcramov.data(i)(7 downto 0);
when others =>
ddatainv(i) := dcramov.data(i)(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatainv(i) := edata(15 downto 0) & dcramov.data(i)(15 downto 0);
else
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatainv(i) := edata;
end case;
end loop;
-- handle double load with pipeline hold
if (r.dstate = idle) and (r.nomds = '1') then
rdatav(0) := r.wb.data2; mexc := r.mexc; set := 0; --FIXME
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
end if;
-- Generate new valid bits
vmaskdbl := decode(maddress(LINE_HIGH downto LINE_LOW+1));
if (size = "11") and (read = '0') then
for i in 0 to (DLINE_SIZE - 1) loop vmaskraw(i) := vmaskdbl(i/2); end loop;
else
vmaskraw := decode(maddress(LINE_HIGH downto LINE_LOW));
end if;
vmask := (others => vmaskraw);
if r.hit = '1' then
for i in 0 to DSETS-1 loop vmask(i) := r.valid(i) or vmaskraw; end loop;
end if;
if r.dstate = idle then
for i in 0 to DSETS-1 loop
vmask(i) := dcramov.tag(i)(dlinesize-1 downto 0) or vmaskraw;
end loop;
end if;
if (mcdo.mexc or r.flush) = '1' then twrite := '0'; dwrite := '0'; end if;
if twrite = '1' then
if tagclear = '1' then vmask := (others => (others => '0')); end if;
v.valid := vmask;
if (DSETS>1) and (DCREPLACE = lru) and (tdiagwrite = '0') then
vl.write := '1'; vl.set := setrepl;
end if;
end if;
if (DSETS>1) and (DCREPLACE = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), conv_integer(rl.set));
end if;
if tdiagwrite = '1' then -- diagnostic tag write
if (dsu = 1) and (dci.dsuen = '1') then
vmask := (others => dci.maddress(dlinesize - 1 downto 0));
else
vmask := (others => dci.edata(dlinesize - 1 downto 0));
newtag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
newptag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
for i in 0 to 3 loop wlrr(i) := dci.edata(CTAG_LRRPOS); end loop;
for i in 0 to DSETS-1 loop wlock(i) := dci.edata(CTAG_LOCKPOS); end loop;
end if;
end if;
-- mmureg write
if mmuregw = '1' then
case mmudiagaddr is
when CNR_CTRL =>
v.mmctrl1.e := mmuwdata(MMCTRL_E);
v.mmctrl1.nf := mmuwdata(MMCTRL_NF);
v.mmctrl1.pso := mmuwdata(MMCTRL_PSO);
v.mmctrl1.tlbdis := mmuwdata(MMCTRL_TLBDIS);
--custom
-- Note: before tlb disable tlb flush is required !!!
when CNR_CTXP =>
v.mmctrl1.ctxp := mmuwdata(MMCTXP_U downto MMCTXP_D);
when CNR_CTX =>
v.mmctrl1.ctx := mmuwdata(MMCTXNR_U downto MMCTXNR_D);
when CNR_F => null;
when CNR_FADDR => null;
when others => null;
end case;
end if;
-- cache flush
--if (dci.flush or flush or mcdo.dflush) = '1' then
if (dci.flush or flush ) = '1' then
v.flush := '1'; v.faddr := (others => '0'); v.pflush := pflush;
v.pflushr := '1';
v.pflushaddr := pflushaddr;
v.pflushtyp := pflushtyp;
end if;
if r.flush = '1' then
twrite := '1'; vmask := (others=>(others => '0')); v.faddr := r.faddr +1;
newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
newptag(TAG_HIGH downto TAG_LOW) := (others => '0');
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := (others => '0'); v.lrr := '0';
if (r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) = '1' then
v.flush := '0';
end if;
if DSNOOP2 = 2 then
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW))) := (others => '0');
end if;
end if;
-- AHB snoop handling (2), bypass write data on read/write contention
if DSNOOP2 /= 0 then
if tdiagwrite = '1' then snoopset2 := ddset;
else snoopset2 := conv_integer(setrepl); end if;
if DSNOOP2 = 2 then
vh.taddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
vh.set := conv_std_logic_vector(set, SETBITS);
if (twrite = '1') and (r.dstate /= idle) then
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW)))(snoopset2) := '0';
end if;
else
if rs.addr(OFFSET_HIGH downto OFFSET_LOW) =
taddr(OFFSET_HIGH downto OFFSET_LOW)
then
if twrite = '0' then
if snoopwe = '1' then
vs.writebp(snoopset) := '1';
if DEST_RW then enable(snoopset) := '0'; end if;
end if;
else
if (snoopwe = '1') and (conv_integer(setrepl) = snoopset) then -- avoid write/write contention
twrite := '0';
if DEST_RW then enable(snoopset) := '0'; end if;
end if;
end if;
end if;
end if;
if (r.dstate = wread) and ((rbphit and rs.snoop) = '1') then v.hit := '0'; end if;
if DEST_RW then
-- disable snoop read enable on write/read contention
if taddr(OFFSET_HIGH downto OFFSET_LOW) = ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW) then
for i in 0 to DSETS-1 loop
if (twrite and senable(i)) = '1' then senable(i) := '0'; end if;
end loop;
end if;
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then
for i in 0 to DSETS-1 loop ddatainv(i) := mcdo.data; end loop;
end if;
-- cache write signals
if twrite = '1' then
if tdiagwrite = '1' then ctwrite(ddset) := '1';
else ctwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if M_EN then
if tpwrite = '1' then
if tdiagwrite = '1' then ctpwrite(ddset) := '1';
else ctpwrite(conv_integer(setrepl)) := '1'; end if;
end if;
end if;
if dwrite = '1' then
if ddiagwrite = '1' then cdwrite(ddset) := '1';
else cdwrite(conv_integer(setrepl)) := '1'; end if;
end if;
csnoopwe := (others => '0');
if ((snoopwe and not mcdo.scanen) = '1') then csnoopwe(snoopset) := '1'; end if;
if (r.flush and twrite) = '1' then -- flush
ctwrite := (others => '1'); wlrr := (others => '0'); wlock := (others => '0');
if M_EN then
ctpwrite := (others => '1');
end if;
-- precise flush, ASI_FLUSH_PAGE & ASI_FLUSH_CTX
if false then --
if M_EN then
if r.pflush = '1' then
twrite := '0'; ctwrite := (others => '0');
for i in DSETS-1 downto 0 loop
wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS);
wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS);
end loop;
if r.pflushr = '0' then
for i in DSETS-1 downto 0 loop
pftag(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
pftag(TAG_HIGH downto TAG_LOW) := dcramov.tag(i)(TAG_HIGH downto TAG_LOW);
if ((pftag(VA_I_U downto VA_I_D) = r.pflushaddr(VA_I_U downto VA_I_D)) or
(r.pflushtyp = '1')) then
ctwrite(i) := '1';
wlrr(i) := '0';
wlock(i) := '0';
end if;
end loop;
else
v.faddr := r.faddr;
end if;
v.pflushr := not r.pflushr;
end if;
end if;
end if;
end if;
if r.flush2 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- reset
if rst = '0' then
v.dstate := idle; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0'; v.holdn := '1';
v.rndcnt := (others => '0'); v.setrepl := (others => '0');
v.dsuset := (others => '0');
v.lrr := '0'; v.lock := '0'; v.flush2 := '1';
v.cctrl.dcs := "00"; v.cctrl.ics := "00";
v.cctrl.burst := '0'; v.cctrl.dsnoop := '0';
v.mmctrl1.e := '0'; v.mmctrl1.nf := '0'; v.mmctrl1.ctx := (others => '0');
v.mmctrl1.tlbdis := '0';
v.mmctrl1.pso := '0';
v.trans_op := '0';
v.flush_op := '0';
v.diag_op := '0';
v.pflush := '0';
v.pflushr := '0';
v.mmctrl1.bar := (others => '0');
end if;
if dsnoop = 0 then v.cctrl.dsnoop := '0'; end if;
-- Drive signals
c <= v; cs <= vs; ch <= vh; -- register inputs
cl <= vl;
-- tag ram inputs
senable := senable and not scanen; enable := enable and not scanen;
if mcdo.scanen = '1' then ctpwrite := (others => '0'); end if;
for i in 0 to DSETS-1 loop
tag(i)(dlinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := newtag(TAG_HIGH downto TAG_LOW);
tag(i)(CTAG_LRRPOS) := wlrr(i);
tag(i)(CTAG_LOCKPOS) := wlock(i);
ctx(i) := r.mmctrl1.ctx;
ptag(i)(TAG_HIGH downto TAG_LOW) := newptag(TAG_HIGH downto TAG_LOW);
end loop;
dcrami.tag <= tag;
dcrami.ptag <= ptag;
dcrami.ctx <= ctx;
dcrami.tenable <= enable;
dcrami.twrite <= ctwrite;
dcrami.tpwrite <= ctpwrite;
dcrami.flush <= r.flush;
dcrami.senable <= senable; --vs.snoop or rs.snoop;
dcrami.swrite <= csnoopwe;
dcrami.saddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.saddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= snoopaddr;
dcrami.stag(31 downto (TAG_HIGH - TAG_LOW +1)) <=
zero32(31 downto (TAG_HIGH - TAG_LOW +1));
dcrami.stag(TAG_HIGH - TAG_LOW downto 0) <= rs.addr(TAG_HIGH downto TAG_LOW);
dcrami.tdiag <= mcdo.testen & "000";
dcrami.ddiag <= mcdo.testen & "000";
-- data ram inputs
dcrami.denable <= enable;
dcrami.address(19 downto (OFFSET_HIGH - LINE_LOW + 1)) <= zero32(19 downto (OFFSET_HIGH - LINE_LOW + 1));
dcrami.address(OFFSET_HIGH - LINE_LOW downto 0) <= taddr;
dcrami.data <= ddatainv;
dcrami.dwrite <= cdwrite;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.cache <= orv(r.cctrl.dcs);
--mcdi.flush <= r.flush;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush;-- or mcdo.iflush;
dco.icdiag.pflush <= pflush;
dco.icdiag.pflushaddr <= pflushaddr;
dco.icdiag.pflushtyp <= pflushtyp;
dco.icdiag.read <= read;
dco.icdiag.tag <= (not r.asi(0));-- and (not r.asi(4));
dco.icdiag.ctx <= r.asi(4); --ASI_ICTX "10101"
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.icdiag.cctrl <= r.cctrl;
dco.icdiag.scanen <= mcdo.scanen;
-- IU data cache inputs
dco.data <= rdatav;
dco.mexc <= mexc;
dco.set <= conv_std_logic_vector(set, 2);
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
dco.idle <= sidle and not r.stpend;
dco.scanen <= mcdo.scanen;
dco.testen <= mcdo.testen;
-- MMU
mmudci.trans_op <= mmudci_trans_op;
mmudci.transdata.data <= mmudci_transdata_data; --r.vaddr;
mmudci.transdata.su <= mmudci_su;
mmudci.transdata.read <= mmudci_read;
mmudci.transdata.isid <= id_dcache;
mmudci.transdata.wb_data <= dci.maddress;
mmudci.flush_op <= mmudci_flush_op;
mmudci.wb_op <= mmudci_wb_op;
mmudci.diag_op <= mmudci_diag_op;
mmudci.fsread <= mmudci_fsread;
mmudci.mmctrl1 <= r.mmctrl1;
end process;
-- Local registers
reg1 : process(clk)
begin if rising_edge(clk ) then r <= c; end if; end process;
sn2 : if DSNOOP2 /= 0 generate
reg2 : process(sclk)
begin if rising_edge(sclk ) then rs <= cs; end if; end process;
end generate;
nosn2 : if DSNOOP2 = 0 generate
rs.snoop <= '0'; rs.writebp <= (others => '0');
rs.addr <= (others => '0'); rs.readbpx <= (others => '0');
end generate;
sn3 : if DSNOOP2 = 2 generate
reg3 : process(sclk)
begin if rising_edge(sclk ) then rh <= ch; end if; end process;
end generate;
sn3no : if DSNOOP2 /= 2 generate
rh.hit <= (others => (others => '0'));
rh.taddr <= (others => '0');
rh.set <= (others => '0');
end generate;
reg2 : if (DSETS>1) and (DCREPLACE = lru) generate
reg2 : process(clk)
begin if rising_edge(clk ) then rl <= cl; end if; end process;
end generate;
noreg2 : if (DSETS = 1) or (drepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((DSETS > 2) and (DCREPLACE = lrr)) report
"Wrong data cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
| mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/eth/core/eth_rstgen.vhd | 2 | 1891 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: eth_rstgen
-- File: eth_rstgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Reset generation with glitch filter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity eth_rstgen is
generic (acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end;
architecture rtl of eth_rstgen is
signal r : std_logic_vector(4 downto 0);
signal rst : std_ulogic;
begin
rst <= not rstin when acthigh = 1 else rstin;
rstoutraw <= rst;
reg1 : process (clk, rst) begin
if rising_edge(clk) then
r <= r(3 downto 0) & clklock;
rstout <= r(4) and r(3) and r(2);
end if;
if rst = '0' then r <= "00000"; rstout <= '0'; end if;
end process;
end;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/fp_explutneg.vhd | 10 | 14862 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUTNEG.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explutneg IS
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explutneg;
ARCHITECTURE rtl OF fp_explutneg IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "0000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "0000001" =>
mantissa <= conv_std_logic_vector(3955378,23);
exponent <= conv_std_logic_vector(125,8);
WHEN "0000010" =>
mantissa <= conv_std_logic_vector(693589,23);
exponent <= conv_std_logic_vector(124,8);
WHEN "0000011" =>
mantissa <= conv_std_logic_vector(4976006,23);
exponent <= conv_std_logic_vector(122,8);
WHEN "0000100" =>
mantissa <= conv_std_logic_vector(1444526,23);
exponent <= conv_std_logic_vector(121,8);
WHEN "0000101" =>
mantissa <= conv_std_logic_vector(6081023,23);
exponent <= conv_std_logic_vector(119,8);
WHEN "0000110" =>
mantissa <= conv_std_logic_vector(2257552,23);
exponent <= conv_std_logic_vector(118,8);
WHEN "0000111" =>
mantissa <= conv_std_logic_vector(7277405,23);
exponent <= conv_std_logic_vector(116,8);
WHEN "0001000" =>
mantissa <= conv_std_logic_vector(3137800,23);
exponent <= conv_std_logic_vector(115,8);
WHEN "0001001" =>
mantissa <= conv_std_logic_vector(92049,23);
exponent <= conv_std_logic_vector(114,8);
WHEN "0001010" =>
mantissa <= conv_std_logic_vector(4090830,23);
exponent <= conv_std_logic_vector(112,8);
WHEN "0001011" =>
mantissa <= conv_std_logic_vector(793249,23);
exponent <= conv_std_logic_vector(111,8);
WHEN "0001100" =>
mantissa <= conv_std_logic_vector(5122658,23);
exponent <= conv_std_logic_vector(109,8);
WHEN "0001101" =>
mantissa <= conv_std_logic_vector(1552426,23);
exponent <= conv_std_logic_vector(108,8);
WHEN "0001110" =>
mantissa <= conv_std_logic_vector(6239800,23);
exponent <= conv_std_logic_vector(106,8);
WHEN "0001111" =>
mantissa <= conv_std_logic_vector(2374373,23);
exponent <= conv_std_logic_vector(105,8);
WHEN "0010000" =>
mantissa <= conv_std_logic_vector(7449310,23);
exponent <= conv_std_logic_vector(103,8);
WHEN "0010001" =>
mantissa <= conv_std_logic_vector(3264281,23);
exponent <= conv_std_logic_vector(102,8);
WHEN "0010010" =>
mantissa <= conv_std_logic_vector(185108,23);
exponent <= conv_std_logic_vector(101,8);
WHEN "0010011" =>
mantissa <= conv_std_logic_vector(4227768,23);
exponent <= conv_std_logic_vector(99,8);
WHEN "0010100" =>
mantissa <= conv_std_logic_vector(894003,23);
exponent <= conv_std_logic_vector(98,8);
WHEN "0010101" =>
mantissa <= conv_std_logic_vector(5270919,23);
exponent <= conv_std_logic_vector(96,8);
WHEN "0010110" =>
mantissa <= conv_std_logic_vector(1661510,23);
exponent <= conv_std_logic_vector(95,8);
WHEN "0010111" =>
mantissa <= conv_std_logic_vector(6400319,23);
exponent <= conv_std_logic_vector(93,8);
WHEN "0011000" =>
mantissa <= conv_std_logic_vector(2492476,23);
exponent <= conv_std_logic_vector(92,8);
WHEN "0011001" =>
mantissa <= conv_std_logic_vector(7623101,23);
exponent <= conv_std_logic_vector(90,8);
WHEN "0011010" =>
mantissa <= conv_std_logic_vector(3392149,23);
exponent <= conv_std_logic_vector(89,8);
WHEN "0011011" =>
mantissa <= conv_std_logic_vector(279189,23);
exponent <= conv_std_logic_vector(88,8);
WHEN "0011100" =>
mantissa <= conv_std_logic_vector(4366209,23);
exponent <= conv_std_logic_vector(86,8);
WHEN "0011101" =>
mantissa <= conv_std_logic_vector(995862,23);
exponent <= conv_std_logic_vector(85,8);
WHEN "0011110" =>
mantissa <= conv_std_logic_vector(5420806,23);
exponent <= conv_std_logic_vector(83,8);
WHEN "0011111" =>
mantissa <= conv_std_logic_vector(1771791,23);
exponent <= conv_std_logic_vector(82,8);
WHEN "0100000" =>
mantissa <= conv_std_logic_vector(6562600,23);
exponent <= conv_std_logic_vector(80,8);
WHEN "0100001" =>
mantissa <= conv_std_logic_vector(2611876,23);
exponent <= conv_std_logic_vector(79,8);
WHEN "0100010" =>
mantissa <= conv_std_logic_vector(7798799,23);
exponent <= conv_std_logic_vector(77,8);
WHEN "0100011" =>
mantissa <= conv_std_logic_vector(3521421,23);
exponent <= conv_std_logic_vector(76,8);
WHEN "0100100" =>
mantissa <= conv_std_logic_vector(374301,23);
exponent <= conv_std_logic_vector(75,8);
WHEN "0100101" =>
mantissa <= conv_std_logic_vector(4506169,23);
exponent <= conv_std_logic_vector(73,8);
WHEN "0100110" =>
mantissa <= conv_std_logic_vector(1098839,23);
exponent <= conv_std_logic_vector(72,8);
WHEN "0100111" =>
mantissa <= conv_std_logic_vector(5572338,23);
exponent <= conv_std_logic_vector(70,8);
WHEN "0101000" =>
mantissa <= conv_std_logic_vector(1883282,23);
exponent <= conv_std_logic_vector(69,8);
WHEN "0101001" =>
mantissa <= conv_std_logic_vector(6726661,23);
exponent <= conv_std_logic_vector(67,8);
WHEN "0101010" =>
mantissa <= conv_std_logic_vector(2732585,23);
exponent <= conv_std_logic_vector(66,8);
WHEN "0101011" =>
mantissa <= conv_std_logic_vector(7976426,23);
exponent <= conv_std_logic_vector(64,8);
WHEN "0101100" =>
mantissa <= conv_std_logic_vector(3652111,23);
exponent <= conv_std_logic_vector(63,8);
WHEN "0101101" =>
mantissa <= conv_std_logic_vector(470458,23);
exponent <= conv_std_logic_vector(62,8);
WHEN "0101110" =>
mantissa <= conv_std_logic_vector(4647665,23);
exponent <= conv_std_logic_vector(60,8);
WHEN "0101111" =>
mantissa <= conv_std_logic_vector(1202946,23);
exponent <= conv_std_logic_vector(59,8);
WHEN "0110000" =>
mantissa <= conv_std_logic_vector(5725533,23);
exponent <= conv_std_logic_vector(57,8);
WHEN "0110001" =>
mantissa <= conv_std_logic_vector(1995997,23);
exponent <= conv_std_logic_vector(56,8);
WHEN "0110010" =>
mantissa <= conv_std_logic_vector(6892523,23);
exponent <= conv_std_logic_vector(54,8);
WHEN "0110011" =>
mantissa <= conv_std_logic_vector(2854620,23);
exponent <= conv_std_logic_vector(53,8);
WHEN "0110100" =>
mantissa <= conv_std_logic_vector(8156001,23);
exponent <= conv_std_logic_vector(51,8);
WHEN "0110101" =>
mantissa <= conv_std_logic_vector(3784235,23);
exponent <= conv_std_logic_vector(50,8);
WHEN "0110110" =>
mantissa <= conv_std_logic_vector(567669,23);
exponent <= conv_std_logic_vector(49,8);
WHEN "0110111" =>
mantissa <= conv_std_logic_vector(4790713,23);
exponent <= conv_std_logic_vector(47,8);
WHEN "0111000" =>
mantissa <= conv_std_logic_vector(1308195,23);
exponent <= conv_std_logic_vector(46,8);
WHEN "0111001" =>
mantissa <= conv_std_logic_vector(5880410,23);
exponent <= conv_std_logic_vector(44,8);
WHEN "0111010" =>
mantissa <= conv_std_logic_vector(2109948,23);
exponent <= conv_std_logic_vector(43,8);
WHEN "0111011" =>
mantissa <= conv_std_logic_vector(7060204,23);
exponent <= conv_std_logic_vector(41,8);
WHEN "0111100" =>
mantissa <= conv_std_logic_vector(2977993,23);
exponent <= conv_std_logic_vector(40,8);
WHEN "0111101" =>
mantissa <= conv_std_logic_vector(8337547,23);
exponent <= conv_std_logic_vector(38,8);
WHEN "0111110" =>
mantissa <= conv_std_logic_vector(3917809,23);
exponent <= conv_std_logic_vector(37,8);
WHEN "0111111" =>
mantissa <= conv_std_logic_vector(665948,23);
exponent <= conv_std_logic_vector(36,8);
WHEN "1000000" =>
mantissa <= conv_std_logic_vector(4935332,23);
exponent <= conv_std_logic_vector(34,8);
WHEN "1000001" =>
mantissa <= conv_std_logic_vector(1414599,23);
exponent <= conv_std_logic_vector(33,8);
WHEN "1000010" =>
mantissa <= conv_std_logic_vector(6036985,23);
exponent <= conv_std_logic_vector(31,8);
WHEN "1000011" =>
mantissa <= conv_std_logic_vector(2225150,23);
exponent <= conv_std_logic_vector(30,8);
WHEN "1000100" =>
mantissa <= conv_std_logic_vector(7229726,23);
exponent <= conv_std_logic_vector(28,8);
WHEN "1000101" =>
mantissa <= conv_std_logic_vector(3102720,23);
exponent <= conv_std_logic_vector(27,8);
WHEN "1000110" =>
mantissa <= conv_std_logic_vector(66239,23);
exponent <= conv_std_logic_vector(26,8);
WHEN "1000111" =>
mantissa <= conv_std_logic_vector(4052849,23);
exponent <= conv_std_logic_vector(24,8);
WHEN "1001000" =>
mantissa <= conv_std_logic_vector(765304,23);
exponent <= conv_std_logic_vector(23,8);
WHEN "1001001" =>
mantissa <= conv_std_logic_vector(5081537,23);
exponent <= conv_std_logic_vector(21,8);
WHEN "1001010" =>
mantissa <= conv_std_logic_vector(1522171,23);
exponent <= conv_std_logic_vector(20,8);
WHEN "1001011" =>
mantissa <= conv_std_logic_vector(6195279,23);
exponent <= conv_std_logic_vector(18,8);
WHEN "1001100" =>
mantissa <= conv_std_logic_vector(2341616,23);
exponent <= conv_std_logic_vector(17,8);
WHEN "1001101" =>
mantissa <= conv_std_logic_vector(7401108,23);
exponent <= conv_std_logic_vector(15,8);
WHEN "1001110" =>
mantissa <= conv_std_logic_vector(3228816,23);
exponent <= conv_std_logic_vector(14,8);
WHEN "1001111" =>
mantissa <= conv_std_logic_vector(159015,23);
exponent <= conv_std_logic_vector(13,8);
WHEN "1010000" =>
mantissa <= conv_std_logic_vector(4189370,23);
exponent <= conv_std_logic_vector(11,8);
WHEN "1010001" =>
mantissa <= conv_std_logic_vector(865751,23);
exponent <= conv_std_logic_vector(10,8);
WHEN "1010010" =>
mantissa <= conv_std_logic_vector(5229346,23);
exponent <= conv_std_logic_vector(8,8);
WHEN "1010011" =>
mantissa <= conv_std_logic_vector(1630923,23);
exponent <= conv_std_logic_vector(7,8);
WHEN "1010100" =>
mantissa <= conv_std_logic_vector(6355309,23);
exponent <= conv_std_logic_vector(5,8);
WHEN "1010101" =>
mantissa <= conv_std_logic_vector(2459360,23);
exponent <= conv_std_logic_vector(4,8);
WHEN "1010110" =>
mantissa <= conv_std_logic_vector(7574370,23);
exponent <= conv_std_logic_vector(2,8);
WHEN "1010111" =>
mantissa <= conv_std_logic_vector(3356295,23);
exponent <= conv_std_logic_vector(1,8);
WHEN "1011000" =>
mantissa <= conv_std_logic_vector(252809,23);
exponent <= conv_std_logic_vector(0,8);
WHEN "1011001" =>
mantissa <= conv_std_logic_vector(4327390,23);
exponent <= conv_std_logic_vector(-2,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_cast_GNJ7VFHJ4A.vhd | 4 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNJ7VFHJ4A is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNJ7VFHJ4A is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 16 + 1 ,
width_inr=> 0,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(15 downto 0) => input,
xin(16) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/altera_lnsim/ama_signed_extension_function/_primary.vhd | 5 | 1086 | library verilog;
use verilog.vl_types.all;
entity ama_signed_extension_function is
generic(
representation : string := "UNSIGNED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_ext : vl_notype;
wdith_data_ext_msb: vl_notype
);
port(
data_in : in vl_logic_vector;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of representation : constant is 1;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_ext : constant is 3;
attribute mti_svvh_generic_type of wdith_data_ext_msb : constant is 3;
end ama_signed_extension_function;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GN46N4UJ5S.vhd | 20 | 844 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN46N4UJ5S is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic;
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN46N4UJ5S is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 1 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(0) => input,
xin(1) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_cast_GN46N4UJ5S.vhd | 20 | 844 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN46N4UJ5S is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic;
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN46N4UJ5S is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 1 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(0) => input,
xin(1) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_testbench_salt_GN6DKNTQ5M.vhd | 13 | 1747 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 2) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_if_statement_GNIV4UP6ZO.vhd | 4 | 1401 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a=b";
number_inputs : integer := 2;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNIV4UP6ZO is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(a=b) ;
true <= result;
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_SInitDelay.vhd | 20 | 3601 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 7.2)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2007 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SInitDelay is
generic (
lpm_width : positive :=8;
lpm_delay : positive :=2;
SequenceLength : positive :=1;
SequenceValue : std_logic_vector :="1";
ResetValue : std_logic_vector :="00000001"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
ena : in std_logic :='1';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
sclr : in std_logic :='0';
result : out std_logic_vector(lpm_width-1 downto 0) :=(others=>'0')
);
end alt_dspbuilder_SInitDelay;
architecture SInitDelay_SYNTH of alt_dspbuilder_SInitDelay is
type StdUArray is array (lpm_delay-1 downto 0) of std_logic_vector (lpm_width-1 downto 0);
signal DelayLine : StdUArray;
signal dataa_int : std_logic_vector(lpm_width-1 downto 0);
signal seqenable : std_logic ;
signal enadff : std_logic ;
signal aclr_i : std_logic ;
begin
aclr_i <= aclr or user_aclr;
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> lpm_width)
port map (d => dataa, r => dataa_int);
gnoseq: if ((SequenceLength=1) and (SequenceValue="1")) generate
enadff <= ena;
end generate gnoseq;
gseq: if not ((SequenceLength=1) and (SequenceValue="1")) generate
u:alt_dspbuilder_vecseq generic map (SequenceLength=>SequenceLength,SequenceValue=>SequenceValue)
port map (clock=>clock, ena=>ena, aclr=>aclr_i, sclr=>sclr, yout=> seqenable);
enadff <= seqenable and ena;
end generate gseq;
gen1:if lpm_delay=1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
result <= ResetValue;
elsif clock'event and clock='1' then
if (sclr ='1') then
result <= ResetValue;
elsif enadff ='1' then
result <= dataa_int;
end if;
end if;
end process;
end generate;
gen2:if lpm_delay>1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
DelayLine <= (others => ResetValue);
elsif clock'event and clock='1' then
if (sclr='1') then
DelayLine <= (others => ResetValue);
elsif (enadff='1') then
DelayLine(0) <= dataa_int;
for i in 1 to lpm_delay-1 loop
DelayLine(i) <= DelayLine(i-1);
end loop;
end if;
end if;
end process;
result <= DelayLine(lpm_delay-1);
end generate;
end SInitDelay_SYNTH;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/altera_lnsim/ama_register_with_ext_function/_primary.vhd | 5 | 1580 | library verilog;
use verilog.vl_types.all;
entity ama_register_with_ext_function is
generic(
width_data_in : integer := 1;
width_data_out : vl_notype;
register_clock : string := "UNREGISTERED";
register_aclr : string := "NONE";
port_sign : string := "PORT_UNUSED";
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_sign_ext_output: vl_notype;
width_sign_ext_output_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
sign : in vl_logic;
data_in : in vl_logic_vector;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of register_clock : constant is 1;
attribute mti_svvh_generic_type of register_aclr : constant is 1;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_sign_ext_output : constant is 3;
attribute mti_svvh_generic_type of width_sign_ext_output_msb : constant is 3;
end ama_register_with_ext_function;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_AROUND.vhd | 20 | 2588 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_AROUND.vhd | 20 | 2588 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_vcc.vhd | 20 | 747 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_constant_GNNCFWNIJI.vhd | 4 | 576 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNCFWNIJI is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000000100";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNCFWNIJI is
Begin
-- Constant
output <= "0000000000000100";
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_bus_concat_GNIIOZRPJD.vhd | 12 | 653 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic ( widthB : natural := 8;
widthA : natural := 8);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNIIOZRPJD is
Begin
output <= a & b;
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/reports/Test_Pattern_Generator/Test_Pattern_Generator_example.vhd | 1 | 1771 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Test_Pattern_Generator_example is
port(
Avalon_ST_Source_startofpacket : out STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Clock : in STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_MM_Slave_write : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Source_endofpacket : out STD_LOGIC);
end entity;
architecture rtl of Test_Pattern_Generator_example is
component Test_Pattern_Generator
port(
Avalon_ST_Source_startofpacket : out STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Clock : in STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_MM_Slave_write : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Source_endofpacket : out STD_LOGIC);
end component;
begin
Test_Pattern_Generator_instance :
component Test_Pattern_Generator
port map(
Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket,
Avalon_MM_Slave_address => Avalon_MM_Slave_address,
Avalon_ST_Source_valid => Avalon_ST_Source_valid,
Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata,
Clock => Clock,
Avalon_ST_Source_ready => Avalon_ST_Source_ready,
aclr => aclr,
Avalon_MM_Slave_write => Avalon_MM_Slave_write,
Avalon_ST_Source_data => Avalon_ST_Source_data,
Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket);
end architecture rtl;
| mit |
Bourgeoisie/ECE368-RISC16 | 368RISC/ipcore_dir/tmp/_cg/Instruct_Memory/simulation/bmg_stim_gen.vhd | 2 | 12278 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((5 <= 5),WR_RD_DEEP_COUNT,
((16/16)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((5 <= 5),WR_RD_DEEP_COUNT,
((16/16)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(4 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(4 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16 ,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_testbench_capture_GNHCRI5YMO.vhd | 20 | 1775 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNHCRI5YMO is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNHCRI5YMO is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/altera_lnsim/dprio_init/_primary.vhd | 5 | 627 | library verilog;
use verilog.vl_types.all;
entity dprio_init is
port(
clk : in vl_logic;
reset_n : in vl_logic;
dprio_address : out vl_logic_vector(5 downto 0);
dprio_byteen : out vl_logic_vector(1 downto 0);
dprio_write : out vl_logic;
dprio_writedata : out vl_logic_vector(15 downto 0);
atpgmode : out vl_logic;
mdio_dis : out vl_logic;
scanen : out vl_logic;
ser_shift_load : out vl_logic;
dprio_init_done : out vl_logic
);
end dprio_init;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_cast_GN33BXJAZX.vhd | 4 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN33BXJAZX is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN33BXJAZX is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 + 1 ,
width_inr=> 0,
width_outl=> 2,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_cast_GNKIWLRTQI.vhd | 4 | 879 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNKIWLRTQI is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(47 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNKIWLRTQI is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 48 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(47 downto 0) => input,
xin(48) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_constant.vhd | 10 | 649 | -- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_constant is
end entity alt_dspbuilder_constant;
architecture rtl of alt_dspbuilder_constant is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_cast_GNTS3MQUMJ.vhd | 4 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNTS3MQUMJ is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNTS3MQUMJ is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 12 + 1 ,
width_inr=> 4,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(15 downto 0) => input,
xin(16) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/altera_lnsim/ama_latency_function/_primary.vhd | 5 | 1256 | library verilog;
use verilog.vl_types.all;
entity ama_latency_function is
generic(
width_data_in : integer := 1;
width_data_out : integer := 1;
latency : integer := 0;
latency_clock : string := "UNREGISTERED";
latency_aclr : string := "NONE";
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
data_in : in vl_logic_vector;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 1;
attribute mti_svvh_generic_type of latency : constant is 1;
attribute mti_svvh_generic_type of latency_clock : constant is 1;
attribute mti_svvh_generic_type of latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
end ama_latency_function;
| mit |
Bourgeoisie/ECE368-RISC16 | 368RISC/ipcore_dir/tmp/_cg/Instruct_Memory/simulation/Instruct_Memory_tb.vhd | 2 | 4559 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Instruct_Memory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Instruct_Memory_tb IS
END ENTITY;
ARCHITECTURE Instruct_Memory_tb_ARCH OF Instruct_Memory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Instruct_Memory_synth_inst:ENTITY work.Instruct_Memory_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_cast_GN5VN2FCXZ.vhd | 4 | 876 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN5VN2FCXZ is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN5VN2FCXZ is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 8 + 1 ,
width_inr=> 8,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(15 downto 0) => input,
xin(16) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_if_statement_GNZR777PB6.vhd | 4 | 1487 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNZR777PB6 is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "((a>b) or (a=b)) and (a<c)";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNZR777PB6 is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(((a>b) or (a=b)) and (a<c)) ;
true <= result;
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_clock_GNF343OQUJ.vhd | 16 | 576 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/altera_lnsim/ama_accumulator_function/_primary.vhd | 5 | 2278 | library verilog;
use verilog.vl_types.all;
entity ama_accumulator_function is
generic(
width_result : integer := 1;
accumulator : string := "NO";
accum_direction : string := "ADD";
loadconst_value : integer := 0;
accum_sload_register: string := "UNREGISTERED";
accum_sload_aclr: string := "NONE";
double_accum : string := "NO";
use_sload_accum_port: string := "NO";
output_register : string := "UNREGISTERED";
output_aclr : string := "NONE";
latency : integer := 0;
accum_sload_latency_clock: string := "UNREGISTERED";
accum_sload_latency_aclr: string := "NONE";
width_result_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
accum_sload : in vl_logic;
sload_accum : in vl_logic;
data_result : in vl_logic_vector;
prev_result : in vl_logic_vector;
result : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_result : constant is 1;
attribute mti_svvh_generic_type of accumulator : constant is 1;
attribute mti_svvh_generic_type of accum_direction : constant is 1;
attribute mti_svvh_generic_type of loadconst_value : constant is 1;
attribute mti_svvh_generic_type of accum_sload_register : constant is 1;
attribute mti_svvh_generic_type of accum_sload_aclr : constant is 1;
attribute mti_svvh_generic_type of double_accum : constant is 1;
attribute mti_svvh_generic_type of use_sload_accum_port : constant is 1;
attribute mti_svvh_generic_type of output_register : constant is 1;
attribute mti_svvh_generic_type of output_aclr : constant is 1;
attribute mti_svvh_generic_type of latency : constant is 1;
attribute mti_svvh_generic_type of accum_sload_latency_clock : constant is 1;
attribute mti_svvh_generic_type of accum_sload_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_result_msb : constant is 3;
end ama_accumulator_function;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Benchy/sync.vhd | 13 | 3382 | ----------------------------------------------------------------------------------
-- sync.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Synchronizes la_input with clock on rising or falling edge and does some
-- optional preprocessing. (Noise filter and demux.)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync is
port(
la_input : in std_logic_vector (31 downto 0);
clock : in std_logic;
enableFilter : in std_logic;
enableDemux : in std_logic;
falling : in std_logic;
output : out std_logic_vector (31 downto 0)
);
end sync;
architecture behavioral of sync is
component demux
port(
la_input : in std_logic_vector(15 downto 0);
la_input180 : in std_logic_vector(15 downto 0);
clock : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end component;
component filter
port(
la_input : in std_logic_vector(31 downto 0);
la_input180 : in std_logic_vector(31 downto 0);
clock : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end component;
attribute equivalent_register_removal : string;
signal filteredla_input, demuxedla_input, synchronizedla_input, synchronizedla_input180: std_logic_vector (31 downto 0);
attribute equivalent_register_removal of demuxedla_input : signal is "no";
begin
Inst_demux: demux
port map(
la_input => synchronizedla_input(15 downto 0),
la_input180 => synchronizedla_input180(15 downto 0),
clock => clock,
output => demuxedla_input
);
Inst_filter: filter
port map(
la_input => synchronizedla_input,
la_input180 => synchronizedla_input180,
clock => clock,
output => filteredla_input
);
-- synch la_input guarantees use of iob ff on spartan 3 (as filter and demux do)
process (clock)
begin
if rising_edge(clock) then
synchronizedla_input <= la_input;
end if;
if falling_edge(clock) then
synchronizedla_input180 <= la_input;
end if;
end process;
-- add another pipeline step for la_input selector to not decrease maximum clock rate
process (clock)
begin
if rising_edge(clock) then
if enableDemux = '1' then
output <= demuxedla_input;
else
if enableFilter = '1' then
output <= filteredla_input;
else
if falling = '1' then
output <= synchronizedla_input180;
else
output <= synchronizedla_input;
end if;
end if;
end if;
end if;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Benchy/sync.vhd | 13 | 3382 | ----------------------------------------------------------------------------------
-- sync.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Synchronizes la_input with clock on rising or falling edge and does some
-- optional preprocessing. (Noise filter and demux.)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync is
port(
la_input : in std_logic_vector (31 downto 0);
clock : in std_logic;
enableFilter : in std_logic;
enableDemux : in std_logic;
falling : in std_logic;
output : out std_logic_vector (31 downto 0)
);
end sync;
architecture behavioral of sync is
component demux
port(
la_input : in std_logic_vector(15 downto 0);
la_input180 : in std_logic_vector(15 downto 0);
clock : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end component;
component filter
port(
la_input : in std_logic_vector(31 downto 0);
la_input180 : in std_logic_vector(31 downto 0);
clock : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end component;
attribute equivalent_register_removal : string;
signal filteredla_input, demuxedla_input, synchronizedla_input, synchronizedla_input180: std_logic_vector (31 downto 0);
attribute equivalent_register_removal of demuxedla_input : signal is "no";
begin
Inst_demux: demux
port map(
la_input => synchronizedla_input(15 downto 0),
la_input180 => synchronizedla_input180(15 downto 0),
clock => clock,
output => demuxedla_input
);
Inst_filter: filter
port map(
la_input => synchronizedla_input,
la_input180 => synchronizedla_input180,
clock => clock,
output => filteredla_input
);
-- synch la_input guarantees use of iob ff on spartan 3 (as filter and demux do)
process (clock)
begin
if rising_edge(clock) then
synchronizedla_input <= la_input;
end if;
if falling_edge(clock) then
synchronizedla_input180 <= la_input;
end if;
end process;
-- add another pipeline step for la_input selector to not decrease maximum clock rate
process (clock)
begin
if rising_edge(clock) then
if enableDemux = '1' then
output <= demuxedla_input;
else
if enableFilter = '1' then
output <= filteredla_input;
else
if falling = '1' then
output <= synchronizedla_input180;
else
output <= synchronizedla_input;
end if;
end if;
end if;
end if;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Benchy/sync.vhd | 13 | 3382 | ----------------------------------------------------------------------------------
-- sync.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Synchronizes la_input with clock on rising or falling edge and does some
-- optional preprocessing. (Noise filter and demux.)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync is
port(
la_input : in std_logic_vector (31 downto 0);
clock : in std_logic;
enableFilter : in std_logic;
enableDemux : in std_logic;
falling : in std_logic;
output : out std_logic_vector (31 downto 0)
);
end sync;
architecture behavioral of sync is
component demux
port(
la_input : in std_logic_vector(15 downto 0);
la_input180 : in std_logic_vector(15 downto 0);
clock : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end component;
component filter
port(
la_input : in std_logic_vector(31 downto 0);
la_input180 : in std_logic_vector(31 downto 0);
clock : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end component;
attribute equivalent_register_removal : string;
signal filteredla_input, demuxedla_input, synchronizedla_input, synchronizedla_input180: std_logic_vector (31 downto 0);
attribute equivalent_register_removal of demuxedla_input : signal is "no";
begin
Inst_demux: demux
port map(
la_input => synchronizedla_input(15 downto 0),
la_input180 => synchronizedla_input180(15 downto 0),
clock => clock,
output => demuxedla_input
);
Inst_filter: filter
port map(
la_input => synchronizedla_input,
la_input180 => synchronizedla_input180,
clock => clock,
output => filteredla_input
);
-- synch la_input guarantees use of iob ff on spartan 3 (as filter and demux do)
process (clock)
begin
if rising_edge(clock) then
synchronizedla_input <= la_input;
end if;
if falling_edge(clock) then
synchronizedla_input180 <= la_input;
end if;
end process;
-- add another pipeline step for la_input selector to not decrease maximum clock rate
process (clock)
begin
if rising_edge(clock) then
if enableDemux = '1' then
output <= demuxedla_input;
else
if enableFilter = '1' then
output <= filteredla_input;
else
if falling = '1' then
output <= synchronizedla_input180;
else
output <= synchronizedla_input;
end if;
end if;
end if;
end if;
end process;
end behavioral;
| mit |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.c-execute.vhd | 1 | 8465 | library ieee;
use ieee.std_logic_1164.all;
-- Units present in this block (refer to DP schematic):
-- adder1
-- adder2
-- jreg_mux21
-- concatenate16
-- oprnd1_mux41
-- oprnd2_mux41
-- regaddr_mux21
-- forwarding unit
-- alusrc_mux21
-- ALU
-- plus4_adder
-- branch_circ
-- PSW
-- link_mux21
-- lhi_mux21
-- movs2i_mux21
entity execute is
port(
clk : in std_logic;
rst : in std_logic;
-- inputs from IDEX pipeline reg
controls_in : in std_logic_vector(21 downto 0); -- we have 22 signals: CU generates a total of 23 signals (including 5 ALUOP signals), but 1 signal (unsigned) is already exhausted in the DECODE stage
ext25_0 : in std_logic_vector(31 downto 0); -- bits 25_0 of instr. sign/unsign extended to 32 bits
nextPC : in std_logic_vector(31 downto 0);
op_A : in std_logic_vector(31 downto 0);
op_B : in std_logic_vector(31 downto 0);
ext15_0 : in std_logic_vector(31 downto 0); -- bits 15_0 of instr. sign/unsign extended to 32 bits
inst15_0 : in std_logic_vector(15 downto 0); -- bits 15_0 of instr.
rt_inst : in std_logic_vector(4 downto 0);
rd_inst : in std_logic_vector(4 downto 0);
rs_inst : in std_logic_vector(4 downto 0);
-- inputs from other sources
unaligned : in std_logic; -- from MMU, '1' when an unaligned access to memory has been done
forw_dataWB : in std_logic_vector(31 downto 0); -- data from WB stage that is used if forwarding needed
forw_dataMEM : in std_logic_vector(31 downto 0); -- data from MEM stage that is used if forwarding needed
RFaddr_WB : in std_logic_vector(4 downto 0); -- addr of RF from WB stage, goes to forwarding unit
RFaddr_MEM : in std_logic_vector(4 downto 0); -- addr of RF from MEM stage, goes to forwarding unit
regwriteWB : in std_logic; -- reg_write ctrl signal from WB stage
regwriteMEM : in std_logic; -- reg_write ctrl signal from MEM stage
-- outputs
controls_out : out std_logic_vector(10 downto 0); -- 11 control signals go to MEM stage (11 are exhausted in the EXE stage)
toPC1 : out std_logic_vector(31 downto 0);
toPC2 : out std_logic_vector(31 downto 0);
branchTaken : out std_logic;
addrMem : out std_logic_vector(31 downto 0);
writeData : out std_logic_vector(31 downto 0);
addrRF : out std_logic_vector(4 downto 0);
IDEX_rt : out std_logic_vector(4 downto 0); -- goes to hazard unit
IDEX_memread : out std_logic_vector(3 downto 0) -- goes to hazard unit
);
end execute;
architecture rtl of execute is
-- component declarations
component adder is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
res : out std_logic_vector(31 downto 0)
);
end component;
component ALU is
port(
-- inputs
alu_op : in std_logic_vector(4 downto 0); -- specifies alu operation to be performed (from CU in ID stage)
a : in std_logic_vector(31 downto 0); -- operand 1
b : in std_logic_vector(31 downto 0); -- operand 2
-- outputs
-- cout : out std_logic; -- cout of operation; to PSW
ovf : out std_logic; -- ovf of operation; to PSW
zero : out std_logic; -- zero when res is all 0s; to branch_circ
res : out std_logic_vector(31 downto 0) -- result of the arit-log operation on a and b
);
end component;
component branch_circ is
port(
branch_type : in std_logic; -- BNEZ is branch_type = '1', BEQZ is branch_type = '0'
zero : in std_logic; -- from ALU, 1 when the result of an operation yields zero
branch_taken : out std_logic -- 1 means the branch has to be taken
);
end component;
component concat16 is
port(
string16 : in std_logic_vector(15 downto 0);
string32 : out std_logic_vector(31 downto 0) -- this goes to lhi_mux21
);
end component;
component forward is
port(
rt_addr_IDEX : in std_logic_vector(4 downto 0);
rs_addr_IDEX : in std_logic_vector(4 downto 0);
rd_addr_EXMEM : in std_logic_vector(4 downto 0);
rd_addr_MEMWB : in std_logic_vector(4 downto 0);
regwrite_EXMEM : in std_logic;
regwrite_MEMWB : in std_logic;
forwardA : out std_logic_vector(1 downto 0); -- 00 from regfile, 01 from memwb, 10 from previous alu result
forwardB : out std_logic_vector(1 downto 0) -- as above
);
end component;
component mux21 is
generic(
NBIT : integer := 32
);
port (
a : in std_logic_vector(NBIT - 1 downto 0);
b : in std_logic_vector(NBIT - 1 downto 0);
s : in std_logic;
y : out std_logic_vector(NBIT - 1 downto 0)
);
end component;
component mux41 is
generic(
NBIT : integer := 32
);
port (
a : in std_logic_vector(NBIT - 1 downto 0);
b : in std_logic_vector(NBIT - 1 downto 0);
c : in std_logic_vector(NBIT - 1 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic_vector(NBIT - 1 downto 0)
);
end component;
component PSWreg is
port(
-- inputs
rst : in std_logic;
clk : in std_logic;
unaligned : in std_logic;
-- cout : in std_logic;
ovf : in std_logic;
-- outputs
status : out std_logic_vector(31 downto 0)
);
end component;
--signal declarations
signal lhi_value_i : std_logic_vector(31 downto 0); -- inst15_0 ## 0...0 for lhi instruction
signal zero_i : std_logic; -- driven by ALU: '0' when result of ALU operation is all 0s
signal psw_status_i : std_logic_vector(31 downto 0); -- content of PSW reg
signal ovf_i : std_logic; -- driven by ALU: '1' when operation had overflow
signal A_inALU_i : std_logic_vector(31 downto 0);
signal B_inALU_i : std_logic_vector(31 downto 0);
signal res_outALU_i : std_logic_vector(31 downto 0);
signal resAdd1_i : std_logic_vector(31 downto 0);
signal link_value_i : std_logic_vector(31 downto 0);
signal link2lhi_wire_i : std_logic_vector(31 downto 0); -- goes from link mux to lhi mux
signal lhi2mov_wire_i : std_logic_vector(31 downto 0); -- goes from lhi mux to movs2i mux
signal mux41B_wire_i : std_logic_vector(31 downto 0); -- goes from oprnd2_mux41 to alusrc_mux
signal forwardA_i : std_logic_vector(1 downto 0);
signal forwardB_i : std_logic_vector(1 downto 0);
begin
-- concurrent signal assignments
controls_out <= controls_in(21) & controls_in(18) & controls_in (13 downto 5); --- regwrite, link, sb, sw, lbu, lw, lhu, lb, memtoreg, jump, branch
writeData <= mux41B_wire_i; -- data that goes into Data Ram for writing
IDEX_rt <= rt_inst;
IDEX_memread <= controls_in(11 downto 8);
--component instantiations
adder1 : adder port map (ext25_0, nextPC, resAdd1_i);
adder2 : adder port map (nextPC, ext15_0, toPC2);
plus4_adder : adder port map(nextPC, X"00000004", link_value_i);
jreg_mux21 : mux21 generic map (32) port map (A_inALU_i, resAdd1_i, controls_in(20),toPC1);
link_mux21 : mux21 generic map (32) port map (link_value_i, res_outALU_i, controls_in(18), link2lhi_wire_i);
lhi_mux21 : mux21 generic map (32) port map (lhi_value_i, link2lhi_wire_i,controls_in(17), lhi2mov_wire_i);
regaddr_mux21 : mux21 generic map (5) port map (rd_inst, rt_inst, controls_in(16), addrRF);
movs2i_mux21 : mux21 generic map (32) port map (psw_status_i, lhi2mov_wire_i, controls_in(15), addrMem);
alusrc_mux21 : mux21 generic map (32) port map (ext15_0, mux41B_wire_i, controls_in(14), B_inALU_i);
oprnd1_mux41 : mux41 generic map (32) port map (op_A, forw_dataWB, forw_dataMEM, forwardA_i, A_inALU_i);
oprnd2_mux41 : mux41 generic map (32) port map (op_B, forw_dataWB, forw_dataMEM, forwardB_i, mux41B_wire_i);
concatenate16 : concat16 port map (inst15_0, lhi_value_i);
forwarding_unit : forward port map (rt_inst, rs_inst, RFaddr_MEM, RFaddr_WB, regwriteMEM, regwriteWB, forwardA_i, forwardB_i);
branch_circuit : branch_circ port map (controls_in(19), zero_i, branchTaken);
PSW : PSWreg port map (rst, clk, unaligned, ovf_i, psw_status_i);
EXALU : ALU port map (controls_in(4 downto 0), A_inALU_i, B_inALU_i, ovf_i, zero_i, res_outALU_i);
end rtl;
| mit |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/clkgen.vhd | 1 | 6857 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
clk_1Mhz_out: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_ulogic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_ulogic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic := '1';
signal rst2_q: std_logic := '1';
signal clkout_i: std_ulogic;
signal clkin_i: std_ulogic;
signal clkfb: std_ulogic;
signal clk0: std_ulogic;
signal clk1: std_ulogic;
signal clk2: std_ulogic;
signal clkin_i_2: std_logic;
-- signal clk_div: std_logic;
-- signal count: integer;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clkout <= clkout_i;
rstout <= rst1_q;
--process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
process(dcmlocked, clkout_i, rstin)
begin
--if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
if dcmlocked='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => clk0,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
clkfb_inst: BUFG
port map (
I=> dcmclock,
O=> clkfb
);
clk1_inst: BUFG port map ( I => clk1, O => clkout1 );
clk2_inst: BUFG port map ( I => clk2, O => clkout2 );
pll_base_inst : PLL_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 250.0,--300.0,--155.52,--103.700,--343.125,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 10,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 31.250,
REF_JITTER => 0.010,
SIM_DEVICE => "SPARTAN6")
port map
-- Output clocks
(CLKFBOUT => dcmclock,
CLKOUT0 => clk0,
CLKOUT1 => clk1,
CLKOUT2 => clk2,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => dcmlocked,
RST => '0',
-- Input clock control
CLKFBIN => clkfb,
CLKIN1 => clkin_i,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0'
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clk_1Mhz_out
);
clkin_i_1mhz <= clkout_i;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/fifo.vhd | 14 | 3063 | --
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/fifo.vhd | 14 | 3063 | --
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/ZPUino_1/fifo.vhd | 14 | 3063 | --
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/waveform_gen.vhd | 13 | 4463 | ----------------------------------------------------------------------
-- --
-- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE --
-- --
----------------------------------------------------------------------
-- --
-- Filename : waveform_gen.vhd --
-- --
-- Author : Simon Doherty --
-- Senior Design Consultant --
-- www.zipcores.com --
-- --
-- Date last modified : 23.10.2008 --
-- --
-- Description : NCO / Periodic Waveform Generator --
-- --
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity waveform_gen is
port (
-- system signals
clk : in std_logic;
reset : in std_logic;
-- NCO frequency control
phase_inc : in std_logic_vector(31 downto 0);
-- Output waveforms
sin_out : out std_logic_vector(11 downto 0);
cos_out : out std_logic_vector(11 downto 0);
squ_out : out std_logic_vector(11 downto 0);
saw_out : out std_logic_vector(11 downto 0) );
end entity;
architecture rtl of waveform_gen is
component sincos_lut
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
sin_out : out std_logic_vector(11 downto 0);
cos_out : out std_logic_vector(11 downto 0));
end component;
signal phase_acc : std_logic_vector(31 downto 0);
signal lut_addr : std_logic_vector(11 downto 0);
signal lut_addr_reg : std_logic_vector(11 downto 0);
signal sin_out_reg : std_logic_vector(11 downto 0);
begin
--------------------------------------------------------------------------
-- Phase accumulator increments by 'phase_inc' every clock cycle --
-- Output frequency determined by formula: Phase_inc = (Fout/Fclk)*2^32 --
-- E.g. Fout = 36MHz, Fclk = 100MHz, Phase_inc = 36*2^32/100 --
-- Frequency resolution is 100MHz/2^32 = 0.00233Hz --
--------------------------------------------------------------------------
phase_acc_reg: process(clk, reset)
begin
if reset = '0' then
phase_acc <= (others => '0');
elsif clk'event and clk = '1' then
phase_acc <= unsigned(phase_acc) + unsigned(phase_inc);
-- sin_out <= signed(sin_out_reg) + 2047; --Modified to make it unsigned - jpg 10/6/2011
end if;
end process phase_acc_reg;
---------------------------------------------------------------------
-- use top 12-bits of phase accumulator to address the SIN/COS LUT --
---------------------------------------------------------------------
lut_addr <= phase_acc(31 downto 20);
----------------------------------------------------------------------
-- SIN/COS LUT is 4096 by 12-bit ROM --
-- 12-bit output allows sin/cos amplitudes between 2047 and -2047 --
-- (-2048 not used to keep the output signal perfectly symmetrical) --
-- Phase resolution is 2Pi/4096 = 0.088 degrees --
----------------------------------------------------------------------
lut: sincos_lut
port map (
clk => clk,
addr => lut_addr,
sin_out => sin_out,
cos_out => cos_out );
---------------------------------
-- Hide the latency of the LUT --
---------------------------------
delay_regs: process(clk)
begin
if clk'event and clk = '1' then
lut_addr_reg <= lut_addr;
end if;
end process delay_regs;
---------------------------------------------
-- Square output is msb of the accumulator --
---------------------------------------------
squ_out <= "011111111111" when lut_addr_reg(11) = '1' else "100000000000";
-------------------------------------------------------
-- Sawtooth output is top 12-bits of the accumulator --
-------------------------------------------------------
saw_out <= lut_addr_reg;
end rtl; | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals/waveform_gen.vhd | 13 | 4463 | ----------------------------------------------------------------------
-- --
-- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE --
-- --
----------------------------------------------------------------------
-- --
-- Filename : waveform_gen.vhd --
-- --
-- Author : Simon Doherty --
-- Senior Design Consultant --
-- www.zipcores.com --
-- --
-- Date last modified : 23.10.2008 --
-- --
-- Description : NCO / Periodic Waveform Generator --
-- --
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity waveform_gen is
port (
-- system signals
clk : in std_logic;
reset : in std_logic;
-- NCO frequency control
phase_inc : in std_logic_vector(31 downto 0);
-- Output waveforms
sin_out : out std_logic_vector(11 downto 0);
cos_out : out std_logic_vector(11 downto 0);
squ_out : out std_logic_vector(11 downto 0);
saw_out : out std_logic_vector(11 downto 0) );
end entity;
architecture rtl of waveform_gen is
component sincos_lut
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
sin_out : out std_logic_vector(11 downto 0);
cos_out : out std_logic_vector(11 downto 0));
end component;
signal phase_acc : std_logic_vector(31 downto 0);
signal lut_addr : std_logic_vector(11 downto 0);
signal lut_addr_reg : std_logic_vector(11 downto 0);
signal sin_out_reg : std_logic_vector(11 downto 0);
begin
--------------------------------------------------------------------------
-- Phase accumulator increments by 'phase_inc' every clock cycle --
-- Output frequency determined by formula: Phase_inc = (Fout/Fclk)*2^32 --
-- E.g. Fout = 36MHz, Fclk = 100MHz, Phase_inc = 36*2^32/100 --
-- Frequency resolution is 100MHz/2^32 = 0.00233Hz --
--------------------------------------------------------------------------
phase_acc_reg: process(clk, reset)
begin
if reset = '0' then
phase_acc <= (others => '0');
elsif clk'event and clk = '1' then
phase_acc <= unsigned(phase_acc) + unsigned(phase_inc);
-- sin_out <= signed(sin_out_reg) + 2047; --Modified to make it unsigned - jpg 10/6/2011
end if;
end process phase_acc_reg;
---------------------------------------------------------------------
-- use top 12-bits of phase accumulator to address the SIN/COS LUT --
---------------------------------------------------------------------
lut_addr <= phase_acc(31 downto 20);
----------------------------------------------------------------------
-- SIN/COS LUT is 4096 by 12-bit ROM --
-- 12-bit output allows sin/cos amplitudes between 2047 and -2047 --
-- (-2048 not used to keep the output signal perfectly symmetrical) --
-- Phase resolution is 2Pi/4096 = 0.088 degrees --
----------------------------------------------------------------------
lut: sincos_lut
port map (
clk => clk,
addr => lut_addr,
sin_out => sin_out,
cos_out => cos_out );
---------------------------------
-- Hide the latency of the LUT --
---------------------------------
delay_regs: process(clk)
begin
if clk'event and clk = '1' then
lut_addr_reg <= lut_addr;
end if;
end process delay_regs;
---------------------------------------------
-- Square output is msb of the accumulator --
---------------------------------------------
squ_out <= "011111111111" when lut_addr_reg(11) = '1' else "100000000000";
-------------------------------------------------------
-- Sawtooth output is top 12-bits of the accumulator --
-------------------------------------------------------
saw_out <= lut_addr_reg;
end rtl; | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Benchy/rle_fmt.vhd | 13 | 3532 | ---------------------------------------------------------------------------------
-- rle_fmt.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- inserts a zero count when the rle bit is not set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle_fmt is
generic(
data_width : integer := 32
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end rle_fmt;
architecture behavioral of rle_fmt is
type state_type is (S0, S1, S2, S3, S4);
signal state, nstate : state_type;
signal tmp, tmp_r, fmt_out_i, fmt_out_r : std_logic_vector ((data_width-1) downto 0);
signal busy_i, rle_ready_i : std_logic;
begin
fmt_out <= fmt_out_i;
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state <= S0;
else
state <= nstate;
tmp_r <= tmp;
busy <= busy_i;
fmt_out_r <= fmt_out_i;
rle_ready <= rle_ready_i;
end if;
end if;
end process;
busy_i <= '1' when state = S4 else '0';
process(state, rle_inp_valid, raw_ready, rle_inp, tmp, tmp_r, fmt_out_r)
begin
case state is
when S0 =>
if rle_inp_valid = '1' then
nstate <= S1;
else
nstate <= state;
end if;
fmt_out_i <= fmt_out_r;
tmp <= tmp_r;
rle_ready_i <= '0';
when S1 =>
if raw_ready = '1' then
if rle_inp(data_width) = '1' then
nstate <= S2;
fmt_out_i <= rle_inp((data_width - 1) downto 0);
else
nstate <= S4;
fmt_out_i <= (others => '0');
end if;
else
nstate <= state;
fmt_out_i <= fmt_out_r;
end if;
tmp <= rle_inp((data_width - 1) downto 0);
rle_ready_i <= raw_ready;
when S2 => -- send RLE data
if rle_inp_valid = '1' then
nstate <= S3;
else
nstate <= state;
end if;
fmt_out_i <= rle_inp((data_width - 1) downto 0);
tmp <= tmp_r;
rle_ready_i <= '0';
when S3 =>
if raw_ready = '1' then
nstate <= S0;
else
nstate <= state;
end if;
fmt_out_i <= rle_inp((data_width - 1) downto 0);
tmp <= tmp_r;
rle_ready_i <= raw_ready;
when S4 => -- send RLE data, counts = 0
if rle_inp_valid = '1' then
nstate <= S0;
fmt_out_i <= tmp;
else
nstate <= state;
fmt_out_i <= fmt_out_r;
end if;
tmp <= tmp_r;
rle_ready_i <= rle_inp_valid;
end case;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Benchy/rle_fmt.vhd | 13 | 3532 | ---------------------------------------------------------------------------------
-- rle_fmt.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- inserts a zero count when the rle bit is not set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle_fmt is
generic(
data_width : integer := 32
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end rle_fmt;
architecture behavioral of rle_fmt is
type state_type is (S0, S1, S2, S3, S4);
signal state, nstate : state_type;
signal tmp, tmp_r, fmt_out_i, fmt_out_r : std_logic_vector ((data_width-1) downto 0);
signal busy_i, rle_ready_i : std_logic;
begin
fmt_out <= fmt_out_i;
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state <= S0;
else
state <= nstate;
tmp_r <= tmp;
busy <= busy_i;
fmt_out_r <= fmt_out_i;
rle_ready <= rle_ready_i;
end if;
end if;
end process;
busy_i <= '1' when state = S4 else '0';
process(state, rle_inp_valid, raw_ready, rle_inp, tmp, tmp_r, fmt_out_r)
begin
case state is
when S0 =>
if rle_inp_valid = '1' then
nstate <= S1;
else
nstate <= state;
end if;
fmt_out_i <= fmt_out_r;
tmp <= tmp_r;
rle_ready_i <= '0';
when S1 =>
if raw_ready = '1' then
if rle_inp(data_width) = '1' then
nstate <= S2;
fmt_out_i <= rle_inp((data_width - 1) downto 0);
else
nstate <= S4;
fmt_out_i <= (others => '0');
end if;
else
nstate <= state;
fmt_out_i <= fmt_out_r;
end if;
tmp <= rle_inp((data_width - 1) downto 0);
rle_ready_i <= raw_ready;
when S2 => -- send RLE data
if rle_inp_valid = '1' then
nstate <= S3;
else
nstate <= state;
end if;
fmt_out_i <= rle_inp((data_width - 1) downto 0);
tmp <= tmp_r;
rle_ready_i <= '0';
when S3 =>
if raw_ready = '1' then
nstate <= S0;
else
nstate <= state;
end if;
fmt_out_i <= rle_inp((data_width - 1) downto 0);
tmp <= tmp_r;
rle_ready_i <= raw_ready;
when S4 => -- send RLE data, counts = 0
if rle_inp_valid = '1' then
nstate <= S0;
fmt_out_i <= tmp;
else
nstate <= state;
fmt_out_i <= fmt_out_r;
end if;
tmp <= tmp_r;
rle_ready_i <= rle_inp_valid;
end case;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/board_Papilio_Pro/prom-generic-dp-32.vhd | 13 | 200723 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity prom_generic_dualport is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(14 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(14 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end entity prom_generic_dualport;
architecture behave of prom_generic_dualport is
subtype RAM_WORD is STD_LOGIC_VECTOR (7 downto 0);
type RAM_TABLE is array (0 to 8191) of RAM_WORD;
shared variable RAM0: RAM_TABLE := RAM_TABLE'(
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shared variable RAM1: RAM_TABLE := RAM_TABLE'(
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shared variable RAM2: RAM_TABLE := RAM_TABLE'(
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shared variable RAM3: RAM_TABLE := RAM_TABLE'(
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signal rwea: std_logic_vector(3 downto 0);
signal rweb: std_logic_vector(3 downto 0);
signal memaread0: std_logic_vector(7 downto 0);
signal membread0: std_logic_vector(7 downto 0);
signal memaread1: std_logic_vector(7 downto 0);
signal membread1: std_logic_vector(7 downto 0);
signal memaread2: std_logic_vector(7 downto 0);
signal membread2: std_logic_vector(7 downto 0);
signal memaread3: std_logic_vector(7 downto 0);
signal membread3: std_logic_vector(7 downto 0);
begin
rwea(0) <= WEA and MASKA(0);
rweb(0) <= WEB and MASKB(0);
rwea(1) <= WEA and MASKA(1);
rweb(1) <= WEB and MASKB(1);
rwea(2) <= WEA and MASKA(2);
rweb(2) <= WEB and MASKB(2);
rwea(3) <= WEA and MASKA(3);
rweb(3) <= WEB and MASKB(3);
DOA(7 downto 0) <= memaread0;
DOB(7 downto 0) <= membread0;
DOA(15 downto 8) <= memaread1;
DOB(15 downto 8) <= membread1;
DOA(23 downto 16) <= memaread2;
DOB(23 downto 16) <= membread2;
DOA(31 downto 24) <= memaread3;
DOB(31 downto 24) <= membread3;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(0)='1' then
RAM0( conv_integer(ADDRA) ) := DIA(7 downto 0);
end if;
memaread0 <= RAM0(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(0)='1' then
RAM0( conv_integer(ADDRB) ) := DIB(7 downto 0);
end if;
membread0 <= RAM0(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(1)='1' then
RAM1( conv_integer(ADDRA) ) := DIA(15 downto 8);
end if;
memaread1 <= RAM1(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(1)='1' then
RAM1( conv_integer(ADDRB) ) := DIB(15 downto 8);
end if;
membread1 <= RAM1(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(2)='1' then
RAM2( conv_integer(ADDRA) ) := DIA(23 downto 16);
end if;
memaread2 <= RAM2(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(2)='1' then
RAM2( conv_integer(ADDRB) ) := DIB(23 downto 16);
end if;
membread2 <= RAM2(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(3)='1' then
RAM3( conv_integer(ADDRA) ) := DIA(31 downto 24);
end if;
memaread3 <= RAM3(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(3)='1' then
RAM3( conv_integer(ADDRB) ) := DIB(31 downto 24);
end if;
membread3 <= RAM3(conv_integer(ADDRB)) ;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Benchy/rle_enc.vhd | 13 | 3072 | ----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle_enc is
generic(
data_width : integer := 32
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end rle_enc;
architecture behavioral of rle_enc is
signal count, data, rle_out_i : std_logic_vector ((data_width-1) downto 0);
signal c0, c1, c2, c3, valid, rle : std_logic;
signal state : std_logic_vector(3 downto 0);
begin
-- count repeating data
process(clock)
begin
if rising_edge(clock) then
if raw_inp_valid = '1' then
if data = raw_inp then
count <= count + 1;
else
data <= raw_inp;
count <= (others => '0');
end if;
end if;
end if;
end process;
-- previous and current data is not the same; send old data
c0 <= '1' when data /= raw_inp and count = 0 else '0';
-- start of repeating data; send current data
c1 <= '1' when data = raw_inp and count = 0 else '0';
-- end of repeating data; send count
c2 <= '1' when data /= raw_inp and count /= 0 else '0';
-- count overflow; send count
c3 <= '1' when data = raw_inp and 0 = not count else '0';
state <= c3 & c2 & c1 & c0;
rle_out_i <=
data when state = "0001" else
data when state = "0010" else
count when state = "0100" else
count when state = "1000" else
(others => 'X');
valid <=
'1' when state = "0001" else
'1' when state = "0010" else
'1' when state = "0100" else
'1' when state = "1000" else
'0';
rle <=
'1' when state = "0100" else
'1' when state = "1000" else
'0';
process(clock)
begin
if rising_edge(clock) then
if raw_inp_valid = '1' then
rle_out <= rle_out_i;
rle_out_valid <= valid;
rle_bit <= rle;
else
rle_out_valid <= '0';
rle_bit <= '0';
end if;
end if;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Benchy/rle_enc.vhd | 13 | 3072 | ----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle_enc is
generic(
data_width : integer := 32
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end rle_enc;
architecture behavioral of rle_enc is
signal count, data, rle_out_i : std_logic_vector ((data_width-1) downto 0);
signal c0, c1, c2, c3, valid, rle : std_logic;
signal state : std_logic_vector(3 downto 0);
begin
-- count repeating data
process(clock)
begin
if rising_edge(clock) then
if raw_inp_valid = '1' then
if data = raw_inp then
count <= count + 1;
else
data <= raw_inp;
count <= (others => '0');
end if;
end if;
end if;
end process;
-- previous and current data is not the same; send old data
c0 <= '1' when data /= raw_inp and count = 0 else '0';
-- start of repeating data; send current data
c1 <= '1' when data = raw_inp and count = 0 else '0';
-- end of repeating data; send count
c2 <= '1' when data /= raw_inp and count /= 0 else '0';
-- count overflow; send count
c3 <= '1' when data = raw_inp and 0 = not count else '0';
state <= c3 & c2 & c1 & c0;
rle_out_i <=
data when state = "0001" else
data when state = "0010" else
count when state = "0100" else
count when state = "1000" else
(others => 'X');
valid <=
'1' when state = "0001" else
'1' when state = "0010" else
'1' when state = "0100" else
'1' when state = "1000" else
'0';
rle <=
'1' when state = "0100" else
'1' when state = "1000" else
'0';
process(clock)
begin
if rising_edge(clock) then
if raw_inp_valid = '1' then
rle_out <= rle_out_i;
rle_out_valid <= valid;
rle_bit <= rle;
else
rle_out_valid <= '0';
rle_bit <= '0';
end if;
end if;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/Wishbone_Peripherals/clk_32to50_dcm.vhd | 13 | 6302 | -- file: clk_32to50_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to50_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to50_dcm;
architecture xilinx of clk_32to50_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to50_dcm,clk_wiz_v3_6,{component_name=clk_32to50_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/clk_32to50_dcm.vhd | 13 | 6302 | -- file: clk_32to50_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to50_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to50_dcm;
architecture xilinx of clk_32to50_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to50_dcm,clk_wiz_v3_6,{component_name=clk_32to50_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/clk_32to50_dcm.vhd | 13 | 6302 | -- file: clk_32to50_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to50_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to50_dcm;
architecture xilinx of clk_32to50_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to50_dcm,clk_wiz_v3_6,{component_name=clk_32to50_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/clk_32to50_dcm.vhd | 13 | 6302 | -- file: clk_32to50_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to50_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to50_dcm;
architecture xilinx of clk_32to50_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to50_dcm,clk_wiz_v3_6,{component_name=clk_32to50_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/ZPUino_1/board_Papilio_Pro/zpupkg.vhd | 39 | 11171 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/board_Papilio_Pro/zpupkg.vhd | 39 | 11171 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/ZPUino_1/board_Papilio_One_500k/zpupkg.vhd | 39 | 11171 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/ZPUino_1/board_Papilio_One_250k/zpupkg.vhd | 39 | 11171 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/ZPUino_1/board_Papilio_One_250k/zpupkg.vhd | 39 | 11171 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/ZPUino_1/papilio_pkg.vhd | 13 | 1565 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package papilio_pkg is
type wishbone_bus_in_type is record
wb_clk_i: std_logic; -- Wishbone clock
wb_rst_i: std_logic; -- Wishbone reset (synchronous)
wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
wb_we_i: std_logic; -- Wishbone write enable signal
wb_cyc_i: std_logic; -- Wishbone cycle signal
wb_stb_i: std_logic; -- Wishbone strobe signal
end record;
type wishbone_bus_out_type is record
wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
wb_ack_o: std_logic; -- Wishbone acknowledge out signal
wb_inta_o: std_logic;
end record;
type gpio_bus_in_type is record
gpio_i: std_logic_vector(48 downto 0);
gpio_spp_data: std_logic_vector(48 downto 0);
end record;
type gpio_bus_out_type is record
gpio_clk: std_logic;
gpio_o: std_logic_vector(48 downto 0);
gpio_t: std_logic_vector(48 downto 0);
gpio_spp_read: std_logic_vector(48 downto 0);
end record;
end papilio_pkg;
package body papilio_pkg is
end papilio_pkg;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/ZPUino_1/papilio_pkg.vhd | 13 | 1565 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package papilio_pkg is
type wishbone_bus_in_type is record
wb_clk_i: std_logic; -- Wishbone clock
wb_rst_i: std_logic; -- Wishbone reset (synchronous)
wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
wb_we_i: std_logic; -- Wishbone write enable signal
wb_cyc_i: std_logic; -- Wishbone cycle signal
wb_stb_i: std_logic; -- Wishbone strobe signal
end record;
type wishbone_bus_out_type is record
wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
wb_ack_o: std_logic; -- Wishbone acknowledge out signal
wb_inta_o: std_logic;
end record;
type gpio_bus_in_type is record
gpio_i: std_logic_vector(48 downto 0);
gpio_spp_data: std_logic_vector(48 downto 0);
end record;
type gpio_bus_out_type is record
gpio_clk: std_logic;
gpio_o: std_logic_vector(48 downto 0);
gpio_t: std_logic_vector(48 downto 0);
gpio_spp_read: std_logic_vector(48 downto 0);
end record;
end papilio_pkg;
package body papilio_pkg is
end papilio_pkg;
| mit |
mwswartwout/EECS318 | hw3/problem1/UPM4x4_tb.vhd | 1 | 796 | entity UPM4x4_tb is
end UPM4x4_tb;
architecture UPM4x4_tb_arch of UPM4x4_tb is
component UPM4x4
port ( X : in bit_vector (3 downto 0);
Y : in bit_vector (3 downto 0);
output : out bit_vector (7 downto 0));
end component;
signal XT, YT : bit_vector (3 downto 0);
signal ZT : bit_vector (7 downto 0);
begin
UPM4x4_1 : UPM4x4 port map (X => XT, Y => YT, output => ZT);
process begin
report "Beginning UPM4x4 test bench" severity note;
XT <= "0010";
YT <= "0100";
wait for 10 ns;
assert (ZT = "00001000") report "Failed, -- 2*4" severity error;
XT <= "1111";
YT <= "0011";
wait for 10 ns;
assert (ZT = "00101101") report "Failed, -- 15*3" severity error;
assert false report "UPM4x4 test bench completed" severity failure;
end process;
end UPM4x4_tb_arch;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/Wing_GPIO.vhd | 13 | 1239 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_Audio - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_GPIO is
port (
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_GPIO;
architecture Behavioral of Wing_GPIO is
begin
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= wt_mosi(5);
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= wt_mosi(7);
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/Wing_GPIO.vhd | 13 | 1239 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_Audio - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_GPIO is
port (
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_GPIO;
architecture Behavioral of Wing_GPIO is
begin
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= wt_mosi(5);
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= wt_mosi(7);
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/Wing_GPIO.vhd | 13 | 1239 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_Audio - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_GPIO is
port (
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_GPIO;
architecture Behavioral of Wing_GPIO is
begin
wt_miso(0) <= wt_mosi(0);
wt_miso(1) <= wt_mosi(1);
wt_miso(2) <= wt_mosi(2);
wt_miso(3) <= wt_mosi(3);
wt_miso(4) <= wt_mosi(4);
wt_miso(5) <= wt_mosi(5);
wt_miso(6) <= wt_mosi(6);
wt_miso(7) <= wt_mosi(7);
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_Pro/wishbonepkg.vhd | 40 | 396 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wishbonepkg is
constant CTI_CYCLE_CLASSIC: std_logic_vector(2 downto 0) := "000";
constant CTI_CYCLE_CONSTADDR: std_logic_vector(2 downto 0) := "001";
constant CTI_CYCLE_INCRADDR: std_logic_vector(2 downto 0) := "010";
constant CTI_CYCLE_ENDOFBURST: std_logic_vector(2 downto 0) := "111";
end wishbonepkg;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_500k/wishbonepkg.vhd | 40 | 396 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wishbonepkg is
constant CTI_CYCLE_CLASSIC: std_logic_vector(2 downto 0) := "000";
constant CTI_CYCLE_CONSTADDR: std_logic_vector(2 downto 0) := "001";
constant CTI_CYCLE_INCRADDR: std_logic_vector(2 downto 0) := "010";
constant CTI_CYCLE_ENDOFBURST: std_logic_vector(2 downto 0) := "111";
end wishbonepkg;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/board_Papilio_One_500k/wishbonepkg.vhd | 40 | 396 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wishbonepkg is
constant CTI_CYCLE_CLASSIC: std_logic_vector(2 downto 0) := "000";
constant CTI_CYCLE_CONSTADDR: std_logic_vector(2 downto 0) := "001";
constant CTI_CYCLE_INCRADDR: std_logic_vector(2 downto 0) := "010";
constant CTI_CYCLE_ENDOFBURST: std_logic_vector(2 downto 0) := "111";
end wishbonepkg;
| mit |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/I2C/testbench/i2c_memory_pkg.vhdl | 1 | 4210 | ------------------------------------------------------------------------------
---- ----
---- I2C Memory Simulator (slave) ----
---- ----
---- Internal file, can't be downloaded. ----
---- ----
---- Description: ----
---- I2C memory simulator package. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador en inti gov ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2005 Salvador E. Tropea <salvador en inti gov ar> ----
---- Copyright (c) 2005 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Covered by the GPL license. ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: I2C_TB (Package) ----
---- File name: i2c_memory_pkg.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: i2c_mwb ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: None ----
---- Language: VHDL ----
---- Wishbone: None ----
---- Synthesis tools: None ----
---- Simulation tools: GHDL [Sokcho edition] (0.1x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: i2c_memory_pkg.vhdl,v $
-- Revision 1.5 2006/04/17 19:44:43 salvador
-- * Modified: License to GPL.
--
-- Revision 1.4 2005/05/20 14:39:05 salvador
-- * Modificado: Mejorado el indentado usando bakalint 0.3.7.
--
-- Revision 1.3 2005/05/18 14:50:20 salvador
-- * Modificado: Los encabezados de los archivos para que cumplan con nuestras
-- recomendaciones.
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package I2C_TB is
component I2C_Memory is
generic(
-- I2C device address
I2C_ADR : std_logic_vector(6 downto 0):="0010000";
-- To make it more verbose
DEBUG : boolean:=false);
port(
-- I2C Clock signal, needs a pull-up ('H')
scl_x_i : in std_logic;
-- I2C Data signal, needs a pull-up ('H')
sda_x_io : inout std_logic;
-- Asynchronous reset
rst_i : in std_logic);
end component I2C_Memory;
end package I2C_TB;
| mit |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/Clock/simulation/Clock_tb.vhd | 1 | 6298 | -- file: Clock_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity Clock_tb is
end Clock_tb;
architecture test of Clock_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 20.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(4 downto 1);
-- Status and control signals
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(4 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component Clock_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(4 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(4 downto 1);
-- Status and control signals
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
wait until LOCKED = '1';
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : Clock_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
LOCKED => LOCKED);
-- Freq Check
end test;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/Arcade_MegaWing_Pinout.vhd | 13 | 12521 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
entity Arcade_MegaWing_Pinout is
port (
--Audio
Audio_Left : in std_logic;
Audio_Right : in std_logic;
--Buttons
BTN_Left : in std_logic;
BTN_Right : in std_logic;
BTN_Up : in std_logic;
BTN_Down : in std_logic;
BTN_Reset : in std_logic;
--Joystick A
JOYA_Left : in std_logic;
JOYA_Right : in std_logic;
JOYA_Up : in std_logic;
JOYA_Down : in std_logic;
JOYA_Fire1 : in std_logic;
JOYA_Fire2 : in std_logic;
JOYA_GND : in std_logic;
--Joystick B
JOYB_Left : in std_logic;
JOYB_Right : in std_logic;
JOYB_Up : in std_logic;
JOYB_Down : in std_logic;
JOYB_Fire1 : in std_logic;
JOYB_Fire2 : in std_logic;
JOYB_GND : in std_logic;
--LED's
LED1 : in std_logic;
LED2 : in std_logic;
LED3 : in std_logic;
LED4 : in std_logic;
--PS2 A
PS2A_CLK : in std_logic;
PS2A_Data : out std_logic;
--PS2 B
PS2B_CLK : in std_logic;
PS2B_Data : out std_logic;
--VGA
VGA_Red : in std_logic_vector (2 downto 0);
VGA_Green : in std_logic_vector (2 downto 0);
VGA_Blue : in std_logic_vector (1 downto 0);
VGA_Hsync : in std_logic;
VGA_Vsync : in std_logic;
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Arcade_MegaWing_Pinout;
architecture BEHAVIORAL of Arcade_MegaWing_Pinout is
-- signal gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
--Audio
WING_AH6 <= Audio_Left;
WING_AH7 <= Audio_Right;
--Buttons
WING_BH0 <= BTN_Left;
WING_BH3 <= BTN_Right;
WING_BH1 <= BTN_Up;
WING_BH2 <= BTN_Down;
WING_AH4 <= BTN_Reset;
--Joystick A
WING_CH3 <= JOYA_Left;
WING_CH5 <= JOYA_Right;
WING_CH0 <= JOYA_Up ;
WING_CH2 <= JOYA_Down;
WING_CH1 <= JOYA_Fire1;
WING_CH7 <= JOYA_Fire2;
WING_CH4 <= JOYA_GND;
--Joystick B
WING_BH7 <= JOYB_Left;
WING_AL1 <= JOYB_Right;
WING_BH4 <= JOYB_Up ;
WING_BH6 <= JOYB_Down;
WING_BH5 <= JOYB_Fire1;
WING_AL3 <= JOYB_Fire2;
WING_AL0 <= JOYB_GND;
--LED's
WING_AL7 <= LED1;
WING_AL6 <= LED2;
WING_AL5 <= LED3;
WING_AL4 <= LED4;
--PS2 A
WING_CL1 <= PS2A_CLK;
PS2A_Data <= WING_CL0;
--PS2 B
WING_AH5 <= PS2B_CLK;
PS2B_Data <= WING_AH4;
--VGA
WING_CL2 <= VGA_Vsync;
WING_CL3 <= VGA_Hsync;
WING_BL0 <= VGA_Blue(0);
WING_BL1 <= VGA_Blue(1);
--WING_BL2 <= VGA_Blue(2);
--WING_BL3 <= VGA_Blue(3);
WING_BL4 <= VGA_Green(0);
WING_BL5 <= VGA_Green(1);
WING_BL6 <= VGA_Green(2);
--WING_BL7 <= VGA_Green(3);
WING_CL4 <= VGA_Red(0);
WING_CL5 <= VGA_Red(1);
WING_CL6 <= VGA_Red(2);
--WING_CL7 <= VGA_Red(3);
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_spp_data <= (others => DontCareValue);
-- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/ZPUino_1/Arcade_MegaWing_Pinout.vhd | 13 | 12521 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
entity Arcade_MegaWing_Pinout is
port (
--Audio
Audio_Left : in std_logic;
Audio_Right : in std_logic;
--Buttons
BTN_Left : in std_logic;
BTN_Right : in std_logic;
BTN_Up : in std_logic;
BTN_Down : in std_logic;
BTN_Reset : in std_logic;
--Joystick A
JOYA_Left : in std_logic;
JOYA_Right : in std_logic;
JOYA_Up : in std_logic;
JOYA_Down : in std_logic;
JOYA_Fire1 : in std_logic;
JOYA_Fire2 : in std_logic;
JOYA_GND : in std_logic;
--Joystick B
JOYB_Left : in std_logic;
JOYB_Right : in std_logic;
JOYB_Up : in std_logic;
JOYB_Down : in std_logic;
JOYB_Fire1 : in std_logic;
JOYB_Fire2 : in std_logic;
JOYB_GND : in std_logic;
--LED's
LED1 : in std_logic;
LED2 : in std_logic;
LED3 : in std_logic;
LED4 : in std_logic;
--PS2 A
PS2A_CLK : in std_logic;
PS2A_Data : out std_logic;
--PS2 B
PS2B_CLK : in std_logic;
PS2B_Data : out std_logic;
--VGA
VGA_Red : in std_logic_vector (2 downto 0);
VGA_Green : in std_logic_vector (2 downto 0);
VGA_Blue : in std_logic_vector (1 downto 0);
VGA_Hsync : in std_logic;
VGA_Vsync : in std_logic;
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Arcade_MegaWing_Pinout;
architecture BEHAVIORAL of Arcade_MegaWing_Pinout is
-- signal gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
--Audio
WING_AH6 <= Audio_Left;
WING_AH7 <= Audio_Right;
--Buttons
WING_BH0 <= BTN_Left;
WING_BH3 <= BTN_Right;
WING_BH1 <= BTN_Up;
WING_BH2 <= BTN_Down;
WING_AH4 <= BTN_Reset;
--Joystick A
WING_CH3 <= JOYA_Left;
WING_CH5 <= JOYA_Right;
WING_CH0 <= JOYA_Up ;
WING_CH2 <= JOYA_Down;
WING_CH1 <= JOYA_Fire1;
WING_CH7 <= JOYA_Fire2;
WING_CH4 <= JOYA_GND;
--Joystick B
WING_BH7 <= JOYB_Left;
WING_AL1 <= JOYB_Right;
WING_BH4 <= JOYB_Up ;
WING_BH6 <= JOYB_Down;
WING_BH5 <= JOYB_Fire1;
WING_AL3 <= JOYB_Fire2;
WING_AL0 <= JOYB_GND;
--LED's
WING_AL7 <= LED1;
WING_AL6 <= LED2;
WING_AL5 <= LED3;
WING_AL4 <= LED4;
--PS2 A
WING_CL1 <= PS2A_CLK;
PS2A_Data <= WING_CL0;
--PS2 B
WING_AH5 <= PS2B_CLK;
PS2B_Data <= WING_AH4;
--VGA
WING_CL2 <= VGA_Vsync;
WING_CL3 <= VGA_Hsync;
WING_BL0 <= VGA_Blue(0);
WING_BL1 <= VGA_Blue(1);
--WING_BL2 <= VGA_Blue(2);
--WING_BL3 <= VGA_Blue(3);
WING_BL4 <= VGA_Green(0);
WING_BL5 <= VGA_Green(1);
WING_BL6 <= VGA_Green(2);
--WING_BL7 <= VGA_Green(3);
WING_CL4 <= VGA_Red(0);
WING_CL5 <= VGA_Red(1);
WING_CL6 <= VGA_Red(2);
--WING_CL7 <= VGA_Red(3);
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_spp_data <= (others => DontCareValue);
-- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Benchy/muldex_8.vhd | 13 | 4970 | ----------------------------------------------------------------------------------
-- muldex_8.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Multiplexes and demultiplexes the 8 bit data into a 32 bit memory bus.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex_8 is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end muldex_8;
architecture behavioral of muldex_8 is
type wr_state_type is (W0, W1, W2, W3);
type rd_state_type is (RI, R0, R1, R2, R3);
signal state_wr, nstate_wr : wr_state_type;
signal state_rd, nstate_rd : rd_state_type;
signal wrtmp, wrtmp_r, rdtmp, rdtmp_r : std_logic_vector (35 downto 0);
signal mw, mr : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state_wr <= W0;
state_rd <= RI;
else
state_wr <= nstate_wr;
state_rd <= nstate_rd;
end if;
wrtmp_r <= wrtmp;
rdtmp_r <= rdtmp;
-- registered outputs
mem_out <= wrtmp;
mem_wr <= mw;
mem_rd <= mr;
end if;
end process;
process(state_wr, data_wr, rle_in, wrtmp_r, data_inp)
begin
case state_wr is
when W0 =>
if data_wr = '1' then
nstate_wr <= W1;
wrtmp <= wrtmp_r(35 downto 33) & rle_in
& wrtmp_r(31 downto 8) & data_inp;
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
end if;
mw <= '0';
when W1 =>
if data_wr = '1' then
nstate_wr <= W2;
wrtmp <= wrtmp_r(35 downto 34) & rle_in
& wrtmp_r(32 downto 16)
& data_inp & wrtmp_r(7 downto 0);
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
end if;
mw <= '0';
when W2 =>
if data_wr = '1' then
nstate_wr <= W3;
wrtmp <= wrtmp_r(35 downto 35) & rle_in
& wrtmp_r(33 downto 24) & data_inp
& wrtmp_r(15 downto 0);
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
end if;
mw <= '0';
when W3 =>
if data_wr = '1' then
nstate_wr <= W0;
wrtmp <= rle_in & wrtmp_r(34 downto 32)
& data_inp & wrtmp_r(23 downto 0);
mw <= '1';
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
mw <= '0';
end if;
end case;
end process;
process(state_rd, data_rd, state_wr, wrtmp, rdtmp_r, mem_inp)
begin
case state_rd is
when RI =>
if data_rd = '1' then
if state_wr = W0 then
nstate_rd <= R0;
mr <= '1';
elsif state_wr = W1 then
nstate_rd <= R1;
mr <= '0';
elsif state_wr = W2 then
nstate_rd <= R2;
mr <= '0';
else
nstate_rd <= R3;
mr <= '0';
end if;
else
nstate_rd <= state_rd;
mr <= '0';
end if;
rdtmp <= wrtmp;
data_out <= (others => 'X');
rle_out <= 'X';
when R0 =>
if data_rd = '1' then
nstate_rd <= R3;
else
nstate_rd <= state_rd;
end if;
rdtmp <= rdtmp_r;
mr <= '0';
data_out <= rdtmp_r(31 downto 24);
rle_out <= rdtmp_r(35);
when R1 =>
if data_rd = '1' then
nstate_rd <= R0;
rdtmp <= mem_inp;
mr <= '1';
else
nstate_rd <= state_rd;
rdtmp <= rdtmp_r;
mr <= '0';
end if;
data_out <= rdtmp_r(7 downto 0);
rle_out <= rdtmp_r(32);
when R2 =>
if data_rd = '1' then
nstate_rd <= R1;
else
nstate_rd <= state_rd;
end if;
rdtmp <= rdtmp_r;
mr <= '0';
data_out <= rdtmp_r(15 downto 8);
rle_out <= rdtmp_r(33);
when R3 =>
if data_rd = '1' then
nstate_rd <= R2;
else
nstate_rd <= state_rd;
end if;
rdtmp <= rdtmp_r;
mr <= '0';
data_out <= rdtmp_r(23 downto 16);
rle_out <= rdtmp_r(34);
end case;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Benchy/muldex_8.vhd | 13 | 4970 | ----------------------------------------------------------------------------------
-- muldex_8.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Multiplexes and demultiplexes the 8 bit data into a 32 bit memory bus.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex_8 is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end muldex_8;
architecture behavioral of muldex_8 is
type wr_state_type is (W0, W1, W2, W3);
type rd_state_type is (RI, R0, R1, R2, R3);
signal state_wr, nstate_wr : wr_state_type;
signal state_rd, nstate_rd : rd_state_type;
signal wrtmp, wrtmp_r, rdtmp, rdtmp_r : std_logic_vector (35 downto 0);
signal mw, mr : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state_wr <= W0;
state_rd <= RI;
else
state_wr <= nstate_wr;
state_rd <= nstate_rd;
end if;
wrtmp_r <= wrtmp;
rdtmp_r <= rdtmp;
-- registered outputs
mem_out <= wrtmp;
mem_wr <= mw;
mem_rd <= mr;
end if;
end process;
process(state_wr, data_wr, rle_in, wrtmp_r, data_inp)
begin
case state_wr is
when W0 =>
if data_wr = '1' then
nstate_wr <= W1;
wrtmp <= wrtmp_r(35 downto 33) & rle_in
& wrtmp_r(31 downto 8) & data_inp;
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
end if;
mw <= '0';
when W1 =>
if data_wr = '1' then
nstate_wr <= W2;
wrtmp <= wrtmp_r(35 downto 34) & rle_in
& wrtmp_r(32 downto 16)
& data_inp & wrtmp_r(7 downto 0);
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
end if;
mw <= '0';
when W2 =>
if data_wr = '1' then
nstate_wr <= W3;
wrtmp <= wrtmp_r(35 downto 35) & rle_in
& wrtmp_r(33 downto 24) & data_inp
& wrtmp_r(15 downto 0);
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
end if;
mw <= '0';
when W3 =>
if data_wr = '1' then
nstate_wr <= W0;
wrtmp <= rle_in & wrtmp_r(34 downto 32)
& data_inp & wrtmp_r(23 downto 0);
mw <= '1';
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
mw <= '0';
end if;
end case;
end process;
process(state_rd, data_rd, state_wr, wrtmp, rdtmp_r, mem_inp)
begin
case state_rd is
when RI =>
if data_rd = '1' then
if state_wr = W0 then
nstate_rd <= R0;
mr <= '1';
elsif state_wr = W1 then
nstate_rd <= R1;
mr <= '0';
elsif state_wr = W2 then
nstate_rd <= R2;
mr <= '0';
else
nstate_rd <= R3;
mr <= '0';
end if;
else
nstate_rd <= state_rd;
mr <= '0';
end if;
rdtmp <= wrtmp;
data_out <= (others => 'X');
rle_out <= 'X';
when R0 =>
if data_rd = '1' then
nstate_rd <= R3;
else
nstate_rd <= state_rd;
end if;
rdtmp <= rdtmp_r;
mr <= '0';
data_out <= rdtmp_r(31 downto 24);
rle_out <= rdtmp_r(35);
when R1 =>
if data_rd = '1' then
nstate_rd <= R0;
rdtmp <= mem_inp;
mr <= '1';
else
nstate_rd <= state_rd;
rdtmp <= rdtmp_r;
mr <= '0';
end if;
data_out <= rdtmp_r(7 downto 0);
rle_out <= rdtmp_r(32);
when R2 =>
if data_rd = '1' then
nstate_rd <= R1;
else
nstate_rd <= state_rd;
end if;
rdtmp <= rdtmp_r;
mr <= '0';
data_out <= rdtmp_r(15 downto 8);
rle_out <= rdtmp_r(33);
when R3 =>
if data_rd = '1' then
nstate_rd <= R2;
else
nstate_rd <= state_rd;
end if;
rdtmp <= rdtmp_r;
mr <= '0';
data_out <= rdtmp_r(23 downto 16);
rle_out <= rdtmp_r(34);
end case;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/Benchy/BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag.vhd | 13 | 7125 | ----------------------------------------------------------------------------------
-- Papilio_Logic.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependent IO modules and defines all la_inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
generic (
brams: integer := 12
);
port(
clk_32Mhz : in std_logic;
--extClockIn : in std_logic;
-- extClockOut : out std_logic;
--extTriggerIn : in std_logic;
--extTriggerOut : out std_logic;
--la_input : in std_logic_vector(31 downto 0);
la0 : in std_logic;
la1 : in std_logic;
la2 : in std_logic;
la3 : in std_logic;
la4 : in std_logic;
la5 : in std_logic;
la6 : in std_logic;
la7 : in std_logic
-- rx : in std_logic;
-- tx : out std_logic
-- miso : out std_logic;
-- mosi : in std_logic;
-- sclk : in std_logic;
-- cs : in std_logic
-- dataReady : out std_logic;
-- adc_cs_n : inout std_logic;
--armLED : out std_logic;
--triggerLED : out std_logic
);
end BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag;
architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag is
component clockman
port(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
end component;
COMPONENT bscan_spi
PORT(
SPI_MISO : IN std_logic;
SPI_MOSI : INOUT std_logic;
SPI_CS : INOUT std_logic;
SPI_SCK : INOUT std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
component spi_slave
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end component;
component core
port(
clock : in std_logic;
cmd : in std_logic_vector(39 downto 0);
execute : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_inputClock : in std_logic;
output : out std_logic_vector (31 downto 0);
outputSend : out std_logic;
outputBusy : in std_logic;
memoryIn : in std_logic_vector(35 downto 0);
memoryOut : out std_logic_vector(35 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
extTriggerIn : in std_logic;
extTriggerOut : out std_logic;
extClockOut : out std_logic;
armLED : out std_logic;
triggerLED : out std_logic;
reset : out std_logic;
tx_bytes : out integer range 0 to 4
);
end component;
component sram_bram
generic (
brams: integer := 12
);
port(
clock : in std_logic;
output : out std_logic_vector(35 downto 0);
la_input : in std_logic_vector(35 downto 0);
read : in std_logic;
write : in std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (35 downto 0);
signal output, la_input : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal tx_bytes : integer range 0 to 4;
signal extClockIn, extTriggerIn : std_logic;
signal dataReady, reset : std_logic;
signal mosi, miso, sclk, cs : std_logic;
--Constants for UART
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54
constant RATE : integer := 115200; -- maximum & base rate
constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications
begin
--la_input <= (others => '0');
la_input(0) <= la0;
la_input(1) <= la1;
la_input(2) <= la2;
la_input(3) <= la3;
la_input(4) <= la4;
la_input(5) <= la5;
la_input(6) <= la6;
la_input(7) <= la7;
-- adc_cs_n <= '1'; --Disables ADC
Inst_clockman: clockman
port map(
clkin => clk_32Mhz,
clk0 => clock
);
Inst_bscan_spi: bscan_spi PORT MAP(
SPI_MISO => miso,
SPI_MOSI => mosi,
SPI_CS => cs,
SPI_SCK => sclk
);
-- Inst_eia232: eia232
-- generic map (
-- FREQ => FREQ,
-- SCALE => TRXSCALE,
-- RATE => RATE
-- )
-- PORT MAP(
-- clock => clock,
-- reset => '0',
-- speed => SPEED,
-- rx => rx,
-- tx => tx,
-- cmd => cmd,
-- execute => execute,
-- data => output,
-- send => send,
-- busy => busy
-- );
Inst_spi_slave: spi_slave
port map(
clock => clock,
data => output,
send => send,
mosi => mosi,
sclk => sclk,
cs => cs,
miso => miso,
cmd => cmd,
execute => execute,
busy => busy,
dataReady => dataReady,
reset => reset,
tx_bytes => tx_bytes
);
extClockIn <= '0'; --External clock disabled
extTriggerIn <= '0'; --External trigger disabled
Inst_core: core
port map(
clock => clock,
cmd => cmd,
execute => execute,
la_input => la_input,
la_inputClock => extClockIn,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write,
extTriggerIn => extTriggerIn,
extTriggerOut => open,
extClockOut => open,
armLED => open,
triggerLED => open,
reset => reset,
tx_bytes => tx_bytes
);
Inst_sram: sram_bram
generic map (
brams => brams
)
port map(
clock => clock,
output => memoryIn,
la_input => memoryOut,
read => read,
write => write
);
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/Wishbone_Peripherals/tx_unit.vhd | 15 | 6083 | ------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals/tx_unit.vhd | 15 | 6083 | ------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Benchy/muldex_16.vhd | 13 | 3865 | ----------------------------------------------------------------------------------
-- muldex_8.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public Licenstate_wre as published by
-- the Free Software Foundation; either version 2 of the Licenstate_wre, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public Licenstate_wre for more details.
--
-- You should have received a copy of the GNU General Public Licenstate_wre along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Multiplexes and demultiplexes the 16 bit data into a 32 bit memory bus.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex_16 is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end muldex_16;
architecture behavioral of muldex_16 is
type wr_state_type is (W0, W1);
type rd_state_type is (RI, R0, R1);
signal state_wr, nstate_wr : wr_state_type;
signal state_rd, nstate_rd : rd_state_type;
signal wrtmp, wrtmp_r, rdtmp, rdtmp_r : std_logic_vector (33 downto 0);
signal mw, mr : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state_wr <= W0;
state_rd <= RI;
else
state_wr <= nstate_wr;
state_rd <= nstate_rd;
end if;
wrtmp_r <= wrtmp;
rdtmp_r <= rdtmp;
-- registered outputs
mem_out <= wrtmp;
mem_wr <= mw;
mem_rd <= mr;
end if;
end process;
process(state_wr, data_wr, rle_in, wrtmp_r, data_inp)
begin
case state_wr is
when W0 =>
if data_wr = '1' then
nstate_wr <= W1;
wrtmp <= wrtmp_r(33) & rle_in
& wrtmp_r(31 downto 16) & data_inp;
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
end if;
mw <= '0';
when W1 =>
if data_wr = '1' then
nstate_wr <= W0;
wrtmp <= rle_in & wrtmp_r(32) & data_inp
& wrtmp_r(15 downto 0);
mw <= '1';
else
nstate_wr <= state_wr;
wrtmp <= wrtmp_r;
mw <= '0';
end if;
end case;
end process;
process(state_rd, data_rd, state_wr, wrtmp, rdtmp_r, mem_inp)
begin
case state_rd is
when RI =>
if data_rd = '1' then
if state_wr = W0 then
nstate_rd <= R0;
mr <= '1';
else
nstate_rd <= R1;
mr <= '0';
end if;
else
nstate_rd <= state_rd;
mr <= '0';
end if;
rdtmp <= wrtmp;
data_out <= (others => 'X');
rle_out <= 'X';
when R0 =>
if data_rd = '1' then
nstate_rd <= R1;
else
nstate_rd <= state_rd;
end if;
rdtmp <= rdtmp_r;
mr <= '0';
data_out <= rdtmp_r(31 downto 16);
rle_out <= rdtmp_r(33);
when R1 =>
if data_rd = '1' then
nstate_rd <= R0;
rdtmp <= mem_inp;
mr <= '1';
else
nstate_rd <= state_rd;
rdtmp <= rdtmp_r;
mr <= '0';
end if;
data_out <= rdtmp_r(15 downto 0);
rle_out <= rdtmp_r(32);
end case;
end process;
end behavioral;
| mit |
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