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chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Benchy/spi_slave.vhd | 13 | 2650 | ----------------------------------------------------------------------------------
-- spi_slave.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- spi_slave
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_slave is
port(
clock : in std_logic;
data : in std_logic_vector(31 downto 0);
send : in std_logic;
mosi : in std_logic;
sclk : in std_logic;
cs : in std_logic;
miso : out std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
busy : out std_logic;
dataReady : out std_logic;
reset : in std_logic;
tx_bytes : in integer range 0 to 4
);
end spi_slave;
architecture behavioral of spi_slave is
component spi_receiver
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector(39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end component;
component spi_transmitter
port(
data : in std_logic_vector(31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic;
cs : in std_logic;
busy : out std_logic;
reset : in std_logic;
dataReady : out std_logic
);
end component;
begin
Inst_spi_receiver: spi_receiver
port map(
rx => mosi,
clock => clock,
sclk => sclk,
cmd => cmd,
execute => execute,
reset => reset,
cs => cs
);
Inst_spi_transmitter: spi_transmitter
port map(
data => data,
tx_bytes => tx_bytes,
send => send,
clock => clock,
sclk => sclk,
tx => miso,
cs => cs,
busy => busy,
reset => reset,
dataReady => dataReady
);
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/Wishbone_Peripherals/BENCHY_zpuino_wb_waveform_generator.vhd | 13 | 7433 | ----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/spimaster.vhd | 13 | 4134 | --
-- SPI master interface
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spimaster is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
miso: out std_logic;
mosi: in std_logic;
sck: in std_logic;
seln: in std_logic
);
end entity spimaster;
architecture behave of spimaster is
signal sck_q: std_logic;
signal sck_rising: std_logic;
signal sck_falling: std_logic;
signal event_sample: std_logic;
signal event_shift: std_logic;
-- Registers
signal spi_cpol_q: std_logic;
signal spi_cpha_q: std_logic;
signal spi_shift_out_q: std_logic_vector(7 downto 0);
signal spi_shift_in_q: std_logic_vector(7 downto 0);
signal spi_read_q: std_logic_vector(7 downto 0);
signal spi_sample_q: std_logic;
signal spi_count_q: integer range 0 to 7;
begin
-- Clock delay
process(clk)
begin
if rising_edge(clk) then
sck_q <= sck;
end if;
end process;
sck_rising<='1' when sck='1' and sck_q='0' else '0';
sck_falling<='1' when sck='0' and sck_q='1' else '0';
process(sck_rising,sck_falling,spi_cpha_q,spi_cpol_q)
variable mode: std_logic_vector(1 downto 0);
begin
event_sample<='0';
event_shift<='0';
mode := spi_cpol_q & spi_cpha_q;
case mode is
when "00" =>
event_sample <= sck_rising;
event_shift <= sck_falling;
when "01" =>
event_sample <= sck_falling;
event_shift <= sck_rising;
when "10" =>
event_sample <= sck_falling;
event_shift <= sck_rising;
when "11" =>
event_sample <= sck_rising;
event_shift <= sck_falling;
when others =>
end case;
end process;
-- Sampling
process(clk)
begin
if rising_edge(clk) then
if event_sample='1' and seln='0' then
spi_sample_q <= mosi;
spi_shift_in_q(0) <= mosi;
spi_shift_in_q(7 downto 1) <= spi_shift_in_q(6 downto 0);
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
spi_cpha_q<='0';
spi_cpol_q<='0';
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if seln='1' then
-- Deselected
spi_count_q<=7;
else
if event_shift='1' then
miso <= spi_shift_out_q(7);
spi_shift_out_q(7 downto 1) <= spi_shift_out_q(6 downto 0);
spi_shift_out_q(0) <= spi_sample_q;
if spi_count_q=0 then
spi_count_q<=7;
-- Event
spi_read_q <= spi_shift_in_q;
else
spi_count_q<=spi_count_q-1;
end if;
end if;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Wishbone_Peripherals/spimaster.vhd | 13 | 4134 | --
-- SPI master interface
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spimaster is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
miso: out std_logic;
mosi: in std_logic;
sck: in std_logic;
seln: in std_logic
);
end entity spimaster;
architecture behave of spimaster is
signal sck_q: std_logic;
signal sck_rising: std_logic;
signal sck_falling: std_logic;
signal event_sample: std_logic;
signal event_shift: std_logic;
-- Registers
signal spi_cpol_q: std_logic;
signal spi_cpha_q: std_logic;
signal spi_shift_out_q: std_logic_vector(7 downto 0);
signal spi_shift_in_q: std_logic_vector(7 downto 0);
signal spi_read_q: std_logic_vector(7 downto 0);
signal spi_sample_q: std_logic;
signal spi_count_q: integer range 0 to 7;
begin
-- Clock delay
process(clk)
begin
if rising_edge(clk) then
sck_q <= sck;
end if;
end process;
sck_rising<='1' when sck='1' and sck_q='0' else '0';
sck_falling<='1' when sck='0' and sck_q='1' else '0';
process(sck_rising,sck_falling,spi_cpha_q,spi_cpol_q)
variable mode: std_logic_vector(1 downto 0);
begin
event_sample<='0';
event_shift<='0';
mode := spi_cpol_q & spi_cpha_q;
case mode is
when "00" =>
event_sample <= sck_rising;
event_shift <= sck_falling;
when "01" =>
event_sample <= sck_falling;
event_shift <= sck_rising;
when "10" =>
event_sample <= sck_falling;
event_shift <= sck_rising;
when "11" =>
event_sample <= sck_rising;
event_shift <= sck_falling;
when others =>
end case;
end process;
-- Sampling
process(clk)
begin
if rising_edge(clk) then
if event_sample='1' and seln='0' then
spi_sample_q <= mosi;
spi_shift_in_q(0) <= mosi;
spi_shift_in_q(7 downto 1) <= spi_shift_in_q(6 downto 0);
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
spi_cpha_q<='0';
spi_cpol_q<='0';
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if seln='1' then
-- Deselected
spi_count_q<=7;
else
if event_shift='1' then
miso <= spi_shift_out_q(7);
spi_shift_out_q(7 downto 1) <= spi_shift_out_q(6 downto 0);
spi_shift_out_q(0) <= spi_sample_q;
if spi_count_q=0 then
spi_count_q<=7;
-- Event
spi_read_q <= spi_shift_in_q;
else
spi_count_q<=spi_count_q-1;
end if;
end if;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_sid6581.vhd | 13 | 5561 | --
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/ZPUino_1/board_Papilio_One_500k/zpuinopkg.vhd | 13 | 22276 | --
-- ZPUINO package
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuino_config.all;
package zpuinopkg is
constant num_devices: integer := (2**zpuino_number_io_select_bits);
type slot_std_logic_type is array(0 to num_devices-1) of std_logic;
subtype cpuword_type is std_logic_vector(31 downto 0);
type slot_cpuword_type is array(0 to num_devices-1) of cpuword_type;
subtype address_type is std_logic_vector(maxIObit downto minIObit);
type slot_address_type is array(0 to num_devices-1) of address_type;
component zpuino_top_icache is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
-- Wishbone MASTER interface (for DMA)
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
memory_enable: out std_logic;
-- Memory connection
ram_wb_ack_i: in std_logic;
ram_wb_stall_i: in std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
ram_wb_cyc_o: out std_logic;
ram_wb_stb_o: out std_logic;
ram_wb_sel_o: out std_logic_vector(3 downto 0);
ram_wb_we_o: out std_logic;
rom_wb_ack_i: in std_logic;
rom_wb_stall_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stb_o: out std_logic;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component zpuino_top_icache;
component zpuino_top is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type
);
end component zpuino_io;
component zpuino_empty_device is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_empty_device;
component zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end component zpuino_spi;
component zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end component zpuino_uart;
component zpuino_gpio is
generic (
gpio_count: integer := 32
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
spp_data: in std_logic_vector(gpio_count-1 downto 0);
spp_read: out std_logic_vector(gpio_count-1 downto 0);
gpio_o: out std_logic_vector(gpio_count-1 downto 0);
gpio_t: out std_logic_vector(gpio_count-1 downto 0);
gpio_i: in std_logic_vector(gpio_count-1 downto 0);
spp_cap_in: in std_logic_vector(gpio_count-1 downto 0); -- SPP capable pin for INPUT
spp_cap_out: in std_logic_vector(gpio_count-1 downto 0) -- SPP capable pin for OUTPUT
);
end component zpuino_gpio;
component zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean := true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end component zpuino_timers;
component zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0);
intr_cfglvl:in std_logic_vector(INTERRUPT_LINES-1 downto 0)
);
end component zpuino_intr;
component zpuino_sigmadelta is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sync_in: in std_logic;
-- Connection to GPIO pin
raw_out: out std_logic_vector(17 downto 0);
spp_data: out std_logic_vector(1 downto 0);
spp_en: out std_logic_vector(1 downto 0)
);
end component zpuino_sigmadelta;
component zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_crc16;
component zpuino_adc is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sample: in std_logic;
-- GPIO SPI pins
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
seln: out std_logic;
enabled: out std_logic
);
end component zpuino_adc;
component sram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
--wb_sel_i: in std_logic_vector(3 downto 0);
--wb_cti_i: in std_logic_vector(2 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
clk_we: in std_logic;
clk_wen: in std_logic;
-- SRAM signals
sram_addr: out std_logic_vector(18 downto 0);
sram_data: inout std_logic_vector(15 downto 0);
sram_ce: out std_logic;
sram_we: out std_logic;
sram_oe: out std_logic;
sram_be: out std_logic
);
end component sram_ctrl;
component zpuino_sevenseg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end component;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
m0_wb_stall_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component wbbootloadermux is
generic (
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
sel: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
m_wb_stall_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(11 downto 2);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic;
s1_wb_stall_i: in std_logic
);
end component wbbootloadermux;
component wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end component;
component generic_sp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component generic_dp_ram;
component zpuino_io_YM2149 is
generic (
FREQMHZ: integer := 96
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
data_out: out std_logic_vector(7 downto 0)
);
end component;
component wb_sid6581 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end component wb_sid6581;
component zpuino_vga is
generic(
vgaclk_divider: integer := 2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
-- VGA interface
vgaclk: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r: out std_logic_vector(2 downto 0);
vga_g: out std_logic_vector(2 downto 0);
vga_b: out std_logic_vector(1 downto 0)
);
end component;
component simple_sigmadelta is
generic (
BITS: integer := 8
);
port (
clk: in std_logic;
rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
data_out: out std_logic
);
end component simple_sigmadelta;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 92
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
end package zpuinopkg; | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_500k/zpuinopkg.vhd | 13 | 22276 | --
-- ZPUINO package
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuino_config.all;
package zpuinopkg is
constant num_devices: integer := (2**zpuino_number_io_select_bits);
type slot_std_logic_type is array(0 to num_devices-1) of std_logic;
subtype cpuword_type is std_logic_vector(31 downto 0);
type slot_cpuword_type is array(0 to num_devices-1) of cpuword_type;
subtype address_type is std_logic_vector(maxIObit downto minIObit);
type slot_address_type is array(0 to num_devices-1) of address_type;
component zpuino_top_icache is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
-- Wishbone MASTER interface (for DMA)
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
memory_enable: out std_logic;
-- Memory connection
ram_wb_ack_i: in std_logic;
ram_wb_stall_i: in std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
ram_wb_cyc_o: out std_logic;
ram_wb_stb_o: out std_logic;
ram_wb_sel_o: out std_logic_vector(3 downto 0);
ram_wb_we_o: out std_logic;
rom_wb_ack_i: in std_logic;
rom_wb_stall_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stb_o: out std_logic;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component zpuino_top_icache;
component zpuino_top is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type
);
end component zpuino_io;
component zpuino_empty_device is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_empty_device;
component zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end component zpuino_spi;
component zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end component zpuino_uart;
component zpuino_gpio is
generic (
gpio_count: integer := 32
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
spp_data: in std_logic_vector(gpio_count-1 downto 0);
spp_read: out std_logic_vector(gpio_count-1 downto 0);
gpio_o: out std_logic_vector(gpio_count-1 downto 0);
gpio_t: out std_logic_vector(gpio_count-1 downto 0);
gpio_i: in std_logic_vector(gpio_count-1 downto 0);
spp_cap_in: in std_logic_vector(gpio_count-1 downto 0); -- SPP capable pin for INPUT
spp_cap_out: in std_logic_vector(gpio_count-1 downto 0) -- SPP capable pin for OUTPUT
);
end component zpuino_gpio;
component zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean := true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end component zpuino_timers;
component zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0);
intr_cfglvl:in std_logic_vector(INTERRUPT_LINES-1 downto 0)
);
end component zpuino_intr;
component zpuino_sigmadelta is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sync_in: in std_logic;
-- Connection to GPIO pin
raw_out: out std_logic_vector(17 downto 0);
spp_data: out std_logic_vector(1 downto 0);
spp_en: out std_logic_vector(1 downto 0)
);
end component zpuino_sigmadelta;
component zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component zpuino_crc16;
component zpuino_adc is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sample: in std_logic;
-- GPIO SPI pins
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
seln: out std_logic;
enabled: out std_logic
);
end component zpuino_adc;
component sram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
--wb_sel_i: in std_logic_vector(3 downto 0);
--wb_cti_i: in std_logic_vector(2 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
clk_we: in std_logic;
clk_wen: in std_logic;
-- SRAM signals
sram_addr: out std_logic_vector(18 downto 0);
sram_data: inout std_logic_vector(15 downto 0);
sram_ce: out std_logic;
sram_we: out std_logic;
sram_oe: out std_logic;
sram_be: out std_logic
);
end component sram_ctrl;
component zpuino_sevenseg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end component;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
m0_wb_stall_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component wbbootloadermux is
generic (
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
sel: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
m_wb_stall_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(11 downto 2);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic;
s1_wb_stall_i: in std_logic
);
end component wbbootloadermux;
component wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end component;
component generic_sp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component generic_dp_ram;
component zpuino_io_YM2149 is
generic (
FREQMHZ: integer := 96
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
data_out: out std_logic_vector(7 downto 0)
);
end component;
component wb_sid6581 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end component wb_sid6581;
component zpuino_vga is
generic(
vgaclk_divider: integer := 2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
-- VGA interface
vgaclk: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r: out std_logic_vector(2 downto 0);
vga_g: out std_logic_vector(2 downto 0);
vga_b: out std_logic_vector(1 downto 0)
);
end component;
component simple_sigmadelta is
generic (
BITS: integer := 8
);
port (
clk: in std_logic;
rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
data_out: out std_logic
);
end component simple_sigmadelta;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 92
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
end package zpuinopkg; | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/board_Papilio_Pro/sdram_wrap.vhd | 13 | 4114 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/board_Papilio_Pro/sdram_wrap.vhd | 13 | 4114 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/sid_components.vhd | 13 | 2504 | -------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits,
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
--Implementation Digital to Analog converter
entity pwm_sddac is
generic (
msbi_g : integer := 9
);
port (
clk_i : in std_logic;
reset : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end pwm_sddac;
architecture rtl of pwm_sddac is
signal sig_in : unsigned(msbi_g+2 downto 0) := (others => '0');
begin
seq: process (clk_i, reset)
begin
if reset = '1' then
sig_in <= to_unsigned(2**(msbi_g+1), sig_in'length);
dac_o <= '0';
elsif rising_edge(clk_i) then
sig_in <= sig_in + unsigned(sig_in(msbi_g+2) & sig_in(msbi_g+2) & dac_i);
dac_o <= sig_in(msbi_g+2);
end if;
end process seq;
end rtl;
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end pwm_sdadc;
-- Dummy implementation (no real A/D conversion performed)
architecture rtl of pwm_sdadc is
begin
process (clk, ADC_in)
begin
if ADC_in = '1' then
ADC_out <= (others => '1');
else
ADC_out <= (others => '0');
end if;
end process;
end rtl;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/sid_components.vhd | 13 | 2504 | -------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits,
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
--Implementation Digital to Analog converter
entity pwm_sddac is
generic (
msbi_g : integer := 9
);
port (
clk_i : in std_logic;
reset : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end pwm_sddac;
architecture rtl of pwm_sddac is
signal sig_in : unsigned(msbi_g+2 downto 0) := (others => '0');
begin
seq: process (clk_i, reset)
begin
if reset = '1' then
sig_in <= to_unsigned(2**(msbi_g+1), sig_in'length);
dac_o <= '0';
elsif rising_edge(clk_i) then
sig_in <= sig_in + unsigned(sig_in(msbi_g+2) & sig_in(msbi_g+2) & dac_i);
dac_o <= sig_in(msbi_g+2);
end if;
end process seq;
end rtl;
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end pwm_sdadc;
-- Dummy implementation (no real A/D conversion performed)
architecture rtl of pwm_sdadc is
begin
process (clk, ADC_in)
begin
if ADC_in = '1' then
ADC_out <= (others => '1');
else
ADC_out <= (others => '0');
end if;
end process;
end rtl;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/sid_filters.vhd | 13 | 6581 | --
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Wishbone_Peripherals/clk_32to100_dcm.vhd | 13 | 6307 | -- file: clk_32to100_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to100_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to100_dcm;
architecture xilinx of clk_32to100_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to100_dcm,clk_wiz_v3_6,{component_name=clk_32to100_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 8,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/transmitter.vhd | 13 | 4797 | ----------------------------------------------------------------------------------
-- transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the serial port.
-- End of transmission is signalled by taking back the busy flag.
-- Supports xon/xoff flow control.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity transmitter is
generic (
FREQ : integer;
RATE : integer
);
Port (
data : in STD_LOGIC_VECTOR (31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : in std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in std_logic;
tx : out STD_LOGIC;
busy: out std_logic
-- pause: out std_logic
);
end transmitter;
architecture Behavioral of transmitter is
type TX_STATES is (IDLE, SEND, POLL);
-- constant BITLENGTH : integer := FREQ / RATE; --FREQ = 100000000/28=3571428 : RATE = 115200 : FREQ/RATE = 3571428/115200 = 31
constant BITLENGTH : integer := 16;
signal dataBuffer : STD_LOGIC_VECTOR (31 downto 0);
signal disabledBuffer : std_logic_vector (3 downto 0);
signal txBuffer : std_logic_vector (9 downto 0) := "1000000000";
signal byte : std_logic_vector (7 downto 0);
signal counter : integer range 0 to BITLENGTH;
signal bits : integer range 0 to 10;
signal bytes : integer range 0 to 4;
signal state : TX_STATES;
signal paused, writeByte, byteDone, disabled : std_logic;
begin
-- pause <= paused;
tx <= txBuffer(0);
-- sends one byte
process(clock)
begin
if rising_edge(clock) then
if writeByte = '1' then
counter <= 0;
bits <= 0;
byteDone <= disabled;
txBuffer <= '1' & byte & "0";
elsif counter = BITLENGTH then
counter <= 0;
txBuffer <= '1' & txBuffer(9 downto 1);
if bits = 10 then
byteDone <= '1';
else
bits <= bits + 1;
end if;
elsif trxClock = '1' then
counter <= counter + 1;
end if;
end if;
end process;
-- control mechanism for sending a 32 bit word
process(clock, reset)
begin
if reset = '1' then
writeByte <= '0';
state <= IDLE;
dataBuffer <= (others => '0');
disabledBuffer <= (others => '0');
elsif rising_edge(clock) then
if (state /= IDLE) or (write = '1') or (paused = '1') then
busy <= '1';
else
busy <= '0';
end if;
case state is
-- when write is '1', data will be available with next cycle
when IDLE =>
if write = '1' then
dataBuffer <= data;
disabledBuffer <= disabledGroups;
state <= SEND;
bytes <= 0;
elsif id = '1' then
dataBuffer <= x"534c4131";
disabledBuffer <= "0000";
state <= SEND;
bytes <= 0;
end if;
when SEND =>
if bytes = 4 then
state <= IDLE;
else
bytes <= bytes + 1;
case bytes is
when 0 =>
byte <= dataBuffer(7 downto 0);
disabled <= disabledBuffer(0);
when 1 =>
byte <= dataBuffer(15 downto 8);
disabled <= disabledBuffer(1);
when 2 =>
byte <= dataBuffer(23 downto 16);
disabled <= disabledBuffer(2);
when others =>
byte <= dataBuffer(31 downto 24);
disabled <= disabledBuffer(3);
end case;
writeByte <= '1';
state <= POLL;
end if;
when POLL =>
writeByte <= '0';
if byteDone = '1' and writeByte = '0' and paused = '0' then
state <= SEND;
end if;
end case;
end if;
end process;
-- set paused mode according to xon/xoff commands
process(clock, reset)
begin
if reset = '1' then
paused <= '0';
elsif rising_edge(clock) then
if xon = '1' then
paused <= '0';
elsif xoff = '1' then
paused <= '1';
end if;
end if;
end process;
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Benchy/transmitter.vhd | 13 | 4797 | ----------------------------------------------------------------------------------
-- transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the serial port.
-- End of transmission is signalled by taking back the busy flag.
-- Supports xon/xoff flow control.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity transmitter is
generic (
FREQ : integer;
RATE : integer
);
Port (
data : in STD_LOGIC_VECTOR (31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : in std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in std_logic;
tx : out STD_LOGIC;
busy: out std_logic
-- pause: out std_logic
);
end transmitter;
architecture Behavioral of transmitter is
type TX_STATES is (IDLE, SEND, POLL);
-- constant BITLENGTH : integer := FREQ / RATE; --FREQ = 100000000/28=3571428 : RATE = 115200 : FREQ/RATE = 3571428/115200 = 31
constant BITLENGTH : integer := 16;
signal dataBuffer : STD_LOGIC_VECTOR (31 downto 0);
signal disabledBuffer : std_logic_vector (3 downto 0);
signal txBuffer : std_logic_vector (9 downto 0) := "1000000000";
signal byte : std_logic_vector (7 downto 0);
signal counter : integer range 0 to BITLENGTH;
signal bits : integer range 0 to 10;
signal bytes : integer range 0 to 4;
signal state : TX_STATES;
signal paused, writeByte, byteDone, disabled : std_logic;
begin
-- pause <= paused;
tx <= txBuffer(0);
-- sends one byte
process(clock)
begin
if rising_edge(clock) then
if writeByte = '1' then
counter <= 0;
bits <= 0;
byteDone <= disabled;
txBuffer <= '1' & byte & "0";
elsif counter = BITLENGTH then
counter <= 0;
txBuffer <= '1' & txBuffer(9 downto 1);
if bits = 10 then
byteDone <= '1';
else
bits <= bits + 1;
end if;
elsif trxClock = '1' then
counter <= counter + 1;
end if;
end if;
end process;
-- control mechanism for sending a 32 bit word
process(clock, reset)
begin
if reset = '1' then
writeByte <= '0';
state <= IDLE;
dataBuffer <= (others => '0');
disabledBuffer <= (others => '0');
elsif rising_edge(clock) then
if (state /= IDLE) or (write = '1') or (paused = '1') then
busy <= '1';
else
busy <= '0';
end if;
case state is
-- when write is '1', data will be available with next cycle
when IDLE =>
if write = '1' then
dataBuffer <= data;
disabledBuffer <= disabledGroups;
state <= SEND;
bytes <= 0;
elsif id = '1' then
dataBuffer <= x"534c4131";
disabledBuffer <= "0000";
state <= SEND;
bytes <= 0;
end if;
when SEND =>
if bytes = 4 then
state <= IDLE;
else
bytes <= bytes + 1;
case bytes is
when 0 =>
byte <= dataBuffer(7 downto 0);
disabled <= disabledBuffer(0);
when 1 =>
byte <= dataBuffer(15 downto 8);
disabled <= disabledBuffer(1);
when 2 =>
byte <= dataBuffer(23 downto 16);
disabled <= disabledBuffer(2);
when others =>
byte <= dataBuffer(31 downto 24);
disabled <= disabledBuffer(3);
end case;
writeByte <= '1';
state <= POLL;
end if;
when POLL =>
writeByte <= '0';
if byteDone = '1' and writeByte = '0' and paused = '0' then
state <= SEND;
end if;
end case;
end if;
end process;
-- set paused mode according to xon/xoff commands
process(clock, reset)
begin
if reset = '1' then
paused <= '0';
elsif rising_edge(clock) then
if xon = '1' then
paused <= '0';
elsif xoff = '1' then
paused <= '1';
end if;
end if;
end process;
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/Benchy/transmitter.vhd | 13 | 4797 | ----------------------------------------------------------------------------------
-- transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the serial port.
-- End of transmission is signalled by taking back the busy flag.
-- Supports xon/xoff flow control.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity transmitter is
generic (
FREQ : integer;
RATE : integer
);
Port (
data : in STD_LOGIC_VECTOR (31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : in std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in std_logic;
tx : out STD_LOGIC;
busy: out std_logic
-- pause: out std_logic
);
end transmitter;
architecture Behavioral of transmitter is
type TX_STATES is (IDLE, SEND, POLL);
-- constant BITLENGTH : integer := FREQ / RATE; --FREQ = 100000000/28=3571428 : RATE = 115200 : FREQ/RATE = 3571428/115200 = 31
constant BITLENGTH : integer := 16;
signal dataBuffer : STD_LOGIC_VECTOR (31 downto 0);
signal disabledBuffer : std_logic_vector (3 downto 0);
signal txBuffer : std_logic_vector (9 downto 0) := "1000000000";
signal byte : std_logic_vector (7 downto 0);
signal counter : integer range 0 to BITLENGTH;
signal bits : integer range 0 to 10;
signal bytes : integer range 0 to 4;
signal state : TX_STATES;
signal paused, writeByte, byteDone, disabled : std_logic;
begin
-- pause <= paused;
tx <= txBuffer(0);
-- sends one byte
process(clock)
begin
if rising_edge(clock) then
if writeByte = '1' then
counter <= 0;
bits <= 0;
byteDone <= disabled;
txBuffer <= '1' & byte & "0";
elsif counter = BITLENGTH then
counter <= 0;
txBuffer <= '1' & txBuffer(9 downto 1);
if bits = 10 then
byteDone <= '1';
else
bits <= bits + 1;
end if;
elsif trxClock = '1' then
counter <= counter + 1;
end if;
end if;
end process;
-- control mechanism for sending a 32 bit word
process(clock, reset)
begin
if reset = '1' then
writeByte <= '0';
state <= IDLE;
dataBuffer <= (others => '0');
disabledBuffer <= (others => '0');
elsif rising_edge(clock) then
if (state /= IDLE) or (write = '1') or (paused = '1') then
busy <= '1';
else
busy <= '0';
end if;
case state is
-- when write is '1', data will be available with next cycle
when IDLE =>
if write = '1' then
dataBuffer <= data;
disabledBuffer <= disabledGroups;
state <= SEND;
bytes <= 0;
elsif id = '1' then
dataBuffer <= x"534c4131";
disabledBuffer <= "0000";
state <= SEND;
bytes <= 0;
end if;
when SEND =>
if bytes = 4 then
state <= IDLE;
else
bytes <= bytes + 1;
case bytes is
when 0 =>
byte <= dataBuffer(7 downto 0);
disabled <= disabledBuffer(0);
when 1 =>
byte <= dataBuffer(15 downto 8);
disabled <= disabledBuffer(1);
when 2 =>
byte <= dataBuffer(23 downto 16);
disabled <= disabledBuffer(2);
when others =>
byte <= dataBuffer(31 downto 24);
disabled <= disabledBuffer(3);
end case;
writeByte <= '1';
state <= POLL;
end if;
when POLL =>
writeByte <= '0';
if byteDone = '1' and writeByte = '0' and paused = '0' then
state <= SEND;
end if;
end case;
end if;
end process;
-- set paused mode according to xon/xoff commands
process(clock, reset)
begin
if reset = '1' then
paused <= '0';
elsif rising_edge(clock) then
if xon = '1' then
paused <= '0';
elsif xoff = '1' then
paused <= '1';
end if;
end if;
end process;
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/zpu_core_extreme.vhd | 13 | 42722 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
-- Copyright 2010-2012 Alvaro Lopes - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.wishbonepkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
break: out std_logic;
-- STACK
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_writeenable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end zpu_core_extreme;
architecture behave of zpu_core_extreme is
component lshifter is
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end component;
signal lshifter_enable: std_logic;
signal lshifter_done: std_logic;
signal lshifter_input: std_logic_vector(31 downto 0);
signal lshifter_amount: std_logic_vector(31 downto 0);
signal lshifter_output: std_logic_vector(63 downto 0);
signal lshifter_multorshift: std_logic;
signal begin_inst: std_logic;
signal trace_opcode: std_logic_vector(7 downto 0);
signal trace_pc: std_logic_vector(maxAddrBitIncIO downto 0);
signal trace_sp: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal trace_topOfStack: std_logic_vector(wordSize-1 downto 0);
signal trace_topOfStackB: std_logic_vector(wordSize-1 downto 0);
-- state machine.
type State_Type is
(
State_Execute,
State_Store,
State_StoreB,
State_StoreB2,
State_Load,
State_LoadMemory,
State_LoadStack,
State_Loadb,
State_Resync1,
State_Resync2,
State_LoadSP,
State_WaitSPB,
State_ResyncFromStoreStack,
State_Neqbranch,
State_Ashiftleft,
State_Mult,
State_MultF16
);
type DecodedOpcodeType is
(
Decoded_Nop,
Decoded_Idle,
Decoded_Im0,
Decoded_ImN,
Decoded_LoadSP,
Decoded_Dup,
Decoded_DupStackB,
Decoded_StoreSP,
Decoded_Pop,
Decoded_PopDown,
Decoded_AddSP,
Decoded_AddStackB,
Decoded_Shift,
Decoded_Emulate,
Decoded_Break,
Decoded_PushSP,
Decoded_PopPC,
Decoded_Add,
Decoded_Or,
Decoded_And,
Decoded_Load,
Decoded_Not,
Decoded_Flip,
Decoded_Store,
Decoded_PopSP,
Decoded_Interrupt,
Decoded_Neqbranch,
Decoded_Eq,
Decoded_Storeb,
Decoded_Storeh,
Decoded_Ulessthan,
Decoded_Lessthan,
Decoded_Ashiftleft,
Decoded_Ashiftright,
Decoded_Loadb,
Decoded_Call,
Decoded_Mult,
Decoded_MultF16
);
constant spMaxBit: integer := 10;
constant minimal_implementation: boolean := false;
subtype index is integer range 0 to 3;
signal tOpcode_sel : index;
function pc_to_cpuword(pc: unsigned) return unsigned is
variable r: unsigned(wordSize-1 downto 0);
begin
r := (others => DontCareValue);
r(maxAddrBit downto 0) := pc;
return r;
end pc_to_cpuword;
function pc_to_memaddr(pc: unsigned) return unsigned is
variable r: unsigned(maxAddrBit downto 0);
begin
r := (others => '0');
r(maxAddrBit downto minAddrBit) := pc(maxAddrBit downto minAddrBit);
return r;
end pc_to_memaddr;
-- Prefetch stage registers
type stackChangeType is (
Stack_Same,
Stack_Push,
Stack_Pop,
Stack_DualPop
);
type tosSourceType is
(
Tos_Source_PC,
Tos_Source_FetchPC,
Tos_Source_Idim0,
Tos_Source_IdimN,
Tos_Source_StackB,
Tos_Source_SP,
Tos_Source_Add,
Tos_Source_And,
Tos_Source_Or,
Tos_Source_Eq,
Tos_Source_Not,
Tos_Source_Flip,
Tos_Source_LoadSP,
Tos_Source_AddSP,
Tos_Source_AddStackB,
Tos_Source_Shift,
Tos_Source_Ulessthan,
Tos_Source_Lessthan,
Tos_Source_None
);
type decoderstate_type is (
State_Run,
State_Jump,
State_Inject,
State_InjectJump
);
type decoderegs_type is record
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opWillFreeze: std_logic; -- '1' if we know in advance this opcode will freeze pipeline
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
pcint: unsigned(maxAddrBit downto 0);
idim: std_logic;
im: std_logic;
stackOperation: stackChangeType;
spOffset: unsigned(4 downto 0);
im_emu: std_logic;
--emumode: std_logic;
break: std_logic;
state: decoderstate_type;
end record;
type prefetchregs_type is record
sp: unsigned(spMaxBit downto 2);
spnext: unsigned(spMaxBit downto 2);
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
idim: std_logic;
break: std_logic;
load: std_logic;
opWillFreeze: std_logic;
recompute_sp: std_logic;
end record;
type exuregs_type is record
idim: std_logic;
break: std_logic;
inInterrupt:std_logic;
tos: unsigned(wordSize-1 downto 0);
tos_save: unsigned(wordSize-1 downto 0);
nos_save: unsigned(wordSize-1 downto 0);
state: State_Type;
-- Wishbone control signals (registered)
wb_cyc: std_logic;
wb_stb: std_logic;
wb_we: std_logic;
end record;
-- Registers for each stage
signal exr: exuregs_type;
signal prefr: prefetchregs_type;
signal decr: decoderegs_type;
signal pcnext: unsigned(maxAddrBit downto 0); -- Helper only. TODO: move into variable
signal sp_load: unsigned(spMaxBit downto 2); -- SP value to load, coming from EXU into PFU
signal decode_load_sp: std_logic; -- Load SP signal from EXU to PFU
signal exu_busy: std_logic; -- EXU busy ( stalls PFU )
signal pfu_busy: std_logic; -- PFU busy ( stalls DFU )
signal decode_jump: std_logic; -- Jump signal from EXU to DFU
signal jump_address: unsigned(maxAddrBit downto 0); -- Jump address from EXU to DFU
signal do_interrupt: std_logic; -- Helper.
-- Sampled signals from the opcode. Left as signals
-- in order to simulate design.
signal sampledOpcode: std_logic_vector(OpCode_Size-1 downto 0);
signal sampledDecodedOpcode: DecodedOpcodeType;
signal sampledOpWillFreeze: std_logic;
signal sampledStackOperation: stackChangeType;
signal sampledspOffset: unsigned(4 downto 0);
signal sampledTosSource: tosSourceType;
signal nos: unsigned(wordSize-1 downto 0); -- This is only a helper
signal wroteback_q: std_logic; -- TODO: get rid of this here, move to EXU regs
-- Test debug signals
signal freeze_all: std_logic := '0';
signal single_step: std_logic := '0';
begin
-- Debug interface
dbg_out.pc <= std_logic_vector(prefr.pc);
dbg_out.opcode <= prefr.opcode;
dbg_out.sp <= std_logic_vector(prefr.sp);
dbg_out.brk <= exr.break;
dbg_out.stacka <= std_logic_vector(exr.tos);
dbg_out.stackb <= std_logic_vector(nos);
dbg_out.idim <= prefr.idim;
shl: lshifter
port map (
clk => wb_clk_i,
rst => wb_rst_i,
enable => lshifter_enable,
done => lshifter_done,
inputA => lshifter_input,
inputB => lshifter_amount,
output => lshifter_output,
multorshift => lshifter_multorshift
);
stack_clk <= wb_clk_i;
traceFileGenerate:
if Generate_Trace generate
trace_file: trace
port map (
clk => wb_clk_i,
begin_inst => begin_inst,
pc => trace_pc,
opcode => trace_opcode,
sp => trace_sp,
memA => trace_topOfStack,
memB => trace_topOfStackB,
busy => '0',--busy,
intsp => (others => 'U')
);
end generate;
tOpcode_sel <= to_integer(decr.pcint(minAddrBit-1 downto 0));
do_interrupt <= '1' when wb_inta_i='1'
and exr.inInterrupt='0'
else '0';
decodeControl:
process(rom_wb_dat_i, tOpcode_sel, sp_load, decr,
do_interrupt, dbg_in.inject, dbg_in.opcode)
variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
variable localspOffset: unsigned(4 downto 0);
begin
if dbg_in.inject='1' then
tOpcode := dbg_in.opcode;
else
case (tOpcode_sel) is
when 0 => tOpcode := std_logic_vector(rom_wb_dat_i(31 downto 24));
when 1 => tOpcode := std_logic_vector(rom_wb_dat_i(23 downto 16));
when 2 => tOpcode := std_logic_vector(rom_wb_dat_i(15 downto 8));
when 3 => tOpcode := std_logic_vector(rom_wb_dat_i(7 downto 0));
when others =>
null;
end case;
end if;
sampledOpcode <= tOpcode;
sampledStackOperation <= Stack_Same;
sampledTosSource <= Tos_Source_None;
sampledOpWillFreeze <= '0';
localspOffset(4):=not tOpcode(4);
localspOffset(3 downto 0) := unsigned(tOpcode(3 downto 0));
if do_interrupt='1' and decr.im='0' then
sampledDecodedOpcode <= Decoded_Interrupt;
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_PC;
else
if (tOpcode(7 downto 7)=OpCode_Im) then
if decr.im='0' then
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_Idim0;
sampledDecodedOpcode<=Decoded_Im0;
else
sampledTosSource <= Tos_Source_IdimN;
sampledDecodedOpcode<=Decoded_ImN;
end if;
elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
sampledStackOperation <= Stack_Pop;
sampledTosSource <= Tos_Source_StackB;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Pop;
sampledTosSource <= Tos_Source_StackB;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_PopDown;
sampledTosSource <= Tos_Source_None;
else
sampledDecodedOpcode<=Decoded_StoreSP;
sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_StackB;
end if;
elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
sampledStackOperation <= Stack_Push;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Dup;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_DupStackB;
sampledTosSource <= Tos_Source_StackB;
else
sampledDecodedOpcode<=Decoded_LoadSP;
sampledTosSource <= Tos_Source_LoadSP;
end if;
elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
-- Emulated instructions implemented in hardware
if minimal_implementation then
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
else
if (tOpcode(5 downto 0)=OpCode_Loadb) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadb;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Neqbranch) then
sampledStackOperation<=Stack_DualPop;
sampledDecodedOpcode<=Decoded_Neqbranch;
sampledOpWillFreeze <= '1';
elsif (tOpcode(5 downto 0)=OpCode_Call) then
sampledDecodedOpcode<=Decoded_Call;
sampledStackOperation<=Stack_Same;
sampledTosSource<=Tos_Source_FetchPC;
elsif (tOpcode(5 downto 0)=OpCode_Eq) then
sampledDecodedOpcode<=Decoded_Eq;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Eq;
elsif (tOpcode(5 downto 0)=OpCode_Ulessthan) then
sampledDecodedOpcode<=Decoded_Ulessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Ulessthan;
elsif (tOpcode(5 downto 0)=OpCode_Lessthan) then
sampledDecodedOpcode<=Decoded_Lessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Lessthan;
elsif (tOpcode(5 downto 0)=OpCode_StoreB) then
sampledDecodedOpcode<=Decoded_StoreB;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Mult) then
sampledDecodedOpcode<=Decoded_Mult;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Ashiftleft) then
sampledDecodedOpcode<=Decoded_Ashiftleft;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
end if;
end if;
elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Shift;
sampledTosSource <= Tos_Source_Shift;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_AddStackB;
sampledTosSource <= Tos_Source_AddStackB;
else
sampledDecodedOpcode<=Decoded_AddSP;
sampledTosSource <= Tos_Source_AddSP;
end if;
else
case tOpcode(3 downto 0) is
when OpCode_Break =>
sampledDecodedOpcode<=Decoded_Break;
sampledOpWillFreeze <= '1';
when OpCode_PushSP =>
sampledStackOperation <= Stack_Push;
sampledDecodedOpcode<=Decoded_PushSP;
sampledTosSource <= Tos_Source_SP;
when OpCode_PopPC =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_PopPC;
sampledTosSource <= Tos_Source_StackB;
when OpCode_Add =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Add;
sampledTosSource <= Tos_Source_Add;
when OpCode_Or =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Or;
sampledTosSource <= Tos_Source_Or;
when OpCode_And =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_And;
sampledTosSource <= Tos_Source_And;
when OpCode_Load =>
sampledDecodedOpcode<=Decoded_Load;
sampledOpWillFreeze<='1';
when OpCode_Not =>
sampledDecodedOpcode<=Decoded_Not;
sampledTosSource <= Tos_Source_Not;
when OpCode_Flip =>
sampledDecodedOpcode<=Decoded_Flip;
sampledTosSource <= Tos_Source_Flip;
when OpCode_Store =>
sampledStackOperation <= Stack_DualPop;
sampledDecodedOpcode<=Decoded_Store;
sampledOpWillFreeze<='1';
when OpCode_PopSP =>
sampledDecodedOpcode<=Decoded_PopSP;
sampledOpWillFreeze<='1';
when OpCode_NA4 =>
if enable_fmul16 then
sampledDecodedOpcode<=Decoded_MultF16;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Nop;
end if;
when others =>
sampledDecodedOpcode<=Decoded_Nop;
end case;
end if;
end if;
sampledspOffset <= localspOffset;
end process;
-- Decode/Fetch unit
rom_wb_stb_o <= not exu_busy;
process(decr, jump_address, decode_jump, wb_clk_i, sp_load,
sampledDecodedOpcode,sampledOpcode,decode_load_sp,
exu_busy, pfu_busy,
pcnext, rom_wb_ack_i, wb_rst_i, sampledStackOperation, sampledspOffset,
sampledTosSource, prefr.recompute_sp, sampledOpWillFreeze,
dbg_in.flush, dbg_in.inject,dbg_in.injectmode,
prefr.valid, prefr.break, rom_wb_stall_i
)
variable w: decoderegs_type;
begin
w := decr;
pcnext <= decr.fetchpc + 1;
rom_wb_adr_o <= std_logic_vector(pc_to_memaddr(decr.fetchpc));
rom_wb_cti_o <= CTI_CYCLE_INCRADDR;
if wb_rst_i='1' then
w.pc := (others => '0');
w.pcint := (others => '0');
w.valid := '0';
w.fetchpc := (others => '0');
w.im:='0';
w.im_emu:='0';
w.state := State_Run;
w.break := '0';
rom_wb_cyc_o <= '0';
else
rom_wb_cyc_o <= '1';
case decr.state is
when State_Run =>
if pfu_busy='0' then
if dbg_in.injectmode='0' and decr.break='0' and rom_wb_stall_i='0' then
w.fetchpc := pcnext;
end if;
-- Jump request
if decode_jump='1' then
w.valid := '0';
w.im := '0';
w.break := '0'; -- Invalidate eventual break after branch instruction
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
rom_wb_cyc_o<='0';
--if rom_wb_stall_i='0' then
w.fetchpc := jump_address;
--else
w.state := State_Jump;
--end if;
else
if dbg_in.injectmode='1' then --or decr.break='1' then
-- At this point we ought to push a new op into the pipeline.
-- Since we're entering inject mode, invalidate next operation,
-- but save the current IM flag.
w.im_emu := decr.im;
w.valid := '0';
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
rom_wb_cyc_o <='0';
-- Wait until no work is to be done
if prefr.valid='0' and decr.valid='0' and exu_busy='0' then
w.state := State_Inject;
w.im:='0';
end if;
if decr.break='0' then
w.pc := decr.pcint;
end if;
else
if decr.break='1' then
w.valid := '0';
else
w.valid := rom_wb_ack_i;
end if;
if rom_wb_ack_i='1' then
w.im := sampledOpcode(7);
if sampledDecodedOpcode=Decoded_Break then
w.break:='1';
end if;
end if;
if prefr.break='0' and rom_wb_stall_i='0' then
w.pcint := decr.fetchpc;
w.pc := decr.pcint;
end if;
if rom_wb_stall_i='0' then
w.opcode := sampledOpcode;
end if;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
when State_Jump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Run;
when State_InjectJump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Inject;
when State_Inject =>
-- NOTE: disable ROM
rom_wb_cyc_o <= '0';
if dbg_in.injectmode='0' then
w.im := decr.im_emu;
w.fetchpc := decr.pcint;
w.state := State_Run;
w.break := '0';
else
-- Handle opcode injection
-- TODO: merge this with main decode.
-- NOTE: we don't check busy here, it's up to debug unit to do it
--if pfu_busy='0' then
--w.fetchpc := pcnext;
-- Jump request
if decode_jump='1' then
w.fetchpc := jump_address;
w.valid := '0';
w.im := '0';
w.state := State_InjectJump;
else
w.valid := dbg_in.inject;
if dbg_in.inject='1' then
w.im := sampledOpcode(7);
--w.break := '0';
--w.pcint := decr.fetchpc;
w.opcode := sampledOpcode;
--w.pc := decr.pcint;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
--end if;
end case;
end if; -- rst
if rising_edge(wb_clk_i) then
decr <= w;
end if;
end process;
-- Prefetch/Load unit.
sp_load <= exr.tos(spMaxBit downto 2); -- Will be delayed one clock cycle
process(wb_clk_i, wb_rst_i, decr, prefr, exu_busy, decode_jump, sp_load,
decode_load_sp, dbg_in.flush)
variable w: prefetchregs_type;
variable i_op_freeze: std_logic;
begin
w := prefr;
pfu_busy<='0';
stack_b_addr <= std_logic_vector(prefr.spnext + 1);
w.recompute_sp:='0';
-- Stack
w.load := decode_load_sp;
if decode_load_sp='1' then
pfu_busy <= '1';
w.spnext := sp_load;
w.recompute_sp := '1';
else
pfu_busy <= exu_busy;
if decr.valid='1' then
if (exu_busy='0' and decode_jump='0') or prefr.recompute_sp='1' then
case decr.stackOperation is
when Stack_Push =>
w.spnext := prefr.spnext - 1;
when Stack_Pop =>
w.spnext := prefr.spnext + 1;
when Stack_DualPop =>
w.spnext := prefr.spnext + 2;
when others =>
end case;
w.sp := prefr.spnext;
end if;
end if;
end if;
case decr.decodedOpcode is
when Decoded_LoadSP | decoded_AddSP =>
stack_b_addr <= std_logic_vector(prefr.spnext + decr.spOffset);
when others =>
end case;
if decode_jump='1' then -- this is a pipeline "invalidate" flag.
w.valid := '0';
else
if dbg_in.flush='1' then
w.valid := '0';
else
w.valid := decr.valid;
end if;
end if;
-- Moved op_will_freeze from decoder to here
case decr.decodedOpcode is
when Decoded_StoreSP
| Decoded_LoadB
| Decoded_Neqbranch
| Decoded_StoreB
| Decoded_Mult
| Decoded_Ashiftleft
| Decoded_Break
| Decoded_Load
| Decoded_Store
| Decoded_PopSP
| Decoded_MultF16 =>
i_op_freeze := '1';
when others =>
i_op_freeze := '0';
end case;
if exu_busy='0' then
w.decodedOpcode := decr.decodedOpcode;
w.tosSource := decr.tosSource;
w.opcode := decr.opcode;
w.opWillFreeze := i_op_freeze;
w.pc := decr.pc;
w.fetchpc := decr.pcint;
w.idim := decr.idim;
w.break := decr.break;
end if;
if wb_rst_i='1' then
w.spnext := unsigned(spStart(10 downto 2));
--w.sp := unsigned(spStart(10 downto 2));
w.valid := '0';
w.idim := '0';
w.recompute_sp:='0';
end if;
if rising_edge(wb_clk_i) then
prefr <= w;
end if;
end process;
process(prefr,exr,nos)
begin
trace_pc <= (others => '0');
trace_pc(maxAddrBit downto 0) <= std_logic_vector(prefr.pc);
trace_opcode <= prefr.opcode;
trace_sp <= (others => '0');
trace_sp(10 downto 2) <= std_logic_vector(prefr.sp);
trace_topOfStack <= std_logic_vector( exr.tos );
trace_topOfStackB <= std_logic_vector( nos );
end process;
-- IO/Memory Accesses
wb_adr_o(maxAddrBitIncIO downto 0) <= std_logic_vector(exr.tos_save(maxAddrBitIncIO downto 0));
wb_cyc_o <= exr.wb_cyc;
wb_stb_o <= exr.wb_stb;
wb_we_o <= exr.wb_we;
wb_dat_o <= std_logic_vector( exr.nos_save );
freeze_all <= dbg_in.freeze;
process(exr, wb_inta_i, wb_clk_i, wb_rst_i, pcnext, stack_a_read,stack_b_read,
wb_ack_i, wb_dat_i, do_interrupt,exr, prefr, nos,
single_step, freeze_all, dbg_in.step, wroteback_q,lshifter_done,lshifter_output
)
variable spOffset: unsigned(4 downto 0);
variable w: exuregs_type;
variable instruction_executed: std_logic;
variable wroteback: std_logic;
begin
w := exr;
instruction_executed := '0'; -- used for single stepping
stack_b_writeenable <= '0';
stack_a_enable <= '1';
stack_b_enable <= '1';
exu_busy <= '0';
decode_jump <= '0';
jump_address <= (others => DontCareValue);
lshifter_enable <= '0';
lshifter_amount <= std_logic_vector(exr.tos_save);
lshifter_input <= std_logic_vector(exr.nos_save);
lshifter_multorshift <= '0';
poppc_inst <= '0';
begin_inst<='0';
stack_a_addr <= std_logic_vector( prefr.sp );
stack_a_writeenable <= '0';
wroteback := wroteback_q;
stack_b_writeenable <= '0';
stack_a_write <= std_logic_vector(exr.tos);
spOffset(4):=not prefr.opcode(4);
spOffset(3 downto 0) := unsigned(prefr.opcode(3 downto 0));
if wb_inta_i='0' then
w.inInterrupt := '0';
end if;
stack_b_write<=(others => DontCareValue);
if wroteback_q='1' then
nos <= unsigned(stack_a_read);
else
nos <= unsigned(stack_b_read);
end if;
decode_load_sp <= '0';
case exr.state is
when State_Resync1 =>
exu_busy <= '1';
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_ResyncFromStoreStack =>
exu_busy <= '1';
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_Resync2 =>
w.tos := unsigned(stack_a_read);
instruction_executed := '1';
exu_busy <= '0';
wroteback := '0';
stack_b_enable <= '1';
w.state := State_Execute;
when State_Execute =>
instruction_executed:='0';
if prefr.valid='1' then
exu_busy <= prefr.opWillFreeze;
if freeze_all='0' or single_step='1' then
wroteback := '0';
w.nos_save := nos;
w.tos_save := exr.tos;
w.idim := prefr.idim;
w.break:= prefr.break;
begin_inst<='1';
instruction_executed := '1';
-- TOS big muxer
case prefr.tosSource is
when Tos_Source_PC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.pc;
when Tos_Source_FetchPC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.fetchpc;
when Tos_Source_Idim0 =>
for i in wordSize-1 downto 7 loop
w.tos(i) := prefr.opcode(6);
end loop;
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_IdimN =>
w.tos(wordSize-1 downto 7) := exr.tos(wordSize-8 downto 0);
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_StackB =>
w.tos := nos;
when Tos_Source_SP =>
w.tos := (others => '0');
w.tos(31) := '1'; -- Stack address
w.tos(10 downto 2) := prefr.sp;
when Tos_Source_Add =>
w.tos := exr.tos + nos;
when Tos_Source_And =>
w.tos := exr.tos and nos;
when Tos_Source_Or =>
w.tos := exr.tos or nos;
when Tos_Source_Eq =>
w.tos := (others => '0');
if nos = exr.tos then
w.tos(0) := '1';
end if;
when Tos_Source_Ulessthan =>
w.tos := (others => '0');
if exr.tos < nos then
w.tos(0) := '1';
end if;
when Tos_Source_Lessthan =>
w.tos := (others => '0');
if signed(exr.tos) < signed(nos) then
w.tos(0) := '1';
end if;
when Tos_Source_Not =>
w.tos := not exr.tos;
when Tos_Source_Flip =>
for i in 0 to wordSize-1 loop
w.tos(i) := exr.tos(wordSize-1-i);
end loop;
when Tos_Source_LoadSP =>
w.tos := unsigned(stack_b_read);
when Tos_Source_AddSP =>
w.tos := w.tos + unsigned(stack_b_read);
when Tos_Source_AddStackB =>
w.tos := w.tos + nos;
when Tos_Source_Shift =>
w.tos := exr.tos + exr.tos;
when others =>
end case;
case prefr.decodedOpcode is
when Decoded_Interrupt =>
w.inInterrupt := '1';
jump_address <= to_unsigned(32, maxAddrBit+1);
decode_jump <= '1';
stack_a_writeenable<='1';
wroteback:='1';
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Im0 =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_ImN =>
when Decoded_Nop =>
when Decoded_PopPC | Decoded_Call =>
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0);
poppc_inst <= '1';
stack_b_enable<='0';
-- Delay
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Emulate =>
decode_jump <= '1';
jump_address <= (others => '0');
jump_address(9 downto 5) <= unsigned(prefr.opcode(4 downto 0));
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_PushSP =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_LoadSP =>
stack_a_writeenable <= '1';
wroteback:='1';
when Decoded_DupStackB =>
stack_a_writeenable <= '1';
wroteback:='1';
when Decoded_Dup =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_AddSP =>
stack_a_writeenable <= '1';
when Decoded_StoreSP =>
stack_a_writeenable <= '1';
wroteback:='1';
stack_a_addr <= std_logic_vector(prefr.sp + spOffset);
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_PopDown =>
stack_a_writeenable<='1';
when Decoded_Pop =>
when Decoded_Ashiftleft =>
w.state := State_Ashiftleft;
when Decoded_Mult =>
w.state := State_Mult;
when Decoded_MultF16 =>
w.state := State_MultF16;
when Decoded_Store =>
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
stack_a_write <= std_logic_vector(nos);
stack_a_writeenable<='1';
w.state := State_ResyncFromStoreStack;
else
w.wb_we := '1';
w.wb_cyc := '1';
w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
stack_a_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_Store;
end if;
when Decoded_Load | Decoded_Loadb | Decoded_StoreB =>
--w.tos_save := exr.tos; -- Byte select
instruction_executed := '0';
wroteback := wroteback_q; -- Keep WB
if exr.tos(wordSize-1)='1' then
stack_a_addr<=std_logic_vector(exr.tos(10 downto 2));
stack_a_enable<='1';
w.state := State_LoadStack;
else
stack_a_enable <= '0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
w.wb_we :='0';
w.wb_cyc :='1';
w.wb_stb :='1';
w.state := State_Load;
end if;
when Decoded_PopSP =>
decode_load_sp <= '1';
instruction_executed := '0';
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
w.state := State_Resync2;
--when Decoded_Break =>
-- w.break := '1';
when Decoded_Neqbranch =>
instruction_executed := '0';
w.state := State_NeqBranch;
when others =>
end case;
else -- freeze_all
--
-- Freeze the entire pipeline.
--
exu_busy<='1';
stack_a_enable<='0';
stack_b_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
end if;
end if; -- valid
when State_Ashiftleft =>
exu_busy <= '1';
lshifter_enable <= '1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_Mult =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_MultF16 =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(47 downto 16));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_WaitSPB =>
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Store =>
exu_busy <= '1';
-- Keep writeback flag
wroteback := wroteback_q;
if wb_ack_i='1' then
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
stack_b_enable<='1';
wroteback := '0';
--exu_busy <= '1';
w.wb_cyc := '0';
w.state := State_Resync2;
else
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_a_enable<='0';
stack_b_enable<='0';
end if;
when State_Loadb =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1 downto 0) is
when "11" =>
w.tos(7 downto 0) := unsigned(exr.tos(7 downto 0));
when "10" =>
w.tos(7 downto 0) := unsigned(exr.tos(15 downto 8));
when "01" =>
w.tos(7 downto 0) := unsigned(exr.tos(23 downto 16));
when "00" =>
w.tos(7 downto 0) := unsigned(exr.tos(31 downto 24));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Load =>
if wb_ack_i='0' then
exu_busy<='1';
else
w.tos := unsigned(wb_dat_i);
w.wb_cyc := '0';
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state := State_Loadb;
elsif prefr.decodedOpcode=Decoded_Storeb then
exu_busy<='1';
w.state := State_Storeb;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
end if;
when State_LoadStack =>
w.tos := unsigned(stack_a_read);
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Storeb then
exu_busy<='1';
w.state:=State_Storeb;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
when State_NeqBranch =>
if exr.nos_save/=0 then
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0) + prefr.pc;
poppc_inst <= '1';
exu_busy <= '0';
else
exu_busy <='1';
end if;
instruction_executed := '0';
stack_a_addr <= std_logic_vector(prefr.spnext);
wroteback:='0';
w.state := State_Resync2;
when State_StoreB =>
exu_busy <= '1';
--
-- At this point, we have loaded the 32-bit, and it's in TOS
-- The IO address is still saved in save_TOS.
-- The original write value is still at save_NOS
--
-- So we mangle the write value, and update save_NOS, and restore
-- the IO address to TOS
--
-- This is still buggy - don't use. Problems arise when writing to stack.
--
w.nos_save := exr.tos;
case exr.tos_save(1 downto 0) is
when "00" =>
w.nos_save(31 downto 24) := exr.nos_save(7 downto 0);
when "01" =>
w.nos_save(23 downto 16) := exr.nos_save(7 downto 0);
when "10" =>
w.nos_save(15 downto 8) := exr.nos_save(7 downto 0);
when "11" =>
w.nos_save(7 downto 0) := exr.nos_save(7 downto 0);
when others =>
null;
end case;
w.tos := exr.tos_save;
w.state := State_StoreB2;
when State_StoreB2 =>
exu_busy <= '1';
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
stack_a_write <= std_logic_vector(exr.nos_save); -- hmm I don't like this
stack_a_writeenable<='1';
w.state := State_ResyncFromStoreStack;
else
w.wb_we := '1';
w.wb_cyc := '1';
w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
stack_a_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_Store;
end if;
when others =>
null;
end case;
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
exr.state <= State_Execute;
exr.idim <= DontCareValue;
exr.inInterrupt <= '0';
exr.break <= '0';
exr.wb_cyc <= '0';
exr.wb_stb <= '1';
else
exr <= w;
-- TODO: move wroteback_q into EXU regs
wroteback_q <= wroteback;
if exr.break='1' then
report "BREAK" severity failure;
end if;
-- Some sanity checks, to be caught in simulation
if prefr.valid='1' then
if prefr.tosSource=Tos_Source_Idim0 and prefr.idim='1' then
report "Invalid IDIM flag 0" severity error;
end if;
if prefr.tosSource=Tos_Source_IdimN and prefr.idim='0' then
report "Invalid IDIM flag 1" severity error;
end if;
end if;
end if;
end if;
end process;
single_step <= dbg_in.step;
dbg_out.valid <= '1' when prefr.valid='1' else '0';
-- Let pipeline finish
dbg_out.ready <= '1' when exr.state=state_execute
and decode_load_sp='0'
and decode_jump='0'
and decr.state = State_Inject
--and jump_q='0'
else '0';
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/zpu_core_extreme_icache.vhd | 13 | 47502 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
-- Copyright 2010-2012 Alvaro Lopes - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.wishbonepkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
break: out std_logic;
-- STACK
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
cache_flush: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end zpu_core_extreme_icache;
architecture behave of zpu_core_extreme_icache is
component lshifter is
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end component;
component zpuino_icache is
generic (
ADDRESS_HIGH: integer := 26
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
valid: out std_logic;
data: out std_logic_vector(wordSize-1 downto 0);
address: in std_logic_vector(maxAddrBit downto 0);
strobe: in std_logic;
enable: in std_logic;
stall: out std_logic;
flush: in std_logic;
-- Master wishbone interface
m_wb_ack_i: in std_logic;
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
m_wb_cyc_o: out std_logic;
m_wb_stb_o: out std_logic;
m_wb_stall_i: in std_logic;
m_wb_we_o: out std_logic
);
end component;
component zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end component;
signal cache_valid: std_logic;
signal cache_data: std_logic_vector(wordSize-1 downto 0);
signal cache_address: std_logic_vector(maxAddrBit downto 0);
signal cache_strobe: std_logic;
signal cache_enable: std_logic;
signal cache_stall: std_logic;
signal lshifter_enable: std_logic;
signal lshifter_done: std_logic;
signal lshifter_input: std_logic_vector(31 downto 0);
signal lshifter_amount: std_logic_vector(31 downto 0);
signal lshifter_output: std_logic_vector(63 downto 0);
signal lshifter_multorshift: std_logic;
signal begin_inst: std_logic;
signal trace_opcode: std_logic_vector(7 downto 0);
signal trace_pc: std_logic_vector(maxAddrBitIncIO downto 0);
signal trace_sp: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal trace_topOfStack: std_logic_vector(wordSize-1 downto 0);
signal trace_topOfStackB: std_logic_vector(wordSize-1 downto 0);
-- state machine.
type State_Type is
(
State_Execute,
State_LoadStack,
State_Loadb,
State_Loadh,
State_Resync2,
State_WaitSPB,
State_ResyncFromStoreStack,
State_Neqbranch,
State_Ashiftleft,
State_Mult,
State_MultF16
);
type DecodedOpcodeType is
(
Decoded_Nop,
Decoded_Idle,
Decoded_Im0,
Decoded_ImN,
Decoded_LoadSP,
Decoded_Dup,
Decoded_DupStackB,
Decoded_StoreSP,
Decoded_Pop,
Decoded_PopDown,
Decoded_AddSP,
Decoded_AddStackB,
Decoded_Shift,
Decoded_Emulate,
Decoded_Break,
Decoded_PushSP,
Decoded_PopPC,
Decoded_Add,
Decoded_Or,
Decoded_And,
Decoded_Load,
Decoded_Not,
Decoded_Flip,
Decoded_Store,
Decoded_PopSP,
Decoded_Interrupt,
Decoded_Neqbranch,
Decoded_Eq,
Decoded_Storeb,
Decoded_Storeh,
Decoded_Ulessthan,
Decoded_Lessthan,
Decoded_Ashiftleft,
Decoded_Ashiftright,
Decoded_Loadb,
Decoded_Loadh,
Decoded_Call,
Decoded_Mult,
Decoded_MultF16
);
constant spMaxBit: integer := stackSize_bits-1;
constant minimal_implementation: boolean := false;
subtype index is integer range 0 to 3;
signal tOpcode_sel : index;
function pc_to_cpuword(pc: unsigned) return unsigned is
variable r: unsigned(wordSize-1 downto 0);
begin
r := (others => DontCareValue);
r(maxAddrBit downto 0) := pc;
return r;
end pc_to_cpuword;
function pc_to_memaddr(pc: unsigned) return unsigned is
variable r: unsigned(maxAddrBit downto 0);
begin
r := (others => '0');
r(maxAddrBit downto minAddrBit) := pc(maxAddrBit downto minAddrBit);
return r;
end pc_to_memaddr;
-- Prefetch stage registers
type stackChangeType is (
Stack_Same,
Stack_Push,
Stack_Pop,
Stack_DualPop
);
type tosSourceType is
(
Tos_Source_PC,
Tos_Source_FetchPC,
Tos_Source_Idim0,
Tos_Source_IdimN,
Tos_Source_StackB,
Tos_Source_SP,
Tos_Source_Add,
Tos_Source_And,
Tos_Source_Or,
Tos_Source_Eq,
Tos_Source_Not,
Tos_Source_Flip,
Tos_Source_LoadSP,
Tos_Source_AddSP,
Tos_Source_AddStackB,
Tos_Source_Shift,
Tos_Source_Ulessthan,
Tos_Source_Lessthan,
Tos_Source_LSU,
Tos_Source_None
);
type decoderstate_type is (
State_Run,
State_Jump,
State_Inject,
State_InjectJump
);
type decoderegs_type is record
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opWillFreeze: std_logic; -- '1' if we know in advance this opcode will freeze pipeline
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
pcint: unsigned(maxAddrBit downto 0);
idim: std_logic;
im: std_logic;
stackOperation: stackChangeType;
spOffset: unsigned(4 downto 0);
im_emu: std_logic;
--emumode: std_logic;
break: std_logic;
state: decoderstate_type;
end record;
type prefetchregs_type is record
sp: unsigned(spMaxBit downto 2);
spnext: unsigned(spMaxBit downto 2);
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
idim: std_logic;
break: std_logic;
load: std_logic;
opWillFreeze: std_logic;
recompute_sp: std_logic;
end record;
type exuregs_type is record
idim: std_logic;
break: std_logic;
inInterrupt:std_logic;
tos: unsigned(wordSize-1 downto 0);
tos_save: unsigned(wordSize-1 downto 0);
nos_save: unsigned(wordSize-1 downto 0);
state: State_Type;
-- Wishbone control signals (registered)
wb_cyc: std_logic;
wb_stb: std_logic;
wb_we: std_logic;
end record;
-- Registers for each stage
signal exr: exuregs_type;
signal prefr: prefetchregs_type;
signal decr: decoderegs_type;
signal pcnext: unsigned(maxAddrBit downto 0); -- Helper only. TODO: move into variable
signal sp_load: unsigned(spMaxBit downto 2); -- SP value to load, coming from EXU into PFU
signal decode_load_sp: std_logic; -- Load SP signal from EXU to PFU
signal exu_busy: std_logic; -- EXU busy ( stalls PFU )
signal pfu_busy: std_logic; -- PFU busy ( stalls DFU )
signal decode_jump: std_logic; -- Jump signal from EXU to DFU
signal jump_address: unsigned(maxAddrBit downto 0); -- Jump address from EXU to DFU
signal do_interrupt: std_logic; -- Helper.
-- Sampled signals from the opcode. Left as signals
-- in order to simulate design.
signal sampledOpcode: std_logic_vector(OpCode_Size-1 downto 0);
signal sampledDecodedOpcode: DecodedOpcodeType;
signal sampledOpWillFreeze: std_logic;
signal sampledStackOperation: stackChangeType;
signal sampledspOffset: unsigned(4 downto 0);
signal sampledTosSource: tosSourceType;
signal nos: unsigned(wordSize-1 downto 0); -- This is only a helper
signal wroteback_q: std_logic; -- TODO: get rid of this here, move to EXU regs
-- Test debug signals
signal freeze_all: std_logic := '0';
signal single_step: std_logic := '0';
-- LSU
signal lsu_req: std_logic;
signal lsu_we: std_logic;
signal lsu_busy: std_logic;
signal lsu_data_read: std_logic_vector(wordSize-1 downto 0);
signal lsu_data_write: std_logic_vector(wordSize-1 downto 0);
signal lsu_data_sel: std_logic_vector(3 downto 0);
signal lsu_address: std_logic_vector(maxAddrBitIncIO downto 0);
begin
-- Debug interface
dbg_out.pc <= std_logic_vector(prefr.pc);
dbg_out.opcode <= prefr.opcode;
--dbg_out.sp <= std_logic_vector(prefr.sp);
dbg_out.brk <= exr.break;
--dbg_out.stacka <= std_logic_vector(exr.tos);
--dbg_out.stackb <= std_logic_vector(nos);
dbg_out.idim <= prefr.idim;
shl: lshifter
port map (
clk => wb_clk_i,
rst => wb_rst_i,
enable => lshifter_enable,
done => lshifter_done,
inputA => lshifter_input,
inputB => lshifter_amount,
output => lshifter_output,
multorshift => lshifter_multorshift
);
stack_clk <= wb_clk_i;
-- synopsys translate_off
traceFileGenerate:
if Generate_Trace generate
trace_file: trace
port map (
clk => wb_clk_i,
begin_inst => begin_inst,
pc => trace_pc,
opcode => trace_opcode,
sp => trace_sp,
memA => trace_topOfStack,
memB => trace_topOfStackB,
busy => '0',--busy,
intsp => (others => 'U')
);
end generate;
-- synopsys translate_on
cache: zpuino_icache
generic map (
ADDRESS_HIGH => maxAddrBitBRAM
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
valid => cache_valid,
data => cache_data,
address => cache_address,
strobe => cache_strobe,
stall => cache_stall,
enable => cache_enable,
flush => cache_flush,
-- Master wishbone interface
m_wb_ack_i => rom_wb_ack_i,
m_wb_dat_i => rom_wb_dat_i,
m_wb_adr_o => rom_wb_adr_o,
m_wb_cyc_o => rom_wb_cyc_o,
m_wb_stb_o => rom_wb_stb_o,
m_wb_stall_i => rom_wb_stall_i
);
lsu: zpuino_lsu
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_ack_i => wb_ack_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_adr_o => wb_adr_o(maxAddrBitIncIO downto 2),
wb_cyc_o => wb_cyc_o,
wb_stb_o => wb_stb_o,
wb_sel_o => wb_sel_o,
wb_we_o => wb_we_o,
req => lsu_req,
we => lsu_we,
busy => lsu_busy,
data_read => lsu_data_read,
data_write => lsu_data_write,
data_sel => lsu_data_sel,
address => lsu_address
);
tOpcode_sel <= to_integer(decr.pcint(minAddrBit-1 downto 0));
do_interrupt <= '1' when wb_inta_i='1'
and exr.inInterrupt='0'
else '0';
decodeControl:
process(cache_data, tOpcode_sel, sp_load, decr,
do_interrupt, dbg_in.inject, dbg_in.opcode)
variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
variable localspOffset: unsigned(4 downto 0);
begin
if dbg_in.inject='1' then
tOpcode := dbg_in.opcode;
else
case (tOpcode_sel) is
when 0 => tOpcode := std_logic_vector(cache_data(31 downto 24));
when 1 => tOpcode := std_logic_vector(cache_data(23 downto 16));
when 2 => tOpcode := std_logic_vector(cache_data(15 downto 8));
when 3 => tOpcode := std_logic_vector(cache_data(7 downto 0));
when others =>
null;
end case;
end if;
sampledOpcode <= tOpcode;
sampledStackOperation <= Stack_Same;
sampledTosSource <= Tos_Source_None;
sampledOpWillFreeze <= '0';
localspOffset(4):=not tOpcode(4);
localspOffset(3 downto 0) := unsigned(tOpcode(3 downto 0));
if do_interrupt='1' and decr.im='0' then
sampledDecodedOpcode <= Decoded_Interrupt;
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_PC;
else
if (tOpcode(7 downto 7)=OpCode_Im) then
if decr.im='0' then
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_Idim0;
sampledDecodedOpcode<=Decoded_Im0;
else
sampledTosSource <= Tos_Source_IdimN;
sampledDecodedOpcode<=Decoded_ImN;
end if;
elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
sampledStackOperation <= Stack_Pop;
sampledTosSource <= Tos_Source_StackB;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Pop;
sampledTosSource <= Tos_Source_StackB;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_PopDown;
sampledTosSource <= Tos_Source_None;
else
sampledDecodedOpcode<=Decoded_StoreSP;
sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_StackB;
end if;
elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
sampledStackOperation <= Stack_Push;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Dup;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_DupStackB;
sampledTosSource <= Tos_Source_StackB;
else
sampledDecodedOpcode<=Decoded_LoadSP;
sampledTosSource <= Tos_Source_LoadSP;
end if;
elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
-- Emulated instructions implemented in hardware
if minimal_implementation then
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
else
if (tOpcode(5 downto 0)=OpCode_Loadb) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadb;
sampledTosSource <= Tos_Source_LSU;
elsif (tOpcode(5 downto 0)=OpCode_Loadh) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadh;
sampledTosSource <= Tos_Source_LSU;
elsif (tOpcode(5 downto 0)=OpCode_Neqbranch) then
sampledStackOperation<=Stack_DualPop;
sampledDecodedOpcode<=Decoded_Neqbranch;
sampledOpWillFreeze <= '1';
elsif (tOpcode(5 downto 0)=OpCode_Call) then
sampledDecodedOpcode<=Decoded_Call;
sampledStackOperation<=Stack_Same;
sampledTosSource<=Tos_Source_FetchPC;
elsif (tOpcode(5 downto 0)=OpCode_Eq) then
sampledDecodedOpcode<=Decoded_Eq;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Eq;
elsif (tOpcode(5 downto 0)=OpCode_Ulessthan) then
sampledDecodedOpcode<=Decoded_Ulessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Ulessthan;
elsif (tOpcode(5 downto 0)=OpCode_Lessthan) then
sampledDecodedOpcode<=Decoded_Lessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Lessthan;
elsif (tOpcode(5 downto 0)=OpCode_StoreB) then
sampledDecodedOpcode<=Decoded_StoreB;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_StoreH) then
sampledDecodedOpcode<=Decoded_StoreH;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Mult) then
sampledDecodedOpcode<=Decoded_Mult;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Ashiftleft) then
sampledDecodedOpcode<=Decoded_Ashiftleft;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
end if;
end if;
elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Shift;
sampledTosSource <= Tos_Source_Shift;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_AddStackB;
sampledTosSource <= Tos_Source_AddStackB;
else
sampledDecodedOpcode<=Decoded_AddSP;
sampledTosSource <= Tos_Source_AddSP;
end if;
else
case tOpcode(3 downto 0) is
when OpCode_Break =>
sampledDecodedOpcode<=Decoded_Break;
sampledOpWillFreeze <= '1';
when OpCode_PushSP =>
sampledStackOperation <= Stack_Push;
sampledDecodedOpcode<=Decoded_PushSP;
sampledTosSource <= Tos_Source_SP;
when OpCode_PopPC =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_PopPC;
sampledTosSource <= Tos_Source_StackB;
when OpCode_Add =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Add;
sampledTosSource <= Tos_Source_Add;
when OpCode_Or =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Or;
sampledTosSource <= Tos_Source_Or;
when OpCode_And =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_And;
sampledTosSource <= Tos_Source_And;
when OpCode_Load =>
sampledDecodedOpcode<=Decoded_Load;
--sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_LSU;
when OpCode_Not =>
sampledDecodedOpcode<=Decoded_Not;
sampledTosSource <= Tos_Source_Not;
when OpCode_Flip =>
sampledDecodedOpcode<=Decoded_Flip;
sampledTosSource <= Tos_Source_Flip;
when OpCode_Store =>
sampledStackOperation <= Stack_DualPop;
sampledDecodedOpcode<=Decoded_Store;
sampledOpWillFreeze<='1';
when OpCode_PopSP =>
sampledDecodedOpcode<=Decoded_PopSP;
sampledOpWillFreeze<='1';
when OpCode_NA4 =>
if enable_fmul16 then
sampledDecodedOpcode<=Decoded_MultF16;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Nop;
end if;
when others =>
sampledDecodedOpcode<=Decoded_Nop;
end case;
end if;
end if;
sampledspOffset <= localspOffset;
end process;
-- Decode/Fetch unit
cache_enable <= not exu_busy;
process(decr, jump_address, decode_jump, wb_clk_i, sp_load,
sampledDecodedOpcode,sampledOpcode,decode_load_sp,
exu_busy, pfu_busy,
pcnext, cache_valid, wb_rst_i, sampledStackOperation, sampledspOffset,
sampledTosSource, prefr.recompute_sp, sampledOpWillFreeze,
dbg_in.flush, dbg_in.inject,dbg_in.injectmode,
prefr.valid, prefr.break, cache_stall
)
variable w: decoderegs_type;
begin
w := decr;
pcnext <= decr.fetchpc + 1;
cache_address(maxAddrBit downto 0) <= std_logic_vector(decr.fetchpc(maxAddrBit downto 0));
if wb_rst_i='1' then
w.pc := (others => '0');
w.pcint := (others => '0');
w.valid := '0';
w.fetchpc := (others => '0');
w.im:='0';
w.im_emu:='0';
w.state := State_Run;
w.break := '0';
cache_strobe <= DontCareValue;
else
cache_strobe <= '1';
case decr.state is
when State_Run =>
if pfu_busy='0' then
if dbg_in.injectmode='0' and decr.break='0' and cache_stall='0' then
w.fetchpc := pcnext;
end if;
-- Jump request
if decode_jump='1' then
w.valid := '0';
w.im := '0';
w.break := '0'; -- Invalidate eventual break after branch instruction
--rom_wb_cyc_o<='0';
cache_strobe<='0';
--if rom_wb_stall_i='0' then
w.fetchpc := jump_address;
--else
w.state := State_Jump;
--end if;
else
if dbg_in.injectmode='1' then --or decr.break='1' then
-- At this point we ought to push a new op into the pipeline.
-- Since we're entering inject mode, invalidate next operation,
-- but save the current IM flag.
w.im_emu := decr.im;
w.valid := '0';
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
--rom_wb_cyc_o <='0';
cache_strobe <= '0';
-- Wait until no work is to be done
if prefr.valid='0' and decr.valid='0' and exu_busy='0' then
w.state := State_Inject;
w.im:='0';
end if;
if decr.break='0' then
w.pc := decr.pcint;
end if;
else
if decr.break='1' then
w.valid := '0';
else
--if exu_busy='0' then
w.valid := cache_valid;
--end if;
end if;
if cache_valid='1' then
--if exu_busy='0' then
w.im := sampledOpcode(7);
--end if;
if sampledDecodedOpcode=Decoded_Break then
w.break:='1';
end if;
end if;
if prefr.break='0' and cache_stall='0' then
w.pcint := decr.fetchpc;
w.pc := decr.pcint;
end if;
--if cache_stall='0' then
if exu_busy='0' then
w.opcode := sampledOpcode;
end if;
--end if;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
when State_Jump =>
w.valid := '0';
if cache_stall='0' then
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Run;
end if;
when State_InjectJump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Inject;
when State_Inject =>
-- NOTE: disable ROM
--rom_wb_cyc_o <= '0';
if dbg_in.injectmode='0' then
w.im := decr.im_emu;
w.fetchpc := decr.pcint;
w.state := State_Run;
w.break := '0';
else
-- Handle opcode injection
-- TODO: merge this with main decode.
-- NOTE: we don't check busy here, it's up to debug unit to do it
--if pfu_busy='0' then
--w.fetchpc := pcnext;
-- Jump request
if decode_jump='1' then
w.fetchpc := jump_address;
w.valid := '0';
w.im := '0';
w.state := State_InjectJump;
else
w.valid := dbg_in.inject;
if dbg_in.inject='1' then
w.im := sampledOpcode(7);
--w.break := '0';
--w.pcint := decr.fetchpc;
w.opcode := sampledOpcode;
--w.pc := decr.pcint;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
--end if;
end case;
end if; -- rst
if rising_edge(wb_clk_i) then
decr <= w;
end if;
end process;
-- Prefetch/Load unit.
sp_load <= exr.tos(spMaxBit downto 2); -- Will be delayed one clock cycle
process(wb_clk_i, wb_rst_i, decr, prefr, exu_busy, decode_jump, sp_load,
decode_load_sp, dbg_in.flush)
variable w: prefetchregs_type;
variable i_op_freeze: std_logic;
begin
w := prefr;
pfu_busy<='0';
stack_b_addr <= std_logic_vector(prefr.spnext + 1);
w.recompute_sp:='0';
-- Stack
w.load := decode_load_sp;
if decode_load_sp='1' then
pfu_busy <= '1';
w.spnext := sp_load;
w.recompute_sp := '1';
else
pfu_busy <= exu_busy;
if decr.valid='1' then
if (exu_busy='0' and decode_jump='0') or prefr.recompute_sp='1' then
case decr.stackOperation is
when Stack_Push =>
w.spnext := prefr.spnext - 1;
when Stack_Pop =>
w.spnext := prefr.spnext + 1;
when Stack_DualPop =>
w.spnext := prefr.spnext + 2;
when others =>
end case;
w.sp := prefr.spnext;
end if;
end if;
end if;
case decr.decodedOpcode is
when Decoded_LoadSP | decoded_AddSP =>
stack_b_addr <= std_logic_vector(prefr.spnext + decr.spOffset);
when others =>
end case;
if decode_jump='1' then -- this is a pipeline "invalidate" flag.
w.valid := '0';
else
if dbg_in.flush='1' then
w.valid := '0';
else
if exu_busy='0' then
w.valid := decr.valid;
end if;
end if;
end if;
-- Moved op_will_freeze from decoder to here
case decr.decodedOpcode is
when Decoded_StoreSP
| Decoded_LoadB
| Decoded_Neqbranch
| Decoded_StoreB
| Decoded_Mult
| Decoded_Ashiftleft
| Decoded_Break
--| Decoded_Load
| Decoded_LoadH
| Decoded_Store
| Decoded_StoreH
| Decoded_PopSP
| Decoded_MultF16 =>
i_op_freeze := '1';
when others =>
i_op_freeze := '0';
end case;
if exu_busy='0' then
w.decodedOpcode := decr.decodedOpcode;
w.tosSource := decr.tosSource;
w.opcode := decr.opcode;
w.opWillFreeze := i_op_freeze;
w.pc := decr.pc;
w.fetchpc := decr.pcint;
w.idim := decr.idim;
w.break := decr.break;
end if;
if wb_rst_i='1' then
w.spnext := unsigned(spStart(spMaxBit downto 2));
--w.sp := unsigned(spStart(10 downto 2));
w.valid := '0';
w.idim := '0';
w.recompute_sp:='0';
end if;
if rising_edge(wb_clk_i) then
prefr <= w;
end if;
end process;
process(prefr,exr,nos)
begin
trace_pc <= (others => '0');
trace_pc(maxAddrBit downto 0) <= std_logic_vector(prefr.pc);
trace_opcode <= prefr.opcode;
trace_sp <= (others => '0');
trace_sp(spMaxBit downto 2) <= std_logic_vector(prefr.sp);
trace_topOfStack <= std_logic_vector( exr.tos );
trace_topOfStackB <= std_logic_vector( nos );
end process;
-- IO/Memory Accesses
lsu_address <= std_logic_vector(exr.tos(maxAddrBitIncIO downto 0));
--wb_cyc_o <= exr.wb_cyc;
--wb_stb_o <= exr.wb_stb;
--wb_we_o <= exr.wb_we;
--lsu_data_write <= std_logic_vector( nos );
freeze_all <= dbg_in.freeze;
process(exr, wb_inta_i, wb_clk_i, wb_rst_i, pcnext, stack_a_read,stack_b_read,
wb_ack_i, wb_dat_i, do_interrupt,exr, prefr, nos,
single_step, freeze_all, dbg_in.step, wroteback_q,lshifter_done,lshifter_output,
lsu_busy, lsu_data_read
)
variable spOffset: unsigned(4 downto 0);
variable w: exuregs_type;
variable instruction_executed: std_logic;
variable wroteback: std_logic;
variable datawrite: std_logic_vector(wordSize-1 downto 0);
variable sel: std_logic_vector(3 downto 0);
begin
w := exr;
instruction_executed := '0'; -- used for single stepping
stack_b_writeenable <= (others => '0');
stack_a_enable <= '1';
stack_b_enable <= '1';
exu_busy <= '0';
decode_jump <= '0';
jump_address <= (others => DontCareValue);
lshifter_enable <= '0';
lshifter_amount <= std_logic_vector(exr.tos_save);
lshifter_input <= std_logic_vector(exr.nos_save);
lshifter_multorshift <= '0';
poppc_inst <= '0';
begin_inst<='0';
stack_a_addr <= std_logic_vector( prefr.sp );
stack_a_writeenable <= (others => '0');
wroteback := wroteback_q;
stack_a_write <= std_logic_vector(exr.tos);
spOffset(4):=not prefr.opcode(4);
spOffset(3 downto 0) := unsigned(prefr.opcode(3 downto 0));
if wb_inta_i='0' then
w.inInterrupt := '0';
end if;
stack_b_write<=(others => DontCareValue);
if wroteback_q='1' then
nos <= unsigned(stack_a_read);
else
nos <= unsigned(stack_b_read);
end if;
decode_load_sp <= '0';
lsu_req <= '0';
lsu_we <= DontCareValue;
lsu_data_sel <= (others => DontCareValue);
lsu_data_write <= (others => DontCareValue);
case exr.state is
when State_ResyncFromStoreStack =>
exu_busy <= '1';
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_Resync2 =>
w.tos := unsigned(stack_a_read);
instruction_executed := '1';
exu_busy <= '0';
wroteback := '0';
stack_b_enable <= '1';
w.state := State_Execute;
when State_Execute =>
instruction_executed:='0';
if prefr.valid='1' then
exu_busy <= prefr.opWillFreeze;
if freeze_all='0' or single_step='1' then
wroteback := '0';
w.nos_save := nos;
w.tos_save := exr.tos;
w.idim := prefr.idim;
w.break:= prefr.break;
begin_inst<='1';
instruction_executed := '1';
-- TOS big muxer
case prefr.tosSource is
when Tos_Source_PC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.pc;
when Tos_Source_FetchPC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.fetchpc;
when Tos_Source_Idim0 =>
for i in wordSize-1 downto 7 loop
w.tos(i) := prefr.opcode(6);
end loop;
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_IdimN =>
w.tos(wordSize-1 downto 7) := exr.tos(wordSize-8 downto 0);
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_StackB =>
w.tos := nos;
when Tos_Source_SP =>
w.tos := (others => '0');
w.tos(31) := '1'; -- Stack address
w.tos(spMaxBit downto 2) := prefr.sp;
when Tos_Source_Add =>
w.tos := exr.tos + nos;
when Tos_Source_And =>
w.tos := exr.tos and nos;
when Tos_Source_Or =>
w.tos := exr.tos or nos;
when Tos_Source_Eq =>
w.tos := (others => '0');
if nos = exr.tos then
w.tos(0) := '1';
end if;
when Tos_Source_Ulessthan =>
w.tos := (others => '0');
if exr.tos < nos then
w.tos(0) := '1';
end if;
when Tos_Source_Lessthan =>
w.tos := (others => '0');
if signed(exr.tos) < signed(nos) then
w.tos(0) := '1';
end if;
when Tos_Source_Not =>
w.tos := not exr.tos;
when Tos_Source_Flip =>
for i in 0 to wordSize-1 loop
w.tos(i) := exr.tos(wordSize-1-i);
end loop;
when Tos_Source_LoadSP =>
w.tos := unsigned(stack_b_read);
when Tos_Source_AddSP =>
w.tos := w.tos + unsigned(stack_b_read);
when Tos_Source_AddStackB =>
w.tos := w.tos + nos;
when Tos_Source_Shift =>
w.tos := exr.tos + exr.tos;
when Tos_Source_LSU =>
if lsu_busy='0' then
w.tos := unsigned(lsu_data_read);
end if;
when others =>
end case;
case prefr.decodedOpcode is
when Decoded_Interrupt =>
w.inInterrupt := '1';
jump_address <= to_unsigned(32, maxAddrBit+1);
decode_jump <= '1';
stack_a_writeenable<=(others =>'1');
wroteback:='1';
stack_b_enable<= '0';
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Im0 =>
stack_a_writeenable<= (others =>'1');
wroteback:='1';
when Decoded_ImN =>
when Decoded_Nop =>
when Decoded_PopPC | Decoded_Call =>
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0);
poppc_inst <= '1';
stack_b_enable<='0';
-- Delay
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Emulate =>
decode_jump <= '1';
jump_address <= (others => '0');
jump_address(9 downto 5) <= unsigned(prefr.opcode(4 downto 0));
stack_a_writeenable<=(others =>'1');
wroteback:='1';
when Decoded_PushSP =>
stack_a_writeenable<=(others =>'1');
wroteback:='1';
when Decoded_LoadSP =>
stack_a_writeenable <= (others =>'1');
wroteback:='1';
when Decoded_DupStackB =>
stack_a_writeenable <= (others => '1');
wroteback:='1';
when Decoded_Dup =>
stack_a_writeenable<= (others =>'1');
wroteback:='1';
when Decoded_AddSP =>
stack_a_writeenable <= (others =>'1');
when Decoded_StoreSP =>
stack_a_writeenable <= (others =>'1');
wroteback:='1';
stack_a_addr <= std_logic_vector(prefr.sp + spOffset);
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_PopDown =>
stack_a_writeenable<=(others =>'1');
when Decoded_Pop =>
when Decoded_Ashiftleft =>
w.state := State_Ashiftleft;
when Decoded_Mult =>
w.state := State_Mult;
when Decoded_MultF16 =>
w.state := State_MultF16;
when Decoded_Store | Decoded_StoreB | Decoded_StoreH =>
if prefr.decodedOpcode=Decoded_Store then
datawrite := std_logic_vector(nos);
sel := "1111";
elsif prefr.decodedOpcode=Decoded_StoreH then
datawrite := (others => DontCareValue);
if exr.tos(1)='1' then
datawrite(15 downto 0) := std_logic_vector(nos(15 downto 0)) ;
sel := "0011";
else
datawrite(31 downto 16) := std_logic_vector(nos(15 downto 0)) ;
sel := "1100";
end if;
else
datawrite := (others => DontCareValue);
case exr.tos(1 downto 0) is
when "11" =>
datawrite(7 downto 0) := std_logic_vector(nos(7 downto 0)) ;
sel := "0001";
when "10" =>
datawrite(15 downto 8) := std_logic_vector(nos(7 downto 0)) ;
sel := "0010";
when "01" =>
datawrite(23 downto 16) := std_logic_vector(nos(7 downto 0)) ;
sel := "0100";
when "00" =>
datawrite(31 downto 24) := std_logic_vector(nos(7 downto 0)) ;
sel := "1000";
when others =>
end case;
end if;
stack_a_writeenable <=sel;
lsu_data_sel <= sel;
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(spMaxBit downto 2));
stack_a_write <= datawrite;
stack_a_writeenable <= sel;
w.state := State_ResyncFromStoreStack;
else
--w.wb_we := '1';
--w.wb_cyc := '1';
--w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
-- stack_a_enable<='0';
stack_a_enable<=not lsu_busy;
stack_a_writeenable <= (others => '0');
-- stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_b_enable<= not lsu_busy;
lsu_data_write <= datawrite;
instruction_executed := '0';
exu_busy <= '1';
lsu_req <= '1';
lsu_we <= '1';
if lsu_busy='0' then
wroteback := '0';
w.state := State_Resync2;
end if;
end if;
when Decoded_Load | Decoded_Loadb | Decoded_Loadh =>
--w.tos_save := exr.tos; -- Byte select
instruction_executed := '0';
wroteback := wroteback_q; -- Keep WB
if exr.tos(wordSize-1)='1' then
stack_a_addr<=std_logic_vector(exr.tos(spMaxBit downto 2));
stack_a_enable<='1';
exu_busy <= '1';
w.state := State_LoadStack;
else
exu_busy <= lsu_busy;
lsu_req <= '1';
lsu_we <= '0';
stack_a_enable <= '0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable <= not lsu_busy;
if lsu_busy='0' then
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Loadh then
exu_busy<='1';
w.state:=State_Loadh;
end if;
end if;
end if;
when Decoded_PopSP =>
decode_load_sp <= '1';
instruction_executed := '0';
stack_a_addr <= std_logic_vector(exr.tos(spMaxBit downto 2));
w.state := State_Resync2;
--when Decoded_Break =>
-- w.break := '1';
when Decoded_Neqbranch =>
instruction_executed := '0';
w.state := State_NeqBranch;
when others =>
end case;
else -- freeze_all
--
-- Freeze the entire pipeline.
--
exu_busy<='1';
stack_a_enable<='0';
stack_b_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
end if;
end if; -- valid
when State_Ashiftleft =>
exu_busy <= '1';
lshifter_enable <= '1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_Mult =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_MultF16 =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(47 downto 16));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_WaitSPB =>
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Loadb =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1 downto 0) is
when "11" =>
w.tos(7 downto 0) := unsigned(exr.tos(7 downto 0));
when "10" =>
w.tos(7 downto 0) := unsigned(exr.tos(15 downto 8));
when "01" =>
w.tos(7 downto 0) := unsigned(exr.tos(23 downto 16));
when "00" =>
w.tos(7 downto 0) := unsigned(exr.tos(31 downto 24));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Loadh =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1) is
when '1' =>
w.tos(15 downto 0) := unsigned(exr.tos(15 downto 0));
when '0' =>
w.tos(15 downto 0) := unsigned(exr.tos(31 downto 16));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_LoadStack =>
w.tos := unsigned(stack_a_read);
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Loadh then
exu_busy<='1';
w.state:=State_Loadh;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
when State_NeqBranch =>
if exr.nos_save/=0 then
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0) + prefr.pc;
poppc_inst <= '1';
exu_busy <= '0';
else
exu_busy <='1';
end if;
instruction_executed := '0';
stack_a_addr <= std_logic_vector(prefr.spnext);
wroteback:='0';
w.state := State_Resync2;
when others =>
null;
end case;
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
exr.state <= State_Execute;
exr.idim <= DontCareValue;
exr.inInterrupt <= '0';
exr.break <= '0';
exr.wb_cyc <= '0';
exr.wb_stb <= '1';
wroteback_q <= '0';
else
exr <= w;
-- TODO: move wroteback_q into EXU regs
wroteback_q <= wroteback;
if exr.break='1' then
report "BREAK" severity failure;
end if;
-- Some sanity checks, to be caught in simulation
if prefr.valid='1' then
if prefr.tosSource=Tos_Source_Idim0 and prefr.idim='1' then
report "Invalid IDIM flag 0" severity error;
end if;
if prefr.tosSource=Tos_Source_IdimN and prefr.idim='0' then
report "Invalid IDIM flag 1" severity error;
end if;
end if;
end if;
end if;
end process;
single_step <= dbg_in.step;
dbg_out.valid <= '1' when prefr.valid='1' else '0';
-- Let pipeline finish
dbg_out.ready <= '1' when exr.state=state_execute
and decode_load_sp='0'
and decode_jump='0'
and decr.state = State_Inject
--and jump_q='0'
else '0';
end behave;
| mit |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.d-memory.vhd | 1 | 3263 | --------------------------------------------------------------------------------
-- Memory stage
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity memory is
port(
-- inputs
rst : in std_logic;
controls_in : in std_logic_vector(10 downto 0);
PC1_in : in std_logic_vector(31 downto 0);
PC2_in : in std_logic_vector(31 downto 0);
takeBranch : in std_logic;
addrMem : in std_logic_vector(31 downto 0);
writeData : in std_logic_vector(31 downto 0);
RFaddr_in : in std_logic_vector(4 downto 0);
-- outputs
controls_out : out std_logic_vector(2 downto 0);
dataOut_mem : out std_logic_vector(31 downto 0); -- data that has been read directly from memory
dataOut_exe : out std_logic_vector(31 downto 0); -- data that has been produced in exe stage
RFaddr_out : out std_logic_vector(4 downto 0);
unaligned : out std_logic;
PCsrc : out std_logic;
flush : out std_logic;
jump : out std_logic;
PC1_out : out std_logic_vector(31 downto 0);
PC2_out : out std_logic_vector(31 downto 0);
regwrite_MEM : out std_logic; -- goes to forwarding unit
RFaddr_MEM : out std_logic_vector(4 downto 0); -- goes to forwarding unit
forw_addr_MEM : out std_logic_vector(31 downto 0) -- goes to EXE stage and is used if forwarding detected by forwarding unit
);
end memory;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture struct of memory is
-- component declarations
component dram_block is
port(
-- inputs
address : in std_logic_vector(31 downto 0);
data_write : in std_logic_vector(31 downto 0);
mem_op : in std_logic_vector(5 downto 0);
rst : in std_logic;
-- outputs
unaligned : out std_logic;
data_read : out std_logic_vector(31 downto 0)
);
end component;
-- internal signals
signal PCsrc_i : std_logic;
signal jump_i : std_logic;
begin
-- concurrent signal assignments
jump_i <= controls_in(1); -- MV
PCsrc_i <= controls_in(0) and takeBranch; -- MV Branch and takeBranch
PCsrc <= PCsrc_i;
jump <= jump_i;
flush <= PCsrc_i or jump_i;
regwrite_MEM <= controls_in(10); -- to forwarding unit
RFaddr_MEM <= RFaddr_in; -- to forwarding unit
forw_addr_MEM <= addrMem; -- to forwarding unit
controls_out <= controls_in(10) & controls_in (9) & controls_in(2); -- pass regwrite, link, memtoreg to WB stage
dataOut_exe <= addrMem;
RFaddr_out <= RFaddr_in;
PC1_out <= PC1_in;
PC2_out <= PC2_in;
-- component instantiations
dram : dram_block port map (addrMem, writeData, controls_in(8 downto 3),rst, unaligned, dataOut_mem);
end struct;
| mit |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.b-decode.core/a.b.b.d-Mux_stall.vhd | 2 | 1542 | -----------------------------------------------------------------------------------------------------
-- Mux Stall
-- This mux is controlled by the Hazard Detection Unit. The control signal is mux_op, when asserted
-- the mux force a Control Word of a NOP (Control Word + ALU Opcode), otherwise the Control Word
-- produced by the CU passes.
-----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
entity mux_stall is
port (
-- INPUTS
cw_from_cu : in std_logic_vector((CW_SIZE + ALUOP_SIZE)-1 downto 0); -- control word produced by the CU
mux_op : in std_logic; -- control signal produced by the hazard detection unit
-- OUTPUTS
cw_from_mux : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0) -- control word produced by the mux
);
end mux_stall;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
architecture behavioral of mux_stall is
begin
cw_from_mux <= (others => '0') when (mux_op = '1') else cw_from_cu;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/Wishbone_Peripherals/zpuino_vga_ram.vhd | 13 | 4286 | --
-- VGA RAM for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0);
mi_addr: in std_logic_vector(14 downto 0)
);
end entity zpuino_vga_ram;
--
-- Address 0 to 15: 1st char
-- Address 16 to 31: 2st char
--
--
architecture behave of zpuino_vga_ram is
signal v_ram_0_en, v_ram_1_en: std_logic;
signal v_ram_0_data, v_ram_1_data: std_logic_vector(7 downto 0);
signal v_addrh_q: std_logic;
signal mi_ram_0_en, mi_ram_1_en: std_logic;
signal mi_ram_0_dat_o, mi_ram_1_dat_o: std_logic_vector(7 downto 0);
signal mi_addrh_q: std_logic;
signal nodata: std_logic_vector(7 downto 0) := (others => '0');
begin
-- vport enable signals
v_ram_0_en <= v_en and not v_addr(14);
v_ram_1_en <= v_en and v_addr(14);
-- vport address decode
process(v_clk)
begin
if rising_edge(v_clk) then
v_addrh_q <= v_ram_1_en;
end if;
end process;
-- vport Output select
v_data <= v_ram_0_data when v_addrh_q='0' else v_ram_1_data;
-- miport enable signals
mi_ram_0_en <= mi_en and not mi_addr(14);
mi_ram_1_en <= mi_en and mi_addr(14);
-- vport address decode
process(mi_clk)
begin
if rising_edge(mi_clk) then
mi_addrh_q <= mi_ram_1_en;
end if;
end process;
-- vport Output select
mi_dat_o <= mi_ram_0_dat_o when mi_addrh_q='0' else mi_ram_1_dat_o;
ram0: generic_dp_ram
generic map (
address_bits => 14,
data_bits => 8
)
port map (
clka => v_clk,
ena => v_ram_0_en,
wea => '0',
addra => v_addr(13 downto 0),
dia => nodata,
doa => v_ram_0_data,
clkb => mi_clk,
enb => mi_ram_0_en,
web => mi_we,
addrb => mi_addr(13 downto 0),
dib => mi_dat_i,
dob => mi_ram_0_dat_o
);
ram1: generic_dp_ram
generic map (
address_bits => 12,
data_bits => 8
)
port map (
clka => v_clk,
ena => v_ram_1_en,
wea => '0',
addra => v_addr(11 downto 0),
dia => nodata,
doa => v_ram_1_data,
clkb => mi_clk,
enb => mi_ram_1_en,
web => mi_we,
addrb => mi_addr(11 downto 0),
dib => mi_dat_i,
dob => mi_ram_1_dat_o
);
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Wishbone_Peripherals/VIDEO_zpuino_wb_vga_hqvga.vhd | 13 | 10522 | --
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/Wishbone_Peripherals/VIDEO_zpuino_wb_vga_hqvga.vhd | 13 | 10522 | --
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/Wishbone_Peripherals/VIDEO_zpuino_wb_vga_hqvga.vhd | 13 | 10522 | --
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/VIDEO_zpuino_wb_vga_hqvga.vhd | 13 | 10522 | --
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/ZPUino_Papilio_One_V1_hyperion.vhd | 13 | 42740 | --
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/ZPUino_1/ZPUino_Papilio_One_V1_hyperion.vhd | 13 | 42740 | --
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/ZPUino_1/ZPUino_Papilio_One_V1_hyperion.vhd | 13 | 42740 | --
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/ZPUino_1/ZPUino_Papilio_One_V1_hyperion.vhd | 13 | 42740 | --
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/ZPUino_1/ZPUino_Papilio_One_V1_hyperion.vhd | 13 | 42740 | --
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/Wishbone_Peripherals/clk_32to350_pll.vhd | 13 | 5913 | -- file: clk_32to350_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___352.000______0.000______50.0______202.756____211.523
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to350_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to350_pll;
architecture xilinx of clk_32to350_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to350_pll,clk_wiz_v3_6,{component_name=clk_32to350_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 22,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
end xilinx;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/Wishbone_Peripherals/clk_32to350_pll.vhd | 13 | 5913 | -- file: clk_32to350_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___352.000______0.000______50.0______202.756____211.523
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to350_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to350_pll;
architecture xilinx of clk_32to350_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to350_pll,clk_wiz_v3_6,{component_name=clk_32to350_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 22,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
end xilinx;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Benchy/stage.vhd | 13 | 6197 | ----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/board_Papilio_One_500k/prom-generic-dp-32_hyperion.vhd | 13 | 102446 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity prom_generic_dualport_hyperion is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(13 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(13 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end entity prom_generic_dualport_hyperion;
architecture behave of prom_generic_dualport_hyperion is
subtype RAM_WORD is STD_LOGIC_VECTOR (7 downto 0);
type RAM_TABLE is array (0 to 4095) of RAM_WORD;
shared variable RAM0: RAM_TABLE := RAM_TABLE'(
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shared variable RAM1: RAM_TABLE := RAM_TABLE'(
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shared variable RAM2: RAM_TABLE := RAM_TABLE'(
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shared variable RAM3: RAM_TABLE := RAM_TABLE'(
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signal rwea: std_logic_vector(3 downto 0);
signal rweb: std_logic_vector(3 downto 0);
signal memaread0: std_logic_vector(7 downto 0);
signal membread0: std_logic_vector(7 downto 0);
signal memaread1: std_logic_vector(7 downto 0);
signal membread1: std_logic_vector(7 downto 0);
signal memaread2: std_logic_vector(7 downto 0);
signal membread2: std_logic_vector(7 downto 0);
signal memaread3: std_logic_vector(7 downto 0);
signal membread3: std_logic_vector(7 downto 0);
begin
rwea(0) <= WEA and MASKA(0);
rweb(0) <= WEB and MASKB(0);
rwea(1) <= WEA and MASKA(1);
rweb(1) <= WEB and MASKB(1);
rwea(2) <= WEA and MASKA(2);
rweb(2) <= WEB and MASKB(2);
rwea(3) <= WEA and MASKA(3);
rweb(3) <= WEB and MASKB(3);
DOA(7 downto 0) <= memaread0;
DOB(7 downto 0) <= membread0;
DOA(15 downto 8) <= memaread1;
DOB(15 downto 8) <= membread1;
DOA(23 downto 16) <= memaread2;
DOB(23 downto 16) <= membread2;
DOA(31 downto 24) <= memaread3;
DOB(31 downto 24) <= membread3;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(0)='1' then
RAM0( conv_integer(ADDRA) ) := DIA(7 downto 0);
end if;
memaread0 <= RAM0(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(0)='1' then
RAM0( conv_integer(ADDRB) ) := DIB(7 downto 0);
end if;
membread0 <= RAM0(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(1)='1' then
RAM1( conv_integer(ADDRA) ) := DIA(15 downto 8);
end if;
memaread1 <= RAM1(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(1)='1' then
RAM1( conv_integer(ADDRB) ) := DIB(15 downto 8);
end if;
membread1 <= RAM1(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(2)='1' then
RAM2( conv_integer(ADDRA) ) := DIA(23 downto 16);
end if;
memaread2 <= RAM2(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(2)='1' then
RAM2( conv_integer(ADDRB) ) := DIB(23 downto 16);
end if;
membread2 <= RAM2(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(3)='1' then
RAM3( conv_integer(ADDRA) ) := DIA(31 downto 24);
end if;
memaread3 <= RAM3(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(3)='1' then
RAM3( conv_integer(ADDRB) ) := DIB(31 downto 24);
end if;
membread3 <= RAM3(conv_integer(ADDRB)) ;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/board_Papilio_One_500k/prom-generic-dp-32_hyperion.vhd | 13 | 102446 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity prom_generic_dualport_hyperion is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(13 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(13 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end entity prom_generic_dualport_hyperion;
architecture behave of prom_generic_dualport_hyperion is
subtype RAM_WORD is STD_LOGIC_VECTOR (7 downto 0);
type RAM_TABLE is array (0 to 4095) of RAM_WORD;
shared variable RAM0: RAM_TABLE := RAM_TABLE'(
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shared variable RAM1: RAM_TABLE := RAM_TABLE'(
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shared variable RAM2: RAM_TABLE := RAM_TABLE'(
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shared variable RAM3: RAM_TABLE := RAM_TABLE'(
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signal rwea: std_logic_vector(3 downto 0);
signal rweb: std_logic_vector(3 downto 0);
signal memaread0: std_logic_vector(7 downto 0);
signal membread0: std_logic_vector(7 downto 0);
signal memaread1: std_logic_vector(7 downto 0);
signal membread1: std_logic_vector(7 downto 0);
signal memaread2: std_logic_vector(7 downto 0);
signal membread2: std_logic_vector(7 downto 0);
signal memaread3: std_logic_vector(7 downto 0);
signal membread3: std_logic_vector(7 downto 0);
begin
rwea(0) <= WEA and MASKA(0);
rweb(0) <= WEB and MASKB(0);
rwea(1) <= WEA and MASKA(1);
rweb(1) <= WEB and MASKB(1);
rwea(2) <= WEA and MASKA(2);
rweb(2) <= WEB and MASKB(2);
rwea(3) <= WEA and MASKA(3);
rweb(3) <= WEB and MASKB(3);
DOA(7 downto 0) <= memaread0;
DOB(7 downto 0) <= membread0;
DOA(15 downto 8) <= memaread1;
DOB(15 downto 8) <= membread1;
DOA(23 downto 16) <= memaread2;
DOB(23 downto 16) <= membread2;
DOA(31 downto 24) <= memaread3;
DOB(31 downto 24) <= membread3;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(0)='1' then
RAM0( conv_integer(ADDRA) ) := DIA(7 downto 0);
end if;
memaread0 <= RAM0(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(0)='1' then
RAM0( conv_integer(ADDRB) ) := DIB(7 downto 0);
end if;
membread0 <= RAM0(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(1)='1' then
RAM1( conv_integer(ADDRA) ) := DIA(15 downto 8);
end if;
memaread1 <= RAM1(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(1)='1' then
RAM1( conv_integer(ADDRB) ) := DIB(15 downto 8);
end if;
membread1 <= RAM1(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(2)='1' then
RAM2( conv_integer(ADDRA) ) := DIA(23 downto 16);
end if;
memaread2 <= RAM2(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(2)='1' then
RAM2( conv_integer(ADDRB) ) := DIB(23 downto 16);
end if;
membread2 <= RAM2(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(3)='1' then
RAM3( conv_integer(ADDRA) ) := DIA(31 downto 24);
end if;
memaread3 <= RAM3(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(3)='1' then
RAM3( conv_integer(ADDRB) ) := DIB(31 downto 24);
end if;
membread3 <= RAM3(conv_integer(ADDRB)) ;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/eia232.vhd | 13 | 4325 | ----------------------------------------------------------------------------------
-- eia232.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- EIA232 aka RS232 interface.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity eia232 is
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
Port (
clock : in STD_LOGIC;
reset : in std_logic;
speed : in std_logic_vector (1 downto 0);
rx : in STD_LOGIC;
tx : out STD_LOGIC;
cmd : out STD_LOGIC_VECTOR (39 downto 0);
execute : out STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
send : in STD_LOGIC;
busy : out STD_LOGIC
);
end eia232;
architecture Behavioral of eia232 is
COMPONENT sump_prescaler
generic (
SCALE : integer
);
PORT(
clock : IN std_logic;
reset : IN std_logic;
div : IN std_logic_vector(1 downto 0);
scaled : OUT std_logic
);
END COMPONENT;
COMPONENT receiver
generic (
FREQ : integer;
RATE : integer
);
PORT(
rx : IN std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out std_logic_vector(7 downto 0);
data : out std_logic_vector(31 downto 0);
execute : out STD_LOGIC
);
END COMPONENT;
COMPONENT transmitter
generic (
FREQ : integer;
RATE : integer
);
PORT(
data : IN std_logic_vector(31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : IN std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in std_logic;
tx : OUT std_logic;
busy : out std_logic
);
END COMPONENT;
constant TRXFREQ : integer := FREQ / SCALE; -- reduced rx & tx clock for receiver and transmitter
signal trxClock, executeReg, executePrev, id, xon, xoff, wrFlags : std_logic;
signal disabledGroupsReg : std_logic_vector(3 downto 0);
signal opcode : std_logic_vector(7 downto 0);
signal opdata : std_logic_vector(31 downto 0);
begin
cmd <= opdata & opcode;
execute <= executeReg;
-- process special uart commands that do not belong in core decoder
process(clock)
begin
if rising_edge(clock) then
id <= '0'; xon <= '0'; xoff <= '0'; wrFlags <= '0';
executePrev <= executeReg;
if executePrev = '0' and executeReg = '1' then
case opcode is
when x"02" => id <= '1';
when x"11" => xon <= '1';
when x"13" => xoff <= '1';
when x"82" => wrFlags <= '1';
when others =>
end case;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if wrFlags = '1' then
disabledGroupsReg <= opdata(5 downto 2);
end if;
end if;
end process;
Inst_sump_prescaler: sump_prescaler
generic map (
SCALE => SCALE
)
PORT MAP(
clock => clock,
reset => reset,
div => speed,
scaled => trxClock
);
Inst_receiver: receiver
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
rx => rx,
clock => clock,
trxClock => trxClock,
reset => reset,
op => opcode,
data => opdata,
execute => executeReg
);
Inst_transmitter: transmitter
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
data => data,
disabledGroups => disabledGroupsReg,
write => send,
id => id,
xon => xon,
xoff => xoff,
clock => clock,
trxClock => trxClock,
reset => reset,
tx => tx,
busy => busy
);
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/Benchy/eia232.vhd | 13 | 4325 | ----------------------------------------------------------------------------------
-- eia232.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- EIA232 aka RS232 interface.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity eia232 is
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
Port (
clock : in STD_LOGIC;
reset : in std_logic;
speed : in std_logic_vector (1 downto 0);
rx : in STD_LOGIC;
tx : out STD_LOGIC;
cmd : out STD_LOGIC_VECTOR (39 downto 0);
execute : out STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
send : in STD_LOGIC;
busy : out STD_LOGIC
);
end eia232;
architecture Behavioral of eia232 is
COMPONENT sump_prescaler
generic (
SCALE : integer
);
PORT(
clock : IN std_logic;
reset : IN std_logic;
div : IN std_logic_vector(1 downto 0);
scaled : OUT std_logic
);
END COMPONENT;
COMPONENT receiver
generic (
FREQ : integer;
RATE : integer
);
PORT(
rx : IN std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out std_logic_vector(7 downto 0);
data : out std_logic_vector(31 downto 0);
execute : out STD_LOGIC
);
END COMPONENT;
COMPONENT transmitter
generic (
FREQ : integer;
RATE : integer
);
PORT(
data : IN std_logic_vector(31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : IN std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in std_logic;
tx : OUT std_logic;
busy : out std_logic
);
END COMPONENT;
constant TRXFREQ : integer := FREQ / SCALE; -- reduced rx & tx clock for receiver and transmitter
signal trxClock, executeReg, executePrev, id, xon, xoff, wrFlags : std_logic;
signal disabledGroupsReg : std_logic_vector(3 downto 0);
signal opcode : std_logic_vector(7 downto 0);
signal opdata : std_logic_vector(31 downto 0);
begin
cmd <= opdata & opcode;
execute <= executeReg;
-- process special uart commands that do not belong in core decoder
process(clock)
begin
if rising_edge(clock) then
id <= '0'; xon <= '0'; xoff <= '0'; wrFlags <= '0';
executePrev <= executeReg;
if executePrev = '0' and executeReg = '1' then
case opcode is
when x"02" => id <= '1';
when x"11" => xon <= '1';
when x"13" => xoff <= '1';
when x"82" => wrFlags <= '1';
when others =>
end case;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if wrFlags = '1' then
disabledGroupsReg <= opdata(5 downto 2);
end if;
end if;
end process;
Inst_sump_prescaler: sump_prescaler
generic map (
SCALE => SCALE
)
PORT MAP(
clock => clock,
reset => reset,
div => speed,
scaled => trxClock
);
Inst_receiver: receiver
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
rx => rx,
clock => clock,
trxClock => trxClock,
reset => reset,
op => opcode,
data => opdata,
execute => executeReg
);
Inst_transmitter: transmitter
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
data => data,
disabledGroups => disabledGroupsReg,
write => send,
id => id,
xon => xon,
xoff => xoff,
clock => clock,
trxClock => trxClock,
reset => reset,
tx => tx,
busy => busy
);
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Benchy/eia232.vhd | 13 | 4325 | ----------------------------------------------------------------------------------
-- eia232.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- EIA232 aka RS232 interface.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity eia232 is
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
Port (
clock : in STD_LOGIC;
reset : in std_logic;
speed : in std_logic_vector (1 downto 0);
rx : in STD_LOGIC;
tx : out STD_LOGIC;
cmd : out STD_LOGIC_VECTOR (39 downto 0);
execute : out STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
send : in STD_LOGIC;
busy : out STD_LOGIC
);
end eia232;
architecture Behavioral of eia232 is
COMPONENT sump_prescaler
generic (
SCALE : integer
);
PORT(
clock : IN std_logic;
reset : IN std_logic;
div : IN std_logic_vector(1 downto 0);
scaled : OUT std_logic
);
END COMPONENT;
COMPONENT receiver
generic (
FREQ : integer;
RATE : integer
);
PORT(
rx : IN std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out std_logic_vector(7 downto 0);
data : out std_logic_vector(31 downto 0);
execute : out STD_LOGIC
);
END COMPONENT;
COMPONENT transmitter
generic (
FREQ : integer;
RATE : integer
);
PORT(
data : IN std_logic_vector(31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : IN std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in std_logic;
tx : OUT std_logic;
busy : out std_logic
);
END COMPONENT;
constant TRXFREQ : integer := FREQ / SCALE; -- reduced rx & tx clock for receiver and transmitter
signal trxClock, executeReg, executePrev, id, xon, xoff, wrFlags : std_logic;
signal disabledGroupsReg : std_logic_vector(3 downto 0);
signal opcode : std_logic_vector(7 downto 0);
signal opdata : std_logic_vector(31 downto 0);
begin
cmd <= opdata & opcode;
execute <= executeReg;
-- process special uart commands that do not belong in core decoder
process(clock)
begin
if rising_edge(clock) then
id <= '0'; xon <= '0'; xoff <= '0'; wrFlags <= '0';
executePrev <= executeReg;
if executePrev = '0' and executeReg = '1' then
case opcode is
when x"02" => id <= '1';
when x"11" => xon <= '1';
when x"13" => xoff <= '1';
when x"82" => wrFlags <= '1';
when others =>
end case;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if wrFlags = '1' then
disabledGroupsReg <= opdata(5 downto 2);
end if;
end if;
end process;
Inst_sump_prescaler: sump_prescaler
generic map (
SCALE => SCALE
)
PORT MAP(
clock => clock,
reset => reset,
div => speed,
scaled => trxClock
);
Inst_receiver: receiver
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
rx => rx,
clock => clock,
trxClock => trxClock,
reset => reset,
op => opcode,
data => opdata,
execute => executeReg
);
Inst_transmitter: transmitter
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
data => data,
disabledGroups => disabledGroupsReg,
write => send,
id => id,
xon => xon,
xoff => xoff,
clock => clock,
trxClock => trxClock,
reset => reset,
tx => tx,
busy => busy
);
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/prescaler.vhd | 14 | 3821 | --
-- Clock prescaler for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity prescaler is
port (
clk: in std_logic;
rst: in std_logic;
prescale: in std_logic_vector(2 downto 0);
event: out std_logic
);
end entity prescaler;
architecture behave of prescaler is
signal counter: unsigned(9 downto 0);
signal event_i: std_logic;
signal ck2: std_logic;
signal ck4: std_logic;
signal ck8: std_logic;
signal ck16: std_logic;
signal ck64: std_logic;
signal ck256: std_logic;
signal ck1024: std_logic;
signal ck2_q: std_logic;
signal ck4_q: std_logic;
signal ck8_q: std_logic;
signal ck16_q: std_logic;
signal ck64_q: std_logic;
signal ck256_q: std_logic;
signal ck1024_q: std_logic;
function edge( now: std_logic; before: std_logic ) return std_logic is
variable result: std_logic;
begin
if (now='1' and before='0') then
result := '1';
else
result := '0';
end if;
return result;
end edge;
begin
ck2 <= counter(0);
ck4 <= counter(1);
ck8 <= counter(2);
ck16 <= counter(3);
ck64 <= counter(5);
ck256 <= counter(7);
ck1024 <= counter(9);
event <= event_i;
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
ck2_q<='0';
ck4_q<='0';
ck8_q<='0';
ck16_q<='0';
ck64_q<='0';
ck256_q<='0';
ck1024_q<='0';
else
ck2_q<=ck2;
ck4_q<=ck4;
ck8_q<=ck8;
ck16_q<=ck16;
ck64_q<=ck64;
ck256_q<=ck256;
ck1024_q<=ck1024;
end if;
end if;
end process;
process(prescale,ck2,ck4,ck8,ck16,ck64,ck256,ck1024,ck2_q,ck4_q,ck8_q,ck16_q,ck64_q,ck256_q,ck1024_q)
begin
case prescale is
when "000" =>
event_i <= '1';
when "001" =>
event_i <= edge(ck2,ck2_q);
when "010" =>
event_i <= edge(ck4,ck4_q);
when "011" =>
event_i <= edge(ck8,ck8_q);
when "100" =>
event_i <= edge(ck16,ck16_q);
when "101" =>
event_i <= edge(ck64,ck64_q);
when "110" =>
event_i <= edge(ck256,ck256_q);
when "111" =>
event_i <= edge(ck1024,ck1024_q);
when others =>
end case;
end process;
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
counter <= (others=>'0');
else
counter<=counter + 1;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/Benchy/prescaler.vhd | 13 | 2089 | ----------------------------------------------------------------------------------
-- prescaler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Shared prescaler for transmitter and receiver timings.
-- Used to control the transfer speed.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sump_prescaler is
generic (
SCALE : integer := 54
);
Port (
clock : in STD_LOGIC;
reset : in std_logic;
div : in std_logic_vector(1 downto 0);
scaled : out std_logic
);
end sump_prescaler;
architecture Behavioral of sump_prescaler is
signal counter : integer range 0 to (6 * SCALE) - 1;
begin
process(clock, reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clock) then
if
(counter = SCALE - 1 and div = "00") -- 115200
or (counter = 2 * SCALE - 1 and div = "01") -- 57600
or (counter = 3 * SCALE - 1 and div = "10") -- 38400
or (counter = 6 * SCALE - 1 and div = "11") -- 19200
then
counter <= 0;
scaled <= '1';
else
counter <= counter + 1;
scaled <= '0';
end if;
end if;
end process;
end Behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/zpuino_timers.vhd | 13 | 6137 | --
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/ZPUino_1/zpuino_timers.vhd | 13 | 6137 | --
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/board_Papilio_One_500k/prom-generic-dp-32.vhd | 13 | 200723 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity prom_generic_dualport is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(14 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(14 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end entity prom_generic_dualport;
architecture behave of prom_generic_dualport is
subtype RAM_WORD is STD_LOGIC_VECTOR (7 downto 0);
type RAM_TABLE is array (0 to 8191) of RAM_WORD;
shared variable RAM0: RAM_TABLE := RAM_TABLE'(
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shared variable RAM1: RAM_TABLE := RAM_TABLE'(
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shared variable RAM2: RAM_TABLE := RAM_TABLE'(
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shared variable RAM3: RAM_TABLE := RAM_TABLE'(
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signal rwea: std_logic_vector(3 downto 0);
signal rweb: std_logic_vector(3 downto 0);
signal memaread0: std_logic_vector(7 downto 0);
signal membread0: std_logic_vector(7 downto 0);
signal memaread1: std_logic_vector(7 downto 0);
signal membread1: std_logic_vector(7 downto 0);
signal memaread2: std_logic_vector(7 downto 0);
signal membread2: std_logic_vector(7 downto 0);
signal memaread3: std_logic_vector(7 downto 0);
signal membread3: std_logic_vector(7 downto 0);
begin
rwea(0) <= WEA and MASKA(0);
rweb(0) <= WEB and MASKB(0);
rwea(1) <= WEA and MASKA(1);
rweb(1) <= WEB and MASKB(1);
rwea(2) <= WEA and MASKA(2);
rweb(2) <= WEB and MASKB(2);
rwea(3) <= WEA and MASKA(3);
rweb(3) <= WEB and MASKB(3);
DOA(7 downto 0) <= memaread0;
DOB(7 downto 0) <= membread0;
DOA(15 downto 8) <= memaread1;
DOB(15 downto 8) <= membread1;
DOA(23 downto 16) <= memaread2;
DOB(23 downto 16) <= membread2;
DOA(31 downto 24) <= memaread3;
DOB(31 downto 24) <= membread3;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(0)='1' then
RAM0( conv_integer(ADDRA) ) := DIA(7 downto 0);
end if;
memaread0 <= RAM0(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(0)='1' then
RAM0( conv_integer(ADDRB) ) := DIB(7 downto 0);
end if;
membread0 <= RAM0(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(1)='1' then
RAM1( conv_integer(ADDRA) ) := DIA(15 downto 8);
end if;
memaread1 <= RAM1(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(1)='1' then
RAM1( conv_integer(ADDRB) ) := DIB(15 downto 8);
end if;
membread1 <= RAM1(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(2)='1' then
RAM2( conv_integer(ADDRA) ) := DIA(23 downto 16);
end if;
memaread2 <= RAM2(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(2)='1' then
RAM2( conv_integer(ADDRB) ) := DIB(23 downto 16);
end if;
membread2 <= RAM2(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(3)='1' then
RAM3( conv_integer(ADDRA) ) := DIA(31 downto 24);
end if;
memaread3 <= RAM3(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(3)='1' then
RAM3( conv_integer(ADDRB) ) := DIB(31 downto 24);
end if;
membread3 <= RAM3(conv_integer(ADDRB)) ;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/timer.vhd | 13 | 9957 | --
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end entity timer;
architecture behave of timer is
component prescaler is
port (
clk: in std_logic;
rst: in std_logic;
prescale: in std_logic_vector(2 downto 0);
event: out std_logic
);
end component prescaler;
type singlepwmregs is record
cmplow: unsigned(WIDTH-1 downto 0);
cmphigh: unsigned(WIDTH-1 downto 0);
en: std_logic;
end record;
type pwmregs is array(PWMCOUNT-1 downto 0) of singlepwmregs;
type timerregs is record
cnt: unsigned(WIDTH-1 downto 0); -- current timer counter value
cmp: unsigned(WIDTH-1 downto 0); -- top timer compare value
ccm: std_logic; -- clear on compare match
en: std_logic; -- enable
dir: std_logic; -- direction
ien: std_logic; -- interrupt enable
intr: std_logic; -- interrupt
pres: std_logic_vector(2 downto 0); -- Prescaler
updp: std_logic_vector(1 downto 0);
presrst: std_logic;
pwmr: pwmregs;
pwmrb:pwmregs;
end record;
constant UPDATE_NOW: std_logic_vector(1 downto 0) := "00";
constant UPDATE_ZERO_SYNC: std_logic_vector(1 downto 0) := "01";
constant UPDATE_LATER: std_logic_vector(1 downto 0) := "10";
signal tmr0_prescale_rst: std_logic;
--signal tmr0_prescale: std_logic_vector(2 downto 0);
signal tmr0_prescale_event: std_logic;
signal TSC_q: unsigned(wordSize-1 downto 0);
signal tmrr: timerregs;
function eq(a:std_logic_vector; b:std_logic_vector) return std_logic is
begin
if a=b then
return '1';
else
return '0';
end if;
end function;
signal do_interrupt: std_logic;
begin
wb_inta_o <= tmrr.intr;
-- comp <= tmrr.cout;
wb_ack_o <= wb_cyc_i and wb_stb_i;
pr: if PRESCALER_ENABLED generate
tmr0prescale_inst: prescaler
port map (
clk => wb_clk_i,
rst => tmrr.presrst,
prescale=> tmrr.pres,
event => tmr0_prescale_event
);
end generate;
npr: if not PRESCALER_ENABLED generate
tmr0_prescale_event<='1';
end generate;
tsc_process: if TSCENABLED generate
TSCgen: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
TSC_q <= (others => '0');
else
TSC_q <= TSC_q + 1;
end if;
end if;
end process;
end generate;
-- Read
process(wb_adr_i, tmrr,TSC_q)
begin
case wb_adr_i(1 downto 0) is
when "00" =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= tmrr.en;
wb_dat_o(1) <= tmrr.ccm;
wb_dat_o(2) <= tmrr.dir;
wb_dat_o(3) <= tmrr.ien;
wb_dat_o(6 downto 4) <= tmrr.pres;
wb_dat_o(7) <= tmrr.intr;
wb_dat_o(10 downto 9) <= tmrr.updp;
when "01" =>
wb_dat_o <= (others => '0');
wb_dat_o(WIDTH-1 downto 0) <= std_logic_vector(tmrr.cnt);
when "10" =>
wb_dat_o <= (others => '0');
wb_dat_o(WIDTH-1 downto 0) <= std_logic_vector(tmrr.cmp);
when others =>
if TSCENABLED then
wb_dat_o <= (others => '0');
wb_dat_o <= std_logic_vector(TSC_q);
else
wb_dat_o <= (others => DontCareValue );
end if;
end case;
end process;
process(wb_clk_i, tmrr, wb_rst_i,wb_cyc_i,wb_stb_i,wb_we_i,wb_adr_i,wb_dat_i,tmrr,do_interrupt,tmr0_prescale_event)
variable w: timerregs;
variable write_ctrl: std_logic;
variable write_cmp: std_logic;
variable write_cnt: std_logic;
variable write_pwm: std_logic;
variable ovf: std_logic;
variable pwmindex: integer;
begin
w := tmrr;
-- These are just helpers
write_ctrl := wb_cyc_i and wb_stb_i and wb_we_i and eq(wb_adr_i,"000000");
write_cnt := wb_cyc_i and wb_stb_i and wb_we_i and eq(wb_adr_i,"000001");
write_cmp := wb_cyc_i and wb_stb_i and wb_we_i and eq(wb_adr_i,"000010");
write_pwm := wb_cyc_i and wb_stb_i and wb_we_i and wb_adr_i(5);
ovf:='0';
if tmrr.cnt = tmrr.cmp then
ovf:='1';
end if;
do_interrupt <= '0';
if wb_rst_i='1' then
w.en := '0';
w.ccm := '0';
w.dir := '0';
w.ien := '0';
w.pres := (others => '0');
w.presrst := '1';
w.updp := UPDATE_ZERO_SYNC;
for i in 0 to PWMCOUNT-1 loop
w.pwmrb(i).en :='0';
w.pwmr(i).en :='0';
end loop;
else
if do_interrupt='1' then
w.intr := '1';
end if;
w.presrst := '0';
-- Wishbone access
if write_ctrl='1' then
w.en := wb_dat_i(0);
w.ccm := wb_dat_i(1);
w.dir := wb_dat_i(2);
w.ien := wb_dat_i(3);
w.pres:= wb_dat_i(6 downto 4);
w.updp := wb_dat_i(10 downto 9);
if wb_dat_i(7)='0' then
w.intr:='0';
end if;
end if;
if write_cmp='1' then
w.cmp := unsigned(wb_dat_i(WIDTH-1 downto 0));
end if;
if write_cnt='1' then
w.cnt := unsigned(wb_dat_i(WIDTH-1 downto 0));
else
if tmrr.en='1' and tmr0_prescale_event='1' then
-- If output matches, set interrupt
if ovf='1' then
if tmrr.ien='1' then
do_interrupt<='1';
end if;
end if;
-- CCM
if tmrr.ccm='1' and ovf='1' then
w.cnt := (others => '0');
else
if tmrr.dir='1' then
w.cnt := tmrr.cnt + 1;
else
w.cnt := tmrr.cnt - 1;
end if;
end if;
end if;
end if;
end if;
if write_pwm='1' then
for i in 0 to PWMCOUNT-1 loop
if wb_adr_i(4 downto 2) = std_logic_vector(to_unsigned(i,3)) then
if BUFFERS then
-- Write values to this PWM
case wb_adr_i(1 downto 0) is
when "00" =>
w.pwmrb(i).cmplow := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "01" =>
w.pwmrb(i).cmphigh := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "10" =>
w.pwmrb(i).en := wb_dat_i(0);
when "11" =>
-- This is sync pulse for UPDATE_LATER
when others =>
end case;
else
-- Write values to this PWM
case wb_adr_i(1 downto 0) is
when "00" =>
w.pwmr(i).cmplow := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "01" =>
w.pwmr(i).cmphigh := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "10" =>
w.pwmr(i).en := wb_dat_i(0);
when "11" =>
-- This is sync pulse for UPDATE_LATER
when others =>
end case;
end if;
end if;
end loop;
end if;
if BUFFERS then
for i in 0 to PWMCOUNT-1 loop
case tmrr.updp is
when UPDATE_NOW =>
w.pwmr(i) := tmrr.pwmrb(i);
when UPDATE_ZERO_SYNC =>
if ovf='1' then
w.pwmr(i) := tmrr.pwmrb(i);
end if;
when UPDATE_LATER =>
--if wb_adr_i(3 downto 2) = std_logic_vector(to_unsigned(i,2)) then
-- if wb_adr_i(1 downto 0)="11" then
-- w.pwmr(i) := tmrr.pwmrb(i);
-- end if;
-- end if;
when others =>
--w.pwmr(i) := tmrr.pwmrb(i);
end case;
end loop;
end if;
if rising_edge(wb_clk_i) then
tmrr <= w;
for i in 0 to PWMCOUNT-1 loop
if tmrr.pwmr(i).en='1' then
if tmrr.cnt >= tmrr.pwmr(i).cmplow and tmrr.cnt<tmrr.pwmr(i).cmphigh then
pwm_out(i) <= '1';
else
pwm_out(i) <= '0';
end if;
else
pwm_out(i)<='0';
end if;
end loop;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/ZPUino_1/timer.vhd | 13 | 9957 | --
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end entity timer;
architecture behave of timer is
component prescaler is
port (
clk: in std_logic;
rst: in std_logic;
prescale: in std_logic_vector(2 downto 0);
event: out std_logic
);
end component prescaler;
type singlepwmregs is record
cmplow: unsigned(WIDTH-1 downto 0);
cmphigh: unsigned(WIDTH-1 downto 0);
en: std_logic;
end record;
type pwmregs is array(PWMCOUNT-1 downto 0) of singlepwmregs;
type timerregs is record
cnt: unsigned(WIDTH-1 downto 0); -- current timer counter value
cmp: unsigned(WIDTH-1 downto 0); -- top timer compare value
ccm: std_logic; -- clear on compare match
en: std_logic; -- enable
dir: std_logic; -- direction
ien: std_logic; -- interrupt enable
intr: std_logic; -- interrupt
pres: std_logic_vector(2 downto 0); -- Prescaler
updp: std_logic_vector(1 downto 0);
presrst: std_logic;
pwmr: pwmregs;
pwmrb:pwmregs;
end record;
constant UPDATE_NOW: std_logic_vector(1 downto 0) := "00";
constant UPDATE_ZERO_SYNC: std_logic_vector(1 downto 0) := "01";
constant UPDATE_LATER: std_logic_vector(1 downto 0) := "10";
signal tmr0_prescale_rst: std_logic;
--signal tmr0_prescale: std_logic_vector(2 downto 0);
signal tmr0_prescale_event: std_logic;
signal TSC_q: unsigned(wordSize-1 downto 0);
signal tmrr: timerregs;
function eq(a:std_logic_vector; b:std_logic_vector) return std_logic is
begin
if a=b then
return '1';
else
return '0';
end if;
end function;
signal do_interrupt: std_logic;
begin
wb_inta_o <= tmrr.intr;
-- comp <= tmrr.cout;
wb_ack_o <= wb_cyc_i and wb_stb_i;
pr: if PRESCALER_ENABLED generate
tmr0prescale_inst: prescaler
port map (
clk => wb_clk_i,
rst => tmrr.presrst,
prescale=> tmrr.pres,
event => tmr0_prescale_event
);
end generate;
npr: if not PRESCALER_ENABLED generate
tmr0_prescale_event<='1';
end generate;
tsc_process: if TSCENABLED generate
TSCgen: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
TSC_q <= (others => '0');
else
TSC_q <= TSC_q + 1;
end if;
end if;
end process;
end generate;
-- Read
process(wb_adr_i, tmrr,TSC_q)
begin
case wb_adr_i(1 downto 0) is
when "00" =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= tmrr.en;
wb_dat_o(1) <= tmrr.ccm;
wb_dat_o(2) <= tmrr.dir;
wb_dat_o(3) <= tmrr.ien;
wb_dat_o(6 downto 4) <= tmrr.pres;
wb_dat_o(7) <= tmrr.intr;
wb_dat_o(10 downto 9) <= tmrr.updp;
when "01" =>
wb_dat_o <= (others => '0');
wb_dat_o(WIDTH-1 downto 0) <= std_logic_vector(tmrr.cnt);
when "10" =>
wb_dat_o <= (others => '0');
wb_dat_o(WIDTH-1 downto 0) <= std_logic_vector(tmrr.cmp);
when others =>
if TSCENABLED then
wb_dat_o <= (others => '0');
wb_dat_o <= std_logic_vector(TSC_q);
else
wb_dat_o <= (others => DontCareValue );
end if;
end case;
end process;
process(wb_clk_i, tmrr, wb_rst_i,wb_cyc_i,wb_stb_i,wb_we_i,wb_adr_i,wb_dat_i,tmrr,do_interrupt,tmr0_prescale_event)
variable w: timerregs;
variable write_ctrl: std_logic;
variable write_cmp: std_logic;
variable write_cnt: std_logic;
variable write_pwm: std_logic;
variable ovf: std_logic;
variable pwmindex: integer;
begin
w := tmrr;
-- These are just helpers
write_ctrl := wb_cyc_i and wb_stb_i and wb_we_i and eq(wb_adr_i,"000000");
write_cnt := wb_cyc_i and wb_stb_i and wb_we_i and eq(wb_adr_i,"000001");
write_cmp := wb_cyc_i and wb_stb_i and wb_we_i and eq(wb_adr_i,"000010");
write_pwm := wb_cyc_i and wb_stb_i and wb_we_i and wb_adr_i(5);
ovf:='0';
if tmrr.cnt = tmrr.cmp then
ovf:='1';
end if;
do_interrupt <= '0';
if wb_rst_i='1' then
w.en := '0';
w.ccm := '0';
w.dir := '0';
w.ien := '0';
w.pres := (others => '0');
w.presrst := '1';
w.updp := UPDATE_ZERO_SYNC;
for i in 0 to PWMCOUNT-1 loop
w.pwmrb(i).en :='0';
w.pwmr(i).en :='0';
end loop;
else
if do_interrupt='1' then
w.intr := '1';
end if;
w.presrst := '0';
-- Wishbone access
if write_ctrl='1' then
w.en := wb_dat_i(0);
w.ccm := wb_dat_i(1);
w.dir := wb_dat_i(2);
w.ien := wb_dat_i(3);
w.pres:= wb_dat_i(6 downto 4);
w.updp := wb_dat_i(10 downto 9);
if wb_dat_i(7)='0' then
w.intr:='0';
end if;
end if;
if write_cmp='1' then
w.cmp := unsigned(wb_dat_i(WIDTH-1 downto 0));
end if;
if write_cnt='1' then
w.cnt := unsigned(wb_dat_i(WIDTH-1 downto 0));
else
if tmrr.en='1' and tmr0_prescale_event='1' then
-- If output matches, set interrupt
if ovf='1' then
if tmrr.ien='1' then
do_interrupt<='1';
end if;
end if;
-- CCM
if tmrr.ccm='1' and ovf='1' then
w.cnt := (others => '0');
else
if tmrr.dir='1' then
w.cnt := tmrr.cnt + 1;
else
w.cnt := tmrr.cnt - 1;
end if;
end if;
end if;
end if;
end if;
if write_pwm='1' then
for i in 0 to PWMCOUNT-1 loop
if wb_adr_i(4 downto 2) = std_logic_vector(to_unsigned(i,3)) then
if BUFFERS then
-- Write values to this PWM
case wb_adr_i(1 downto 0) is
when "00" =>
w.pwmrb(i).cmplow := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "01" =>
w.pwmrb(i).cmphigh := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "10" =>
w.pwmrb(i).en := wb_dat_i(0);
when "11" =>
-- This is sync pulse for UPDATE_LATER
when others =>
end case;
else
-- Write values to this PWM
case wb_adr_i(1 downto 0) is
when "00" =>
w.pwmr(i).cmplow := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "01" =>
w.pwmr(i).cmphigh := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "10" =>
w.pwmr(i).en := wb_dat_i(0);
when "11" =>
-- This is sync pulse for UPDATE_LATER
when others =>
end case;
end if;
end if;
end loop;
end if;
if BUFFERS then
for i in 0 to PWMCOUNT-1 loop
case tmrr.updp is
when UPDATE_NOW =>
w.pwmr(i) := tmrr.pwmrb(i);
when UPDATE_ZERO_SYNC =>
if ovf='1' then
w.pwmr(i) := tmrr.pwmrb(i);
end if;
when UPDATE_LATER =>
--if wb_adr_i(3 downto 2) = std_logic_vector(to_unsigned(i,2)) then
-- if wb_adr_i(1 downto 0)="11" then
-- w.pwmr(i) := tmrr.pwmrb(i);
-- end if;
-- end if;
when others =>
--w.pwmr(i) := tmrr.pwmrb(i);
end case;
end loop;
end if;
if rising_edge(wb_clk_i) then
tmrr <= w;
for i in 0 to PWMCOUNT-1 loop
if tmrr.pwmr(i).en='1' then
if tmrr.cnt >= tmrr.pwmr(i).cmplow and tmrr.cnt<tmrr.pwmr(i).cmphigh then
pwm_out(i) <= '1';
else
pwm_out(i) <= '0';
end if;
else
pwm_out(i)<='0';
end if;
end loop;
end if;
end process;
end behave;
| mit |
pdt/ttask | test/xilinx-ise/lib/my_lib/sim/and_gate_test.vhdl | 1 | 880 | --
-- and_gate_test.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
entity and_gate_test is
end entity;
architecture sim of and_gate_test is
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic;
begin
uut : entity work.and_gate port map (
a => a,
b => b,
c => c
);
test : process
begin
report "Starting and_gate test";
wait for 1 us;
assert c = '0' report "Error, output should be '0'";
a <= '1';
wait for 1 us;
assert c = '0' report "Error, output should be '0'";
b <= '1';
wait for 1 us;
assert c = '1' report "Error, output should be '1'";
a <= '0';
wait for 1 us;
assert c = '0' report "Error, output should be '0'";
report "Completed and_gate test";
wait;
end process;
end;
| mit |
capitanov/Stupid_watch | src/rtl/game_cores/cl_text.vhd | 1 | 3957 | --------------------------------------------------------------------------------
--
-- Title : cl_text.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for main text
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.array8x8;
entity cl_text is
generic(
constant yend : std_logic_vector(4 downto 0); --! Y end area
constant ystart : std_logic_vector(4 downto 0); --! Y start area
constant xend : std_logic_vector(6 downto 0); --! X end area
constant xstart : std_logic_vector(6 downto 0) --! X start area
);
port(
-- system signals:
clk : in std_logic; --! clock
reset : in std_logic; --! system reset
-- control signals:
addr_rnd : in std_logic_vector(4 downto 0); --! address round
display : in std_logic; --! display enable
cntgames : in std_logic; --! games counter enable
win : in std_logic; --! win value
lose : in std_logic; --! lose value
game : in std_logic; --! game value
flash : in std_logic_vector(2 downto 0); --! RGB blinking
-- vga XoY:
x_char : in std_logic_vector(9 downto 0); --! X line: 0:79
y_char : in std_logic_vector(8 downto 0); --! Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0) --! RGB Colour
);
end cl_text;
architecture cl_text of cl_text is
component ctrl_8x16_rom is
port(
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end component;
component cl_select_text is
port(
x_char : in std_logic_vector(6 downto 0);
y_char : in std_logic_vector(4 downto 0);
win : in std_logic;
lose : in std_logic;
game : in std_logic;
cntgames: in std_logic;
addr_rnd: in std_logic_vector(4 downto 0);
ch_data : out std_logic_vector(7 downto 0)
);
end component;
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal data : std_logic;
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal color : std_logic_vector(2 downto 0):="111";
signal addr_rom : std_logic_vector(10 downto 0);
signal data_rom : std_logic_vector(7 downto 0);
signal data_box : std_logic_vector(7 downto 0);
begin
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
x_select_text: cl_select_text
port map (
x_char => x_in,
y_char => y_in,
win => win,
lose => lose,
game => game,
cntgames=> cntgames,
addr_rnd=> addr_rnd,
ch_data => data_box
);
addr_rom <= data_box(6 downto 0) & y_char(3 downto 0) when rising_edge(clk);
x_char_rom: ctrl_8x16_rom
port map (
clk => clk,
addr => addr_rom,
data => data_rom
);
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
color <= flash when (x_in > "0011001") and (y_in = "10000") else "100" when (y_in < "00111") else "010";
pr_sw_sel: process(clk, reset) is
begin
if reset = '0' then
data <= '0';
elsif rising_edge(clk) then
if display = '0' then
data <= '0';
else
data <= data_rom(to_integer(unsigned(x_del)));
end if;
end if;
end process;
g_rgb: for ii in 0 to 2 generate
begin
rgb(ii) <= data and color(ii);
end generate;
end cl_text; | mit |
IamVNIE/Hardware-Security | DES CryptoCore/src/pp.vhd | 2 | 944 | library ieee;
use ieee.std_logic_1164.all;
entity pp is port
(
so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x
: in std_logic_vector(1 to 4);
ppo : out std_logic_vector(1 to 32)
);
end pp;
architecture behaviour of pp is
signal XX : std_logic_vector(1 to 32);
begin
XX(1 to 4)<=so1x; XX(5 to 8)<=so2x; XX(9 to 12)<=so3x; XX(13 to 16)<=so4x;
XX(17 to 20)<=so5x; XX(21 to 24)<=so6x; XX(25 to 28)<=so7x; XX(29 to 32)<=so8x;
ppo(1)<=XX(16); ppo(2)<=XX(7); ppo(3)<=XX(20); ppo(4)<=XX(21);
ppo(5)<=XX(29); ppo(6)<=XX(12); ppo(7)<=XX(28); ppo(8)<=XX(17);
ppo(9)<=XX(1); ppo(10)<=XX(15); ppo(11)<=XX(23); ppo(12)<=XX(26);
ppo(13)<=XX(5); ppo(14)<=XX(18); ppo(15)<=XX(31); ppo(16)<=XX(10);
ppo(17)<=XX(2); ppo(18)<=XX(8); ppo(19)<=XX(24); ppo(20)<=XX(14);
ppo(21)<=XX(32); ppo(22)<=XX(27); ppo(23)<=XX(3); ppo(24)<=XX(9);
ppo(25)<=XX(19); ppo(26)<=XX(13); ppo(27)<=XX(30); ppo(28)<=XX(6);
ppo(29)<=XX(22); ppo(30)<=XX(11); ppo(31)<=XX(4); ppo(32)<=XX(25);
end; | mit |
IamVNIE/Hardware-Security | DES CryptoCore/src/s6.vhd | 2 | 3965 | library ieee;
use ieee.std_logic_1164.all;
entity s6 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s6;
architecture behaviour of s6 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
end case;
end process;
end; | mit |
pdt/ttask | test/ghdl/lib/my_lib/rtl/and_gate.vhdl | 4 | 267 | --
-- and_gate.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port (
a : in std_logic;
b : in std_logic;
c : out std_logic
);
end entity and_gate;
architecture rtl of and_gate is
begin
c <= a and b;
end;
| mit |
IamVNIE/Hardware-Security | RC5 CryptoCore/Rc5 Codes/RC5_enc_full.vhd | 2 | 2330 | Library IEEE;
Use IEEE.std_logic_1164.All;
Use IEEE.std_logic_arith.All;
Use IEEE.std_logic_unsigned.All;
Use Work.RC5_pkg.All;
Entity rc5_Struct is
Port
(
clr : in std_logic;
clk : in std_logic;
enc : in std_logic;
key_vld : in std_logic;
key : in std_logic_vector (127 downto 0);
data_vld : in std_logic;
din : in std_logic_vector (63 downto 0);
dout : out std_logic_vector (63 downto 0);
data_rdy : out std_logic
);
End rc5_Struct;
--Architecture
Architecture struct of rc5_Struct is
--Key Expansion Module
Component rc5_rnd_key
Port
(
clr : in std_logic;
clk : in std_logic;
key_vld : in std_logic;
key_in : in Std_logic_vector (127 downto 0);
skey : out rom;
key_rdy : out std_logic
);
End Component;
--Encryption Module
Component rc5_enc
Port
(
clr : in std_logic;
clk : in std_logic;
din : in std_logic_vector(63 downto 0);
di_vld : in std_logic;
key_rdy : in std_logic;
skey : in rom;
dout : out std_logic_vector(63 downto 0);
do_rdy : out std_logic
);
End Component;
--Decryption Module
Component rc5_dec
Port
(
clr : In std_logic;
clk : In std_logic;
din : In std_logic_vector(63 downto 0);
din_vld : In std_logic;
key_rdy : In std_logic;
skey : In rom;
dout : Out std_logic_vector(63 downto 0);
dout_rdy : Out std_logic
);
End Component;
--Signals
Signal skey : rom;
Signal key_rdy : std_logic;
Signal dout_enc : std_logic_vector (63 downto 0);
Signal dout_dec : std_logic_vector (63 downto 0);
Signal enc_rdy : std_logic;
Signal dec_rdy : std_logic;
Signal i_cnt : std_logic_vector (3 downto 0);
Begin
--Port Maps
U1 : rc5_rnd_key Port Map (clr => clr, clk => clk, key_in => key, key_vld => key_vld, skey => skey, key_rdy => key_rdy);
U2 : rc5_enc Port Map (clr => clr, clk => clk, din => din, di_vld => key_rdy, skey => skey, dout => dout_enc, do_rdy => enc_rdy, key_rdy => key_rdy);
U3 : rc5_dec Port Map (clr => clr, clk => clk, din => din, din_vld => key_rdy, skey => skey, dout => dout_dec, dout_rdy => dec_rdy, key_rdy => key_rdy);
--Select
With enc select
dout <= dout_enc when '1',
dout_dec when others;
With enc select
data_rdy <= enc_rdy when '1',
dec_rdy when others;
--End structure
End struct;
| mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/digit/simulation/random.vhd | 101 | 4108 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/startBtn/simulation/random.vhd | 101 | 4108 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| mit |
hmdgharb/5-Staged-MIPS-Pipeline | work/bench/_primary.vhd | 1 | 70 | library verilog;
use verilog.vl_types.all;
entity bench is
end bench;
| gpl-2.0 |
hmdgharb/5-Staged-MIPS-Pipeline | work/@e@x_@s@t@a@g@e/_primary.vhd | 1 | 386 | library verilog;
use verilog.vl_types.all;
entity EX_STAGE is
port(
EX_AluCmd : in vl_logic_vector(3 downto 0);
EX_AluSrc1 : in vl_logic_vector(15 downto 0);
EX_AluSrc2 : in vl_logic_vector(15 downto 0);
zeroFlag : out vl_logic;
EX_LowResult : out vl_logic_vector(15 downto 0)
);
end EX_STAGE;
| gpl-2.0 |
hmdgharb/5-Staged-MIPS-Pipeline | work/@instruction@memory/_primary.vhd | 1 | 339 | library verilog;
use verilog.vl_types.all;
entity InstructionMemory is
generic(
SIZE : integer := 256
);
port(
reset : in vl_logic;
addr : in vl_logic_vector(7 downto 0);
inst : out vl_logic_vector(15 downto 0)
);
end InstructionMemory;
| gpl-2.0 |
hsm5xw/ece4435-final-project | ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab7/lab7_lib/hdl/fetch_struct_config.vhd | 2 | 429 | -- Generation properties:
-- Format : hierarchical
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use library name
-- View name : include
--
LIBRARY lab7_lib;
CONFIGURATION fetch_struct_config OF fetch IS
FOR struct
FOR ALL : Fetch_FSM
USE ENTITY lab7_lib.Fetch_FSM(FSM);
END FOR;
END FOR;
END fetch_struct_config;
| gpl-2.0 |
hsm5xw/ece4435-final-project | ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab7/lab7_lib/fetch_struct_config.vhd | 2 | 429 | -- Generation properties:
-- Format : hierarchical
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use library name
-- View name : include
--
LIBRARY lab7_lib;
CONFIGURATION fetch_struct_config OF fetch IS
FOR struct
FOR ALL : Fetch_FSM
USE ENTITY lab7_lib.Fetch_FSM(FSM);
END FOR;
END FOR;
END fetch_struct_config;
| gpl-2.0 |
hmdgharb/5-Staged-MIPS-Pipeline | work/@m@e@m_@s@t@a@g@e/_primary.vhd | 1 | 378 | library verilog;
use verilog.vl_types.all;
entity MEM_STAGE is
port(
rst : in vl_logic;
DataMemoryAddress: in vl_logic_vector(15 downto 0);
DataMemoryWriteData: in vl_logic_vector(15 downto 0);
DataMemoryWriteEnable: in vl_logic;
DataMemoryOut : out vl_logic_vector(15 downto 0)
);
end MEM_STAGE;
| gpl-2.0 |
hsm5xw/ece4435-final-project | ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab9_new/lab9_new_lib/hdl/mini_alu_struct.vhd | 1 | 10180 | -- VHDL Entity lab9_new_lib.mini_ALU.symbol
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 03:34:23 04/26/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mini_ALU IS
PORT(
ALU_cin : IN std_logic;
ALU_mode : IN std_logic;
Left : IN std_logic_vector (15 DOWNTO 0);
Right : IN std_logic_vector (15 DOWNTO 0);
operation : IN std_logic_vector (3 DOWNTO 0);
pcval : IN std_logic_vector (15 DOWNTO 0);
ALU_Result : OUT std_logic_vector (15 DOWNTO 0);
ALU_cout : OUT std_logic;
Is_negative : OUT std_logic;
Is_ovfl : OUT std_logic;
Is_zero : OUT std_logic;
next_pc_val : OUT std_logic_vector (15 DOWNTO 0)
);
-- Declarations
END mini_ALU ;
--
-- VHDL Architecture lab9_new_lib.mini_ALU.struct
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 03:34:23 04/26/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE struct OF mini_ALU IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL dout : std_logic_vector(15 DOWNTO 0);
SIGNAL dout1 : std_logic_vector(15 DOWNTO 0);
-- Implicit buffer signal declarations
SIGNAL ALU_Result_internal : std_logic_vector (15 DOWNTO 0);
-- ModuleWare signal declarations(v1.12) for instance 'custom_ALU' of 'alu181'
SIGNAL mw_custom_ALUa_in : std_logic_vector(15 DOWNTO 0);
SIGNAL mw_custom_ALUb_in : std_logic_vector(15 DOWNTO 0);
SIGNAL mw_custom_ALUaout : unsigned(15 DOWNTO 0);
SIGNAL mw_custom_ALUlout : std_logic_vector(15 DOWNTO 0);
SIGNAL mw_custom_ALUcarryout : std_logic;
BEGIN
-- ModuleWare code(v1.12) for instance 'custom_Adder' of 'add'
custom_addercombo_proc: PROCESS (pcval, dout1)
VARIABLE temp_din0 : std_logic_vector(16 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(16 DOWNTO 0);
VARIABLE temp_sum : unsigned(16 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & pcval;
temp_din1 := '0' & dout1;
temp_carry := '0';
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
next_pc_val <= conv_std_logic_vector(temp_sum(15 DOWNTO 0),16);
END PROCESS custom_addercombo_proc;
-- ModuleWare code(v1.12) for instance 'custom_ALU' of 'alu181'
ALU_cout <= mw_custom_ALUcarryout AND (NOT(ALU_mode));
Is_ovfl <= (mw_custom_ALUcarryout) AND (NOT(ALU_mode));
custom_aluarith_proc: PROCESS (mw_custom_ALUa_in, mw_custom_ALUb_in, ALU_cin)
VARIABLE temp_atemp : std_logic_vector(16 DOWNTO 0);
VARIABLE temp_btemp : std_logic_vector(16 DOWNTO 0);
VARIABLE temp_otemp : unsigned(16 DOWNTO 0);
VARIABLE temp_carryin : std_logic;
BEGIN
temp_atemp := '0' & mw_custom_ALUa_in;
temp_btemp := '0' & mw_custom_ALUb_in;
temp_carryin := ALU_cin;
temp_otemp := (unsigned(temp_atemp) + unsigned(temp_btemp) + temp_carryin);
mw_custom_ALUaout <= temp_otemp(15 DOWNTO 0);
mw_custom_ALUcarryout <= temp_otemp(16) ;
END PROCESS custom_aluarith_proc;
custom_alufdrive_proc: PROCESS (mw_custom_ALUaout, mw_custom_ALUlout, ALU_mode)
BEGIN
IF (ALU_mode = '1') THEN
ALU_Result_internal <= mw_custom_ALUlout;
ELSIF (ALU_mode = '0') THEN
ALU_Result_internal <= std_logic_vector(mw_custom_ALUaout);
ELSE
ALU_Result_internal <= (OTHERS => 'X');
END IF;
END PROCESS custom_alufdrive_proc;
custom_alumux_proc: PROCESS (operation, Left, Right)
VARIABLE temp_or0 : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_and0 : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_not_a : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_tain0 : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_or1 : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_and1 : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_not_b : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_tain1 : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_orout : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_andout : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_xorout : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_ltemp : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_s3_0 : std_logic_vector (3 DOWNTO 0);
CONSTANT S0 :std_logic_vector(3 DOWNTO 0 ) := "0000";
CONSTANT S1 :std_logic_vector(3 DOWNTO 0 ) := "0001";
CONSTANT S2 :std_logic_vector(3 DOWNTO 0 ) := "0010";
CONSTANT S3 :std_logic_vector(3 DOWNTO 0 ) := "0011";
CONSTANT S4 :std_logic_vector(3 DOWNTO 0 ) := "0100";
CONSTANT S5 :std_logic_vector(3 DOWNTO 0 ) := "0101";
CONSTANT S6 :std_logic_vector(3 DOWNTO 0 ) := "0110";
CONSTANT S7 :std_logic_vector(3 DOWNTO 0 ) := "0111";
CONSTANT S8 :std_logic_vector(3 DOWNTO 0 ) := "1000";
CONSTANT S9 :std_logic_vector(3 DOWNTO 0 ) := "1001";
CONSTANT S10 :std_logic_vector(3 DOWNTO 0 ) := "1010";
CONSTANT S11 :std_logic_vector(3 DOWNTO 0 ) := "1011";
CONSTANT S12 :std_logic_vector(3 DOWNTO 0 ) := "1100";
CONSTANT S13 :std_logic_vector(3 DOWNTO 0 ) := "1101";
CONSTANT S14 :std_logic_vector(3 DOWNTO 0 ) := "1110";
CONSTANT S15 :std_logic_vector(3 DOWNTO 0 ) := "1111";
BEGIN
temp_s3_0 := operation;
temp_or1 := (OTHERS => '0');
temp_or0 := (OTHERS => '0');
temp_and1 := (OTHERS => '1');
temp_and0 := (OTHERS => '1');
temp_not_a := NOT(Left);
temp_not_b := NOT(Right);
CASE temp_s3_0 IS
WHEN S1 =>
temp_or0 := temp_not_a;
temp_or1 := temp_not_b;
temp_and0 := Left;
temp_and1 := Right;
WHEN S2 =>
temp_or0 := temp_not_a;
temp_or1 := Right;
temp_and0 := Left;
temp_and1 := temp_not_b;
WHEN S4 =>
temp_and0 := temp_not_a;
temp_and1 := temp_not_b;
temp_or0 := Left;
temp_or1 := temp_not_b;
WHEN S5 =>
temp_and0 := Left;
temp_and1 := Right;
temp_or0 := Left;
temp_or1 := temp_not_b;
WHEN S6 =>
temp_and0 := temp_not_a;
temp_and1 := temp_not_b;
WHEN S7 =>
temp_or0 := Left;
temp_or1 := temp_not_b;
WHEN S8 =>
temp_and0 := temp_not_a;
temp_and1 := Right;
temp_or0 := Left;
temp_or1 := Right;
WHEN S9 =>
temp_or0 := Left;
temp_or1 := Right;
WHEN S10 =>
temp_and0 := Left;
temp_and1 := temp_not_b;
temp_or0 := Left;
temp_or1 := Right;
WHEN S11 =>
temp_or0 := Left;
temp_or1 := Right;
WHEN S13 | S14 =>
temp_and0 := Left;
temp_and1 := Right;
temp_or0 := temp_not_a;
temp_or1 := Right;
WHEN OTHERS =>
temp_and0 := (OTHERS => 'X');
temp_and1 := (OTHERS => 'X');
temp_or0 := (OTHERS => 'X');
temp_or1 := (OTHERS => 'X');
END CASE;
temp_xorout := Left XOR Right;
temp_andout := temp_and0 AND temp_and1;
temp_orout := temp_or0 OR temp_or1;
temp_tain0 := (OTHERS => '0');
temp_tain1 := (OTHERS => '1'); -- minus 1
temp_ltemp := (OTHERS => '0');
CASE temp_s3_0 IS
WHEN S0 =>
temp_ltemp := temp_not_a;
temp_tain0 := Left;
WHEN S1 | S2 =>
temp_ltemp := temp_orout;
temp_tain0 := temp_andout;
WHEN S3 =>
temp_ltemp := (OTHERS => '0');
temp_ltemp(0) := '1';
WHEN S4 =>
temp_ltemp := temp_andout;
temp_tain0 := Left;
temp_tain1 := temp_orout;
WHEN S5 =>
temp_ltemp := temp_not_b;
temp_tain0 := temp_andout;
temp_tain1 := temp_orout;
WHEN S6 =>
temp_ltemp := NOT(temp_xorout);
temp_tain0 := Left;
temp_tain1 := temp_not_b;
WHEN S7 =>
temp_ltemp := temp_orout;
temp_tain1 := temp_orout;
WHEN S8 =>
temp_ltemp := temp_andout;
temp_tain0 := Left;
temp_tain1 := temp_orout;
WHEN S9 =>
temp_ltemp := temp_xorout;
temp_tain0 := Left;
temp_tain1 := Right;
WHEN S10 =>
temp_ltemp := Right;
temp_tain0 := temp_andout;
temp_tain1 := temp_orout;
WHEN S11 =>
temp_ltemp := temp_orout;
temp_tain1 := temp_orout;
WHEN S12 =>
temp_ltemp := (OTHERS => '0');
temp_tain0 := Left;
temp_tain1 := Left;
WHEN S13 =>
temp_ltemp := NOT(temp_orout);
temp_tain0 := temp_andout;
temp_tain1 := Left;
WHEN S14 =>
temp_ltemp := temp_andout;
temp_tain0 := NOT(temp_orout);
temp_tain1 := Left;
WHEN S15 =>
temp_ltemp := Left;
temp_tain1 := Left;
WHEN OTHERS =>
temp_ltemp := (OTHERS => 'X');
temp_tain0 := (OTHERS => 'X');
temp_tain1 := (OTHERS => 'X');
END CASE;
mw_custom_ALUlout <= temp_ltemp;
mw_custom_ALUa_in <= temp_tain0;
mw_custom_ALUb_in <= temp_tain1;
END PROCESS custom_alumux_proc;
-- ModuleWare code(v1.12) for instance 'Comparator' of 'cmp'
comparatorcombo_proc : PROCESS (ALU_Result_internal, dout)
VARIABLE temp_lgt : std_logic;
VARIABLE temp_leq : std_logic;
BEGIN
temp_lgt := '0';
temp_leq := '0';
IF (signed(ALU_Result_internal) > signed(dout)) THEN
temp_lgt := '1';
ELSIF (signed(ALU_Result_internal) = signed(dout)) THEN
temp_leq := '1';
END IF;
Is_zero <= temp_leq;
Is_negative <= NOT(temp_lgt OR temp_leq);
END PROCESS comparatorcombo_proc;
-- ModuleWare code(v1.12) for instance 'ZERO' of 'constval'
dout <= "0000000000000000";
-- ModuleWare code(v1.12) for instance 'pc_increment_Amount' of 'constval'
dout1 <= "0000000000000001";
-- Instance port mappings.
-- Implicit buffered output assignments
ALU_Result <= ALU_Result_internal;
END struct;
| gpl-2.0 |
hmdgharb/5-Staged-MIPS-Pipeline | work/@six@to@sixteen/_primary.vhd | 1 | 225 | library verilog;
use verilog.vl_types.all;
entity SixToSixteen is
port(
\In\ : in vl_logic_vector(5 downto 0);
\Out\ : out vl_logic_vector(15 downto 0)
);
end SixToSixteen;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_fifo_ifmodule.vhd | 1 | 16786 | -------------------------------------------------------------------------------
-- qspi_fifo_ifmodule.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_fifo_ifmodule.vhd
-- Version: v3.0
-- Description: Quad Serial Peripheral Interface (QSPI) Module for interfacing
-- with a 32-bit axi Bus. FIFO Interface module
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Bus2IP_RcFIFO_RdCE -- Bus2IP receive FIFO read CE
-- Bus2IP_TxFIFO_WrCE -- Bus2IP transmit FIFO write CE
-- Rd_ce_reduce_ack_gen -- commong logid to generate the write ACK
-- Wr_ce_reduce_ack_gen -- commong logid to generate the write ACK
-- IP2Bus_RX_FIFO_Data -- Data to send on the bus
-- Transmit_ip2bus_error -- Transmit FIFO error signal
-- Receive_ip2bus_error -- Receive FIFO error signal
-- FIFO INTERFACE
-- Data_From_TxFIFO -- Data from transmit FIFO
-- Tx_FIFO_Data_WithZero -- Components to put zeros on input
-- to Shift Register when FIFO is empty
-- Data_From_Rc_FIFO -- Receive FIFO data output
-- Rc_FIFO_Empty -- Receive FIFO empty
-- Rc_FIFO_Full -- Receive FIFO full
-- Rc_FIFO_Full_strobe -- 1 cycle wide receive FIFO full strobe
-- Tx_FIFO_Empty -- Transmit FIFO empty
-- Tx_FIFO_Empty_strobe -- 1 cycle wide transmit FIFO full strobe
-- Tx_FIFO_Full -- Transmit FIFO full
-- Tx_FIFO_Occpncy_MSB -- Transmit FIFO occupancy register
-- MSB bit
-- Tx_FIFO_less_half -- Transmit FIFO less than half empty
-- SPI MODULE INTERFACE
-- DRR_Overrun -- DRR Overrun bit
-- SPIXfer_done -- SPI transfer done flag
-- DTR_Underrun_strobe -- DTR Underrun Strobe bit
-- DTR_underrun -- DTR underrun generation signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_fifo_ifmodule is
generic
(
C_NUM_TRANSFER_BITS : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Bus2IP_RcFIFO_RdCE : in std_logic;
Bus2IP_TxFIFO_WrCE : in std_logic;
Rd_ce_reduce_ack_gen : in std_logic;
-- FIFO ports
Data_From_TxFIFO : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Data_From_Rc_FIFO : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Tx_FIFO_Data_WithZero: out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
IP2Bus_RX_FIFO_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
---------------------
Rc_FIFO_Full : in std_logic;
Rc_FIFO_Full_strobe : out std_logic;
---------------------
Tx_FIFO_Empty : in std_logic;
Tx_FIFO_Empty_strobe : out std_logic;
---------------------
Rc_FIFO_Empty : in std_logic;
Receive_ip2bus_error : out std_logic;
Tx_FIFO_Full : in std_logic;
Transmit_ip2bus_error: out std_logic;
---------------------
Tx_FIFO_Occpncy_MSB : in std_logic;
Tx_FIFO_less_half : out std_logic;
---------------------
DTR_underrun : in std_logic;
DTR_Underrun_strobe : out std_logic;
---------------------
SPIXfer_done : in std_logic;
rready : in std_logic
--DRR_Overrun_reg : out std_logic
---------------------
);
end qspi_fifo_ifmodule;
-------------------------------------------------------------------------------
-- Architecture
---------------
architecture imp of qspi_fifo_ifmodule is
---------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
-- signal drr_Overrun_i : std_logic;
signal rc_FIFO_Full_d1 : std_logic;
signal dtr_Underrun_strobe_i : std_logic;
signal tx_FIFO_Empty_d1 : std_logic;
signal tx_FIFO_Occpncy_MSB_d1 : std_logic;
signal dtr_underrun_d1 : std_logic;
signal RST_TxFIFO_ptr_int : std_logic;
signal DRR_Overrun_reg_int : std_logic;
---------------------------------------------
begin
-----
-- Combinatorial operations
-------------------------------------------------------------------------------
-- DRR_Overrun_reg <= DRR_Overrun_reg_int;
-------------------------------------------------------------------------------
-- SPI_RECEIVE_FIFO_RD_GENERATE : Read of SPI receive FIFO
----------------------------------
SPI_RECEIVE_FIFO_RD_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
-----
begin
-----
IP2Bus_RX_FIFO_Data(i) <= Data_From_Rc_FIFO(i) and
(
(Rd_ce_reduce_ack_gen or rready) and
Bus2IP_RcFIFO_RdCE
);
end generate SPI_RECEIVE_FIFO_RD_GENERATE;
-------------------------------------------------------------------------------
-- PUT_ZEROS_IN_SR_GENERATE : Put zeros on input to SR when FIFO is empty.
-- Requested by software designers
------------------------------
PUT_ZEROS_IN_SR_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
-----
Tx_FIFO_Data_WithZero(i) <= Data_From_TxFIFO(i) and (not Tx_FIFO_Empty);
end generate PUT_ZEROS_IN_SR_GENERATE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RX_ERROR_ACK_REG_PROCESS : Strobe error when receive FIFO is empty.
-------------------------------- This signal will be OR'ed to generate IP2Bus_Error signal.
RX_ERROR_ACK_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Receive_ip2bus_error <= '0';
else
Receive_ip2bus_error <= Rc_FIFO_Empty and Bus2IP_RcFIFO_RdCE;
end if;
end if;
end process RX_ERROR_ACK_REG_PROCESS;
-------------------------------------------------------------------------------
-- TX_ERROR_ACK_REG_PROCESS : Strobe error when transmit FIFO is full
-------------------------------- This signal will be OR'ed to generate IP2Bus_Error signal.
TX_ERROR_ACK_REG_PROCESS:process(Bus2IP_Clk) is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Transmit_ip2bus_error <= '0';
else
Transmit_ip2bus_error <= Tx_FIFO_Full and Bus2IP_TxFIFO_WrCE;
end if;
end if;
end process TX_ERROR_ACK_REG_PROCESS;
-------------------------------------------------------------------------------
-- **********************************************************
-- Below logic will generate the inputs to the Interrupt bits
-- **********************************************************
-------------------------------------------------------------------------------
-- I_DRR_OVERRUN_REG_PROCESS:DRR overrun strobe-1 cycle strobe will be generated
-----------------------------
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rc_FIFO_Full and
SPIXfer_done;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
-------------------------------------------------------------------------------
-- RX_FIFO_STROBE_REG_PROCESS : Strobe when receive FIFO is full
----------------------------------
RX_FIFO_STROBE_REG_PROCESS:process(Bus2IP_Clk) is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
rc_FIFO_Full_d1 <= '0';
else
rc_FIFO_Full_d1 <= Rc_FIFO_Full;
end if;
end if;
end process RX_FIFO_STROBE_REG_PROCESS;
-----------------------------------------
Rc_FIFO_Full_strobe <= (not rc_FIFO_Full_d1) and Rc_FIFO_Full;
-- TX_FIFO_STROBE_REG_PROCESS : Strobe when transmit FIFO is empty
----------------------------------
TX_FIFO_STROBE_REG_PROCESS:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
tx_FIFO_Empty_d1 <= '1';
else
tx_FIFO_Empty_d1 <= Tx_FIFO_Empty;
end if;
end if;
end process TX_FIFO_STROBE_REG_PROCESS;
-----------------------------------------
Tx_FIFO_Empty_strobe <= (not tx_FIFO_Empty_d1) and Tx_FIFO_Empty;
-------------------------------------------------------------------------------
-- DTR_UNDERRUN_REG_PROCESS_P : Strobe to interrupt for transmit data underrun
-- which happens only in slave mode
-----------------------------
DTR_UNDERRUN_REG_PROCESS_P:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
dtr_underrun_d1 <= '0';
else
dtr_underrun_d1 <= DTR_underrun;
end if;
end if;
end process DTR_UNDERRUN_REG_PROCESS_P;
---------------------------------------
DTR_Underrun_strobe <= DTR_underrun and (not dtr_underrun_d1);
-------------------------------------------------------------------------------
-- TX_FIFO_HALFFULL_STROBE_REG_PROCESS_P : Strobe for when transmit FIFO is
-- less than half full
-------------------------------------------
TX_FIFO_HALFFULL_STROBE_REG_PROCESS_P:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
tx_FIFO_Occpncy_MSB_d1 <= '0';
else
tx_FIFO_Occpncy_MSB_d1 <= Tx_FIFO_Occpncy_MSB;
end if;
end if;
end process TX_FIFO_HALFFULL_STROBE_REG_PROCESS_P;
--------------------------------------------------
Tx_FIFO_less_half <= tx_FIFO_Occpncy_MSB_d1 and (not Tx_FIFO_Occpncy_MSB);
--------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
| gpl-2.0 |
INTI-CMNB/Lattuino_IP_Core | Work/lattuino_1_bl_2.vhdl | 1 | 11197 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx/Lattice BRAM ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- This is a program memory for the AVR. It maps to a Xilinx/Lattice ----
---- BRAM. ----
---- This version can be modified by the CPU (i. e. SPM instruction) ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortPM(Xilinx) (Entity and architecture) ----
---- File name: pm_s_rw.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- iCE40 (iCE40HX4K) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- iCEcube2.2016.02 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lattuino_1_blPM_2 is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end entity lattuino_1_blPM_2;
architecture Xilinx of lattuino_1_blPM_2 is
constant ROM_SIZE : natural:=2**ADDR_W;
type rom_t is array(natural range 0 to ROM_SIZE-1) of std_logic_vector(WORD_SIZE-1 downto 0);
signal addr_r : std_logic_vector(ADDR_W-1 downto 0);
signal rom : rom_t :=
(
696 => x"c00e",
697 => x"c01b",
698 => x"c01a",
699 => x"c019",
700 => x"c018",
701 => x"c017",
702 => x"c016",
703 => x"c015",
704 => x"c014",
705 => x"c013",
706 => x"c012",
707 => x"c011",
708 => x"c010",
709 => x"c00f",
710 => x"c00e",
711 => x"2411",
712 => x"be1f",
713 => x"edcf",
714 => x"bfcd",
715 => x"e020",
716 => x"e6a0",
717 => x"e0b0",
718 => x"c001",
719 => x"921d",
720 => x"36a5",
721 => x"07b2",
722 => x"f7e1",
723 => x"d036",
724 => x"c125",
725 => x"cfe2",
726 => x"e081",
727 => x"bb8f",
728 => x"e681",
729 => x"ee93",
730 => x"e1a6",
731 => x"e0b0",
732 => x"99f1",
733 => x"c00a",
734 => x"9701",
735 => x"09a1",
736 => x"09b1",
737 => x"9700",
738 => x"05a1",
739 => x"05b1",
740 => x"f7b9",
741 => x"e0e0",
742 => x"e0f0",
743 => x"9509",
744 => x"ba1f",
745 => x"b38e",
746 => x"9508",
747 => x"e091",
748 => x"bb9f",
749 => x"9bf0",
750 => x"cffe",
751 => x"ba1f",
752 => x"bb8e",
753 => x"e080",
754 => x"e090",
755 => x"9508",
756 => x"dfe1",
757 => x"3280",
758 => x"f421",
759 => x"e184",
760 => x"dff2",
761 => x"e180",
762 => x"cff0",
763 => x"9508",
764 => x"93cf",
765 => x"2fc8",
766 => x"dfd7",
767 => x"3280",
768 => x"f439",
769 => x"e184",
770 => x"dfe8",
771 => x"2f8c",
772 => x"dfe6",
773 => x"e180",
774 => x"91cf",
775 => x"cfe3",
776 => x"91cf",
777 => x"9508",
778 => x"9abe",
779 => x"e044",
780 => x"e450",
781 => x"e020",
782 => x"e030",
783 => x"b388",
784 => x"2785",
785 => x"bb88",
786 => x"01c9",
787 => x"9701",
788 => x"f7f1",
789 => x"5041",
790 => x"f7c1",
791 => x"e011",
792 => x"dfbd",
793 => x"3380",
794 => x"f0c9",
795 => x"3381",
796 => x"f499",
797 => x"dfb8",
798 => x"3280",
799 => x"f7c1",
800 => x"e184",
801 => x"dfc9",
802 => x"e481",
803 => x"dfc7",
804 => x"e586",
805 => x"dfc5",
806 => x"e582",
807 => x"dfc3",
808 => x"e280",
809 => x"dfc1",
810 => x"e489",
811 => x"dfbf",
812 => x"e583",
813 => x"dfbd",
814 => x"e580",
815 => x"c0c2",
816 => x"3480",
817 => x"f421",
818 => x"dfa3",
819 => x"dfa2",
820 => x"dfbf",
821 => x"cfe2",
822 => x"3481",
823 => x"f469",
824 => x"df9d",
825 => x"3880",
826 => x"f411",
827 => x"e082",
828 => x"c029",
829 => x"3881",
830 => x"f411",
831 => x"e081",
832 => x"c025",
833 => x"3882",
834 => x"f511",
835 => x"e182",
836 => x"c021",
837 => x"3482",
838 => x"f429",
839 => x"e1c4",
840 => x"df8d",
841 => x"50c1",
842 => x"f7e9",
843 => x"cfe8",
844 => x"3485",
845 => x"f421",
846 => x"df87",
847 => x"df86",
848 => x"df85",
849 => x"cfe0",
850 => x"eb90",
851 => x"0f98",
852 => x"3093",
853 => x"f2f0",
854 => x"3585",
855 => x"f439",
856 => x"df7d",
857 => x"9380",
858 => x"0063",
859 => x"df7a",
860 => x"9380",
861 => x"0064",
862 => x"cfd5",
863 => x"3586",
864 => x"f439",
865 => x"df74",
866 => x"df73",
867 => x"df72",
868 => x"df71",
869 => x"e080",
870 => x"df95",
871 => x"cfb0",
872 => x"3684",
873 => x"f009",
874 => x"c039",
875 => x"df6a",
876 => x"9380",
877 => x"0062",
878 => x"df67",
879 => x"9380",
880 => x"0061",
881 => x"9210",
882 => x"0060",
883 => x"df62",
884 => x"3485",
885 => x"f419",
886 => x"9310",
887 => x"0060",
888 => x"c00a",
889 => x"9180",
890 => x"0063",
891 => x"9190",
892 => x"0064",
893 => x"0f88",
894 => x"1f99",
895 => x"9390",
896 => x"0064",
897 => x"9380",
898 => x"0063",
899 => x"e0c0",
900 => x"e0d0",
901 => x"9180",
902 => x"0061",
903 => x"9190",
904 => x"0062",
905 => x"17c8",
906 => x"07d9",
907 => x"f008",
908 => x"cfa7",
909 => x"df48",
910 => x"2f08",
911 => x"df46",
912 => x"9190",
913 => x"0060",
914 => x"91e0",
915 => x"0063",
916 => x"91f0",
917 => x"0064",
918 => x"1191",
919 => x"c005",
920 => x"921f",
921 => x"2e00",
922 => x"2e18",
923 => x"95e8",
924 => x"901f",
925 => x"9632",
926 => x"93f0",
927 => x"0064",
928 => x"93e0",
929 => x"0063",
930 => x"9622",
931 => x"cfe1",
932 => x"3784",
933 => x"f009",
934 => x"c03e",
935 => x"df2e",
936 => x"9380",
937 => x"0062",
938 => x"df2b",
939 => x"9380",
940 => x"0061",
941 => x"9210",
942 => x"0060",
943 => x"df26",
944 => x"3485",
945 => x"f419",
946 => x"9310",
947 => x"0060",
948 => x"c00a",
949 => x"9180",
950 => x"0063",
951 => x"9190",
952 => x"0064",
953 => x"0f88",
954 => x"1f99",
955 => x"9390",
956 => x"0064",
957 => x"9380",
958 => x"0063",
959 => x"df16",
960 => x"3280",
961 => x"f009",
962 => x"cf55",
963 => x"e184",
964 => x"df26",
965 => x"e0c0",
966 => x"e0d0",
967 => x"9180",
968 => x"0061",
969 => x"9190",
970 => x"0062",
971 => x"17c8",
972 => x"07d9",
973 => x"f528",
974 => x"9180",
975 => x"0060",
976 => x"2388",
977 => x"f011",
978 => x"e080",
979 => x"c005",
980 => x"91e0",
981 => x"0063",
982 => x"91f0",
983 => x"0064",
984 => x"9184",
985 => x"df11",
986 => x"9180",
987 => x"0063",
988 => x"9190",
989 => x"0064",
990 => x"9601",
991 => x"9390",
992 => x"0064",
993 => x"9380",
994 => x"0063",
995 => x"9621",
996 => x"cfe2",
997 => x"3785",
998 => x"f479",
999 => x"deee",
1000 => x"3280",
1001 => x"f009",
1002 => x"cf2d",
1003 => x"e184",
1004 => x"defe",
1005 => x"e18e",
1006 => x"defc",
1007 => x"e981",
1008 => x"defa",
1009 => x"e088",
1010 => x"def8",
1011 => x"e180",
1012 => x"def6",
1013 => x"cf22",
1014 => x"3786",
1015 => x"f009",
1016 => x"cf1f",
1017 => x"cf6b",
1018 => x"94f8",
1019 => x"cfff",
others => x"0000"
);
begin
use_rising_edge:
if FALL_EDGE='0' generate
do_rom:
process (clk_i)
begin
if rising_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_rising_edge;
use_falling_edge:
if FALL_EDGE='1' generate
do_rom:
process (clk_i)
begin
if falling_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_falling_edge;
data_o <= rom(to_integer(unsigned(addr_r)));
end architecture Xilinx; -- Entity: lattuino_1_blPM_2
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Ctrl_core_1.1/src/ppm_decoder.vhd | 2 | 4769 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/09/2015 10:34:39 AM
-- Design Name:
-- Module Name: ppm_decoder - ppm_decoder_behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ppm_decoder is
Port (
clk : in std_logic;
ppm_in : in STD_LOGIC;
ppm_out_1 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_2 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_3 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_4 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_5 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_6 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_7 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_8 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
intr_1 : out std_logic := '0';
intr_comp : out std_logic := '0');
-- ppm_sample : inout std_logic_vector (1 downto 0) := "00";
-- counter : inout unsigned (31 downto 0) := x"00_00_00_00";
-- reg_nr : inout unsigned (3 downto 0) := "0000");
end ppm_decoder;
architecture ppm_decoder_behavioral of ppm_decoder is
signal ppm_sample : std_ulogic_vector (1 downto 0) := "00";
signal counter : unsigned (31 downto 0) := x"00_00_00_00";
signal reg_nr : unsigned (3 downto 0) := "0000";
signal counter_valid : std_logic := '0';
signal reg_nr_last : unsigned (3 downto 0) := "0000";
begin
ppm_edge_detection: process (clk)
begin
if rising_edge(clk) then
ppm_sample(1) <= ppm_sample(0); -- record last ppm signal level in ppm_sample(1)
ppm_sample(0) <= ppm_in; -- record current ppm signal level in ppm_sample(0)
case ppm_sample is
when "11" => -- signal level high, reset counter to "0"
counter <= (others => '0');
counter_valid <= '0';
when "10" => -- falling edge -> start counting
counter <= x"00_00_00_01";
counter_valid <= '0';
when "00" => -- signal level is high -> count until overrun detected
if counter < x"00_03_00_00" then
counter <= counter + 1;
end if;
counter_valid <= '0';
when "01" => -- rising edge -> save counter value to corresponding register, reset on counter "overflow"
if counter = x"00_03_00_00" then
reg_nr <= "0000";
else
reg_nr <= reg_nr + 1;
end if;
counter_valid <= '1'
;
when others =>
ppm_sample <= "11";
counter_valid <= '0';
end case;
end if;
end process;
rigister_write: process (clk)
begin
if rising_edge(clk) and counter_valid = '1' then
case reg_nr is
-- when "0000" =>; in this case an overrun occured and there is no valid value
when "0001" =>
ppm_out_1 <= std_logic_vector(counter);
when "0010" =>
ppm_out_2 <= std_logic_vector(counter);
when "0011" =>
ppm_out_3 <= std_logic_vector(counter);
when "0100" =>
ppm_out_4 <= std_logic_vector(counter);
when "0101" =>
ppm_out_5 <= std_logic_vector(counter);
when "0110" =>
ppm_out_6 <= std_logic_vector(counter);
when "0111" =>
ppm_out_7 <= std_logic_vector(counter);
when "1000" =>
ppm_out_8 <= std_logic_vector(counter);
when others =>
-- the values should be saved when not altered -> latches should be generated
end case;
end if;
end process;
interrupt: process (clk)
begin
if rising_edge(clk) then
if reg_nr /= "0000" and reg_nr /= reg_nr_last then
intr_1 <= '1';
else
intr_1 <= '0';
end if;
if reg_nr = "0000" and reg_nr /= reg_nr_last then
intr_comp <= '1';
else
intr_comp <= '1';
end if;
reg_nr_last <= reg_nr;
end if;
end process; --interrupt
end ppm_decoder_behavioral;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/rcs.ei.tum.de/Syma_Ctrl_core_v1_2/5d78a94c/src/ppm_decoder.vhd | 2 | 4769 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/09/2015 10:34:39 AM
-- Design Name:
-- Module Name: ppm_decoder - ppm_decoder_behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ppm_decoder is
Port (
clk : in std_logic;
ppm_in : in STD_LOGIC;
ppm_out_1 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_2 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_3 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_4 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_5 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_6 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_7 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_8 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
intr_1 : out std_logic := '0';
intr_comp : out std_logic := '0');
-- ppm_sample : inout std_logic_vector (1 downto 0) := "00";
-- counter : inout unsigned (31 downto 0) := x"00_00_00_00";
-- reg_nr : inout unsigned (3 downto 0) := "0000");
end ppm_decoder;
architecture ppm_decoder_behavioral of ppm_decoder is
signal ppm_sample : std_ulogic_vector (1 downto 0) := "00";
signal counter : unsigned (31 downto 0) := x"00_00_00_00";
signal reg_nr : unsigned (3 downto 0) := "0000";
signal counter_valid : std_logic := '0';
signal reg_nr_last : unsigned (3 downto 0) := "0000";
begin
ppm_edge_detection: process (clk)
begin
if rising_edge(clk) then
ppm_sample(1) <= ppm_sample(0); -- record last ppm signal level in ppm_sample(1)
ppm_sample(0) <= ppm_in; -- record current ppm signal level in ppm_sample(0)
case ppm_sample is
when "11" => -- signal level high, reset counter to "0"
counter <= (others => '0');
counter_valid <= '0';
when "10" => -- falling edge -> start counting
counter <= x"00_00_00_01";
counter_valid <= '0';
when "00" => -- signal level is high -> count until overrun detected
if counter < x"00_03_00_00" then
counter <= counter + 1;
end if;
counter_valid <= '0';
when "01" => -- rising edge -> save counter value to corresponding register, reset on counter "overflow"
if counter = x"00_03_00_00" then
reg_nr <= "0000";
else
reg_nr <= reg_nr + 1;
end if;
counter_valid <= '1'
;
when others =>
ppm_sample <= "11";
counter_valid <= '0';
end case;
end if;
end process;
rigister_write: process (clk)
begin
if rising_edge(clk) and counter_valid = '1' then
case reg_nr is
-- when "0000" =>; in this case an overrun occured and there is no valid value
when "0001" =>
ppm_out_1 <= std_logic_vector(counter);
when "0010" =>
ppm_out_2 <= std_logic_vector(counter);
when "0011" =>
ppm_out_3 <= std_logic_vector(counter);
when "0100" =>
ppm_out_4 <= std_logic_vector(counter);
when "0101" =>
ppm_out_5 <= std_logic_vector(counter);
when "0110" =>
ppm_out_6 <= std_logic_vector(counter);
when "0111" =>
ppm_out_7 <= std_logic_vector(counter);
when "1000" =>
ppm_out_8 <= std_logic_vector(counter);
when others =>
-- the values should be saved when not altered -> latches should be generated
end case;
end if;
end process;
interrupt: process (clk)
begin
if rising_edge(clk) then
if reg_nr /= "0000" and reg_nr /= reg_nr_last then
intr_1 <= '1';
else
intr_1 <= '0';
end if;
if reg_nr = "0000" and reg_nr /= reg_nr_last then
intr_comp <= '1';
else
intr_comp <= '1';
end if;
reg_nr_last <= reg_nr;
end if;
end process; --interrupt
end ppm_decoder_behavioral;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/bd/Test_AXI_Master_simple_v1_0_hw_1/ip/Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_1/synth/Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0.vhd | 2 | 9530 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_timer_v2_0;
USE axi_timer_v2_0.axi_timer;
ENTITY Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0;
ARCHITECTURE Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch: ARCHITECTURE IS "axi_timer,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch : ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0,axi_timer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch: ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0,axi_timer,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_timer,x_ipVersion=2.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_COUNT_WIDTH=32,C_ONE_TIMER_ONLY=0,C_TRIG0_ASSERT=1,C_TRIG1_ASSERT=1,C_GEN0_ASSERT=1,C_GEN1_ASSERT=1,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "zynq",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/bd/Test_AXI_Master_simple_v1_0_hw_1/ip/Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_2/synth/Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0.vhd | 2 | 4416 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0;
ARCHITECTURE Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_arch OF Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_arch : ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0,util_vector_logic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_arch: ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0,util_vector_logic,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_OPERATION=xor,C_SIZE=1}";
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "xor",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => Op2,
Res => Res
);
END Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_arch;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/bd/Test_AXI_Master_simple_v1_0_hw_1/ip/Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_1/synth/Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0.vhd | 2 | 4416 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0;
ARCHITECTURE Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_arch OF Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_arch : ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0,util_vector_logic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_arch: ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0,util_vector_logic,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_OPERATION=xor,C_SIZE=1}";
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "xor",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => Op2,
Res => Res
);
END Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0_arch;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/xip_status_reg.vhd | 1 | 11235 | -------------------------------------------------------------------------------
-- SPI Status Register Module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2011] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: xip_status_reg.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI4 Bus. The file defines the logic for
-- status register in XIP mode.
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.log2;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_SPI_NUM_BITS_REG -- Width of SPI registers
-- C_S_AXI_DATA_WIDTH -- Native data bus width 32 bits only
-- C_NUM_SS_BITS -- Number of bits in slave select
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- STATUS REGISTER RELATED SIGNALS
--================================
-- REGISTER/FIFO INTERFACE
-- Bus2IP_SPISR_RdCE -- Status register Read Chip Enable
-- IP2Bus_SPISR_Data -- Status register data to PLB based on PLB read
-- SR_3_modf -- Mode fault error status flag
-- SR_4_Tx_Full -- Transmit register full status flag
-- SR_5_Tx_Empty -- Transmit register empty status flag
-- SR_6_Rx_Full -- Receive register full status flag
-- SR_7_Rx_Empty -- Receive register empty stauts flag
-- ModeFault_Strobe -- Mode fault strobe
-- SLAVE REGISTER RELATED SIGNALS
--===============================
-- Bus2IP_SPISSR_WrCE -- slave select register write chip enable
-- Bus2IP_SPISSR_RdCE -- slave select register read chip enable
-- Bus2IP_SPISSR_Data -- slave register data from PLB Bus
-- IP2Bus_SPISSR_Data -- Data from slave select register during PLB rd
-- SPISSR_Data_reg_op -- Data to SPI Module
-- Wr_ce_reduce_ack_gen -- commaon write ack generation signal
-- Rd_ce_reduce_ack_gen -- commaon read ack generation signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity xip_status_reg is
generic
(
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
------------------------
C_XIP_SPISR_REG_WIDTH : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
--------------------------
XIPSR_AXI_TR_ERR : in std_logic; -- bit 4 of XIPSR
XIPSR_CPHA_CPOL_ERR : in std_logic; -- bit 3 of XIPSR
XIPSR_MST_MODF_ERR : in std_logic; -- bit 2 of XIPSR
XIPSR_AXI_RX_FULL : in std_logic; -- bit 1 of XIPSR
XIPSR_AXI_RX_EMPTY : in std_logic; -- bit 0 of XIPSR
--------------------------
Bus2IP_XIPSR_WrCE : in std_logic;
Bus2IP_XIPSR_RdCE : in std_logic;
--------------------------
--IP2Bus_XIPSR_RdAck : out std_logic;
--IP2Bus_XIPSR_WrAck : out std_logic;
IP2Bus_XIPSR_Data : out std_logic_vector((C_XIP_SPISR_REG_WIDTH-1) downto 0);
ip2Bus_RdAck : in std_logic
);
end xip_status_reg;
-------------------------------------------------------------------------------
-- Architecture
---------------
architecture imp of xip_status_reg is
----------------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal XIPSR_data_int : std_logic_vector(C_XIP_SPISR_REG_WIDTH-1 downto 0);
--signal ip2Bus_RdAck_core_reg : std_logic;
--signal ip2Bus_RdAck_core_reg_d1 : std_logic;
--signal ip2Bus_WrAck_core_reg : std_logic;
--signal ip2Bus_WrAck_core_reg_d1 : std_logic;
----------------------
begin
-----
-- XIPSR - 31 -- -- 5 4 3 2 1 0
-- <-- NA --> AXI CPOL_CPHA MODF Rx Rx
-- Transaction Error Error Error Full Empty
-- Default 0 0 0 0 0
-------------------------------------------------------------------------------
--XIPSR_CMD_ERR <= '0';
---------------------------------------
XIPSR_DATA_STORE_P:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
XIPSR_data_int((C_XIP_SPISR_REG_WIDTH-1) downto 0)<= (others => '0');
elsif(ip2Bus_RdAck = '1') then
XIPSR_data_int((C_XIP_SPISR_REG_WIDTH-1) downto 0)<= (others => '0');
else
XIPSR_data_int((C_XIP_SPISR_REG_WIDTH-1) downto 0)
<= XIPSR_AXI_TR_ERR & -- bit 4
XIPSR_CPHA_CPOL_ERR &
XIPSR_MST_MODF_ERR &
XIPSR_AXI_RX_FULL &
XIPSR_AXI_RX_EMPTY ; -- bit 0
end if;
end if;
end process XIPSR_DATA_STORE_P;
--------------------------------------------------
XIPSR_REG_RD_GENERATE: for i in C_XIP_SPISR_REG_WIDTH-1 downto 0 generate
-----
begin
-----
IP2Bus_XIPSR_Data(i) <= XIPSR_data_int(i) and Bus2IP_XIPSR_RdCE ; --and ip2Bus_RdAck_core_reg;
end generate XIPSR_REG_RD_GENERATE;
-----------------------------------
---------------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
| gpl-2.0 |
INTI-CMNB/Lattuino_IP_Core | FPGA/lattuino_stick/lattuino_stick.vhdl | 1 | 15402 | ------------------------------------------------------------------------------
---- ----
---- AVR ATtX5 CPU for Lattuino ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- This module implements the CPU for Lattuino (iCE40HX1K Lattice FPGA ----
---- available in the iCE Stick board). ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL v2 or newer license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: Lattuino_Stick(FPGA) (Entity and architecture) ----
---- File name: lattuino_stick.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- avr.Micros ----
---- miniuart.UART ----
---- CapSense.Devices ----
---- work.WBDevInterconPkg ----
---- work.CPUConfig ----
---- lattice.components ----
---- Target FPGA: iCE40HX1K-TQ144 ----
---- Language: VHDL ----
---- Wishbone: None ----
---- Synthesis tools: Lattice iCECube2 2016.02.27810 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library avr;
use avr.Micros.all;
library miniuart;
use miniuart.UART.all;
library CapSense;
use CapSense.Devices.all;
library lattice;
use lattice.components.all;
library lattuino;
use lattuino.PrgMems.all;
library work;
use work.CPUConfig.all;
entity Lattuino_Stick is
port(
CLK : in std_logic; -- CPU clock
-- Buil-in LEDs
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
LED4 : out std_logic;
LED5 : out std_logic;
-- Arduino UNO I/O
ARDU00 : inout std_logic;
ARDU01 : inout std_logic;
ARDU02 : inout std_logic;
ARDU03 : inout std_logic;
ARDU04 : inout std_logic;
ARDU05 : inout std_logic;
ARDU06 : inout std_logic;
ARDU07 : inout std_logic;
ARDU08 : inout std_logic;
ARDU09 : inout std_logic;
ARDU10 : inout std_logic; -- SS
ARDU11 : inout std_logic; -- MOSI
ARDU12 : inout std_logic; -- MISO
ARDU13 : inout std_logic; -- SCK
-- UART
FTDI_RXD : out std_logic; -- to UART Tx
FTDI_TXD : in std_logic; -- to UART Rx
FTDI_DTR : in std_logic); -- UART DTR
end entity Lattuino_Stick;
architecture FPGA of Lattuino_Stick is
constant BRDIVISOR : natural:=natural(real(F_CLK)/real(BAUD_RATE)/4.0+0.5);
constant CNT_PRESC : natural:=F_CLK/1e6; -- Counter prescaler (1 µs)
constant DEBUG_SPI : boolean:=false;
signal pc : unsigned(15 downto 0); -- PROM address
signal pcsv : std_logic_vector(ROM_ADDR_W-1 downto 0); -- PROM address
signal inst : std_logic_vector(15 downto 0); -- PROM data
signal inst_w : std_logic_vector(15 downto 0); -- PROM data
signal we : std_logic;
signal rst : std_logic;
signal rst2 : std_logic:='0';
signal portb_in : std_logic_vector(6 downto 0);
signal portb_out : std_logic_vector(6 downto 0);
signal portb_oe : std_logic_vector(6 downto 0);
signal portd_in : std_logic_vector(7 downto 0);
signal portd_out : std_logic_vector(7 downto 0);
signal portd_oe : std_logic_vector(7 downto 0);
signal pin_irq : std_logic_vector(1 downto 0); -- Pin interrupts INT0/1
signal dev_irq : std_logic_vector(2 downto 0); -- Device interrupts
signal dev_ack : std_logic_vector(2 downto 0); -- Device ACK
-- WISHBONE signals:
-- cpu
signal cpu_dati : std_logic_vector(7 downto 0);
signal cpu_acki : std_logic;
signal cpu_dato : std_logic_vector(7 downto 0);
signal cpu_weo : std_logic;
signal cpu_adro : std_logic_vector(7 downto 0);
signal cpu_cyco : std_logic;
signal cpu_stbo : std_logic;
-- rs2
signal rs2_dato : std_logic_vector(7 downto 0);
signal rs2_acko : std_logic;
signal rs2_dati : std_logic_vector(7 downto 0);
signal rs2_wei : std_logic;
signal rs2_adri : std_logic_vector(0 downto 0);
signal rs2_stbi : std_logic;
-- tmr
signal tmr_dato : std_logic_vector(7 downto 0);
signal tmr_acko : std_logic;
signal tmr_dati : std_logic_vector(7 downto 0);
signal tmr_wei : std_logic;
signal tmr_adri : std_logic_vector(2 downto 0);
signal tmr_stbi : std_logic;
signal pwm : std_logic_vector(5 downto 0);
signal pwm_ena : std_logic_vector(5 downto 0);
signal t16_irq : std_logic;
signal t16_ack : std_logic;
signal inttx : std_logic;
signal intrx : std_logic;
signal dtr_r : std_logic;
signal dtr_reset : std_logic;
-- SPI
signal spi_sck : std_logic;
signal mosi : std_logic;
signal miso : std_logic;
signal spi_ena : std_logic; -- The CPU enabled the SPI pins
-- PLL
signal clk_spi : std_logic; -- SPI core clock
signal clk_sys : std_logic; -- CPU clock
signal pll_lock : std_logic;
begin
-------------------------------
-- RESET logic --
-- Power-On Reset + UART DTR --
-------------------------------
rst <= not(rst2) or dtr_reset;
do_reset:
process (clk_sys)
begin
if rising_edge(clk_sys) then
if rst2='0' and pll_lock='1' then
rst2 <= '1';
end if;
end if;
end process do_reset;
-- The DTR reset is triggered by a falling edge at DTR
do_sample_dtr:
process (clk_sys)
begin
if rising_edge(clk_sys) then
dtr_r <= FTDI_DTR;
end if;
end process do_sample_dtr;
dtr_reset <= '1' when dtr_r='1' and FTDI_DTR='0' else '0';
-- Built-in LEDs
LED1 <= portb_out(6); -- pin IO14
LED2 <= portd_out(0);
LED3 <= portd_out(1);
LED4 <= portd_out(2);
LED5 <= portd_out(3);
-- Arduino IOx pins:
ARDU00 <= portd_out(0) when portd_oe(0)='1' else 'Z';
ARDU01 <= portd_out(1) when portd_oe(1)='1' else 'Z';
ARDU02 <= portd_out(2) when portd_oe(2)='1' else 'Z';
ARDU03 <= portd_out(3) when portd_oe(3)='1' else 'Z';
ARDU04 <= portd_out(4) when portd_oe(4)='1' else 'Z';
ARDU05 <= portd_out(5) when portd_oe(5)='1' else 'Z';
ARDU06 <= portd_out(6) when portd_oe(6)='1' else 'Z';
ARDU07 <= portd_out(7) when portd_oe(7)='1' else 'Z';
ARDU08 <= portb_out(0) when portb_oe(0)='1' else 'Z';
ARDU09 <= portb_out(1) when portb_oe(1)='1' else 'Z';
ARDU10 <= portb_out(2) when portb_oe(2)='1' else 'Z';
ARDU11 <= portb_out(3) when portb_oe(3)='1' else 'Z';
ARDU12 <= portb_out(4) when portb_oe(4)='1' else 'Z';
ARDU13 <= portb_out(5) when portb_oe(5)='1' else 'Z';
portd_in(0) <= ARDU00;
portd_in(1) <= ARDU01;
portd_in(2) <= ARDU02;
portd_in(3) <= ARDU03;
portd_in(4) <= ARDU04;
portd_in(5) <= ARDU05;
portd_in(6) <= ARDU06;
portd_in(7) <= ARDU07;
portb_in(0) <= ARDU08;
portb_in(1) <= ARDU09;
portb_in(2) <= ARDU10;
portb_in(3) <= ARDU11;
portb_in(4) <= ARDU12;
portb_in(5) <= ARDU13;
miso <= ARDU12;
-- INT0/1 pins (PD2 and PD3)
pin_irq(0) <= ARDU02 when ENA_INT0 else '0';
pin_irq(1) <= ARDU03 when ENA_INT1 else '0';
-- Device interrupts
dev_irq(0) <= intrx; -- UART Rx
dev_irq(1) <= inttx; -- UART Tx
dev_irq(2) <= t16_irq; -- 16 bits Timer
t16_ack <= dev_ack(2);
micro : entity avr.ATtX5
generic map(
ENA_WB => '1', ENA_SPM => '1', ENA_PORTB => '1',
ENA_PORTC => '0', ENA_PORTD => '1', PORTB_SIZE => 7,
PORTC_SIZE => 6, PORTD_SIZE => 8, RESET_JUMP => RESET_JUMP,
ENA_IRQ_CTRL => '1', ENA_AVR25 => '0', RAM_ADDR_W => RAM_ADDR_W,
ENA_SPI => ENABLE_SPI)
port map(
rst_i => rst, clk_i => clk_sys, clk2x_i => clk_spi,
pc_o => pc, inst_i => inst, ena_i => '1', portc_i => open,
portb_i => portb_in, pgm_we_o => we, inst_o => inst_w,
portd_i => portd_in, pin_irq_i => pin_irq, dev_irq_i => dev_irq,
dev_ack_o => dev_ack, portb_o => portb_out, portd_o => portd_out,
portb_oe_o => portb_oe, portd_oe_o => portd_oe,
-- SPI
spi_ena_o => spi_ena, sclk_o => spi_sck, miso_i => miso, mosi_o => mosi,
-- WISHBONE
wb_adr_o => cpu_adro, wb_dat_o => cpu_dato, wb_dat_i => cpu_dati,
wb_stb_o => cpu_stbo, wb_we_o => cpu_weo, wb_ack_i => cpu_acki,
-- Debug
dbg_stop_i => '0', dbg_rf_fake_i => '0', dbg_rr_data_i => (others => '0'),
dbg_rd_data_i => (others => '0'));
cpu_cyco <= '0';
pcsv <= std_logic_vector(pc(ROM_ADDR_W-1 downto 0));
-- Program memory (1/2/4Kx16) (2/4/8 kiB)
pm_2k:
if ROM_ADDR_W=10 generate
PM_Inst2 : lattuino_1_blPM_2S
generic map(
WORD_SIZE => 16, ADDR_W => ROM_ADDR_W)
port map(
clk_i => clk_sys, addr_i => pcsv, data_o => inst,
data_i => inst_w, we_i => we);
end generate pm_2k;
pm_4k:
if ROM_ADDR_W=11 generate
PM_Inst4 : lattuino_1_blPM_4
generic map(
WORD_SIZE => 16, ADDR_W => ROM_ADDR_W)
port map(
clk_i => clk_sys, addr_i => pcsv, data_o => inst,
data_i => inst_w, we_i => we);
end generate pm_4k;
pm_8k:
if ROM_ADDR_W=12 generate
PM_Inst8 : lattuino_1_blPM_8
generic map(
WORD_SIZE => 16, ADDR_W => ROM_ADDR_W)
port map(
clk_i => clk_sys, addr_i => pcsv, data_o => inst,
data_i => inst_w, we_i => we);
end generate pm_8k;
-------------------
-- WISHBONE UART --
-------------------
the_uart : UART_C
generic map(
BRDIVISOR => BRDIVISOR,
WIP_ENABLE => '1',
AUX_ENABLE => '0')
port map(
-- Wishbone signals
wb_clk_i => clk_sys, wb_rst_i => rst, wb_adr_i => cpu_adro(0 downto 0),
wb_dat_i => cpu_dato, wb_dat_o => cpu_dati, wb_we_i => cpu_weo,
wb_stb_i => cpu_stbo, wb_ack_o => cpu_acki,
-- Process signals
inttx_o => inttx, intrx_o => intrx, br_clk_i => '1',
txd_pad_o => FTDI_RXD, rxd_pad_i => FTDI_TXD);
----------------------------
-- WISHBONE time counters --
----------------------------
pwm <= (others => '0');
pwm_ena <= (others => '0');
------------------------------
-- WISHBONE 16 bits counter --
------------------------------
-- Not supported
t16_irq <= '0';
do_2xSPI:
if ENA_2xSCK generate
-- *************************************************************************
-- PLL: 48 MHz clock from 24 MHz clock
-- *************************************************************************
PLL1 : SB_PLL40_2F_PAD
generic map(
--- Feedback (all defaults)
FEEDBACK_PATH => "SIMPLE",
DELAY_ADJUSTMENT_MODE_FEEDBACK => "FIXED",
-- DELAY_ADJUSTMENT_MODE_RELATIVE => "FIXED",
SHIFTREG_DIV_MODE => "00", -- 0 --> Divide by 4, 1 --> Divide by 7, 3 --> Divide by 5
FDA_FEEDBACK => "0000",
-- FDA_RELATIVE => "0000",
PLLOUT_SELECT_PORTA => "GENCLK",
PLLOUT_SELECT_PORTB => "GENCLK_HALF",
-- Freq. Multiplier (DIVF+1)/((2**DIVQ)*(DIVR+1))=32/16=2
DIVF => "0011111", -- 31
DIVR => "0000",
DIVQ => "100", -- 4
FILTER_RANGE => "010", -- Not documented!
--- Output clock gates (for low power modes)
ENABLE_ICEGATE_PORTA => '0',
ENABLE_ICEGATE_PORTB => '0'
--- Test Mode Parameter
-- TEST_MODE => '0',
-- EXTERNAL_DIVIDE_FACTOR => 1 -- Not Used by model, Added for PLL config GUI
)
port map(
PACKAGEPIN => CLK, -- Clock pin from GBx
PLLOUTCOREA => open, -- Clock A (to logic)
PLLOUTGLOBALA => clk_spi, -- Clock A (to global lines)
PLLOUTCOREB => open, -- Clock B (to logic)
PLLOUTGLOBALB => clk_sys, -- Clock B (to global lines)
EXTFEEDBACK => open, -- External feedback (not used here)
DYNAMICDELAY => open, -- Dynamic delay (not used here)
LOCK => pll_lock, -- PLL is locked
BYPASS => '0', -- Bypass enable
RESETB => '1', -- /Reset
LATCHINPUTVALUE => open, -- Clock gate enable
-- Test Pins (not documented)
SDO => open, SDI => open, SCLK => open);
end generate do_2xSPI;
do_1xSPI:
if not(ENA_2xSCK) generate
clk_spi <= CLK;
clk_sys <= CLK;
pll_lock <= '1';
end generate do_1xSPI;
end architecture FPGA; -- Entity: Lattuino_Stick
| gpl-2.0 |
gustavowl/ProjetoOAC | ULA64bit/ula_tb.vhd | 1 | 1105 | library ieee;
use ieee.std_logic_1164.all;
entity ula_tb is
end ula_tb;
architecture ula_tb of ula_tb is
signal ma, mb, ms: std_logic_vector(63 downto 0);
signal mw, mx, my, mz, mcout, mclk, mdo_op, mdone, mst: std_logic;
begin
vector: entity work.ula
port map (
a => ma,
b => mb,
s => ms,
x => mx,
y => my,
z => mz,
clk => mclk,
do_op => mdo_op,
done => mdone,
state => mst,
couterro => mcout
);
process
begin
ma <= "0011111111111110000000000000101000111111111111100000000000001010";
mb <= "0011111101010110101010010011101000111111111111100000000000000010";
mw <= '0';
mx <= '0';
my <= '0';
mz <= '0';
wait for 50 ns;
mx <= '0';
my <= '0';
mz <= '1';
wait for 50 ns;
mx <= '0';
my <= '1';
mz <= '0';
wait for 50 ns;
mx <= '0';
my <= '1';
mz <= '1';
wait for 50 ns;
mx <= '1';
my <= '0';
mz <= '0';
wait for 50 ns;
mx <= '1';
my <= '0';
mz <= '1';
wait for 50 ns;
mx <= '1';
my <= '1';
mz <= '0';
wait for 50 ns;
mx <= '1';
my <= '1';
mz <= '1';
wait for 50 ns;
wait;
end process;
end ula_tb;
| gpl-2.0 |
universal-ctags/ctags | Units/parser-vhdl.r/bug2374109.vhd.d/input.vhd | 98 | 196 | function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
| gpl-2.0 |
anbe42/tmp-geda-gaf | gnetlist/examples/vams/vhdl/new-vhdl/top_test_entity.vhdl | 14 | 203 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY top_test_entity IS
END ENTITY top_test_entity;
| gpl-2.0 |
adamgreig/bladeRF | hdl/fpga/ip/altera/rx_fifo/rx_fifo_inst.vhd | 1 | 359 | rx_fifo_inst : rx_fifo PORT MAP (
aclr => aclr_sig,
data => data_sig,
rdclk => rdclk_sig,
rdreq => rdreq_sig,
wrclk => wrclk_sig,
wrreq => wrreq_sig,
q => q_sig,
rdempty => rdempty_sig,
rdfull => rdfull_sig,
rdusedw => rdusedw_sig,
wrempty => wrempty_sig,
wrfull => wrfull_sig,
wrusedw => wrusedw_sig
);
| gpl-2.0 |
andipla/autosub | src/tests/testTasksVHDL/testsubmissions/pwm/pwm_beh.vhdl | 2 | 646 | library IEEE;
use IEEE.std_logic_1164.all;
architecture behavior of pwm is
signal clk_cnt: natural := 0;
constant period :integer := 2500;
constant duty : integer := 1400;
begin
clk_count : process(CLK)
begin
if(rising_edge(CLK)) then
if(clk_cnt = period) then
clk_cnt <= 1;
else
clk_cnt <= clk_cnt + 1;
end if;
end if;
end process;
siggen: process(clk_cnt)
begin
if(clk_cnt = duty) then
O <= '0';
elsif(clk_cnt = period) then
O <= '1';
end if;
end process;
end behavior;
| gpl-2.0 |
dondamage/libhdl | lib/cells/bram_sp/bram_sp.vhd | 1 | 2270 |
library work;
use work.numeric_std.all;
use work.std_logic_1164.all;
entity bram_sp is
generic (
RAM_DEPTH : integer := 1024;
RAM_WIDTH : integer := 8;
RAM_RDWR_ORDER : string := "READ_FIRST"; -- {READ_FIRST, WRITE_FIRST}
RAM_INIT : string := "DEFAULT"; -- {DEFAULT, INIT_DATA, INIT_FILE}
RAM_INIT_DATA : std_logic_vector(RAM_DEPTH*RAM_WIDTH-1 downto 0) :=
(others => '0');
RAM_INIT_FILE : string
);
port (
clk_i : std_logic;
wraddr_i : std_logic_vector(clog2(RAM_DEPTH)-1 downto 0);
wren_i : std_logic;
wrdata_i : std_logic_vector(RAM_WIDTH-1 downto 0);
rdaddr_i : std_logic_vector(clog2(RAM_DEPTH)-1 downto 0);
rddata_o : std_logic_vector(RAM_WIDTH-1 downto 0)
);
end entity bram_sp;
architecture rtl of bram_sp is
type ram_t is array 0 to RAM_DEPTH-1 of std_logic_vector(RAM_WIDTH-1 downto 0);
function initialize_ram(
init_type : string;
init_data : std_logic_vector;
init_file : string
) return ram_t is
variable reval : ram_t;
begin
case init_type is
when "INIT_DATA" =>
for i in 0 to RAM_DEPTH-1 loop
reval(i) := RAM_INIT_DATA((i+1)*RAM_WIDTH-1 downto i*RAM_WIDTH);
end loop;
when "INIT_FILE" =>
when others =>
reval := (others => 'U');
end case;
return reval;
end function initialize_ram;
shared variable ram : ram_t := initialize_ram(RAM_INIT, RAM_INIT_DATA, RAM_INIT_FILE);
begin
p_bram_sp: process (clk_i) is
variable wraddr_int : integer;
variable rdaddr_int : integer;
begin
if rising_edge(clk_i) then
wraddr_int := to_integer(unsigned(wraddr_i));
if (RAM_RDWR_ORDER = "READ_FIRST") then
rddata_o <= ram(rdaddr_int);
end if;
if (wren_i = '1') then
ram(wraddr_int) := wrdata_i;
end if;
if (RAM_RDWR_ORDER = "WRITE_FIRST") then
rddata_o <= ram(rdaddr_int);
end if;
end if;
end process p_bram_sp;
end architecture rtl;
| gpl-2.0 |
dondamage/libhdl | doc/example_module.vhd | 1 | 4024 | --============================================================================
--!
--! \file example_module
--!
--! \project libhdl
--!
--! \author Andreas Muller
--!
--! \date 2015-04-20
--!
--! \version 1.0
--!
--! \brief Brief module description in one or two sentences.
--!
--! \details More detailed description. This should focus on the interfaces,
--! and at most give a rough outline of the internal
--! implementation.
--!
--! \bug No bugs or known issues.
--!
--! \see List of references useful for the understanding of this module.
--! e.g. standards, RFCs, papers, book chapters, web links &cetera.
--!
--! \copyright Copyright (C) 2015, Andreas Muller
--! GNU General Public License Version 2
--!
--! This program is free software; you can redistribute it and/or
--! modify it under the terms of the GNU General Public License as
--! published by the Free Software Foundation; either version 2 of
--! the License, or (at your option) any later version.
--! This program is distributed in the hope that it will be useful,
--! but WITHOUT ANY WARRANTY; without even the implied warranty of
--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--============================================================================
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
--! \brief A brief package description.
package template_module_package is
--! \brief This is the component declaration for my entity.
component template_module is
generic (
my_generic : integer := 0
);
port (
my_port : std_logic
);
end component template_module;
end package template_module_package;
--! \brief Import standard packages.
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
--! \brief A brief entity description.
entity template_module is
generic (
MY_GENERIC_A : integer := 8; --! This generic does foo.
MY_GENERIC_B : integer := 3 --! That generic does bar.
);
port (
clk_i : in std_logic; --! Clock input.
rst_i : in std_logic; --! Reset input.
my_port_i : in std_logic_vector(MY_GENERIC_A-1 downto 0); --! My input port description.
my_select_i : in std_logic_vector(MY_GENERIC_B-1 downto 0); --! My select description.
my_port_o : out std_logic_vector(MY_GENERIC_A-1 downto 0) --! My output port description.
);
begin
assert (2**MY_GENERIC_B >= MY_GENERIC_A)
report "example_module: Incompatible choice of generic values."
severity FAILURE;
end entity template_module;
--! \brief A brief architecture description.
architecture rtl of template_module is
--! \brief A brief function description.
--! \param Description of parameter 1.
--! \return Description of return value.
function my_function(param1 : integer) return integer is
begin
return param1;
end function my_function;
--! \brief A brief procedure description.
--! \param Description of parameter 1.
--! \return Description of return value.
procedure my_procedure(param1 : in integer, reval1 : out integer) is
begin
reval1 <= param1;
end function my_procedure;
begin
--! \brief A brief process description.
--! \vhdlflow
p_my_process_label:
process (clk_i, rst_i) is
begin
if (rst_i = '1') then
my_port_o <= (others => '0');
elsif rising_edge(clk_i) then
assert (to_integer(unsigned(my_select_i)) < my_port_i'length)
report "example_module: Invalid signal value."
severity error;
my_port_o <= (others => my_port_i(to_integer(unsigned(
my_select_i))));
end if;
end process;
end architecture rtl;
| gpl-2.0 |
dondamage/libhdl | comp/_template/vhdl/vhdl-1987/template_package.vhd | 1 | 860 | --============================================================================
--!
--! \file <FILE_NAME>
--!
--! \project <PROJECT_NAME>
--!
--! \langv VHDL-1987
--!
--! \brief <BRIEF_DESCRIPTION>.
--!
--! \details <DETAILED_DESCRIPTION>.
--!
--! \bug <BUGS_OR_KNOWN_ISSUES>.
--!
--! \see <REFERENCES>
--!
--! \copyright <COPYRIGHT_OR_LICENSE>
--!
--! Revision history:
--!
--! \version <VERSION>
--! \date <YYYY-MM-DD>
--! \author <AUTHOR_NAME>
--! \brief Create file.
--!
--============================================================================
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
package template_package is
end template_package;
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
package body template_package is
end template_package;
| gpl-2.0 |
peter-scholtens/geany | data/filedefs/filetypes.vhdl | 22 | 3042 | # For complete documentation of this file, please see Geany's main documentation
[styling]
# Edit these in the colorscheme .conf file instead
default=default
comment=comment
comment_line_bang=comment_line
block_comment=comment
number=number_1
string=string_1
operator=operator
identifier=identifier_1
stringeol=string_eol
keyword=keyword_1
stdoperator=operator
attribute=attribute
stdfunction=function
stdpackage=preprocessor
stdtype=type
userword=keyword_2
[keywords]
# all items must be in one line
keywords=access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity shared signal subtype then to transport type unaffected units until use variable wait when while with
operators=abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
attributes=left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction event active last_event last_active last_value driving driving_value simple_name path_name instance_name
std_functions=now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
std_packages=std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
std_types=boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
userwords=
[settings]
# default extension used when saving files
extension=vhd
# MIME type
mime_type=text/x-vhdl
# the following characters are these which a "word" can contains, see documentation
#wordchars=_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
# single comments, like # in this file
comment_single=--
# multiline comments
#comment_open=
#comment_close=
# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
#command_example();
# setting to false would generate this
# command_example();
# This setting works only for single line comments
comment_use_indent=true
# context action command (please see Geany's main documentation for details)
context_action_cmd=
[indentation]
#width=4
# 0 is spaces, 1 is tabs, 2 is tab & spaces
#type=1
| gpl-2.0 |
dondamage/libhdl | comp/_template/vhdl/vhdl-1987/template_testbench.vhdl | 1 | 792 | --============================================================================
--!
--! \file <FILE_NAME>
--!
--! \project <PROJECT_NAME>
--!
--! \langv VHDL-1987
--!
--! \brief <BRIEF_DESCRIPTION>.
--!
--! \details <DETAILED_DESCRIPTION>.
--!
--! \bug <BUGS_OR_KNOWN_ISSUES>.
--!
--! \see <REFERENCES>
--!
--! \copyright <COPYRIGHT_OR_LICENSE>
--!
--! Revision history:
--!
--! \version <VERSION>
--! \date <YYYY-MM-DD>
--! \author <AUTHOR_NAME>
--! \brief Create file.
--!
--============================================================================
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity template_testbench is
end entity template_testbench;
architecture tb of template_testbench is
begin
end tb;
| gpl-2.0 |
andipla/autosub | src/tests/testTasksVHDL/testsubmissions/crc/crc_beh.vhdl | 2 | 2789 | library IEEE;
use IEEE.std_logic_1164.all;
architecture behavior of crc is
constant msg_len :integer := 21;
constant gen_degree : integer := 8;
type crc_state is
(
PREPARE,
CALC,
FINISH,
IDLE
);
signal state,state_next : crc_state;
signal EN_next, RST_next,CRC_VALID_next: std_logic;
signal bit_nr,bit_nr_next:integer;
signal DATA_IN_next: std_logic;
component fsr is
port
(
EN : in std_logic;
RST : in std_logic; -- rising edge of RST should reset the content of the shift register to all 0
CLK : in std_logic; -- shift and feedback operations should be done on rising edge of CLK
DATA_IN : in std_logic; -- the bit which shall be shifted in
DATA : out std_logic_vector(gen_degree-1 downto 0) -- the current content of the feedback shift register
);
end component;
signal EN,RST,CLK_UUT,DATA_In : std_logic;
signal DATA: std_logic_vector(gen_degree-1 downto 0);
begin
CLK_UUT<=CLK;
UUT:fsr
port map
(
EN=>EN,
RST=>RST,
CLK=>CLK_UUT,
DATA_IN=>DATA_IN,
DATA=>DATA
);
--Next State Logic and communication with FSR----
nextState : process(state,bit_nr)
constant top_bit :integer:= msg_len-1;
begin
case state is
when PREPARE =>
CRC_VALID_next<='0';
EN_next<='1';
RST_next<='1';
bit_nr_next<=top_bit;
state_next<=CALC;
when CALC =>
RST_next<='0';
DATA_IN_next<=MSG(bit_nr);
if(bit_nr=0) then
state_next<=FINISH;
else
state_next<=CALC;
bit_nr_next<=bit_nr-1;
end if;
when FINISH =>
EN_next<='0';
CRC_VALID_next<='1';
state_next<=IDLE;
when IDLE =>
CRC <= DATA;
state_next <= IDLE;
when others=>
null;
end case;
end process nextState;
--Sync and Reset Logic--
sync_proc : process(clk, NEW_MSG)
begin
if rising_edge(NEW_MSG) then
state <= PREPARE;
elsif(rising_edge(CLK)) then
state <= state_next;
EN <= EN_next;
RST <= RST_next;
CRC_VALID <= CRC_VALID_next;
bit_nr <=bit_nr_next;
DATA_in<=DATA_IN_next;
end if;
end process sync_proc;
end behavior;
| gpl-2.0 |
NickTGraham/Traffic-Light-Controller | Traffic.vhd | 1 | 7749 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Traffic IS
PORT ( SW : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
Clock_50 : IN STD_LOGIC;
LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 6);
LEDG : OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END Traffic;
ARCHITECTURE Behavior OF Traffic IS
COMPONENT CONTROL
PORT( S:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
a, b, c, d, e, f, g, h :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M :OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END COMPONENT;
COMPONENT LIGHT
PORT(C :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
COLOR :OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT;
COMPONENT UpCounter
PORT( myClock : IN STD_LOGIC;
O : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT;
COMPONENT Clockz
Generic (N : INTEGER);
PORT ( Clock_50 : IN STD_LOGIC;
C : BUFFER STD_LOGIC);
END COMPONENT;
COMPONENT WALK
PORT (Blink : IN STD_LOGIC;
LSTATUS: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
WSTATUS : OUT STD_LOGIC);
END COMPONENT;
COMPONENT MODCLOCK
Generic (N : INTEGER);
PORT ( Clock_50, Trigger : IN STD_LOGIC;
Light : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
C : BUFFER STD_LOGIC);
END COMPONENT;
SIGNAL R, G, Y, A, B, C, D : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL WA, WB, WC, WD : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL S : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL L, T, L1, L2, Bl : STD_LOGIC;
BEGIN
G <= "00";
Y <= "01";
R <= "10";
T <= SW(5) OR SW(4) OR SW(1);
L0: Clockz Generic Map (50000000) --dropped a zero for testing
PORT MAP (Clock_50, L1);
B9: Clockz Generic Map (25000000) --droped a zero for testing
PORT MAP (Clock_50, Bl);
L5: ModClock Generic Map (50000000)
PORT MAP (Clock_50, T, A, L2);
L <= (Not SW(6) And L1) OR (SW(6) And L2);
S0: UpCounter PORT MAP(L, S); --Run through the Select options
A0: CONTROL PORT MAP (S, R, G, G, Y, R, R, R, R, A); --Light 1's State
B0: LIGHT PORT MAP (A, LEDR(17 DOWNTO 15)); --Control Light 1
WA(0) <= (NOT SW(2)) OR (SW(2) AND A(0)); --set up the Walk signal connected to light 1
WA(1) <= (NOT SW(2)) OR (SW(2) AND A(1)); --such that it displays Don't walk until the request is given, then it waits until it is safe to switch to walk
W0: WALK PORT MAP (Bl, WA, LEDG(0)); --control the Walk Sign.
C0: CONTROL PORT MAP (S, R, R, R, R, R, G, G, Y, B); --Set up for second Light and its Walk sign
D0: LIGHT PORT MAP (B, LEDR(14 DOWNTO 12));
WB(0) <= (NOT SW(1)) OR (SW(1) AND B(0));
WB(1) <= (NOT SW(1)) OR (SW(1) AND B(1));
W1: WALK PORT MAP (Bl, WB, LEDG(1));
E0: CONTROL PORT MAP (S, R, G, G, Y, R, R, R, R, C); --Set up for third Light and its Walk sign
F0: LIGHT PORT MAP (C, LEDR(11 DOWNTO 9));
WC(0) <= (NOT SW(2)) OR (SW(2) AND C(0));
WC(1) <= (NOT SW(2)) OR (SW(2) AND C(1));
W2: WALK PORT MAP (Bl, WC, LEDG(2));
G0: CONTROL PORT MAP (S, R, R, R, R, R, G, G, Y, D); --Set up for third Light and its Walk sign
H0: LIGHT PORT MAP (D, LEDR(8 DOWNTO 6));
WD(0) <= (NOT SW(1)) OR (SW(1) AND D(0));
WD(1) <= (NOT SW(1)) OR (SW(1) AND D(1));
W3: WALK PORT MAP (Bl, WD, LEDG(3));
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- implements a 2-bit wide 8-to-1 multiplexer
ENTITY CONTROL IS
PORT ( S : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
a, b, c, d, e, f, g, h : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END CONTROL;
ARCHITECTURE Behavior OF CONTROL IS
signal OUTPUT1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal OUTPUT2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal OUTPUT3 : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal OUTPUT4 : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal OUTPUT5 : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal OUTPUT6 : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
--LEDR <= SW;
--bit 0
OUTPUT1(0) <= ((NOT S(0) And a(0)) OR (S(0) And b(0)));
OUTPUT2(0) <= ((NOT S(0) And c(0)) OR (S(0) And d(0)));
OUTPUT3(0) <= ((NOT S(0) And e(0)) OR (S(0) And f(0)));
OUTPUT4(0) <= ((NOT S(0) And g(0)) OR (S(0) And h(0)));
OUTPUT5(0) <= ((NOT S(1) And OUTPUT1(0)) OR (S(1) And OUTPUT2(0)));
OUTPUT6(0) <= ((NOT S(1) And OUTPUT3(0)) OR (S(1) And OUTPUT4(0)));
M(0) <= ((NOT S(2) And OUTPUT5(0)) OR (S(2) And OUTPUT6(0)));
--bit 1
OUTPUT1(1) <= ((NOT S(0) And a(1)) OR (S(0) And b(1)));
OUTPUT2(1) <= ((NOT S(0) And c(1)) OR (S(0) And d(1)));
OUTPUT3(1) <= ((NOT S(0) And e(1)) OR (S(0) And f(1)));
OUTPUT4(1) <= ((NOT S(0) And g(1)) OR (S(0) And h(1)));
OUTPUT5(1) <= ((NOT S(1) And OUTPUT1(1)) OR (S(1) And OUTPUT2(1)));
OUTPUT6(1) <= ((NOT S(1) And OUTPUT3(1)) OR (S(1) And OUTPUT4(1)));
M(1) <= ((NOT S(2) And OUTPUT5(1)) OR (S(2) And OUTPUT6(1)));
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY LIGHT IS
PORT (C: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
COLOR : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END LIGHT;
ARCHITECTURE Behavior OF LIGHT IS
BEGIN
COLOR(0) <= NOT(C(1)) AND NOT(C(0)); --green light
COLOR(1) <= NOT(C(1)) AND C(0); --yellow light
COLOR(2) <= C(1); --red light
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY WALK IS
PORT (Blink : IN STD_LOGIC;
LSTATUS: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
WSTATUS : OUT STD_LOGIC);
END WALK;
ARCHITECTURE Behavior OF WALK IS
BEGIN
WITH LSTATUS SELECT
WSTATUS <= '1' WHEN "00",
Blink WHEN "01",
'0' WHEN OTHERS;
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Clockz IS
Generic (N : INTEGER);
PORT ( Clock_50 : IN STD_LOGIC;
C : BUFFER STD_LOGIC);
END Clockz;
ARCHITECTURE Behavior OF Clockz IS --clock behavior
Signal Count : INTEGER RANGE 0 to N; --clock frequency
BEGIN
PROCESS
BEGIN
wait until Clock_50='1';
Count<=Count+1;
if (Count = N) Then --dropped a zero for testing
Count<=0;
C <= Not C;
end if;
END PROCESS;
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY myflipflop IS --flip flop behavior
PORT ( D, Clock : IN STD_LOGIC ;
Q :BUFFER STD_LOGIC );
END myflipflop;
ARCHITECTURE Behavior OF myflipflop IS --wait until clock event and then push D to Q
BEGIN
Process
Begin
Wait until Clock'Event And Clock='1' AND D='1';
Q <= NOT(Q);
End Process;
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY UpCounter IS
PORT(myClock : IN STD_LOGIC;
O : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END UpCounter;
ARCHITECTURE Behavior OF UpCounter IS
COMPONENT myflipflop
PORT(D, Clock :IN STD_LOGIC;
Q :OUT STD_LOGIC);
END COMPONENT;
SIGNAL X, Y, Z, V, W : STD_LOGIC;
BEGIN
W <= myClock;
X0 : myflipflop PORT MAP ('1', W, X);
O(0) <= X; --LSB (Bit 0)
Y0 : myflipflop PORT MAP (X, W, Y);
O(1) <= Y; --Bit 1
V <= X AND Y;
Z0 : myflipflop PORT MAP (V, W, Z);
O(2) <= Z; --MSB (Bit 2)
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ModClock IS
GENERIC (N : integer);
PORT ( Clock_50, Trigger : IN STD_LOGIC;
Light : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
C : BUFFER STD_LOGIC);
END ModClock;
ARCHITECTURE Behavior OF ModClock IS --clock behavior
Signal Count : INTEGER RANGE 0 to N; --clock frequency
BEGIN
PROCESS
BEGIN
wait until Clock_50='1';
Count<=Count+1;
if (Count = N) Then
Count<=0;
if (Not (Light = "00")) Then
C<= NOT C;
elsif (Trigger = '1') Then
C <= Not C;
else
C <= C;
end if;
end if;
END PROCESS;
END Behavior;
| gpl-2.0 |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/axi_powerlink_v1_00_a/hdl/vhdl/pdi_dpr_Xilinx.vhd | 2 | 3626 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR for Xilinx
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-11-17 V0.01 zelenkaj First version
-- 2011-12-06 V0.02 zelenkaj Uses openMAC DPR implementation
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
architecture struct of pdi_dpr is
constant cActivated : std_logic := '1';
begin
abuseMacDpr : entity work.dc_dpr_be
generic map (
gDoInit => true,
WIDTH => data_a'length,
SIZE => NUM_WORDS,
ADDRWIDTH => LOG2_NUM_WORDS
)
port map (
clkA => clock_a, clkB => clock_b,
enA => cActivated, enB => cActivated,
addrA => address_a, addrB => address_b,
diA => data_a, diB => data_b,
doA => q_a, doB => q_b,
weA => wren_a, weB => wren_b,
beA => byteena_a, beB => byteena_b
);
end architecture struct;
| gpl-2.0 |
Charlesworth/Albot | Albot VHDL/altaccumulate0.vhd | 1 | 4654 | -- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: altaccumulate0.vhd
-- Megafunction Name(s):
-- altaccumulate
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altaccumulate0 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
cout : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END altaccumulate0;
ARCHITECTURE SYN OF altaccumulate0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT altaccumulate
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
width_in : NATURAL;
width_out : NATURAL
);
PORT (
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
result <= sub_wire1(15 DOWNTO 0);
altaccumulate_component : altaccumulate
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "altaccumulate",
width_in => 8,
width_out => 16
)
PORT MAP (
clken => clken,
aclr => aclr,
clock => clock,
data => data,
cout => sub_wire0,
result => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
-- Retrieval info: PRIVATE: CIN NUMERIC "0"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "1"
-- Retrieval info: PRIVATE: COUT NUMERIC "1"
-- Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "1"
-- Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_IN NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
-- Retrieval info: CONSTANT: WIDTH_IN NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "16"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0_inst.vhd TRUE
| gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd | 2 | 5890 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating
-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_xlnx_512x36_2clk IS
port (
din: IN std_logic_VECTOR(35 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(35 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
rd_data_count: OUT std_logic_VECTOR(8 downto 0);
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
END fifo_xlnx_512x36_2clk;
ARCHITECTURE fifo_xlnx_512x36_2clk_a OF fifo_xlnx_512x36_2clk IS
-- synthesis translate_off
component wrapped_fifo_xlnx_512x36_2clk
port (
din: IN std_logic_VECTOR(35 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(35 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
rd_data_count: OUT std_logic_VECTOR(8 downto 0);
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_xlnx_512x36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral)
generic map(
c_has_int_clk => 0,
c_rd_freq => 1,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 1,
c_din_width => 36,
c_has_wr_data_count => 1,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 0,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 0,
c_dout_width => 36,
c_msgon_val => 1,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 1,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 510,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_thresh_assert_val => 4,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 511,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_xlnx_512x36_2clk
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count);
-- synthesis translate_on
END fifo_xlnx_512x36_2clk_a;
| gpl-2.0 |
Charlesworth/Albot | Albot VHDL/lpm_add_sub1.vhd | 1 | 4562 | -- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: lpm_add_sub1.vhd
-- Megafunction Name(s):
-- lpm_add_sub
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_add_sub1 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
cout : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_add_sub1;
ARCHITECTURE SYN OF lpm_add_sub1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
cout : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
result <= sub_wire1(7 DOWNTO 0);
lpm_add_sub_component : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_type => "LPM_ADD_SUB",
lpm_width => 8
)
PORT MAP (
dataa => dataa,
datab => datab,
cout => sub_wire0,
result => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: Function NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0]
-- Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0]
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
-- Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1_inst.vhd TRUE
| gpl-2.0 |
Charlesworth/Albot | Albot VHDL/lpm_add_sub1_inst.vhd | 1 | 139 | lpm_add_sub1_inst : lpm_add_sub1 PORT MAP (
dataa => dataa_sig,
datab => datab_sig,
cout => cout_sig,
result => result_sig
);
| gpl-2.0 |
gauravks/i210dummy | Examples/altera_nios2/ipcore/powerlink/src/lib/slow2fastSync.vhd | 3 | 3726 | -------------------------------------------------------------------------------
--
-- Title : slow2fastSync
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\lib\slow2fastSync.vhd
-- Generated : Tue Aug 9 16:38:41 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-09 V0.01 zelenkaj First version
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY slow2fastSync IS
GENERIC (
doSync_g : BOOLEAN := TRUE
);
PORT (
dataSrc : IN STD_LOGIC;
dataDst : OUT STD_LOGIC;
clkSrc : IN STD_LOGIC;
rstSrc : IN STD_LOGIC;
clkDst : IN STD_LOGIC;
rstDst : IN STD_LOGIC
);
END ENTITY slow2fastSync;
ARCHITECTURE rtl OF slow2fastSync IS
signal toggle, toggleSync, pulse, dataDst_s : std_logic;
begin
dataDst <= dataDst_s when doSync_g = TRUE else dataSrc;
genSync : IF doSync_g = TRUE GENERATE
firstEdgeDet : entity work.edgeDet
port map (
din => dataSrc,
rising => pulse,
falling => open,
any => open,
clk => clkSrc,
rst => rstSrc
);
process(clkSrc, rstSrc)
begin
if rstSrc = '1' then
toggle <= '0';
elsif clkSrc = '1' and clkSrc'event then
if pulse = '1' then
toggle <= not toggle;
end if;
end if;
end process;
sync : entity work.sync
port map (
din => toggle,
dout => toggleSync,
clk => clkDst,
rst => rstDst
);
secondEdgeDet : entity work.edgeDet
port map (
din => toggleSync,
rising => open,
falling => open,
any => dataDst_s,
clk => clkDst,
rst => rstDst
);
END GENERATE;
END ARCHITECTURE rtl; | gpl-2.0 |
Charlesworth/Albot | Albot VHDL/lpm_add_sub0.vhd | 1 | 4439 | -- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: lpm_add_sub0.vhd
-- Megafunction Name(s):
-- lpm_add_sub
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_add_sub0 IS
PORT
(
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END lpm_add_sub0;
ARCHITECTURE SYN OF lpm_add_sub0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1_bv : BIT_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(31 DOWNTO 0) <= "00000000000000000000000000010100";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
result <= sub_wire0(31 DOWNTO 0);
lpm_add_sub_component : lpm_add_sub
GENERIC MAP (
lpm_direction => "SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO",
lpm_type => "LPM_ADD_SUB",
lpm_width => 32
)
PORT MAP (
dataa => sub_wire1,
datab => datab,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "20"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: Function NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "1"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "1"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 20 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0_inst.vhd TRUE
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_14_12_2012/TEST_CTRL_9P6_50MHZ_SCH/NIB2_7SEG.vhd | 6 | 4367 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity NIB2_7SEG_SRC is
Port ( NIB0 : in std_logic_vector(7 downto 0); -- Nibble Ziffer 0
NIB1 : in std_logic_vector(7 downto 0); -- Nibble Ziffer 1
CLK_DISPL : in std_logic; -- Umschaltfrequenz empfohlen: 1 kHz
ZI0 : out std_logic; -- 1: Ziffer 0 soll leuchten
ZI1 : out std_logic; -- 1: Ziffer 1 soll leuchten
ZI2 : out std_logic; -- 1: Ziffer 2 soll leuchten
ZI3 : out std_logic; -- 1: Ziffer 3 soll leuchten
BA : out std_logic; -- 0: Segment A soll leuchten
BB : out std_logic; -- 0: Segment B soll leuchten
BC : out std_logic; -- 0: Segment C soll leuchten
BD : out std_logic; -- 0: Segment D soll leuchten
BE : out std_logic; -- 0: Segment E soll leuchten
BF : out std_logic; -- 0: Segment F soll leuchten
BG : out std_logic); -- 0: Segment G soll leuchten
end NIB2_7SEG_SRC;
architecture Behavioral of NIB2_7SEG_SRC is
signal COUNTER : std_logic;
signal NIB_ANZ : std_logic_vector(7 downto 0);
begin
process(CLK_DISPL, NIB1, NIB0, NIB_ANZ, COUNTER)
begin
If (CLK_DISPL'event and CLK_DISPL = '1')
then
IF COUNTER = '0'
then COUNTER <= '1';
else COUNTER <= '0';
end if;
end if;
case COUNTER is
when '0' => ZI0 <= '1';
ZI1 <= '0';
ZI2 <= '1';
ZI3 <= '0';
NIB_ANZ <= NIB0;
when '1' => ZI0 <= '0';
ZI1 <= '1';
ZI2 <= '0';
ZI3 <= '1';
NIB_ANZ <= NIB1;
when others => ZI0 <= '1';
ZI1 <= '0';
ZI2 <= '1';
ZI3 <= '0';
NIB_ANZ <= NIB0;
end case;
case NIB_ANZ is
when "00000000" => BG <= '1'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --00
when "00000001" => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '1'; --01
when "00000010" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '0'; BA <= '0'; --02
when "00000011" => BG <= '0'; BF <= '1'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --03
when "00000100" => BG <= '0'; BF <= '0'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '1'; --04
when "00000101" => BG <= '0'; BF <= '0'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '1'; BA <= '0'; --05
when "00000110" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '1'; BA <= '0'; --06
when "00000111" => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '0'; --07
when "00001000" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --08
when "00001001" => BG <= '0'; BF <= '0'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --09
when "00001010" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '0'; --0A
when "00001011" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '1'; BA <= '1'; --0B
when "00001100" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '1'; BA <= '1'; --0C
when "00001101" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '1'; --0D
when "00001110" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '1'; BA <= '0'; --0E
when "00001111" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '1'; BC <= '1'; BB <= '1'; BA <= '0'; --0F
when "00010000" => BG <= '1'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --10
when "00010001" => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '1'; --11
when "00010010" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '0'; BA <= '0'; --12
when "00010011" => BG <= '0'; BF <= '1'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --13
when others => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '1'; BB <= '1'; BA <= '1';
end case;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_BYTE_CHECK/CTRL_BYTE_CHECK.vhd | 4 | 6763 | -- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 19.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK is
Port (BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_NUM : out std_logic_vector (7 downto 0); --Ausgangswariable, Bytenummer
NEXT_BYTE : in std_logic; --Eingangsvariable, naechstes Byte
PARITY_OK : in std_logic; --Eingangsvariable, Parität in Ordnung
BYTE_CMPLT : in std_logic; --Eingangsvariable, Byte vollständig
DISPL_COUNT : in std_logic; --Eingangsvariable, Folgeszustand oder Bytezaehler anzeigen
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_BYTE_CHECK;
architecture Behavioral of CTRL_BYTE_CHECK is
type TYPE_STATE is
(ST_BC_00, --Zustaende BYTE_CHECK
ST_BC_01,
ST_BC_02);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit
signal n_BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, neuer Wert
signal BYTE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, Ausgang Master
signal NEXT_BYTE_S : std_logic; --Eingangsvariable, zwischengespeichert im Eingangsregister
signal BYTE_CMPLT_S : std_logic; --Eingangsvariable, zwischengespeichert im Eingangsregister
signal PARITY_OK_S : std_logic; --Eingangsvariable, zwischengespeichert im Eingangsregister
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (BYTE_CMPLT, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then NEXT_BYTE_S <= NEXT_BYTE;
BYTE_CMPLT_S <= BYTE_CMPLT;
PARITY_OK_S <= PARITY_OK;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_BC_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
BYTE_COUNT_M <= n_BYTE_COUNT;
else SV_M <= SV_M;
BYTE_COUNT_M <= BYTE_COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_BC_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
BYTE_COUNT <= BYTE_COUNT_M;
end if;
end if;
end process;
BYTE_CHECK_PROC:process (NEXT_BYTE_S, BYTE_CMPLT_S, PARITY_OK_S, SV, BYTE_COUNT) --Bytes zählen und prüfen
begin
case SV is
when ST_BC_00 =>
if (NEXT_BYTE_S = '1')
then
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --kein Zustandsübergang
end if;
when ST_BC_01 =>
if (BYTE_CMPLT_S = '1')
then
--BC02
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_02; --Zustandsübergang
else
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --kein Zustandsübergang
end if;
when ST_BC_02 =>
if (PARITY_OK_S = '1')
then
--BC03
BYTE_OK <= '1';
n_BYTE_COUNT <= BYTE_COUNT+1; --wird erhoeht
n_SV <= ST_BC_00; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end if;
when others =>
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end case;
end process;
BYTE_NUM_PROC:process (BYTE_COUNT) --Ausgabe BYTE_NUM aus BYTE_COUNT
begin
BYTE_NUM <= BYTE_COUNT;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, LONG_STATE_SV, LONG_STATE_n_SV, BYTE_COUNT) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
--anktuellen Zustand anzeigen
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
if (DISPL_COUNT ='0')
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
else --BYTEzaehler anzeigen
DISPL1_n_SV(0) <= BYTE_COUNT(0);
DISPL1_n_SV(1) <= BYTE_COUNT(1);
DISPL1_n_SV(2) <= BYTE_COUNT(2);
DISPL1_n_SV(3) <= BYTE_COUNT(3);
DISPL2_n_SV(0) <= BYTE_COUNT(4);
DISPL2_n_SV(1) <= BYTE_COUNT(5);
DISPL2_n_SV(2) <= BYTE_COUNT(6);
DISPL2_n_SV(3) <= BYTE_COUNT(7);
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/TEST_CTRL_TELEGRAM_CHECK/NIB4_7SEG_SRC.vhd | 38 | 4182 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity NIB4_7SEG_SRC is
Port ( NIB0 : in std_logic_vector(3 downto 0); -- Nibble Ziffer 0
NIB1 : in std_logic_vector(3 downto 0); -- Nibble Ziffer 1
NIB2 : in std_logic_vector(3 downto 0); -- Nibble Ziffer 2
NIB3 : in std_logic_vector(3 downto 0); -- Nibble Ziffer 3
CLK_DISPL : in std_logic; -- Umschaltfrequenz empfohlen: 1 kHz
ZI0 : out std_logic; -- 1: Ziffer 0 soll leuchten
ZI1 : out std_logic; -- 1: Ziffer 1 soll leuchten
ZI2 : out std_logic; -- 1: Ziffer 2 soll leuchten
ZI3 : out std_logic; -- 1: Ziffer 3 soll leuchten
BA : out std_logic; -- 0: Segment A soll leuchten
BB : out std_logic; -- 0: Segment B soll leuchten
BC : out std_logic; -- 0: Segment C soll leuchten
BD : out std_logic; -- 0: Segment D soll leuchten
BE : out std_logic; -- 0: Segment E soll leuchten
BF : out std_logic; -- 0: Segment F soll leuchten
BG : out std_logic); -- 0: Segment G soll leuchten
end NIB4_7SEG_SRC;
architecture Behavioral of NIB4_7SEG_SRC is
signal COUNTER : std_logic_vector(1 downto 0);
signal NIB_ANZ : std_logic_vector(3 downto 0);
begin
process(CLK_DISPL, NIB3, NIB2, NIB1, NIB0, NIB_ANZ, COUNTER)
begin
If (CLK_DISPL'event and CLK_DISPL = '1')
then COUNTER <= COUNTER +1;
end if;
case COUNTER is
when "00" => ZI0 <= '1';
ZI1 <= '0';
ZI2 <= '0';
ZI3 <= '0';
NIB_ANZ <= NIB0;
when "01" => ZI0 <= '0';
ZI1 <= '1';
ZI2 <= '0';
ZI3 <= '0';
NIB_ANZ <= NIB1;
when "10" => ZI0 <= '0';
ZI1 <= '0';
ZI2 <= '1';
ZI3 <= '0';
NIB_ANZ <= NIB2;
when "11" => ZI0 <= '0';
ZI1 <= '0';
ZI2 <= '0';
ZI3 <= '1';
NIB_ANZ <= NIB3;
when others => ZI0 <= '1';
ZI1 <= '0';
ZI2 <= '0';
ZI3 <= '0';
NIB_ANZ <= NIB0;
end case;
case NIB_ANZ is
when "0000" => BG <= '1'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --0
when "0001" => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '1'; --1
when "0010" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '0'; BA <= '0'; --2
when "0011" => BG <= '0'; BF <= '1'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --3
when "0100" => BG <= '0'; BF <= '0'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '1'; --4
when "0101" => BG <= '0'; BF <= '0'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '1'; BA <= '0'; --5
when "0110" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '1'; BA <= '0'; --6
when "0111" => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '0'; --7
when "1000" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --8
when "1001" => BG <= '0'; BF <= '0'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --9
when "1010" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '0'; --A
when "1011" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '1'; BA <= '1'; --B
when "1100" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '1'; BA <= '1'; --C
when "1101" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '1'; --D
when "1110" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '1'; BA <= '0'; --E
when "1111" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '1'; BC <= '1'; BB <= '1'; BA <= '0'; --F
when others => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '1'; BB <= '1'; BA <= '1';
end case;
end process;
end Behavioral;
| gpl-2.0 |
ErikAndren/ov7660-object-tracker | SpatialAverager.vhd | 1 | 3143 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
use work.OV76X0Pack.all;
entity SpatialAverager is
generic (
DataW : positive
);
port (
RstN : in bit1;
Clk : in bit1;
--
Vsync : in bit1;
--
PixelInVal : in bit1;
PixelIn : in word(DataW-1 downto 0);
--
SramAddr : out word(SramAddrW-1 downto 0);
SramReq : out bit1;
SramWe : out bit1;
SramRe : out bit1;
--
PopWrite : in bit1;
PopRead : in bit1;
PixelFromSram : in word(DataW-1 downto 0);
PixelToSram : out word(DataW-1 downto 0)
);
end entity;
architecture rtl of SpatialAverager is
signal LineCnt_N, LineCnt_D : word(FrameHW-1 downto 0);
signal PixelCnt_N, PixelCnt_D : word(FrameWW-1 downto 0);
signal PixelFromSram_N, PixelFromSram_D : word(DataW-1 downto 0);
signal PixelToSram_N, PixelToSram_D : word(DataW-1 downto 0);
signal SramWe_N, SramWe_D, SramRe_N, SramRe_D : bit1;
begin
SyncProc : process (Clk, RstN)
begin
if RstN = '0' then
LineCnt_D <= (others => '0');
PixelCnt_D <= (others => '0');
PixelFromSram_D <= (others => '0');
PixelToSram_D <= (others => '0');
SramWe_D <= '0';
SramRe_D <= '0';
elsif rising_edge(Clk) then
LineCnt_D <= LineCnt_N;
PixelCnt_D <= PixelCnt_N;
PixelFromSram_D <= PixelFromSram_N;
PixelToSram_D <= PixelToSram_N;
SramWe_D <= SramWe_N;
SramRe_D <= SramRe_N;
if Vsync = '1' then
LineCnt_D <= (others => '0');
PixelCnt_D <= (others => '0');
PixelFromSram_D <= (others => '0');
PixelToSram_D <= (others => '0');
SramRe_D <= '0';
SramWe_D <= '0';
end if;
end if;
end process;
ASyncProc : process (LineCnt_D, PixelCnt_D, PixelInVal, SramRe_D, SramWe_D, PixelIn, PixelFromSram, PopRead, PixelFromSram_D)
variable Avg : word(DataW downto 0);
begin
LineCnt_N <= LineCnt_D;
PixelCnt_N <= PixelCnt_D;
SramRe_N <= SramRe_D;
if PopRead = '1' then
SramRe_N <= '0';
PixelFromSram_N <= PixelFromSram;
end if;
SramWe_N <= SramWe_D;
if PopWrite = '1' then
SramWe_N <= '0';
end if;
if PixelInVal = '1' then
PixelCnt_N <= PixelCnt_D + 1;
if PixelCnt_D + 1 = FrameW then
PixelCnt_N <= (others => '0');
LineCnt_N <= LineCnt_D + 1;
if LineCnt_D + 1 = FrameH then
LineCnt_N <= (others => '0');
end if;
end if;
-- Perform delta calculation
-- newAvg = oldAvg - oldAvg>>2 + newColor>>2.
Avg := (PixelFromSram - PixelFromSram(PixelFromSram'high downto 2)) + PixelIn;
PixelToSram <= Avg(PixelToSram'high downto 0);
SramWe_N <= '1';
SramRe_N <= '1';
end if;
end process;
SramAddr <= xt0(LineCnt_D & PixelCnt_D, SramAddr'length);
end architecture rtl;
| gpl-2.0 |
plorefice/vhdl-simple-processor | src/reg_file.vhd | 1 | 1873 | --==============================================================================
-- File: reg_file.vhd
-- Author: Pietro Lorefice
--==============================================================================
-- Description:
-- Register file used to implement general registers R0..Rn in the CPU.
--
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg_file is
generic (
B : integer; -- Register size
R : integer -- 2**R registers
);
port (
clk : in std_logic; -- Clock
rst : in std_logic; -- Synch. reset
we_l : in std_logic; -- Write enable
w_data : in std_logic_vector(B-1 downto 0); -- Data to be written
w_addr : in std_logic_vector(R-1 downto 0); -- Write address
rd_addr_1 : in std_logic_vector(R-1 downto 0); -- 1st read address
rd_addr_2 : in std_logic_vector(R-1 downto 0); -- 2nd read address
rd_data_1 : out std_logic_vector(B-1 downto 0); -- 1st datum read
rd_data_2 : out std_logic_vector(B-1 downto 0) -- 2ns datum read
);
end entity reg_file;
architecture RTL of reg_file is
type reg_t is array(2**R - 1 downto 0) of std_logic_vector(B-1 downto 0);
signal reg_file_q : reg_t;
begin
-- =======================
-- | Register file logic |
-- =======================
reg_logic : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
reg_file_q <= (others => (others => '0'));
elsif we_l = '0' then
reg_file_q(to_integer(unsigned(w_addr))) <= w_data;
end if;
end if;
end process reg_logic;
-- =============================
-- | Output signal assignments |
-- =============================
rd_data_1 <= reg_file_q(to_integer(unsigned(rd_addr_1)));
rd_data_2 <= reg_file_q(to_integer(unsigned(rd_addr_2)));
end architecture RTL;
| gpl-2.0 |
ReconOS/reconos | lib/pcores/reconos_proc_control_v1_00_a/hdl/vhdl/reconos_proc_control.vhd | 1 | 12142 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - PROC_CONTROL - Proc control implementation
--
-- project: ReconOS
-- author: Christoph R??thing, University of Paderborn
-- description: The Proc Conrol is used to control the different
-- hardware parts through a single interface. It allows
-- to reset the HWTs seperately and asynchronously and
-- configures the MMU. To provide its functionality it
-- has several registers.
-- Register Definition (as seen from Bus):
-- Reg0: Number of HWT-Slots (OSIFS) - Read only
-- # all MMU related stuff
-- Reg1: PGD address - Read / Write
-- Reg2: Page fault address (only valid on interrupt)
-- read to clear interrupt, write after handling
-- Reg3: TLB hits - Read only
-- Reg4: TLB misses - Read only
-- # resets
-- Reg5: ReconOS reset (reset everything) - Write only
-- Reg6: HWT reset (multiple registers) - Write only
-- | x , x-1, ... | x-32 , x-33, ... 0 |
-- Reg7: HWT signal - Write only
-- | x , x-1, ... | x-32 , x-33, ... 0 |
--
-- Page fault handling works the following:
-- 1.) MMU raises MMU_Pgf
-- 2.) Proc control raises PROC_Pgf_Int
-- 3.) CPU clears interrupt by reading register 2
-- 4.) CPU handles page fault and acknowledges this
-- by writing to register 2
-- 5.) Proc control informs MMU by raising MMU_Ready
-- that the page fault has been handled
--
-- ======================================================================
<<reconos_preproc>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
entity reconos_proc_control is
generic (
-- Proc Control paramters
C_NUM_HWTS : integer := 1;
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port (
<<generate for SLOTS>>
PROC_Hwt_Rst_<<Id>> : out std_logic;
PROC_Hwt_Signal_<<Id>> : out std_logic;
<<end generate>>
PROC_Sys_Rst : out std_logic;
PROC_Pgf_Int : out std_logic;
-- MMU related ports
MMU_Pgf : in std_logic;
MMU_Fault_Addr : in std_logic_vector(31 downto 0);
MMU_Retry : out std_logic;
MMU_Pgd : out std_logic_vector(31 downto 0);
-- These input ports are optional and only used in conjunction with the microblaze mmu
MMU_Tlb_Hits : in std_logic_vector(31 downto 0) := X"00000000";
MMU_Tlb_Misses : in std_logic_vector(31 downto 0) := X"00000000";
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
end entity reconos_proc_control;
architecture implementation of reconos_proc_control is
-- Declare port attributes for the Vivado IP Packager
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of S_AXI_ACLK: SIGNAL is "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of S_AXI_ACLK: SIGNAL is "ASSOCIATED_RESET <<generate for SLOTS>>PROC_Hwt_Rst_<<Id>>:<<end generate>>PROC_Sys_Rst:S_AXI_ARESETN";
ATTRIBUTE X_INTERFACE_INFO of PROC_Pgf_Int: SIGNAL is "xilinx.com:signal:interrupt:1.0 PROC_Pgf_Int INTERRUPT";
ATTRIBUTE X_INTERFACE_PARAMETER of PROC_Pgf_Int: SIGNAL is "SENSITIVITY LEVEL_HIGH";
ATTRIBUTE X_INTERFACE_INFO of PROC_Sys_Rst: SIGNAL is "xilinx.com:signal:reset:1.0 PROC_Sys_Rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER of PROC_Sys_Rst: SIGNAL is "POLARITY ACTIVE_HIGH";
<<generate for SLOTS>>
ATTRIBUTE X_INTERFACE_INFO of PROC_Hwt_Rst_<<Id>>: SIGNAL is "xilinx.com:signal:reset:1.0 PROC_Hwt_Rst_<<Id>> RST";
ATTRIBUTE X_INTERFACE_PARAMETER of PROC_Hwt_Rst_<<Id>>: SIGNAL is "POLARITY ACTIVE_HIGH";
<<end generate>>
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant NUM_HWT_REGS : integer := ((C_NUM_HWTS - 1) / C_SLV_DWIDTH) + 1;
constant USER_SLV_NUM_REG : integer := NUM_HWT_REGS * 2 + 6;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
-- Index for CS/CE
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
-- IP Interconnect (IPIC) signal declarations
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal hwt_rst : std_logic_vector(C_NUM_HWTS - 1 downto 0);
signal hwt_signal : std_logic_vector(C_NUM_HWTS - 1 downto 0);
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : entity work.reconos_proc_control_user_logic
generic map (
-- Proc Control parameters
C_NUM_HWTS => C_NUM_HWTS,
-- Bus protocol parameters
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map (
-- Proc Control ports
PROC_Hwt_Rst => hwt_rst,
PROC_Hwt_Signal => hwt_signal,
PROC_Sys_Rst => PROC_Sys_Rst,
PROC_Pgf_Int => PROC_Pgf_Int,
-- MMU related ports
MMU_Pgf => MMU_Pgf,
MMU_Fault_Addr => MMU_Fault_Addr,
MMU_Retry => MMU_Retry,
MMU_Pgd => MMU_Pgd,
MMU_Tlb_Hits => MMU_Tlb_Hits,
MMU_Tlb_Misses => MMU_Tlb_Misses,
-- Bus protocol ports
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
-- connect internal signals
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
<<generate for SLOTS>>
PROC_Hwt_Rst_<<Id>> <= hwt_rst(<<_i>>);
PROC_Hwt_Signal_<<Id>> <= hwt_signal(<<_i>>);
<<end generate>>
end implementation;
| gpl-2.0 |
ErikAndren/ov7660-object-tracker | MedianFilter.vhd | 1 | 3401 | -- Implements median filter
-- Sorts all entries and selects the median value
-- Optimized comparator tree picked from
-- www.ijetae.com ISSN 2250-2459, Vol 2, Issue 8, Aug 2012. Fig 5
--
-- Copyright Erik Zachrisson - [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
use work.OV76X0Pack.all;
entity MedianFilter is
generic (
DataW : in positive;
Res : in positive
);
port (
Clk : in bit1;
RstN : in bit1;
--
PixelIn : in PixVec2d(Res-1 downto 0);
PixelInVal : in bit1;
--
PixelOut : out word(DataW-1 downto 0);
PixelOutVal : out bit1
);
end entity;
architecture rtl of MedianFilter is
constant Threshold : natural := 255;
signal PixelOut_N, PixelOut_D : word(DataW-1 downto 0);
signal PixelOutVal_N, PixelOutVal_D : bit1;
signal PixelOutVal_D2 : bit1;
procedure Comparator (signal X : in word; signal Y : in word; signal Higher : out word; signal Lower : out word) is
begin
if X > Y then
Higher <= X;
Lower <= Y;
else
Higher <= Y;
Lower <= X;
end if;
end procedure;
signal A_H, A_L, B_H, B_L, C_H, C_L, D_H, D_L, E_H, E_L, F_H, F_L : word(PixelW-1 downto 0);
signal G_H, G_L, H_H, H_L, I_H, I_L, J_H, J_L, K_H, K_L, L_H, L_L : word(PixelW-1 downto 0);
signal M_H, M_L, N_H, N_L, O_H, O_L, Q_H, Q_L, S_H, S_L, T_H, T_L : word(PixelW-1 downto 0);
signal U_H, U_L, Median : word(PixelW-1 downto 0);
--
signal J_L_D, I_H_D, K_H_D, K_L_D, I_L_D, D_L_D, L_H_D : word(PixelW-1 downto 0);
begin
A : Comparator(PixelIn(0)(0), PixelIn(0)(1), A_H, A_L);
B : Comparator(PixelIn(1)(0), PixelIn(1)(1), B_H, B_L);
C : Comparator(PixelIn(2)(0), PixelIn(2)(1), C_H, C_L);
--
D : Comparator(PixelIn(0)(2), A_L, D_H, D_L);
E : Comparator(PixelIn(1)(2), B_L, E_H, E_L);
F : Comparator(PixelIn(2)(2), C_L, F_H, F_L);
--
G : Comparator(A_H, D_H, G_H, G_L);
H : Comparator(B_H, E_H, H_H, H_L);
I : Comparator(C_H, F_H, I_H, I_L);
--
J : Comparator(G_H, H_H, J_H, J_L);
K : Comparator(G_L, H_L, K_H, K_L);
L : Comparator(E_L, F_L, L_H, L_L);
--
M : Comparator(J_L_D, I_H_D, M_H, M_L);
N : Comparator(K_L_D, I_L_D, N_H, N_L);
O : Comparator(D_L_D, L_H_D, O_H, O_L);
--
Q : Comparator(K_H_D, N_H, Q_H, Q_L);
S : Comparator(M_L, Q_L, S_H, S_L);
T : Comparator(S_L, O_H, T_H, T_L);
--
U : Comparator(S_H, T_H, U_H, U_L);
MedianAssign : Median <= U_L;
SyncRstProc : process (Clk, RstN)
begin
if RstN = '0' then
PixelOutVal_D <= '0';
PixelOutVal_D2 <= '0';
elsif rising_edge(Clk) then
PixelOutVal_D <= PixelOutVal_N;
PixelOutVal_D2 <= PixelOutVal_D;
end if;
end process;
SyncNoRstProc : process (Clk)
begin
if rising_edge(Clk) then
PixelOut_D <= PixelOut_N;
J_L_D <= J_L;
I_H_D <= I_H;
K_H_D <= K_H;
K_L_D <= K_L;
I_L_D <= I_L;
D_L_D <= D_L;
L_H_D <= L_H;
end if;
end process;
AsyncProc : process (PixelIn, PixelInVal, Median)
begin
PixelOutVal_N <= PixelInVal;
PixelOut_N <= Median;
end process;
PixelOut <= PixelOut_D;
PixelOutVal <= PixelOutVal_D2;
end architecture rtl;
| gpl-2.0 |
plorefice/vhdl-simple-processor | src/ctrl_fsm.vhd | 1 | 7551 | --==============================================================================
-- File: ctrl_fsm.vhd
-- Author: Pietro Lorefice
--==============================================================================
-- Description:
-- FSM portion of the FSMD processor architecture. It keeps track of the
-- internal state and provides the datapath with the correct signals.
--
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_fsm is
port (
clk : in std_logic; -- Clock
rst : in std_logic; -- Reset
opcode : in std_logic_vector(3 downto 0); -- Instruction opcode
alu_op_b_sel : out std_logic; -- ALU operand B select
alu_ctrl_op : out std_logic_vector(1 downto 0); -- ALU control unit operation
pc_en : out std_logic; -- Program counter register enable
ir_en : out std_logic; -- Instruction register enable
reg_we_l : out std_logic; -- Register file write enable
reg_op_a_sel : out std_logic; -- Register file operand A select
reg_op_b_sel : out std_logic; -- Register file operand B select
reg_wr_d_sel : out std_logic; -- Register file write data select
mem_sel_l : out std_logic; -- Data memory select
mem_we_l : out std_logic -- Data memory write enable
);
end entity ctrl_fsm;
architecture RTL of ctrl_fsm is
-- ==================
-- | State register |
-- ==================
type state_t is (fetch, fetch_w,
decode,
read_dab, read_dai, read_d_b, read_d_i,
add, sub, addi, log, logi, ld, st,
write_reg_alu, write_reg_mem, write_reg_mem_w, write_mem,
hlt
);
signal state_q, state_n : state_t;
-- ====================
-- | Output registers |
-- ====================
signal alu_op_b_sel_q, alu_op_b_sel_n : std_logic;
signal alu_ctrl_op_q, alu_ctrl_op_n : std_logic_vector(1 downto 0);
signal pc_en_q, pc_en_n : std_logic;
signal ir_en_q, ir_en_n : std_logic;
signal reg_we_l_q, reg_we_l_n : std_logic;
signal reg_op_a_sel_q, reg_op_a_sel_n : std_logic;
signal reg_op_b_sel_q, reg_op_b_sel_n : std_logic;
signal reg_wr_d_sel_q, reg_wr_d_sel_n : std_logic;
signal mem_sel_l_q, mem_sel_l_n : std_logic;
signal mem_we_l_q, mem_we_l_n : std_logic;
begin
-- ==================
-- | State register |
-- ==================
star : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
state_q <= fetch;
alu_ctrl_op_q <= "00";
alu_op_b_sel_q <= '0';
pc_en_q <= '0';
ir_en_q <= '0';
reg_we_l_q <= '1';
reg_op_a_sel_q <= '0';
reg_op_b_sel_q <= '0';
reg_wr_d_sel_q <= '0';
mem_sel_l_q <= '1';
mem_we_l_q <= '1';
else
state_q <= state_n;
alu_ctrl_op_q <= alu_ctrl_op_n;
alu_op_b_sel_q <= alu_op_b_sel_n;
pc_en_q <= pc_en_n;
ir_en_q <= ir_en_n;
reg_we_l_q <= reg_we_l_n;
reg_op_a_sel_q <= reg_op_a_sel_n;
reg_op_b_sel_q <= reg_op_b_sel_n;
reg_wr_d_sel_q <= reg_wr_d_sel_n;
mem_sel_l_q <= mem_sel_l_n;
mem_we_l_q <= mem_we_l_n;
end if;
end if;
end process star;
-- =============
-- | FSM logic |
-- =============
fsm : process(state_q, opcode,
alu_ctrl_op_q, alu_op_b_sel_q,
ir_en_q, pc_en_q,
mem_sel_l_q, mem_we_l_q,
reg_op_a_sel_q, reg_op_b_sel_q, reg_we_l_q, reg_wr_d_sel_q
) is
begin
state_n <= state_q;
alu_ctrl_op_n <= alu_ctrl_op_q;
alu_op_b_sel_n <= alu_op_b_sel_q;
pc_en_n <= pc_en_q;
ir_en_n <= ir_en_q;
reg_we_l_n <= reg_we_l_q;
reg_op_a_sel_n <= reg_op_a_sel_q;
reg_op_b_sel_n <= reg_op_b_sel_q;
reg_wr_d_sel_n <= reg_wr_d_sel_q;
mem_sel_l_n <= mem_sel_l_q;
mem_we_l_n <= mem_we_l_q;
case state_q is
-- ===============
-- | Fetch phase |
-- ===============
when fetch =>
reg_we_l_n <= '1';
mem_sel_l_n <= '1';
mem_we_l_n <= '1';
pc_en_n <= '1';
ir_en_n <= '1';
state_n <= fetch_w;
when fetch_w =>
pc_en_n <= '0';
state_n <= decode;
-- ================
-- | Decode phase |
-- ================
when decode =>
ir_en_n <= '0';
case opcode is
when X"0" | X"1" =>
state_n <= read_dab;
when X"2" | X"5" | X"6" | X"8" | X"9" =>
state_n <= read_dai;
when X"3" =>
state_n <= read_d_b;
when X"4" =>
state_n <= read_d_i;
when others =>
null;
end case;
-- ==============
-- | Read phase |
-- ==============
when read_dab =>
reg_op_a_sel_n <= '1'; -- 1st operand = Ra
reg_op_b_sel_n <= '1'; -- 2nd operand = Rb
alu_op_b_sel_n <= '0'; -- 2nd ALU operand = Rb
case opcode is
when X"0" =>
state_n <= add;
when X"1" =>
state_n <= sub;
when others =>
state_n <= hlt;
end case;
when read_dai =>
reg_op_a_sel_n <= '1'; -- 1st operand = Ra
reg_op_b_sel_n <= '0'; -- 2nd operand = Rd
alu_op_b_sel_n <= '1'; -- 2nd ALU operand = Immediate
case opcode is
when X"2" =>
state_n <= addi;
when X"5" | X"6" =>
state_n <= ld;
when X"8" | X"9" =>
state_n <= st;
when others =>
state_n <= hlt;
end case;
when read_d_b =>
reg_op_a_sel_n <= '0'; -- 1st operand = Rd
reg_op_b_sel_n <= '1'; -- 2nd operand = Rb
alu_op_b_sel_n <= '0'; -- 2nd ALU operand = Rb
state_n <= log;
when read_d_i =>
reg_op_a_sel_n <= '0'; -- 1st operand = Rd
reg_op_b_sel_n <= '0'; -- 2nd operand = Don't care
alu_op_b_sel_n <= '1'; -- 2nd ALU operand = Immediate
state_n <= logi;
-- ===================
-- | Execution phase |
-- ===================
when add =>
alu_ctrl_op_n <= "10"; -- Ra + Rb
state_n <= write_reg_alu;
when sub =>
alu_ctrl_op_n <= "11"; -- Ra - Rb
state_n <= write_reg_alu;
when addi =>
alu_ctrl_op_n <= "10"; -- Ra + imm
state_n <= write_reg_alu;
when log =>
alu_ctrl_op_n <= "00"; -- Rd {&|!x} Rb
state_n <= write_reg_alu;
when logi =>
alu_ctrl_op_n <= "00"; -- Rd {&|!x} imm
state_n <= write_reg_alu;
when ld =>
alu_ctrl_op_n <= "10"; -- Ra + imm
state_n <= write_reg_mem;
when st =>
alu_ctrl_op_n <= "10"; -- Ra + imm
state_n <= write_mem;
-- ===============
-- | Write phase |
-- ===============
when write_reg_alu =>
reg_wr_d_sel_n <= '1'; -- Result = ALU
reg_we_l_n <= '0';
state_n <= fetch;
when write_reg_mem =>
reg_wr_d_sel_n <= '0'; -- Result = Memory
reg_we_l_n <= '0';
mem_sel_l_n <= '0';
state_n <= write_reg_mem_w;
when write_reg_mem_w =>
state_n <= fetch;
when write_mem =>
mem_sel_l_n <= '0';
mem_we_l_n <= '0';
state_n <= fetch;
-- ================
-- | !! HALTED !! |
-- ================
when hlt =>
state_n <= hlt;
end case;
end process fsm;
-- ======================
-- | Output assignments |
-- ======================
alu_op_b_sel <= alu_op_b_sel_q;
alu_ctrl_op <= alu_ctrl_op_q;
pc_en <= pc_en_q;
ir_en <= ir_en_q;
reg_we_l <= reg_we_l_q;
reg_op_a_sel <= reg_op_a_sel_q;
reg_op_b_sel <= reg_op_b_sel_q;
reg_wr_d_sel <= reg_wr_d_sel_q;
mem_sel_l <= mem_sel_l_q;
mem_we_l <= mem_we_l_q;
end architecture RTL;
| gpl-2.0 |
plorefice/vhdl-simple-processor | src/alu_ctrl.vhd | 1 | 897 | --==============================================================================
-- File: alu_ctrl.vhd
-- Author: Pietro Lorefice
--==============================================================================
-- Description:
-- ALU control circuitry, driven by control signals coming from FSM.
--
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity alu_ctrl is
port (
op : in std_logic_vector(1 downto 0); -- Type of operation
log : in std_logic_vector(1 downto 0); -- Logic operator
ctrl : out std_logic_vector(2 downto 0) -- Control signal
);
end entity alu_ctrl;
architecture RTL of alu_ctrl is
begin
ctrl_2 : with op select
ctrl(2) <=
'1' when "00",
'0' when others;
ctrl_1_0 : with op select
ctrl(1 downto 0) <=
log when "00",
op when others;
end architecture RTL;
| gpl-2.0 |
konsolebox/geany | data/filedefs/filetypes.vhdl | 22 | 3042 | # For complete documentation of this file, please see Geany's main documentation
[styling]
# Edit these in the colorscheme .conf file instead
default=default
comment=comment
comment_line_bang=comment_line
block_comment=comment
number=number_1
string=string_1
operator=operator
identifier=identifier_1
stringeol=string_eol
keyword=keyword_1
stdoperator=operator
attribute=attribute
stdfunction=function
stdpackage=preprocessor
stdtype=type
userword=keyword_2
[keywords]
# all items must be in one line
keywords=access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity shared signal subtype then to transport type unaffected units until use variable wait when while with
operators=abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
attributes=left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction event active last_event last_active last_value driving driving_value simple_name path_name instance_name
std_functions=now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
std_packages=std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
std_types=boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
userwords=
[settings]
# default extension used when saving files
extension=vhd
# MIME type
mime_type=text/x-vhdl
# the following characters are these which a "word" can contains, see documentation
#wordchars=_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
# single comments, like # in this file
comment_single=--
# multiline comments
#comment_open=
#comment_close=
# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
#command_example();
# setting to false would generate this
# command_example();
# This setting works only for single line comments
comment_use_indent=true
# context action command (please see Geany's main documentation for details)
context_action_cmd=
[indentation]
#width=4
# 0 is spaces, 1 is tabs, 2 is tab & spaces
#type=1
| gpl-2.0 |
freecores/lq057q3dc02 | design/hsyncx_control.vhd | 1 | 6094 | ------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
------------------------------------------------------------------------------
--
-- $Id: hsyncx_control.vhd,v 1.1 2008-11-07 00:48:12 jwdonal Exp $
--
-- Description:
-- This file controls the HSYNCx signal. The HSYNCx state machine is
-- very simplistic since the current state is only dependent on the number
-- of LCD clocks that have occurred. It has no other dependencies whatsoever!
-- However, all other controllers (i.e. VSYNCx, ENAB, PIX_gen) are all dependent
-- upon HSYNCx.
--
-- Notes: that even though VSYNCx controls the start of a frame
-- you cannot simply disable HSYNCx cycling once the data has been shifted
-- into the LCD. This is b/c there is a MAX cycle time spec in the datasheet
-- of 450 clocks! It is simplest to just leave HSYNCx running at all times
-- no matter what.
--
-- Structure:
-- - xupv2p.ucf
-- - components.vhd
-- - lq057q3dc02_tb.vhd
-- - lq057q3dc02.vhd
-- - dcm_sys_to_lcd.xaw
-- - video_controller.vhd
-- - enab_control.vhd
-- - hsyncx_control.vhd
-- - vsyncx_control.vhd
-- - clk_lcd_cyc_cntr.vhd
-- - image_gen_bram.vhd
-- - image_gen_bram_red.xco
-- - image_gen_bram_green.xco
-- - image_gen_bram_blue.xco
--
------------------------------------------------------------------------------
--
-- Naming Conventions:
-- active low signals "*x"
-- clock signal "CLK_*"
-- reset signal "RST"
-- generic/constant "C_*"
-- user defined type "TYPE_*"
-- state machine next state "*_ns"
-- state machine current state "*_cs""
-- pipelined signals "*_d#"
-- register delay signals "*_p#"
-- signal "*_sig"
-- variable "*_var"
-- storage register "*_reg"
-- clock enable signals "*_ce"
-- internal version of output port used as connecting wire "*_wire"
-- input/output port "ALL_CAPS"
-- process "*_PROC"
--
------------------------------------------------------------------------------
--////////////////////--
-- LIBRARY INCLUSIONS --
--////////////////////--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--////////////////////--
-- ENTITY DECLARATION --
--////////////////////--
ENTITY hsyncx_control IS
generic (
C_HSYNC_TH,
C_HSYNC_THP,
C_NUM_CLKS_WIDTH : POSITIVE
);
port (
RSTx,
CLK_LCD : IN std_logic;
HSYNCx : OUT std_logic
);
END ENTITY hsyncx_control;
--////////////////////////--
-- ARCHITECTURE OF ENTITY --
--////////////////////////--
ARCHITECTURE hsyncx_control_arch OF hsyncx_control IS
signal num_hsyncx_clks_reg : std_logic_vector(C_NUM_CLKS_WIDTH-1 downto 0) := (others => '0');
begin
------------------------------------------------------------------
-- Process Description:
-- This process enables or disables the HSYNCx port depending
-- upon the number of clocks that have passed (num_hsyncx_clks_reg)
-- relative to C_HSYNC_THP.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- HSYNCx
--
-- Notes:
-- N/A
------------------------------------------------------------------
HSYNCx_cntrl_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
HSYNCx <= '1';
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
if( num_hsyncx_clks_reg < C_HSYNC_THP ) then
HSYNCx <= '0';
else
HSYNCx <= '1';
end if;
end if;
end process HSYNCx_cntrl_PROC;
------------------------------------------------------------------
-- Process Description:
-- This process controls the num_hsyncx_clks_reg counter
-- and resets it when it has reached the defined C_HSYNC_TH
-- parameter.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- num_hsyncx_clks_reg
--
-- Notes:
-- N/A
------------------------------------------------------------------
HSYNCx_CLK_LCD_Cntr_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
num_hsyncx_clks_reg <= (others => '0');
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
if( num_hsyncx_clks_reg = C_HSYNC_TH - 1 ) then -- 0 to (TH - 1) = TH clocks!
num_hsyncx_clks_reg <= (others => '0'); -- a full HSYNC cycle has completed. START OVER!
else
num_hsyncx_clks_reg <= num_hsyncx_clks_reg + 1; -- keep counting until we have reached a full HSYNC cycle
end if;
end if;
end process HSYNCx_CLK_LCD_Cntr_PROC;
END ARCHITECTURE hsyncx_control_arch;
| gpl-2.0 |
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